Clock signal control method, clock signal control device and clock signal verification method

Abstract

The invention discloses a clock signal control method and device and a verification method, and the method comprises the steps: obtaining the original clock frequency of each node on a data communication path, the node being an object with an independent clock signal, and the node comprising an equipment internal node and a peripheral node connected with the equipment; if the difference between the original clock frequency of the peripheral node and the maximum original clock frequency in the internal nodes of the equipment meets a set condition, determining a target matching frequency based on the original clock frequency of each node on the communication path, the target matching frequency including the target clock frequency of each node; the target clock frequency of at least one node in the nodes is greater than the original clock frequency; based on the original clock frequency and the target clock frequency of each node, determining a node which needs to be subjected to clock frequency raising as a target node; and controlling the clock frequency of the target node to rise to the target clock frequency of the target node so as to improve the overall data transmission rate of the data communication path.

Description

Technical Field

[0001] The present application relates to technical signal control technology, and more specifically, to a clock signal control method, device and verification method. Background Art

[0002] The clock frequency of the interface related to low-speed peripherals is often relatively low, resulting in a relatively slow data transmission speed. If low-speed peripherals and other modules with relatively high data transmission or data processing speeds are used together for related verification, the overall simulation speed will be slowed down due to their relatively low clock frequency. Summary of the invention

[0003] In view of this, this application provides the following technical solutions: In a first aspect, the present application provides a method for controlling a clock signal, the method comprising: Obtaining the original clock frequency of each node on the data communication path, wherein the node is an object having an independent clock signal, and the node includes an internal node of the device and an external node connected to the device; If the difference between the original clock frequency of the peripheral node and the maximum original clock frequency of the internal nodes of the device meets the set condition, a target matching frequency is determined based on the original clock frequency of each node on the communication path, wherein the target matching frequency includes the target clock frequency of each node, and at least one of the nodes has a target clock frequency greater than its original clock frequency; Based on the original clock frequency and the target clock frequency of each node, a node that needs to perform clock frequency increase is determined as a target node; The clock frequency of the target node is controlled to be increased to the target clock frequency of the target node, so as to increase the data transmission rate of the entire data communication path.

[0004] In a possible implementation, determining the target matching frequency based on the original clock frequency of each node on the communication path includes: Determine a first node having the lowest original clock frequency; Determining a data synchronization type between the first node and a second node connected thereto; A relationship of clock frequencies between the first node and the second node is determined based on the data synchronization type.

[0005] In a possible implementation, determining the relationship between the clock frequencies of the first node and the second node based on the data synchronization type includes at least one of the following: If the data synchronization type is a first type, determining that a ratio of a target clock frequency of the second node to a target clock frequency of the first node is at least 2, the first type representing a synchronization mode without data buffering; If the data synchronization type is the second type, it is determined that the ratio of the target clock frequency of the second node to the target clock frequency of the first node is greater than 1, and the second type is a synchronization mode with data buffering.

[0006] In a possible implementation, it also includes: Determine whether there is a serial-to-parallel conversion between the first node and the second node; If so, determining a relationship between clock frequencies of the first node and the second node based on the data synchronization type includes: The multiple relationship between the first node and the second node is determined based on the data bit width converted into parallel data and the data synchronization type.

[0007] In a possible implementation, the target clock frequency of each node on the data communication path is not higher than the highest operating frequency of each node in the device.

[0008] In a possible implementation, if the data communication path is a serial data path, in the target matching frequency, in the data upstream direction, the clock frequency of the downstream node is not lower than the clock frequency of the upstream node.

[0009] In a possible implementation, the target nodes include at least two, and controlling the clock frequency of the target nodes to increase to the target clock frequency of the target nodes includes at least one of the following: Controlling the clock frequencies of the at least two target nodes to be synchronously increased to their respective corresponding target clock frequencies; The at least two target nodes are controlled to perform frequency up-conversion operations in sequence from downstream to upstream, and each target node is frequency up-converted to a corresponding target clock frequency.

[0010] In a possible implementation, the target node includes the first node, the second node, and the third node connected in sequence, and controlling the clock frequencies of the at least two target nodes to be synchronously increased to the respective corresponding target clock frequencies includes: Synchronously determining a first target clock frequency of the first node and a second target clock frequency of the second node so that the first target clock frequency and the second target clock frequency conform to the relationship between the clock frequencies of the first node and the second node; If the second target clock frequency is higher than the original clock frequency of the third node, determining a third target clock frequency of the third node, wherein the third target clock frequency makes the data reception amount of the third node greater than the data output amount of the second node; The clock frequencies of the first node, the second node and the third node are controlled to be synchronously increased to their respective corresponding target clock frequencies.

[0011] A second aspect of the present application provides a verification method, which uses any of the above-mentioned clock signal control methods to control the clock frequency.

[0012] A third aspect of the present application provides a clock signal control device, comprising: An original frequency acquisition module, used to obtain the original clock frequency of each node on the data communication path, wherein the node is an object with an independent clock signal, and the node includes an internal node of the device and an external node connected to the device; a target frequency determination module, configured to determine a target matching frequency based on the original clock frequency of each node on the communication path when the difference between the original clock frequency of the peripheral node and the maximum original clock frequency of the internal nodes of the device meets a set condition, wherein the target matching frequency includes the target clock frequency of each node, and at least one of the nodes has a target clock frequency greater than its original clock frequency; A target node determination module is used to determine the node that needs to perform clock frequency increase as the target node based on the original clock frequency and the target clock frequency of each node; The frequency adjustment control module is used to control the clock frequency of the target node to increase to the target clock frequency of the target node, so as to improve the data transmission rate of the entire data communication path. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0014] Figure 1 A flowchart of a clock signal control method disclosed in an embodiment of the present application; Figure 2 A flowchart of determining a target collocation frequency disclosed in an embodiment of the present application; Figure 3 A flowchart of controlling the frequency of a target node to be increased disclosed in an embodiment of the present application; Figure 4 A schematic diagram of the structure of a clock signal control device disclosed in an embodiment of the present application. DETAILED DESCRIPTION

[0015] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0016] The embodiments of the present application can be applied to electronic devices. The present application does not limit the product form of the electronic device, which can include but is not limited to smart phones, tablet computers, wearable devices, personal computers (PCs), netbooks, etc., and can be selected according to application requirements.

[0017] Figure 1 This is a flowchart of a clock signal control method disclosed in an embodiment of the present application. Figure 1 The solution shown is used to solve the problem that the clock frequency of the low-speed peripheral interface is significantly different from the highest system-level clock frequency in the connected device, affecting the overall communication efficiency. Figure 1 As shown, the clock signal control method may include: Step 101: obtaining the original clock frequency of each node on the data communication path, wherein the node is an object having an independent clock signal, and the node includes an internal node of the device and a peripheral node connected to the device.

[0018] The data communication path is a communication path including peripherals and nodes inside the device, and the nodes in the data communication path may include, but are not limited to, a connection interface between a low-speed peripheral and the device, a data sampling interface of a processor inside the device, a processor, etc. The connection interface between the low-speed peripheral and the device may be, for example, a JTAG interface, a PDM interface, an I2S interface, etc.

[0019] Generally speaking, the clock frequency of the peripheral interface is low, resulting in a relatively slow data transmission rate. In this way, even if the clock frequency of other nodes inside the device is very high, the data transmission rate of the overall data communication path will be limited by the data transmission rate of the low-speed peripheral interface. In order to improve the overall data transmission rate of the data transmission path, you can try to increase the clock frequency of the node with the lowest and relatively low clock frequency in the data communication path, so that the clock frequency of all nodes in the data communication path is more balanced, thereby improving the overall data transmission rate of the data communication path.

[0020] In the embodiment of the present application, the original clock frequency of each node on the data communication path needs to be obtained first, and then the original clock frequency of each node can be used as the basis to determine which nodes need to increase their clock frequency based on certain rules. The original clock frequency is the default clock frequency of the node without any subsequent configuration, such as the clock frequency of the node when the electronic device is powered on.

[0021] Step 102: If the difference between the original clock frequency of the peripheral node and the maximum original clock frequency of the internal nodes of the device meets the set condition, determine the target matching frequency based on the original clock frequency of each node on the communication path.

[0022] The target matching frequency includes the target clock frequency of each node, and at least one of the nodes has a target clock frequency greater than its original clock frequency. That is, among the target matching frequencies, if the target clock frequency of some nodes is the same as its original clock frequency, then the node does not need to perform clock frequency up-conversion; if the target clock frequency of some nodes is greater than its original clock frequency, then the node needs to perform frequency up-conversion. The overall principle for determining the target matching frequency is to up-convert the low clock frequency to a high clock frequency, so as to improve the data transmission rate of the entire data communication path as a whole.

[0023] The difference between the original clock frequency of the peripheral node and the maximum original clock frequency in the internal node of the device meets the set conditions, such as the maximum original clock frequency in the internal node of the device is more than 5 times the original clock frequency of the peripheral node, or the order of magnitude of the difference between the maximum original clock frequency in the internal node of the device and the original clock frequency of the peripheral node is greater than the order of magnitude of the original clock frequency of the peripheral node, then it is determined that the set conditions are met.

[0024] It is understandable that if the clock frequencies of the nodes in the data communication path are not much different, such as the electronic device is connected to a high-speed peripheral, the data transmission rate of the connection port is close to the data transmission rate and data processing rate of each node inside the device, then the data "flow" speed of the entire data communication path is balanced, and there is no situation where the data transmission speed of a few nodes is low and affects the overall data transmission rate. There is no need to up-convert the nodes in the data communication path, and thus there is no need to determine the target matching frequency. In this application, the setting conditions are used as the basis for determining whether to determine the target matching frequency. The setting conditions define that the difference between the original clock frequency of the peripheral node and the maximum original clock frequency on the data communication path needs to be large enough, and then determine that the node with a low original clock frequency needs to be up-converted, so as to determine the target matching frequency and control the up-converting of the corresponding node, so as to ensure that the data transmission rate of the entire data communication path is significantly improved after the up-converting process.

[0025] The determination of the target frequency of each node in the target matching frequency needs to consider the upstream and downstream connection relationship of each node in the data communication path, and also needs to consider the data sampling principle and synchronization method between adjacent nodes, so as to increase the clock frequency of the node as much as possible while ensuring that each node in the data communication path will not cause data overflow after the node frequency is increased. The specific method for determining the target frequency of each node will be described in detail in the embodiments below, and will not be described in detail here.

[0026] Step 103: Based on the original clock frequency and the target clock frequency of each node, determine the node that needs to perform clock frequency increase as the target node.

[0027] After determining the target matching frequency, the target clock frequency of each node can be compared with the original clock frequency to determine which nodes in the data communication path need to be frequency-upgraded, and the nodes that need to be frequency-upgraded are the target nodes.

[0028] Step 104: Control the clock frequency of the target node to increase the clock frequency to the target clock frequency of the target node, so as to increase the data transmission rate of the entire data communication path.

[0029] There are different implementations for controlling the clock frequency increase of the target node. For example, the nodes that need to be increased in frequency can be controlled to synchronously complete the clock frequency increase, or the target nodes can be controlled to increase the clock frequency in sequence according to a certain order. The present application does not impose any fixed restrictions on this.

[0030] After the clock frequencies of all target nodes are upgraded, the data transmission rates of the nodes in the data communication path that originally lowered the data transmission rate are increased to a certain extent, thereby improving the data transmission rate of the data transmission path as a whole.

[0031] The clock signal control method described in this embodiment determines the target node that can be frequency-upgraded through the original clock frequency of each node in the data communication path, and performs frequency-upgrading processing on the clock signal of the target node, thereby improving the data transmission capacity of the node that originally lowers the data transmission rate of the entire data communication path, thereby improving the data transmission rate of the data communication path.

[0032] Figure 2 This is a flow chart of determining the target collocation frequency disclosed in the embodiment of the present application. Figure 2 As shown, in the above embodiment, determining the target matching frequency based on the original clock frequency of each node on the communication path may include: Step 201: Determine the first node with the lowest original clock frequency.

[0033] On the data communication path, the clock frequencies of different nodes may be the same or different. In this application, it is first necessary to determine the first node with the lowest original clock frequency in the data communication path. It is understandable that in the application scenario where a low-speed peripheral is connected to an electronic device, since the clock frequencies of the nodes inside the electronic device often do not differ too much, the first node with the lowest original clock frequency is usually the interface connecting the low-speed peripheral to the electronic device, such as the JTAG interface.

[0034] Since the data transmission rate of the entire data communication path is limited by the node with the lowest data transmission rate, in the embodiment of the present application, it is necessary to first find the first node with the lowest original clock frequency and control it to perform frequency up-conversion processing.

[0035] Step 202: Determine the data synchronization type between the first node and a second node connected thereto.

[0036] Since the data transmission rate of the first node will increase after the frequency is upgraded, it is necessary to ensure that the second node downstream also has sufficient data receiving capabilities. If the second node can still fully receive the data output by the first node after the frequency is upgraded, the clock frequency of the second node can remain unchanged; if the second node is no longer able to fully receive the data output by the first node after the frequency is upgraded, in order to enable the second node to fully receive the data output by the first node, the clock frequency of the second node also needs to be upgraded following the upstream node to prevent the data output by the first node from overflowing and being lost. The same is true for other nodes. If the downstream node on the data communication path does not have sufficient capacity to receive the data output by the node after the frequency is upgraded, the downstream node also needs to follow the frequency upgrade process.

[0037] Those skilled in the art will know that when the data synchronization type between two nodes is different, the relationship that the clock frequencies of the two nodes need to satisfy is also different. The data synchronization type between nodes is determined when the chip in the device is designed. Therefore, when the data synchronization type is determined, the relationship that the clock frequencies of the two nodes that need to perform data synchronization need to satisfy is also determined.

[0038] Step 203: Determine a relationship between clock frequencies of the first node and the second node based on the data synchronization type.

[0039] In one implementation, if the data synchronization type is a first type, it is determined that a ratio of a target clock frequency of the second node to a target clock frequency of the first node is at least 2, and the first type represents a synchronization mode without data buffering.

[0040] The first type may be data synchronization in a beat mode, which may be performed in two beats, three beats or other numbers of beats. Since there is no buffer space for transmitting data during data synchronization in a beat mode, in order to ensure that the data output from the first node to the second node does not overflow, the ratio of the target clock frequency of the second node to the target clock frequency of the first node is required to be at least 2.

[0041] In another implementation, if the data synchronization type is a second type, it is determined that a ratio of a target clock frequency of the second node to a target clock frequency of the first node is greater than 1, and the second type is a synchronization mode with data buffering.

[0042] The second type may be fifo data synchronization. Since there is a data buffer storage space in the fifo data synchronization mode, the target clock frequency of the second node theoretically only needs to be not less than the target clock frequency of the first node. Even if the data of the first node suddenly increases in a certain period of time, under the effect of the data buffer space, it will not cause the overflow of the output data of the first node.

[0043] The above content introduces the specific implementation of determining the target matching frequency, which is convenient for technical personnel in the field to better understand and implement the technical solution of this application.

[0044] Based on the content of the aforementioned embodiment, the clock signal control method may further include: determining whether there is serial-to-parallel conversion between the first node and the second node. If so, determining the relationship between the clock frequencies of the first node and the second node based on the data synchronization type may include: determining the multiple relationship between the first node and the second node based on the data bit width converted to parallel data and the data synchronization type.

[0045] For example, the first node outputs serial data to the second node. If the clock frequency of the serial bit stream is 3200Mhz, the second node performs serial-to-parallel conversion at 32bit, and the first node and the second node are synchronized by fifo, then the clock frequency of the second node is theoretically not less than 3200÷32=100Mhz. If the first node and the second node are synchronized by beat, then the clock frequency of the second node is theoretically not less than 3200÷32×2=200Mhz.

[0046] In order to more clearly understand the relationship between the target clock frequencies of each node, the following content is introduced. Assume that the input and output frequency of the serial bit stream is xMHz, the sampling frequency of the upstream and downstream is yMHz, the upstream and downstream operating frequency is zMHz, and the highest operating frequency of other nodes in the device is hMHz. Check the upstream and downstream sampling frequencies for the sampling and driving of the serial bits. If the synchronization is done by fifo or other methods, you don’t need to worry about whether x will be greater than y / 2 after the increase (that is, it does not need to meet the requirement of the beat synchronization method that the clock frequency ratio of the downstream node to the upstream node is at least 2), resulting in failure to sample. If the upstream and downstream nodes are 32bit for serial-to-parallel conversion, then x can be increased to (32 / 2)*yMHz, or even higher, and theoretically no more than 32yMHz.

[0047] In an example, under the original clock frequency, x=100Mhz, y=200 Mhz, z=500MHz, h=3000MHz, in order to improve the overall data transmission rate of the data communication path, x needs to be increased. According to the Nyquist sampling principle, if x is increased, y must also be increased, otherwise data loss will occur. The increase in the clock frequency y of the downstream sampling module also requires the clock frequency z of the downstream node of the sampling module to be increased. How much x is increased can be estimated according to the values ​​of the frequencies of x / y / z / h. For example, the frequency of x / y can be increased as a whole. When the frequency of x / y increases more than z, z is increased at the same time.

[0048] In practical applications, when x increases to a certain value, the overall data transmission rate of the data communication path may have been saturated, and further increasing x will not significantly increase the data transmission rate. Therefore, it is sufficient to ultimately make the clock frequencies of each node in the data communication path at the same level.

[0049] In practical applications, when determining the target clock frequency of each node in the data communication path, the target clock frequency of each node can be determined according to the set logic or the experience of relevant staff. In order to avoid the situation where the target clock frequency of the node is raised too high at one time, which may cause data overflow and abnormal failure of related functions, and in order to avoid increasing the target clock frequency of the node by an amount exceeding the amount required for the saturation state of the data transmission rate of the data communication path, the process of determining the target clock frequency can be performed several times, that is, the clock frequency of the node can be controlled to be increased one by one. In the process of gradually increasing the target clock frequency, if it is found that the overall data transmission rate of the data transmission path has not been significantly improved after a certain frequency increase, it can be considered that the overall data transmission rate of the data communication path may have been saturated, and even if the clock frequency of the node is increased, it will not bring obvious positive effects, so the frequency increase control of the node can be stopped.

[0050] It should be noted that the target clock frequency of each node on the data communication path is not higher than the highest operating frequency of each node in the device, such as the aforementioned x, y and z cannot be greater than h. That is, the processing logic of the present application scheme is to increase the data transmission capacity of the node with a low data transmission rate in the data communication path so that its clock frequency is close to a higher clock frequency, rather than increasing the clock frequency of the originally high clock frequency without limit.

[0051] If there is no serial-to-parallel conversion on the data communication path, that is, the data communication path is a serial data path, then in the target matching frequency, in the data upstream direction, that is, the direction in which the low-speed peripheral transmits data to the inside of the device, the clock frequency of the downstream node shall not be lower than the clock frequency of the upstream node, so as to ensure that the data transmitted by the upstream node does not overflow.

[0052] In one implementation of the aforementioned embodiment, the target nodes include at least two, and controlling the clock frequency of the target nodes to upgrade to the target clock frequency of the target nodes includes: controlling the clock frequencies of the at least two target nodes to be synchronously upgraded to their respective corresponding target clock frequencies; or controlling the at least two target nodes to perform frequency upgrading operations in sequence from downstream to upstream, and each target node is upgraded to its respective corresponding target clock frequency.

[0053] The target node may include the first node, the second node and the third node connected in sequence. The process of controlling the target node to perform frequency up-conversion can be referred to in Figure 3 . Combined Figure 3 As shown, controlling the clock frequencies of the at least two target nodes to be synchronously increased to their respective corresponding target clock frequencies may include: Step 301: Synchronously determine a first target clock frequency of the first node and a second target clock frequency of the second node, so that the first target clock frequency and the second target clock frequency conform to the relationship between the clock frequencies of the first node and the second node.

[0054] Step 302: If the second target clock frequency is higher than the original clock frequency of the third node, determine a third target clock frequency of the third node, wherein the third target clock frequency makes the data reception amount of the third node greater than the data output amount of the second node.

[0055] If the second target clock frequency is lower than or equal to the original clock frequency of the third node, it indicates that the data receiving capability of the third node can cover the data output capability of the second node, that is, the third node can completely receive the data output by the second node without causing data overflow and loss. Therefore, there is no need to increase the clock frequency of the third node, that is, there is no need to determine the third target clock frequency of the third node.

[0056] Step 303: Control the clock frequencies of the first node, the second node, and the third node to be synchronously increased to their corresponding target clock frequencies.

[0057] The frequency is increased from downstream to upstream to ensure that the downstream node can receive more data. If the upstream node is increased first, the downstream node may not have sufficient data receiving capacity, resulting in data overflow and loss.

[0058] The clock signal control scheme disclosed in the above-mentioned multiple embodiments of the present application can be applied to verification, including but not limited to IT (Integration Testing) verification, ST (System Testing) verification, SV (SystemVerilog) verification, etc. Referring to the contents of the above-mentioned embodiments, the clock signal control method can improve the data transmission rate of the overall data communication path, so applying it in the verification field that requires a large amount of data transmission can effectively improve the simulation verification efficiency.

[0059] For example, when Coresight (CoreSight is a comprehensive debugging and tracing system) needs to be connected to an external host computer through JTAG, if the original clock frequency of JTAG is 50MHz, and a processing node of the host computer may run at 3GHz, there is a 60-fold difference. At this time, trace (in the simulation field, trace usually refers to recording and tracking the behavior and state of the system or model during the simulation process) will take a lot of time, generally around 4ms. If you do discovery (scan) and other related simulations at this time, the time required may even reach 40ms, which will cause the verification speed to be very slow, and the waveform is also very large, and the demand for processing resources and hard disk storage resources is very large. If you follow the traditional method without any clock signal control, the entire simulation process may take dozens of hours or even days. The clock signal control scheme provided by this application can effectively improve the overall data transmission rate and increase the overall simulation speed by several times.

[0060] Based on the above, the present application further discloses a verification method, which uses any of the clock signal control methods in the aforementioned embodiments to control the clock frequency.

[0061] It should be noted that when the clock signal control scheme of the present application is applied in the verification implementation, when the simulation server resources and / or simulation time are limited, the aforementioned clock signal control scheme can be used in the early simulation and NLP simulation stages of the entire verification cycle. In the later simulation, since there are some tasks involving timing delays such as adjusting the netlist, it is necessary to use a standard clock, that is, the original clock frequency, for simulation verification; however, in the later simulation, in the debugging stage when there is no SDF (timing design file), the clock signal control scheme described in the present application can also be used.

[0062] Based on the above, in the regression verification phase of simulation verification, the original clock frequency of each node can be used to verify the accuracy of the simulation results of the simulation using the target matching frequency. Each time a version regression verification is performed, several instance cases that need to be simulated can be selected using the target matching frequency for regression simulation, and then other instance cases can be simulated using the standard clock frequency (original clock frequency) after the server is relieved of pressure, so as to reasonably use the acceleration solution to help verify the acceleration and completeness and authenticity.

[0063] In addition, in SV verification, different instance cases can use different clock frequencies, that is, in order to speed up the simulation efficiency, the target clock frequencies in the target matching frequency can be used; in order to ensure the authenticity of the simulation results, the original clock frequency can be used for simulation.

[0064] In combination with the above, the application of the clock signal control scheme in chip verification has the following advantages: Simulation with large data volume can also realize EDA (Electronics Design Automation) simulation; In the early debugging stage of chip verification, reducing case simulation time and server time can quickly complete the execution of related testing work, thereby speeding up case development and debugging and bug discovery; When each version is regressed, it can be regressed quickly without blocking other work tasks or occupying work resources for a long time; Reduce the use of hard disks. Reducing fsdb (Fast Signal Database, in the simulation field, is a file format used to store signal waveform information generated during the simulation process) and logs can free up hard disk resources. It is suitable for integration and system-level verification of various products with large frequency differences. It also has a certain effect on tranning (training) in high-speed interfaces, which can reduce tranning and ensure delivery of each link.

[0065] In addition, it should be noted that for some special projects, such as natural language processing applications, since their back-end simulation requires the use of a sign-off frequency, during the back-end simulation process, in the debugging phase when there is no SDF (timing design file), the target matching frequency determined by the present application solution can be used. When there is an SDF, the standard clock frequency needs to be used.

[0066] For the aforementioned method embodiments, for the sake of simplicity, they are all described as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the order of the actions described, because according to the present application, some steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0067] The method is described in detail in the embodiments disclosed in the above-mentioned application. The method of the application can be implemented by various forms of devices. Therefore, the application also discloses a device, and a specific embodiment is given below for detailed description.

[0068] Figure 4 Schematic diagram of the structure of a clock signal control device disclosed in an embodiment of the present application. Figure 4 As shown, the control device of the clock signal may include: The original frequency acquisition module 401 is used to obtain the original clock frequency of each node on the data communication path, wherein the node is an object with an independent clock signal, and the node includes an internal node of the device and an external node connected to the device.

[0069] The target frequency determination module 402 is used to determine the target matching frequency based on the original clock frequency of each node on the communication path when the difference between the original clock frequency of the peripheral node and the maximum original clock frequency in the internal nodes of the device meets the set conditions. The target matching frequency includes the target clock frequency of each node, and at least one node among each node has a target clock frequency greater than its original clock frequency.

[0070] The target node determination module 403 is used to determine the node that needs to perform clock frequency increase as the target node based on the original clock frequency of each node and the target clock frequency.

[0071] The frequency adjustment control module 404 is used to control the clock frequency of the target node to be increased to the target clock frequency of the target node, so as to improve the data transmission rate of the entire data communication path.

[0072] The control device for the clock signal described in this embodiment determines the target node that can be frequency-upgraded through the original clock frequency of each node in the data communication path, and performs frequency-upgrading processing on the clock signal of the target node, thereby improving the data transmission capacity of the node that originally lowers the data transmission rate of the entire data communication path, thereby improving the data transmission rate of the data communication path.

[0073] The clock signal control device can be used as a verification device for IT verification, ST verification, SV verification, etc. Since the clock signal control device can increase the data transmission rate of the overall data communication path, it is applied in the verification field where a large amount of data transmission is required, which can effectively improve the simulation verification efficiency. The specific implementation and application effect can be referred to the content introduction of the corresponding part in the method embodiment.

[0074] In one implementation, the target frequency determination module may include: a first determination module, used to determine the first node with the lowest original clock frequency; a synchronization type determination module, used to determine the data synchronization type between the first node and the second node connected thereto; and a relationship determination module, used to determine the relationship between the clock frequencies between the first node and the second node based on the data synchronization type.

[0075] In one implementation, the relationship determination module can be specifically used for at least one of the following: if the data synchronization type is a first type, determining that the ratio of the target clock frequency of the second node to the target clock frequency of the first node is at least 2, and the first type represents a synchronization method without data buffering; if the data synchronization type is a second type, determining that the ratio of the target clock frequency of the second node to the target clock frequency of the first node is greater than 1, and the second type is a synchronization method with data buffering.

[0076] In one implementation, the control device for the clock signal may also include: a serial-to-parallel conversion determination module for determining whether there is a serial-to-parallel conversion between the first node and the second node; and a relationship determination module for determining the multiple relationship between the first node and the second node based on the data bit width converted to parallel data and the data synchronization type.

[0077] In one implementation, the target clock frequency of each node on the data communication path is not higher than the highest operating frequency of each node in the device.

[0078] In one implementation, if the data communication path is a serial data path, in the target matching frequency, in the data upstream direction, the clock frequency of the downstream node is not lower than the clock frequency of the upstream node.

[0079] In one implementation, the target node includes at least two, and the frequency adjustment control module is used for at least one of the following: controlling the clock frequencies of the at least two target nodes to be synchronously upgraded to their respective corresponding target clock frequencies; controlling the at least two target nodes to perform frequency upgrade operations in sequence from downstream to upstream, and each target node is upgraded to its respective corresponding target clock frequency.

[0080] In one implementation, the target node includes the first node, the second node and the third node connected in sequence, and the frequency adjustment control module can be specifically used to: synchronously determine the first target clock frequency of the first node and the second target clock frequency of the second node, so that the first target clock frequency and the second target clock frequency conform to the relationship between the clock frequencies of the first node and the second node; if the second target clock frequency is higher than the original clock frequency of the third node, determine the third target clock frequency of the third node, and the third target clock frequency makes the data reception amount of the third node greater than the data output amount of the second node; control the clock frequencies of the first node, the second node and the third node to be synchronously upgraded to their respective corresponding target clock frequencies.

[0081] The specific implementation of the above-mentioned clock signal control device and each module included therein can be found in the corresponding part of the method embodiment, but the content is introduced and will not be repeated here.

[0082] The control device for any one of the clock signals described in the above embodiments includes a processor and a memory. The original frequency acquisition module, target frequency determination module, target node determination module, frequency adjustment control module, etc. in the above embodiments are all stored in the memory as program modules, and the processor executes the above program modules stored in the memory to realize corresponding functions.

[0083] The processor includes a kernel, which retrieves the corresponding program module from the memory. One or more kernels can be set, and the processing of the access data can be realized by adjusting the kernel parameters.

[0084] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM, and the memory includes at least one memory chip.

[0085] In an exemplary embodiment, a computer-readable storage medium is also provided, which can be directly loaded into the internal memory of a computer and contains software code. After being loaded and executed by a computer, the computer program can implement the steps shown in any embodiment of the above-mentioned clock signal control method.

[0086] In an exemplary embodiment, a computer program product is also provided, which can be directly loaded into the internal memory of a computer and contains software codes. After being loaded and executed by a computer, the computer program can implement the steps shown in any embodiment of the clock signal control method described above.

[0087] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0088] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0089] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0090] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for controlling a clock signal, the method comprising: Obtaining the original clock frequency of each node on the data communication path, wherein the node is an object having an independent clock signal, and the node includes an internal node of the device and an external node connected to the device; If the difference between the original clock frequency of the peripheral node and the maximum original clock frequency of the internal nodes of the device meets the set condition, a target matching frequency is determined based on the original clock frequency of each node on the communication path, wherein the target matching frequency includes the target clock frequency of each node, and at least one of the nodes has a target clock frequency greater than its original clock frequency; Based on the original clock frequency and the target clock frequency of each node, a node that needs to perform clock frequency increase is determined as a target node; The clock frequency of the target node is controlled to be increased to the target clock frequency of the target node, so as to increase the data transmission rate of the entire data communication path.

2. The clock signal control method according to claim 1, wherein the step of determining the target matching frequency based on the original clock frequency of each node on the communication path comprises: Determine a first node having the lowest original clock frequency; Determining a data synchronization type between the first node and a second node connected thereto; A relationship of clock frequencies between the first node and the second node is determined based on the data synchronization type.

3. The clock signal control method according to claim 2, wherein the determining the relationship between the clock frequencies of the first node and the second node based on the data synchronization type comprises at least one of the following: If the data synchronization type is a first type, determining that a ratio of a target clock frequency of the second node to a target clock frequency of the first node is at least 2, the first type representing a synchronization mode without data buffering; If the data synchronization type is the second type, it is determined that the ratio of the target clock frequency of the second node to the target clock frequency of the first node is greater than 1, and the second type is a synchronization mode with data buffering.

4. The clock signal control method according to claim 2, further comprising: Determine whether there is a serial-to-parallel conversion between the first node and the second node; If so, determining a relationship between clock frequencies of the first node and the second node based on the data synchronization type includes: The multiple relationship between the first node and the second node is determined based on the data bit width converted into parallel data and the data synchronization type.

5. The clock signal control method according to claim 1, wherein: The target clock frequency of each node on the data communication path is not higher than the highest operating frequency of each node in the device. 6 . The clock signal control method according to claim 1 , wherein if the data communication path is a serial data path, in the target matching frequency, in the data upstream direction, the clock frequency of the downstream node is not lower than the clock frequency of the upstream node.

7. The clock signal control method according to claim 2, wherein the target nodes include at least two, and the step of controlling the clock frequency of the target node to increase the clock frequency to the target clock frequency of the target node includes at least one of the following: Controlling the clock frequencies of the at least two target nodes to be synchronously increased to their respective corresponding target clock frequencies; The at least two target nodes are controlled to perform frequency up-conversion operations in sequence from downstream to upstream, and each target node is frequency up-converted to a corresponding target clock frequency.

8. The clock signal control method according to claim 7, wherein the target node comprises the first node, the second node and the third node connected in sequence, and the step of controlling the clock frequencies of the at least two target nodes to be synchronously increased to the respective corresponding target clock frequencies comprises: Synchronously determining a first target clock frequency of the first node and a second target clock frequency of the second node so that the first target clock frequency and the second target clock frequency conform to the relationship between the clock frequencies of the first node and the second node; If the second target clock frequency is higher than the original clock frequency of the third node, determining a third target clock frequency of the third node, wherein the third target clock frequency makes the data reception amount of the third node greater than the data output amount of the second node; The clock frequencies of the first node, the second node and the third node are controlled to be synchronously increased to their respective corresponding target clock frequencies.

9. A verification method, wherein the verification method adopts the clock signal control method described in any one of claims 1 to 8 to control the clock frequency.

10. A clock signal control device, comprising: An original frequency acquisition module, used to obtain the original clock frequency of each node on the data communication path, wherein the node is an object with an independent clock signal, and the node includes an internal node of the device and an external node connected to the device; a target frequency determination module, configured to determine a target matching frequency based on the original clock frequency of each node on the communication path when the difference between the original clock frequency of the peripheral node and the maximum original clock frequency of the internal nodes of the device meets a set condition, wherein the target matching frequency includes the target clock frequency of each node, and at least one of the nodes has a target clock frequency greater than its original clock frequency; A target node determination module is used to determine the node that needs to perform clock frequency increase as the target node based on the original clock frequency and the target clock frequency of each node; The frequency adjustment control module is used to control the clock frequency of the target node to increase to the target clock frequency of the target node, so as to improve the data transmission rate of the entire data communication path.

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