Method for providing exposure temperature and storage device

Abstract

The invention provides a method for providing exposure temperature and a storage device. The method of providing an exposure temperature includes: generating reference information indicating a relationship between an exposure condition and a retention value, where the exposure condition includes an exposure temperature and an exposure time of a non-volatile memory device, and the retention value indicates a retention characteristic of the non-volatile memory device; performing a monitoring program operation to write monitoring data into a target memory cell included in the non-volatile memory device before a power-off time point when the non-volatile memory device is powered off; generating a measured hold value by performing a monitored read operation to read data from the target memory cell after a power-on point in time when the non-volatile memory device is powered on; and estimating a measured exposure temperature corresponding to the measured hold value based on the reference information and the measured exposure time between the power-off time point and the power-on time point.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2023-0097269 filed on July 26, 2023 in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Aspects of the present disclosure relate to semiconductor integrated circuits, and in some embodiments, to memory devices and methods of providing an exposure temperature of a nonvolatile memory device in a power-off state. Background Art

[0004] Battery performance and life management are some of the most important issues in products such as autonomous electric vehicles, and battery management systems (BMS) are used to effectively manage these issues.

[0005] Problems with electric vehicle batteries include fire due to excessive heat radiation, reduced ability to hold a charge (overcharging, cycling, aging, etc.), and degradation of battery performance due to degradation caused by hot weather and frequent charging and discharging.

[0006] To address these issues, manufacturers use thermal management systems to keep the battery cool and BMS to optimize the charging and discharging of the battery, providing a way to extend its life. In addition, many electric vehicle manufacturers offer warranties that cover battery performance degradation.

[0007] In these products, heat detection and management are very important issues, and in a power-on state, the operating temperature is detected by a temperature sensor, the temperature information is provided to a necessary system, and control operations are performed using the temperature information. Summary of the invention

[0008] Some embodiments provide a memory device and method for efficiently providing an exposure temperature of a non-volatile memory device in a powered-off state.

[0009] According to some embodiments, a method for providing an exposure temperature of a nonvolatile memory device in a power-off state includes: generating reference information indicating a relationship between an exposure condition and a retention value, wherein the exposure condition includes an exposure temperature and an exposure time of the nonvolatile memory device, and the retention value indicates a retention characteristic of the nonvolatile memory device; before a power-off time point when the nonvolatile memory device is powered off, performing a monitoring programming operation to write monitoring data into a target memory cell included in the nonvolatile memory device; after a power-on time point when the nonvolatile memory device is powered on, generating a measured retention value by performing a monitoring read operation to read data from the target memory cell, and estimating a measured exposure temperature corresponding to the measured retention value based on the reference information and the measured exposure time between the power-off time point and the power-on time point.

[0010] According to some embodiments, a storage device includes: a storage device including a nonvolatile memory device and a storage controller. The nonvolatile memory device is configured to store reference information indicating a relationship between an exposure condition and a retention value, wherein the exposure condition includes an exposure temperature and an exposure time of the nonvolatile memory device, and the retention value indicates a retention characteristic of the nonvolatile memory device. The storage controller is configured to control the nonvolatile memory device: before a power-off time point when the nonvolatile memory device is powered off, a monitoring program operation is performed to write monitoring data into a target memory cell included in the nonvolatile memory device, after a power-on time point when the nonvolatile memory device is powered on, a measured retention value is generated by performing a monitoring read operation to read data from the target memory cell, and a measured exposure temperature corresponding to the measured retention value is estimated based on the reference information and the measured exposure time between the power-off time point and the power-on time point.

[0011] According to some embodiments, a method for providing an exposure temperature of a nonvolatile memory device in a power-off state includes: performing a test programming operation to write monitoring data into a test memory cell included in a test nonvolatile memory device, exposing the test nonvolatile memory device to a test environment corresponding to a test condition including a test temperature and a test time, after exposing the test nonvolatile memory device to the test environment, generating a retention value corresponding to the test condition by performing a test read operation on the test memory cell, generating reference information indicating a relationship between the exposure condition, the retention value, and the exposure temperature, and performing the monitoring programming operation before a power-off time point at which the nonvolatile memory device is powered off. The invention relates to a method for writing monitoring data into target memory cells included in a nonvolatile memory device, generating a measured retention value by performing a monitoring read operation to read data from the target memory cells after a power-on time point at which the nonvolatile memory device is powered on, the measured retention value corresponding to at least one of the number of target memory cells having a threshold voltage higher than a monitoring voltage, the number of target memory cells having a threshold voltage between a first monitoring voltage and a second monitoring voltage, and the number of error bits of data read from the target memory cells, and estimating a measured exposure temperature corresponding to the measured retention value based on reference information and a measured exposure time between a power-off time point and a power-on time point.

[0012] The storage device and the method of providing the exposure temperature according to some embodiments can reduce power consumption and enhance the performance of the battery by providing the exposure information in the power-off state using the retention characteristics of the non-volatile memory device without supplying power to the circuit for temperature monitoring in the power-off state. By using the exposure temperature in the power-off state, products containing temperature-sensitive components can be effectively managed and controlled. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Some embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0014] Figure 1 is a block diagram illustrating a storage system according to some embodiments.

[0015] Figure 2 is a flow chart illustrating a method of providing a temperature exposure of a non-volatile memory device in a powered-off state according to some embodiments.

[0016] Figure 3 is a diagram illustrating a state change of a memory cell in a nonvolatile memory device according to some embodiments.

[0017] Figure 4 It shows instructions Figure 3A diagram of an example of state-bit mapping information showing a mapping relationship between states and bit values ​​in FIG.

[0018] Figure 5 is a block diagram illustrating a storage controller according to some embodiments.

[0019] Figure 6 is a block diagram illustrating a nonvolatile memory device according to some embodiments.

[0020] Figure 7 It is shown that the Figure 6 A block diagram of a memory cell array in a nonvolatile memory device.

[0021] Figure 8 It is shown that the Figure 7 A circuit diagram of the equivalent circuit of a memory block in a memory cell array.

[0022] Fig. 9 is a circuit diagram illustrating erase bias conditions of a nonvolatile memory device according to some embodiments.

[0023] Fig.10 is a circuit diagram illustrating read bias conditions for a nonvolatile memory device according to some embodiments.

[0024] Fig.11 is a circuit diagram illustrating programming bias conditions for a nonvolatile memory device according to some embodiments.

[0025] Fig. 12A and Fig. 12B is a diagram illustrating degradation of retention characteristics according to temperature in a nonvolatile memory device according to some embodiments.

[0026] Fig.13 , Fig.14A and Fig. 14B is a diagram showing changes in a retention value in a nonvolatile memory device in a power-off state according to an exposure temperature and an exposure time.

[0027] Fig.15 , Fig.16 and Fig.17 is a flow chart illustrating some examples of generating a retention value in a method of providing an exposure temperature of a non-volatile memory device in a power-off state according to some implementations.

[0028] Fig.18 is a flow chart illustrating an example of generating reference information in a method of providing an exposure temperature of a nonvolatile memory device in a power-off state according to some embodiments.

[0029] Fig.19is a diagram illustrating an example of reference information in a method of providing an exposure temperature of a nonvolatile memory device in a power-off state according to some embodiments.

[0030] Fig. 20 is a block diagram illustrating a computing device according to some implementations.

[0031] Fig.21 and Fig. 22 is a diagram for describing an example of a deep learning neural network structure driven by a machine learning device according to some embodiments.

[0032] Fig.23 is a diagram illustrating an example of nodes included in a neural network.

[0033] Fig.24 is a diagram illustrating an example of a deep learning model in a method of providing an exposure temperature of a nonvolatile memory device in a power-off state according to some embodiments.

[0034] Fig.25 is a graph showing data in a method of providing an exposure temperature of a nonvolatile memory device in a power-off state according to some embodiments.

[0035] Fig.26 is a diagram illustrating an example structure of a cell string included in a nonvolatile memory device according to some embodiments.

[0036] Fig. 27 is a diagram illustrating an example of a word line group in a nonvolatile memory device according to some embodiments.

[0037] Figures 28 to 30B is a diagram illustrating some examples of monitoring a programming operation in a method of providing an exposure temperature of a nonvolatile memory device in a power-off state according to some embodiments.

[0038] Fig.31 is a block diagram illustrating an autonomous driving device including a non-volatile memory device according to some embodiments. DETAILED DESCRIPTION

[0039] Various embodiments will be described more fully below with reference to the accompanying drawings, in which some embodiments are shown. In the accompanying drawings, the same reference numerals represent the same elements throughout. Repeated descriptions may be omitted.

[0040] For purposes of this disclosure, it has been recognized that temperature information in a powered-off state (as opposed to a powered-on state only) can be useful in order to accurately predict and manage battery remaining capacity, performance, and life. The systems and processes described herein facilitate determining temperature in a powered-off state.

[0041] Figure 1 is a block diagram illustrating a storage system according to some embodiments, and Figure 2 is a flow chart illustrating a method of providing an exposure temperature of a nonvolatile memory device in a powered-off state (eg, a temperature to which the nonvolatile memory device has been exposed while powered-off) according to some embodiments.

[0042] Reference Figure 1 , the storage system 1000 includes a host device 1100, a storage device 1200, and a link 30 connecting the host device 1100 and the storage device 1200. The storage device 1200 may include a storage controller 100 and a non-volatile memory device 400. For example, the storage device 1200 may be a solid state drive (SSD), an embedded multimedia card (eMMC), or a universal flash memory (UFS) device. In some embodiments, the link 30 may be a PCIe link. According to some embodiments, the storage device 1200 may also include a temperature sensor (TS), a timer (TM), and the like. The temperature sensor TS may provide an operating temperature in a power-on state and may be disabled in a power-off state to save power consumption. The timer TM may provide time information (e.g., a timestamp) corresponding to a power-off time point and a power-on time point to calculate an exposure time, as will be described below.

[0043] The host device 1100 may be a data processing device capable of processing data, such as a central processing unit (CPU), a processor, a microprocessor, an application processor, etc. The storage device 1200 may be embedded in an electronic device together with the host device 1100, and may be electrically connected to the electronic device including the host device 1100 in a detachable manner.

[0044] The host device 1100 may send a data operation request REQ (i.e., request) and a logical address LADD to the memory controller 100, and may exchange data DTA with the memory controller 100. The memory controller 100 may send a response RSND in response to the data operation request REQ to the host device 1100. The data operation request REQ may include a data read request, a data write request, and a data erase request.

[0045] The storage controller 100 may control the nonvolatile memory device 400 in response to a request REQ from the host device 1100. Read and write operations may be performed on the nonvolatile memory device 400 by providing a physical address PADD mapped to a logical address LADD, a command CMD, and a control signal CTRL to the nonvolatile memory device 400. The write operation may be referred to as a programming operation. For example, the storage controller 100 may perform a flash translation layer FTL operation to convert the logical address LADD sent from the host device 1100 into a physical address PADD.

[0046] The storage controller 100 may control the nonvolatile memory device 400 to read the data DTA stored in the nonvolatile memory device 400 in response to a read request received from the host device 1100. The storage controller 100 may control the nonvolatile memory device 400 to write or program the data DTA into the nonvolatile memory device 400 in response to a write request or a program request received from the host device 1100. The storage controller 100 may control the nonvolatile memory device 400 to erase the data stored in the nonvolatile memory device 400 in response to an erase request received from the host device 1100. The nonvolatile memory device 400 may send a response RSND to the storage controller 100 in response to the command CMD.

[0047] The nonvolatile memory device 400 may be implemented with a nonvolatile memory such as a flash memory, MRAM (magnetic RAM), FeRAM (ferroelectric RAM), PRAM (phase change RAM), ReRAM (resistive RAM), etc. The nonvolatile memory device 400 may be connected to the memory controller 100 through a plurality of channels. Hereinafter, some embodiments will be described based on NAND flash memory, but the embodiments are not limited to any particular type of nonvolatile memory.

[0048] The storage controller 100 may include a metadata manager MDTMG that monitors metadata errors. Metadata is distinguished from user data stored in the nonvolatile memory device 400 at the request of the host device 1100, and the metadata is generated and managed by the firmware of the storage controller 100 to manage user data or the nonvolatile memory device 400. The metadata may include a mapping table indicating a mapping relationship between a logical address of the host device 1100 and a physical address of the nonvolatile memory device 400, and may include other information such as bad blocks, program-erase cycles, and valid page count values ​​for managing a memory space of the nonvolatile memory device 400.

[0049] When the storage system 1000 is powered on, metadata may be loaded from the nonvolatile memory device 400 and stored in a memory (e.g., a volatile memory such as a DRAM or SRAM) of the storage controller 100. The metadata stored in the nonvolatile memory device 400 may be referred to as nonvolatile metadata NVMDT, and the metadata stored in the storage controller 100 may be referred to as firmware metadata FMDT. The firmware metadata FMDT may change during the operation of the storage device 1200, and a log technique may be used to maintain consistency of the firmware metadata FMDT and the nonvolatile metadata NVMDT.

[0050] During the power-on process of the storage device 1200, the metadata manager MDTMG may generate the firmware metadata FMDT based on the nonvolatile metadata NVMDT stored in the nonvolatile memory device 400. Alternatively, during the power-off process, the metadata manager MDTMG may perform a metadata backup operation to store the firmware metadata FMDT of the volatile memory device to the nonvolatile memory device 400.

[0051] In addition, the storage controller 100 may include an exposure temperature monitor ETM that provides an exposure temperature of the non-volatile memory device 400 in a power-off state. In some embodiments, the storage controller 100 may also include a satellite management controller SMC that performs communication with peripheral devices. The exposure temperature monitor ETM may provide an estimated exposure temperature to a peripheral device such as a battery management system BMS using the satellite management controller SMC. In addition, the exposure temperature monitor ETM may provide an estimated exposure temperature or a measured exposure temperature to the host device 1100 via the link 30.

[0052] Reference Figure 1 and Figure 2 , reference information RFI indicating the relationship between exposure conditions and retention values ​​can be generated, wherein the exposure conditions include the exposure temperature and exposure time of the nonvolatile memory device 400, and the retention value represents the retention characteristics of the nonvolatile memory device 400 (S100). Nonvolatile memory devices manufactured in the same manufacturing process can be considered to have the same characteristics. Therefore, the reference information RFI can be generated during testing before and / or after the nonvolatile memory device is integrated into the memory device. The generated reference information RFI can be stored in each nonvolatile memory device and used to estimate the exposure temperature in the power-off state. The following will refer to Figures 18 to 25 Some implementations of generating reference information RFI are described.

[0053] Before the power-off time point when the nonvolatile memory device 400 is powered off, the exposure temperature monitor ETM may perform a monitoring programming operation to write monitoring data into a target memory cell included in the nonvolatile memory device 400 (S200). The monitoring data may have an appropriate data pattern to facilitate degradation of retention characteristics according to the exposure temperature. Figures 28 to 30B Some implementations of monitoring data are described.

[0054] After the power-on time point when the nonvolatile memory device 400 is powered on, the exposure temperature monitor ETM may generate a measured retention value by performing a monitoring read operation to read data from a target memory cell (S300). The measured retention value may be set to an appropriate value that may reflect the degradation of the retention characteristic according to the exposure temperature, and the operating condition of the monitoring read operation may be determined to correspond to the set measured retention value. FIG. 12A to FIG. 17 Some embodiments of measured hold values ​​are described.

[0055] Based on the reference information RFI, the exposure temperature monitor ETM can estimate the measured exposure temperature corresponding to the measured retention value and the measured exposure time between the power-off time point and the power-on time point (S400). Semiconductor products produced during mass production have substantially the same characteristics. Therefore, even if the reference information RFI is generated using a test nonvolatile memory device different from the nonvolatile memory device 400, an exposure temperature very close to the actual exposure temperature can be estimated using the reference information RFI. According to some embodiments, before the reference information RFI is provided to the memory device 1200, the reference information RFI can be calibrated to reflect the operational deviation of each nonvolatile memory device.

[0056] Thus, the method of providing exposure temperature and the storage device 1200 according to some embodiments can reduce power consumption and enhance the performance of the battery by providing exposure information in a power-off state using the retention characteristics of a non-volatile memory device, without supplying power to a circuit for temperature monitoring in a power-off state. By using the exposure temperature in a power-off state, products containing temperature-sensitive components can be effectively managed and controlled.

[0057] In the following, reference will be made to Figures 3 to 11 A NAND flash memory device used in a method of providing an exposure temperature of a nonvolatile memory device in a power-off state according to some embodiments is described. Some embodiments are not limited to NAND flash memory devices and may be applied to any nonvolatile memory device that retains stored data even in a power-off state and in which data retention characteristics deteriorate differently according to exposure temperature.

[0058] Figure 3is a diagram illustrating a state change of a memory cell in a nonvolatile memory device according to some embodiments.

[0059] exist Figure 3 , the horizontal axis represents the threshold voltage VTH of the memory cell, and the vertical axis represents the number of memory cells corresponding to the threshold voltage VTH. Figure 3 A triple-level cell (TLC) scheme is shown in which each memory cell stores a 3-bit value, but some embodiments are not limited thereto and the number of bits stored in each selected memory cell may be determined differently. In other words, the method of providing an exposure temperature according to some embodiments may be performed using a nonvolatile memory device that not only uses Figure 3 In addition to the TLC scheme shown in , a single-level cell (SLC) scheme in which each memory cell stores a 1-bit value, a multi-level cell (MLC) scheme in which each memory cell stores a 2-bit value, a quad-level cell (QLC) scheme in which each memory cell stores a 4-bit value, a penta-level cell (PLC) scheme in which each memory cell stores a 5-bit value, or a combination thereof is also adopted.

[0060] Reference Figure 3 , the selected memory cells may be erased by the erase operation EO to have a threshold voltage lower than the erase verification voltage VVE. Here, some of the selected memory cells may be over-erased and have a too low threshold voltage, and these memory cells may be referred to as over-erased memory cells DEC.

[0061] Through the pre-programming operation PPO, the threshold voltage of the over-erased memory cell DEC may be increased to be higher than the pre-verification read voltage VVRE. Figure 3 As shown, the erased state S0 ′ after the pre-program operation PPO may have a narrower threshold voltage range than the erased state S0 before the pre-program operation PPO.

[0062] Thereafter, a data programming operation DPO may be performed so that each selected memory cell corresponds to one state of the first state S1 to the eighth state S8 depending on the written data. Here, the first state S1 corresponds to an unprogrammed erased state. During the data programming operation DPO, the program execution results of the first state S1 to the eighth state S8 may be determined by sequentially applying the first data verification read voltage VVR1 to the seventh data verification read voltage VVR7 to the selected word line. In addition, during a read operation, each bit of the first state S1 to the eighth state S8 may be determined by sequentially applying some of the normal read voltages VR1 to VR7 to the selected word line.

[0063] Figure 4It shows instructions Figure 3 A diagram of an example of state-bit mapping information showing a mapping relationship between states and bit values ​​in FIG.

[0064] Reference Figure 4 , the state-bit mapping information SBM may indicate a mapping relationship between states and bits stored in a plurality of multi-level cells. Figure 4 is shown with Figure 3 . The first state S1 to the eighth state S8 may be represented by different values ​​corresponding to the least significant bit (LSB), the center bit (CSB), and the most significant bit (MSB) (e.g., different values ​​of the first LSB, the second CSB, and the third MSB). Figure 4 As shown in the figure, and in the order of MBS, CSB, LSB, the first state S1 corresponds to "111", the second state S2 corresponds to "110", the third state S3 corresponds to "100", the fourth state S4 corresponds to "000", the fifth state S5 corresponds to "010", the sixth state S6 corresponds to "011", the seventh state S7 corresponds to "001", and the eighth state S8 corresponds to "101".

[0065] In this case, the first LSB can be determined using the first read voltage VR1 and the fifth read voltage VR5, the second CSB can be determined using the second read voltage VR2, the fourth read voltage VR4, and the sixth read voltage VR6, and the third MSB can be determined using the third read voltage VR3 and the seventh read voltage VR7.

[0066] In the over-erased state, holes accumulate in the charge storage layer of the memory cell, and due to the over-erasing effect, these holes diffuse to the surrounding area over time. The diffused holes combine with the electrons stored in the programmed memory cell and distort the threshold voltage distribution of the programmed memory cell. As a result, as the number of over-erased memory cells increases after the write operation is completed, the retention characteristics of the non-volatile memory device may deteriorate.

[0067] Figure 5 is a block diagram illustrating a storage controller according to some embodiments.

[0068] Reference Figure 5 The storage controller 100 may include a processor 110, a buffer memory (BUFF) 140, an exposure temperature monitor (ETM) 130, a host interface (HIF) 120, an error correction code (ECC) engine 170, a memory interface (MIF) 150, an advanced encryption standard (AES) engine 180, and an internal bus system 160 connecting the components in the storage controller 100.

[0069] The processor 110 may respond to a request from a host device (eg, Figure 1 The processor 110 may control the operation of the storage controller 100 by receiving commands from the host device 1100 in the storage controller 100. For example, the processor 110 may control the storage device (e.g., Figure 1 The operation of the storage device 1200 in the embodiment of the present invention can be controlled, and the corresponding components can be controlled by adopting firmware for operating the storage device.

[0070] The buffer memory 140 may store instructions and data executed and processed by the processor 110. For example, the buffer memory 140 may be implemented with a volatile memory such as a DRAM, an SRAM, a cache memory, or the like.

[0071] The ECC engine 170 for error correction may perform coded modulation using Bose-Chaudhuri-Hocquenghem (BCH) codes, low-density parity-check (LDPC) codes, turbo codes, Reed-Solomon codes, convolutional codes, recursive systematic codes (RSC), trellis coded modulation (TCM), block coded modulation (BCM), etc. In some embodiments, the ECC engine 170 may perform ECC encoding and ECC decoding using the above codes or other error correction codes.

[0072] The host interface 120 may provide a physical connection between the host device 1100 and the storage device 1200. The host interface 120 may provide an interface corresponding to the bus format of the host device 1100 for communication between the host device 1100 and the storage device 1200. In some embodiments, the bus format of the host device 1100 may be a small computer system interface (SCSI) or a serial attached SCSI (SAS) interface. In other embodiments, the bus format of the host device may be USB, peripheral component interconnect (PCI) Express (PCIe), Advanced Technology Attachment (ATA), Parallel ATA (PATA), SATA, Non-Volatile Memory (NVM) Express (NVMe), or other formats.

[0073] The memory interface 150 can communicate with a non-volatile memory device (eg, Figure 1The memory interface 150 may be configured to communicate with the nonvolatile memory device 400 in the memory interface 150. The memory interface 150 may transmit data to the nonvolatile memory device 400 and / or may receive data read from the nonvolatile memory device 400. In some embodiments, the memory interface 150 may be connected to the nonvolatile memory device 400 via one channel. In other embodiments, the memory interface 150 may be connected to the nonvolatile memory device 400 via two or more channels. The memory interface 150 may be configured to comply with a standard protocol such as Toggle or Open NAND Flash Interface (ONFI).

[0074] The AES engine 180 may use a symmetric key algorithm to perform at least one of an encryption operation or a decryption operation on data input to the storage controller 100. The AES engine 180 may include an encryption module and a decryption module. For example, the encryption module and the decryption module may be implemented as separate modules. In another example, one module capable of performing both encryption and decryption operations may be implemented in the AES engine 180.

[0075] The exposure temperature monitor 130 can control the nonvolatile memory device to perform the monitoring program operation and the monitoring read operation as described above and below. The exposure temperature monitor 130 can generate a measured retention value by monitoring the read operation and estimate the exposure temperature corresponding to the measured retention value based on the reference information RFI.

[0076] Figure 6 is a block diagram illustrating a nonvolatile memory device according to some embodiments.

[0077] Reference Figure 6 , the nonvolatile memory device 800 may include a memory cell array 900, a page buffer circuit 810, a data input / output (I / O) circuit 820, an address decoder 830, a control circuit 850, and a voltage generator 860. In some embodiments, the nonvolatile memory device 800 may have a cell-on-periphery (COP) structure in which the memory cell array is arranged above the peripheral circuit. In this case, the memory cell array 900 may be formed in the cell region CREG, and the page buffer circuit 810, the data I / O circuit 820, the address decoder 830, the control circuit 850, and the voltage generator 860 may be formed in the peripheral region PREG.

[0078] The memory cell array 900 may be coupled to the address decoder 830 via string selection lines SSL, word lines WL, and ground selection lines GSL. The memory cell array 900 may be coupled to the page buffer circuit 810 via bit lines BL. The memory cell array 900 may include memory cells coupled to the word lines WL and the bit lines BL. In some embodiments, the memory cell array 900 may be a three-dimensional memory cell array, which may be formed on a substrate in a three-dimensional structure (or a vertical structure). In this case, the memory cell array 900 may include a vertically oriented cell string (e.g., a NAND string) such that at least one memory cell is located above another memory cell.

[0079] The control circuit 850 may receive a command signal CMD and an address signal PADD from a memory controller, and may control an erase operation, a program operation, and a read operation of the nonvolatile memory device 800 in response to (or based on) at least one of the command signal CMD and the address signal PADD. The erase operation may include performing a series of erase cycles, and the program operation may include performing a series of program cycles. Each program cycle may include a program operation and a program verification operation. Each erase cycle may include an erase operation and an erase verification operation. The read operation may include a normal read operation and a data recovery read operation.

[0080] In some embodiments, the control circuit 850 may generate a control signal CTL for controlling the operation of the voltage generator 860 based on the command signal CMD, and may generate a page buffer control signal PBC for controlling the page buffer circuit 810, and may generate a row address R_ADDR and a column address C_ADDR based on the address signal PADD. The control circuit 850 may provide the row address R_ADDR to the address decoder 830, and may provide the column address C_ADDR to the data I / O circuit 820.

[0081] The address decoder 830 may be coupled to the memory cell array 900 through string selection lines SSL, word lines WL, and ground selection lines GSL.

[0082] Hereinafter, a program operation may include both a normal program operation and a monitoring program operation for monitoring an exposure temperature, and a read operation may include both a normal read operation and a monitoring read operation for monitoring an exposure temperature.

[0083] During a program operation or a read operation, the address decoder 830 may determine (or select) one of the word lines WL as a selected word line based on the row address R_ADDR, and may determine or designate the remaining word lines WL except the selected word line as unselected word lines.

[0084] In addition, during a program operation or a read operation, the address decoder 830 may determine one of the string selection lines SSL as a selected string selection line based on the row address R_ADDR, and determine or designate the remaining string selection lines SSL except the selected string selection line as unselected string selection lines. The aforementioned selected memory cells correspond to memory cells connected to the selected word line and the selected string selection line.

[0085] The voltage generator 860 may generate a word line voltage VWL for operation of the memory cell array 900 of the nonvolatile memory device 800 based on the control signal CTL. The voltage generator 860 may receive power PWR from the memory controller. The word line voltage VWL may be applied to the word line WL through the address decoder 830.

[0086] In some embodiments, during an erase operation, the voltage generator 860 may apply an erase voltage to the well and / or common source line of the memory block based on the erase address, and may apply an erase enable voltage (e.g., a ground voltage) to all or part of the word lines of the memory block. During an erase verification operation, the voltage generator 860 may apply an erase verification voltage to all word lines of the memory block simultaneously, or sequentially (e.g., one by one) to the word lines.

[0087] In some embodiments, during a program operation, the voltage generator 860 may apply a program voltage to a selected word line and may apply a program pass voltage to unselected word lines. During a program verification operation, the voltage generator 860 may apply a program verification voltage to a selected word line and may apply a verification pass voltage to unselected word lines.

[0088] During a normal read operation, the voltage generator 860 may apply a read voltage to a selected word line and may apply a read pass voltage to unselected word lines. During a data recovery read operation, the voltage generator 860 may apply a read voltage to a word line adjacent to a selected word line and may apply a recovery read voltage to a selected word line.

[0089] The page buffer circuit 810 may be coupled to the memory cell array 900 via the bit lines BL. The page buffer circuit 810 may include a plurality of buffers. In some embodiments, each buffer may be connected to only a single bit line. In some embodiments, each buffer may be connected to two or more bit lines. The page buffer circuit 810 may temporarily store data to be programmed in a selected page, or data read out from a selected page of the memory cell array 900.

[0090] The data I / O circuit 820 may be coupled to the page buffer circuit 810 through the data line DL. During a program operation, the data I / O circuit 820 may receive program data DATA received from the memory controller based on the column address C_ADDR received from the control circuit 850, and provide the program data DATA to the page buffer circuit 810. During a read operation, the data I / O circuit 820 may provide the memory controller with read data DATA read from the memory cell array 900 and stored in the page buffer circuit 810 based on the column address C_ADDR received from the control circuit 850.

[0091] The page buffer circuit 810 and the data I / O circuit 820 can read data from a first region of the memory cell array 900, and can write the read data to a second region of the memory cell array 900 (e.g., without sending the data to a source external to the nonvolatile memory device 800, such as a memory controller). Thus, the page buffer circuit 810 and the data I / O circuit 820 can perform a copy-back operation.

[0092] Figure 7 It is shown that the Figure 6 A block diagram of a memory cell array in a nonvolatile memory device, and Figure 8 It is shown that the Figure 7 A circuit diagram of the equivalent circuit of a memory block in a memory cell array.

[0093] Reference Figure 7 , the memory cell array 900 may include memory blocks BLK1 to BLKz. In some embodiments, the memory blocks BLK1 to BLKz may be composed of Figure 6 The address decoder 830 selects the memory block BLK1 to BLKz. For example, the address decoder 830 may select a specific memory block BLK corresponding to the block address among the memory blocks BLK1 to BLKz.

[0094] Figure 8 The memory block BLKi (i is an integer from 1 to z) can be formed on the substrate in a three-dimensional structure (or vertical structure). For example, the NAND string or cell string included in the memory block BLKi can be formed and stacked in a vertical direction D3 perpendicular to the upper surface of the substrate.

[0095] Reference Figure 8 , the memory block BLKi may include NAND strings NS11 to NS33 coupled between bit lines BL1, BL2, and BL3 and a common source line CSL. Each of the NAND strings NS11 to NS33 may include a string selection transistor SST, memory cells MC1 to MC8, and a ground selection transistor GST. Figure 8, each of the NAND strings NS11 to NS33 is illustrated as including eight memory cells MC1 to MC8. However, embodiments are not limited thereto, and each of the NAND strings NS11 to NS33 may include various numbers of memory cells.

[0096] Each string selection transistor SST may be connected to a corresponding string selection line (one of SSL1 to SSL3). Memory cells MC1 to MC8 may be connected to corresponding gate lines GTL1 to GTL8, respectively. Gate lines GTL1 to GTL8 may be word lines, and some of gate lines GTL1 to GTL8 may be dummy word lines. Each ground selection transistor GST may be connected to a corresponding ground selection line (one of GSL1 to GSL3). Each string selection transistor SST may be connected to a corresponding bit line (e.g., one of BL1, BL2, and BL3), and each ground selection transistor GST may be connected to a common source line CSL.

[0097] Word lines (eg, WL1) having the same or similar heights may be commonly connected, and ground selection lines GSL1 to GSL3 and string selection lines SSL1 to SSL3 may be separated. Figure 8 , the memory block BLKi is shown to be coupled to eight gate lines GTL1 to GTL8 and three bit lines BL1 to BL3. However, embodiments are not limited thereto, and each memory block in the memory cell array 900 may be coupled to various numbers of word lines and various numbers of bit lines.

[0098] Fig. 9 is a circuit diagram illustrating erase bias conditions of a nonvolatile memory device according to some embodiments.

[0099] For ease of description, Fig. 9 NAND strings NS11 and NS21 connected to a first bit line BL1 and NAND strings NS12 and NS22 connected to a second bit line BL2 are shown in FIG.

[0100] During the erase operation, the erase voltage VERS may be applied to the first bit line BL1 and the second bit line BL2. In this case, for example, the power supply voltage Vcc may be applied to the first string selection line SSL1 and the second string selection line SSL2. In addition, during the erase operation, the erase voltage VERS may be applied to the common source line CSL. In this case, the power supply voltage Vcc may be applied to the first ground selection line GSL1 and the second ground selection line GSL2. The erase permission voltage VERSWL may be applied to the word lines WL4, WL5, and WL6.

[0101] Under this erase bias condition, the voltages of the drains and sources of the memory cells of the memory block may be, for example, 20 V, and a voltage of, for example, 0 V may be applied to the gates. Figure 6 The voltage generator 860 may generate an erase voltage VERS applied to the bit lines BL1 and BL2 and / or the common source line CSL during an erase operation.

[0102] In some embodiments, in order to facilitate degradation of retention characteristics of a target memory cell, an erase voltage VERS corresponding to the target memory cell may be set lower than an erase voltage VERS corresponding to a typical memory cell storing data.

[0103] Fig.10 is a circuit diagram illustrating read bias conditions for a nonvolatile memory device according to some embodiments.

[0104] For ease of description, Fig.10 NAND strings NS11 and NS21 connected to a first bit line BL1 and NAND strings NS12 and NS22 connected to a second bit line BL2 are shown in FIG.

[0105] The first bit line BL1 and the second bit line BL2 may be precharged with a precharge voltage (e.g., 0.5V). During a read operation, if the NAND strings NS21 and NS22 are selected, a voltage of 0V may be applied to the first string selection line SSL1, and a power supply voltage Vcc may be applied to the second string selection line SSL2. In addition, a voltage of 0V may be applied to the first ground selection line GSL1, and a power supply voltage Vcc may be applied to the second ground selection line GSL2. A read voltage VR may be applied to a selected word line (e.g., WL5), and a read pass voltage VPS may be applied to unselected word lines (e.g., WL4 and WL6).

[0106] In this example of the read bias condition, the drain voltage of the selected memory cells A and B may be, for example, 0.5 V, and the source voltage of the selected memory cells A and B may be, for example, 0 V. In addition, a read voltage VR is applied to the gates of the selected memory cells A and B. In addition, a read operation for verifying the data stored at the memory cells may be performed while changing the voltage level of the read voltage VR. The channels of the unselected NAND strings NS11 and NS12 including the memory cells C and D are floated. Figure 6 The voltage generator 860 may generate a read voltage VR and a read pass voltage VPS applied to a plurality of word lines during a read operation.

[0107] Fig.11 is a circuit diagram illustrating programming bias conditions for a nonvolatile memory device according to some embodiments.

[0108] For ease of description, Fig.11 NAND strings NS11 and NS21 connected to a first bit line BL1 and NAND strings NS12 and NS22 connected to a second bit line BL2 are shown in FIG.

[0109] The first bit line BL1 may be a program bit line to which a program enable voltage (e.g., 0V) is applied, and the second bit line BL2 may be a program inhibit bit line to which a program inhibit voltage such as a power supply voltage Vcc is applied. If the NAND string NS21 of the NAND strings NS11 and NS21 is selected, during a program operation, a voltage of 0V may be applied to the first string selection line SSL1, and the power supply voltage Vcc may be applied to the second string selection line SSL2.

[0110] A voltage of 0 V may be applied to the ground selection lines GSL1 and GSL2. In addition, a voltage higher than 0 V (e.g., Vcc) may be applied to the common source line CSL. A program voltage Vpgm (e.g., 18 V) may be applied to a selected word line (e.g., WL5), and a pass voltage Vpass (e.g., 8 V) may be applied to unselected word lines (e.g., WL4 and WL6).

[0111] Under the programming bias condition, a programming voltage Vpgm of 18 V may be applied to the gate of the memory cell A having a channel voltage of 0 V. Since a strong electric field is formed between the gate and the channel of the memory cell A, the memory cell A may be programmed. However, since the corresponding channels of the memory cells C and D are in a floating state, their channel voltages may be boosted to, for example, about 8 V, and thus the memory cells C and D may not be programmed. Since a weak electric field is formed between the gate and the channel of the memory cell B, the memory cell B may not be programmed. Figure 6 The voltage generator 860 may generate a program voltage Vpgm and a program pass voltage Vpass applied to a plurality of word lines during a program operation.

[0112] In some embodiments, in order to facilitate degradation of retention characteristics of a target memory cell, a program voltage Vpgm corresponding to the target memory cell may be set lower than a program voltage Vpgm corresponding to a typical memory cell storing data.

[0113] Fig. 12A and Fig. 12B is a diagram illustrating degradation of retention characteristics according to temperature in a nonvolatile memory device according to some embodiments. Fig. 12B yes Fig. 12A A magnified view of a portion of the threshold voltage range.

[0114] exist Fig. 12A and Fig. 12B , the horizontal axis represents the threshold voltage VTH of the memory cell, and the vertical axis represents the number of memory cells corresponding to the threshold voltage VTH. Fig. 12A A TLC (Triple Level Cell) scheme in which each memory cell stores a 3-bit value is shown. However, the embodiment is not limited thereto, and the number of bits stored in each memory cell may be determined according to other schemes.

[0115] Fig. 12A and Fig. 12B 1 shows that when a nonvolatile memory device is exposed to a specific exposure temperature, the retention characteristics deteriorate over time. DST1 represents the threshold voltage distribution immediately after data is programmed, DST2 represents the threshold voltage distribution after a first exposure time has passed, and DST3 represents the threshold voltage distribution after a second exposure time longer than the first exposure time has passed. Fig. 12A and Fig. 12B As shown, it can be seen that the programming state with the highest threshold voltage distribution (i.e., the eighth state S8) has the greatest degradation. In other words, it can be seen that the number of memory cells belonging to the threshold voltage range between the first monitoring voltage VM1 and the second monitoring voltage VM2 varies the most. Considering the retention characteristics of the nonvolatile memory device, the retention value used to estimate the above-mentioned exposure temperature can be appropriately determined.

[0116] Fig.13 , Fig.14A and Fig. 14B is a diagram showing changes in a retention value in a nonvolatile memory device in a power-off state according to an exposure temperature and an exposure time.

[0117] Fig.13 The exposure condition EPC and the holding value RTV corresponding to the exposure condition EPC are shown. Fig.13 , A, B, C, D and E represent each exposure time ETm, and Pi, Qi and Ri (i=0, 1, 2) are the hold values ​​dCNT, CNT and NEB corresponding to the exposure time ETm, respectively.

[0118] The exposure conditions EPC may include at least an exposure temperature ETp and an exposure time ETc. Fig.25 As described, the exposure condition EPC may also include factors other than the exposure temperature ETp and the exposure time ETc or factors other than the exposure temperature ETp and the exposure time ETc. The more various factors of the exposure condition are considered, the more accurately the exposure temperature can be estimated, but the size of the reference information RFI increases, and the power and time required to generate the measured hold value may increase. The type and number of appropriate exposure condition EPCs may be determined in consideration of the accuracy of the required exposure temperature estimation.

[0119] As an example, Fig.13 Three types of holding values ​​dCNT, CNT and NEB are shown. Fig.15 , Fig.16 and Fig.17 These hold values ​​dCNT, CNT and NEB are described.

[0120] Fig.14A shows the trend of the holding value dCNT according to the exposure temperature ETp, and Fig. 14B The trend of the holding value dCNT according to the exposure time ETm is shown. Fig.14A and Fig. 14B As shown in , the hold value dCNT has a nonlinear characteristic with respect to the exposure conditions ETp and ETm. The hold value dCNT is shown to increase as a function of each of ETp and ETm.

[0121] Fig.15 , Fig.16 and Fig.17 is a flow chart illustrating some examples of generating a retention value in a method of providing an exposure temperature of a non-volatile memory device in a power-off state according to some implementations.

[0122] Reference Figure 1 and Fig.15 , the exposure temperature monitor ETM can monitor the voltage (for example, Fig. 12B The monitor voltage VM1 is applied to the word line connected to the target memory cell to provide a count value (eg, Fig.13 The exposure temperature monitor ETM may provide the count value CNT as the above-mentioned measured holding value (S312).

[0123] Reference Figure 1 and Fig.16 , the exposure temperature monitor ETM may be configured to generate a first monitoring voltage (eg, Fig. 12B The exposure temperature monitor ETM may apply a second monitoring voltage (e.g., VM1 in FIG. 1 ) to a word line connected to a target memory cell to provide a first count value indicating the number of target memory cells having a threshold voltage higher than the first monitoring voltage VM1 (S321). In addition, the exposure temperature monitor ETM may apply a second monitoring voltage (e.g., VM1 in FIG. 1 ) lower than the first monitoring voltage VM1 to a word line connected to the target memory cell to provide a first count value indicating the number of target memory cells having a threshold voltage higher than the first monitoring voltage VM1 (S321). Fig. 12B The exposure temperature monitor ETM may provide a difference between the first count value and the second count value (e.g., Fig.13dCNT in ) is used as the maintained value of the above measurement (S323).

[0124] Reference Figure 1 and Fig.17 , the exposure temperature monitor ETM may generate read data corresponding to at least a portion of the monitoring data by performing a read operation on a target memory cell ( S331 ). Figure 5 The ECC engine 170 in the embodiment can provide the number of error bits (eg, Fig.13 The exposure temperature monitor ETM may provide the number of error bits NEB as a hold value of the above measurement (S333).

[0125] For example, as referenced Figure 4 As described above, when three bits are written to each memory cell, the MSB page data can be read using the third read voltage VR3 and the seventh read voltage VR7. Fig. 12A and Fig. 12B As shown in , the maximum degradation of the retention characteristic corresponds to the eighth state S8, and the MSB page data may best reflect the degradation of the retention characteristic.

[0126] In some embodiments, when multiple bits are written to each of the target memory cells, the read data used to monitor the read operation may correspond to the MSB page data corresponding to the most significant bit among the multiple bits. By using only the MSB page data having the greatest degradation characteristics in the monitoring data, the time for estimating the exposure temperature can be reduced.

[0127] Fig.18 is a flow chart illustrating an example of generating reference information in a method of providing an exposure temperature of a nonvolatile memory device in a power-off state according to some embodiments.

[0128] Reference Fig.18 A test programming operation may be performed to write monitoring data to a test memory cell of a test nonvolatile memory device (S110). The monitoring data of the test programming operation may be equal to the monitoring data of the monitoring programming operation for estimating the exposure temperature described above.

[0129] The test nonvolatile memory device may be exposed to a test environment corresponding to a test condition including a test temperature and a test time (S120). The test environment may be implemented using a test chamber for testing semiconductor devices. In order to shorten the test time, the test nonvolatile memory device may be exposed to a relatively high exposure temperature with a relatively short exposure time, and then a retention value corresponding to a lower exposure temperature and a longer exposure time may be estimated by simulation.

[0130] After exposing the test nonvolatile memory device to the test environment, a test read operation may be performed through the test memory cells of the device to generate a retention value corresponding to the test condition (S130).

[0131] In some embodiments, the physical location of the test memory cell for the reference information RFI in the test nonvolatile memory device may be equal to the physical location of the target memory cell for monitoring the exposure temperature in the nonvolatile memory device. Fig.26 and Fig. 27 As described, the degradation of the retention characteristics according to the exposure temperature of the memory cell may vary according to the physical location of the nonvolatile memory device. By setting the physical location of the test memory cell to be the same as the physical location of the target memory cell, the correlation between the reference information RFI and the measured retention value can be further increased, and the accuracy of the exposure temperature estimation can be improved.

[0132] In some embodiments, the position of the word line connected to the test memory cell in the memory block may be the same as the position of the word line connected to the target memory cell in the memory block. According to some embodiments, the memory block to which the target memory cell belongs may be changed. In this case, the physical position of the word line for the reference information RFI and the physical position of the word line for estimating the exposure temperature may be set to be the same, and the accuracy of the estimated measured exposure temperature may be improved.

[0133] In some embodiments, the operating conditions of the test program operation may be the same as the operating conditions of the monitor program operation, and the operating conditions of the test read operation may be the same as the operating conditions of the monitor read operation. Here, the operating conditions may include operating voltage, operating timing, etc.

[0134] While changing the exposure conditions (such as exposure time and exposure temperature), the Fig.18 The reference information RFI may be generated based on a plurality of exposure conditions and retention values ​​corresponding to the plurality of exposure conditions.

[0135] Fig.19 is a diagram illustrating an example of reference information in a method of providing an exposure temperature of a nonvolatile memory device in a power-off state according to some embodiments.

[0136] In some embodiments, the reference information RFI may be provided as a reference table RFTBL, wherein the reference table RFTBL includes: Fig.19. Once the measured holding value is obtained by exposure temperature monitoring as described above, the exposure temperature ETp corresponding to the combination of the exposure time ETm and the measured holding value VL can be extracted using the reference table RFTBL. The combination of the exposure time ETm and the measured holding value VL not included in the reference table RFTBL can be obtained by interpolation. For example, the exposure temperature corresponding to the combination of the exposure time between two exposure times ta and tb and the measured holding value between two measured holding values ​​VLc and VLd can be obtained by interpolation using four exposure temperatures T1, T2, T3 and T4.

[0137] In some embodiments, the reference information RFI may be provided in the form of a function having at least the exposure time ETm and the hold value VL as inputs and the exposure temperature ETp as output. The function may be provided by using Fig.19 Several test results shown in the figure were obtained using various fitting methods.

[0138] In some embodiments, as will be referred to below Figure 20 to Figure 25 As described, the reference information RFI can be provided as an artificial neural network having at least the exposure time ETm and the holding value VL as input and the exposure temperature ETp as output.

[0139] Fig. 20 is a block diagram illustrating a computing device according to some implementations.

[0140] Reference Fig. 20 , the computing device 2100 includes a processor 2110 , a random access memory 2120 , a device driver 2130 , a storage device 2140 , a modem 2150 , and a user interface 2160 .

[0141] At least one of the processors 2110 may execute a deep learning model (DLM) 2220 and a training control module (TCM) 2240 that controls training of the deep learning model 2200. The training control module 2240 may train the deep learning model 2220 to perform estimation of the exposure temperature as described above.

[0142] In some embodiments, the deep learning model 2220 and the training control module 2240 may be implemented in the form of instructions (and / or program codes) executed by at least one processor in the processor 2110. The deep learning model 2220 and the training control module 2240 may be stored in a computer-readable medium. Here, at least one processor may load the instructions (and / or program codes) of the deep learning model 2220 and the training control module 2240 into the random access memory 2120.

[0143] In some embodiments, at least one processor may be manufactured to implement the deep learning model 2220 and the training control module 2240. For another example, at least one processor may be manufactured to implement various machine learning models or deep learning models. At least one processor may implement the deep learning model 2220 and the training control module 2240 by receiving information corresponding to the deep learning model 2220 and the training control module 2240.

[0144] The processor 2110 may include at least one general-purpose processor, such as a central processing unit (CPU) 2111, an application processor (AP), etc. The processor 2110 may also include at least one special-purpose processor, such as a neural processing unit (NPU) 2113, a neuromorphic processor (NP) 2114, a graphics processing unit (GPU) 2115, etc. The processor 2110 may include two or more processors of the same type.

[0145] The random access memory 2120 is used as an operation memory of the processor 2110, and may be used as a main memory or a system memory of the computing device 2100. The random access memory 2120 includes a volatile memory (such as a dynamic random access memory or a static random access memory) or a nonvolatile memory (such as a phase change random access memory, a ferroelectric random access memory, a magnetic random access memory, or a resistive random access memory).

[0146] The device driver 2130 may control peripheral devices such as the storage device 2140, the modem 2150, and the user interface 2160 according to a request from the processor 2110. The storage device 2140 may include a fixed storage device such as a hard disk drive, a solid state drive, or a removable storage device such as an external hard disk drive, an external solid state drive, or a removable memory card.

[0147] The modem 2150 may provide remote communication with an external device. The modem 2150 may perform wireless or wired communication with an external device. The modem 2150 may communicate with an external device through at least one of various communication forms such as Ethernet, Wi-Fi, LTE, and 5G mobile communication.

[0148] The user interface 2160 can receive information from the user and provide information to the user. The user interface 2160 includes at least one user output interface (such as a display 2161, a speaker 2162, etc.) and at least one user input interface (such as a mouse 2163, a keyboard 2164, a touch input device 2165, etc.).

[0149] The instructions (or program codes) of the deep learning model 2220 and the training control module 2240 may be received through the modem 2150 and stored in the storage device 2140. The instructions (or program codes) of the deep learning model 2220 and the training control module 2240 may be stored in a removable storage device coupled to the computing device 2100. The instructions (or program codes) of the deep learning model 2220 and the training control module 2240 may be loaded from the storage device 2140 to the random access memory 2120 and then executed.

[0150] The computer program instructions, the deep learning model DLM, and the training control module TCM may be stored in a temporary computer-readable medium or a non-transitory computer-readable medium. In addition, in at least some embodiments, the result value generated by the processor or the value of the arithmetic processing performed by the processor may be stored in a temporary computer-readable medium or a non-transitory computer-readable medium. In addition, in at least some embodiments, the intermediate values ​​generated during deep learning may be stored in a temporary computer-readable medium or a non-transitory computer-readable medium. However, some embodiments are not limited thereto.

[0151] Fig.21 and Fig. 22 is a diagram for describing an example of a deep learning neural network structure driven by a machine learning device according to some embodiments.

[0152] Reference Fig.21 A general neural network may include an input layer IL, multiple hidden layers HL1, HL2, ..., HLn and an output layer OL.

[0153] The input layer IL may include i input nodes x1, x2, ..., xi, where i is a natural number. Input data (e.g., vector input data) X of length i may be input to the input nodes x1, x2, ..., xi, so that each element of the input data X is input to a corresponding node in the input nodes x1, x2, ..., xi.

[0154] The plurality of hidden layers HL1, HL2, ..., HLn may include n hidden layers, where n is a natural number, and may include a plurality of hidden nodes h 1 1 、h 1 2 、h 1 3 ,...,h 1 m 、h 2 1 、h 2 2 、h 23 ,...,h 2 m 、h n 1 、h n 2 、h n 3 ,...,h n m For example, the hidden layer HL1 may include m hidden nodes h 1 1 、h 1 2 、h 1 3 ,...,h 1 m , the hidden layer HL2 may include m hidden nodes h 2 1 、h 2 2 、h 2 3 ,...,h 2 m , and the hidden layer HLn may include m hidden nodes h n 1 、h n 2 、h n 3 ,...,h n m , where m is a natural number.

[0155] The output layer OL may include j output nodes y1, y2, ..., yj providing output data Y, where j is a natural number. The output layer OL may output output data Y associated with the input data X.

[0156] Fig.21 The structure of the neural network shown in can be represented by information about branches (and / or connections) between nodes shown as lines and weight values ​​assigned to each branch. Nodes within one layer may not be connected to each other, but nodes in different layers may be fully (and / or partially) connected to each other.

[0157] Each node (for example, node h 1 1 ) can receive the output of the previous node (e.g., node x1), can perform a computation operation, calculation, and / or operation on the received output, and can output the result of the computation operation, calculation, or operation as an output to the next node (e.g., node h 2 1). Each node can calculate the value to be output by applying a specific function (e.g., a nonlinear function) to the input.

[0158] Generally, the structure of the neural network can be set in advance, and the weight values ​​of the connections between nodes are appropriately set using data with known answers to which class the data belongs. The data with known answers can be called "training data", and the process of determining the weight values ​​can be called "training". The neural network "learns" during the training process. A set of independently trainable structures and weight values ​​is called a "model", and the process of predicting which class the input data belongs to by the model with determined weight values ​​and then outputting the predicted value is called a "testing" process.

[0159] Fig.21 The general neural network shown in may not be suitable for processing input image data (or input sound data) because each node (e.g., node h 1 1 ) is connected to all nodes of the previous layer (e.g., nodes x1, x2, ..., xi included in layer IL), and then the number of weighted values ​​increases sharply as the size of the input image data increases. Therefore, a convolutional neural network (CNN) implemented by combining a filtering technique with a general neural network has been studied so that a two-dimensional image (e.g., input image data) can be efficiently trained by a convolutional neural network.

[0160] Reference Fig. 22 , a convolutional neural network (CNN) may include multiple layers CONV1, RELU1, CONV2, RELU2, POOL1, CONV3, RELU3, CONV4, RELU4, POOL2, CONV5, RELU5, CONV6, RELU6, POOL3, and FC (in Fig. 22 not shown).

[0161] Unlike a general neural network, each layer of a convolutional neural network may have three dimensions of width, height, and depth, and thus the data input to each layer may be volumetric data having three dimensions of width, height, and depth.

[0162] Each of the convolution layers CONV1, CONV2, CONV3, CONV4, CONV5, and CONV6 may perform a convolution operation on the input volume data. For example, in image processing, a convolution operation refers to an operation of processing image data based on a mask having a weighted value and obtaining an output value by multiplying the input value by the weighted value and adding the total multiplied value. The mask may be referred to as a filter, a window, and / or a kernel.

[0163] In more detail, the parameters of each convolutional layer may include a set of learnable filters. Each filter may be spatially small (e.g., along width and / or height), but may extend throughout the entire depth of the input volume. For example, during the forward pass, each filter may slide across the width and height of the input volume (e.g., convolution), and dot products may be calculated between the entries of the filter and the input at any position. As the filter slides across the width and height of the input volume, a two-dimensional activation map may be generated that gives the response of the filter at each spatial position. As a result, an output volume may be generated by stacking these activation maps along the depth dimension. For example, if input volume data having a size of 32×32×3 passes through a convolutional layer CONV1 having four filters with zero padding, the output volume data of the convolutional layer CONV1 may have a size of 32×32×12 (e.g., the depth of the volume data increases).

[0164] Each of the rectified linear unit (RELU) layers RELU1, RELU2, RELU3, RELU4, RELU5, and RELU6 may perform a rectified linear unit operation corresponding to, for example, an activation function defined by a function f(x)=max(0,x) (e.g., for all negative inputs x, the output is zero). For example, if input volume data having a size of 32×32×12 passes through the RELU layer RELU1 to perform the rectified linear unit operation, the output volume data of the RELU layer RELU1 may have a size of 32×32×12 (e.g., the size of the volume data is maintained).

[0165] Each of the pooling layers POOL1, POOL2, and POOL3 can perform a downsampling operation on the input volume data along the spatial dimensions of width and height. For example, four input values ​​arranged in a 2×2 matrix form can be converted into one output value based on a 2×2 filter. For example, the maximum value of the four input values ​​arranged in a 2×2 matrix form can be selected based on 2×2 maximum pooling, or the average value of the four input values ​​arranged in a 2×2 matrix form can be obtained based on 2×2 average pooling. For example, if input volume data having a size of 32×32×12 passes through a pooling layer POOL1 having a 2×2 filter, the output volume data of the pooling layer POOL1 can have a size of 16×16×12 (for example, the width and height of the volume data are reduced, and the depth of the volume data is maintained).

[0166] Generally, a convolution layer (e.g., CONV1) and a RELU layer (e.g., RELU1) may form a pair of CONV / RELU layers in a convolutional neural network, pairs of CONV / RELU layers may be repeatedly arranged in the convolutional neural network, and pooling layers may be periodically inserted in the convolutional neural network to reduce characteristics of input data X. The type and number of layers included in the convolutional neural network may be variously changed.

[0167] Some embodiments of the deep learning model are not limited to a specific neural network. The deep learning model may include, for example, PNN (perceptron neural network), CNN (convolutional neural network), R-CNN (regional convolutional neural network), RPN (region proposal network), RNN (recursive neural network), S-DNN (stacked deep neural network), S-SDNN (state space dynamic neural network), deconvolution network, DBN (deep belief network), RBM (restricted Boltzmann machine), full convolution network, LSTM (long short-term memory) network, classification network, BNN (Bayesian neural network), etc. In addition (and / or alternatively), (one or more) deep learning models can be trained based on at least one of various algorithms, such as regression, linear and / or logistic regression, random forest, support vector machine (SVM) and / or other types of models, such as statistical clustering, Bayesian classification, decision tree, dimensionality reduction (such as principal component analysis), expert system and / or their combination (including such as random forest collection).

[0168] Fig.23 is a diagram illustrating an example of nodes included in a neural network.

[0169] Fig.23 An example node operation performed by a node ND in a neural network is shown. When N inputs a1 to an are provided to the node ND, the node ND may multiply the n inputs a1 to an and the corresponding n weights w1 to wn, respectively, may sum the n values ​​obtained by the multiplication, may add an offset "b" to the summed value, and may generate an output value by applying the value added to the offset "b" to a specific function "σ". A learning operation may be performed based on training data to update all nodes in the neural network.

[0170] In the case of predicting exposure temperature based on deep learning, a sufficient amount of training data and / or learning data may be utilized (and / or required) in the training of the deep learning model (and / or deep learning module). For example, various types of training data may be utilized (and / or required) to prevent overfitting during training and to enhance the performance of the deep learning model.

[0171] According to some embodiments, the Fig.19The training data is generated in the same way as the reference table RFTBL to effectively build a database for training deep learning models.

[0172] Fig.24 is a diagram illustrating an example of a deep learning model in a method of providing an exposure temperature of a nonvolatile memory device in a power-off state according to some embodiments. For ease of explanation, the detailed configuration of the deep learning model is omitted, and Fig.24 Only the input layer IL receiving input data X and the output layer OL providing output data Y are shown.

[0173] Reference Fig.24 , you can create and replace Fig.19 Reference table of RFTBL’s deep learning model DLM.

[0174] The learning data or training data TRD can be generated through a test process of a plurality of nonvolatile memory devices. The training data TRD corresponds to a combination of an exposure time ETm, a retention value VL, and an exposure temperature ETp. According to different exposure times ETm and exposure temperatures ETp, a plurality of training data TRD corresponding to different combinations can be generated through testing.

[0175] In this case, the input data X of the deep learning model DLM may include at least the exposure time ETm and the hold value VL. The output data Y may include at least the estimated exposure temperature ETp or the measured exposure temperature ETp. The supervised learning of the deep learning model DLM may be performed using the exposure temperature ETp of the training data TRD as the standard answer (ground truth) of the estimated exposure temperature ETp.

[0176] Fig.25 is a graph showing data in a method of providing an exposure temperature of a nonvolatile memory device in a power-off state according to some embodiments.

[0177] Reference Fig.25 , the input data X of the deep learning model may include not only the exposure time ETm and the retention value VL, but also various exposure conditions that affect the degradation of the retention characteristics, such as the program-erase cycle P / E, the erase-program interval EPI, the temperature Ton at the power-on time point, the temperature Toff at the power-off time point, the usage time UT of the non-volatile memory device, etc.

[0178] In some embodiments, when the exposure condition further includes a program-erase cycle P / E of a target memory cell of the nonvolatile memory device, Fig.24The training data TRD may also include program-erase cycles P / E, and the program-erase cycles P / E may be added as input to the deep learning model DLM. In this case, the exposure temperature monitor ETM described above may estimate an estimated exposure temperature ETp corresponding to the measured exposure time ETm, the measured retention value VL, and the current program-erase cycle P / E of the target memory cell based on the reference information RFI (e.g., using the deep learning model DLM).

[0179] like Fig.25 As shown, the output data Y of the deep learning model DLM may also include the reliability value RB of the estimated exposure temperature ETp and the exposure temperature ETp. The deep learning model DLM may be trained to output the exposure temperature ETp and the reliability value RB. The reliability value RB may represent the uncertainty in the estimated exposure temperature ETp due to lack of training data or the uncertainty due to noise in the training data.

[0180] Fig.26 is a diagram illustrating an example structure of a cell string included in a nonvolatile memory device according to some embodiments.

[0181] Reference Fig.26 In order to form a cell string CS, a pillar PL extending in a direction perpendicular to the surface of the substrate SUB and contacting the substrate SUB may be provided on the substrate SUB. The ground selection line GSL, the word line WL, and the string selection line SSL may be formed of a conductive material parallel to the substrate SUB, for example, a metal material. The pillar PL may contact the substrate SUB by passing through the conductive material forming the ground selection line GSL, the word line WL, and the string selection line SSL. In addition, the word line WL may include a dummy word line connected to a word line not used for data storage. The dummy word line may be used for various purposes.

[0182] For example, in the manufacturing process of the cell string CS, as the distance from the substrate SUB decreases, the width of the column PL or the cross-sectional area parallel to the upper surface of the substrate SUB is formed smaller. Therefore, when the same voltage is applied to the body of the ground selection transistor GST, the memory cell MC, and the string selection transistor SST, the electric field formed in the memory cell adjacent to the substrate SUB or the ground selection transistor GST is greater than the electric field formed in the memory cell far from the substrate SUB or the string selection transistor SST. These characteristics affect the retention characteristics of the memory cell. The width of the column PL or the cross-sectional area parallel to the upper surface of the substrate SUB is not limited to Fig.26 Depending on the etching process, the width of the pillar PL or the cross-sectional area parallel to the upper surface of the substrate SUB may be formed differently according to the distance from the substrate SUB.

[0183] Fig. 27is a diagram illustrating an example of a word line group in a nonvolatile memory device according to some embodiments.

[0184] In a nonvolatile memory device, the interval between adjacent word lines may be differently set according to the height in the vertical direction D3 according to limitations of a manufacturing process, a relationship with peripheral components, etc. As the word line interval decreases, interference between adjacent memory cells may increase and retention characteristics may deteriorate.

[0185] In some embodiments, a test memory cell for generating the reference information RFI and a target memory cell for estimating the exposure temperature may be set based on a word line interval.

[0186] Reference Fig. 27 , the spacing Lm of the word lines WLm+1, WLm and WLm-1 belonging to the first group WG1 is relatively small, and the spacing Ln of the word lines WLn+1, WLn and WLn-1 belonging to the second group WG2 is relatively large. In this case, the first group WG1 has degraded retention characteristics and is more affected by the exposure temperature than the second group WG2. The memory cells connected to the word lines WLm+1, WLm and WLm-1 of the first group WG1 can be set as the above-mentioned test memory cells and target memory cells.

[0187] In the following, reference will be made to Figures 28 to 30B Some embodiments of setting the monitoring data written to the test memory cell for generating the reference information RFI and the target memory cell for estimating the exposure temperature are described. Figure 3 Duplicate description.

[0188] Figures 28 to 30B is a diagram illustrating some embodiments of monitoring a programming operation in a method of providing (eg, determining) an exposure temperature of a nonvolatile memory device in a power-off state according to some embodiments.

[0189] Reference Fig.28 , the monitoring data can be set so that the number of states S1 to S8 of the target memory cell can be consistent. At this time, a randomization scheme can be used to balance the number of states S1 to S8.

[0190] In a normal programming operation for writing data to a nonvolatile memory device, it is necessary to minimize the degradation of the retention characteristics. Figure 3 As described above, the degradation of the retention characteristics can be reduced by the pre-programming operation PPO. Fig.28As shown, in the monitoring program operation MPO for estimating the exposure temperature according to some embodiments, the pre-programming operation PPO can be omitted. The degradation of the retention characteristics of the target memory cells according to the exposure temperature can be accelerated by the remaining over-erased memory cells DEC, and the accuracy of the exposure temperature measurement can be improved.

[0191] Reference Fig.29A and Fig.29B , the monitoring data may be set so that all target memory cells are programmed to a programming state having a highest threshold voltage distribution. In other words, the monitoring data may be set so that the target memory cells are in the eighth state S8, and a monitoring programming operation MPO may be performed based on such monitoring data. Fig. 12A and Fig. 12B As described above, since the eighth state S8 has the greatest degradation of the holding characteristic depending on the exposure temperature, the degradation of the holding characteristic can be accelerated, and the accuracy of the exposure temperature measurement can be improved.

[0192] In some embodiments, Fig.29B As shown in , an aggressor memory cell AMC adjacent to a target memory cell TMC may be set, and the aggressor memory cell AMC may be maintained in an erase state S0 during a power-off state. For example, when a memory cell connected to a word line WLn is set to a target memory cell TMC, memory cells connected to word lines WLn+1 and WLn-1 adjacent above and below may be set to the aggressor memory cell AMC. In this case, the vertical disturbance VDST by which the aggressor memory cell AMC affects the target memory cell TMC may be increased to promote degradation of the retention characteristics of the target memory cell TMC according to the exposure temperature, and the accuracy of the exposure temperature measurement may be improved.

[0193] Reference Fig. 30A and Fig. 30B , the monitoring data may be set so that the target memory cell is programmed to the erased state or the programmed state having the highest threshold voltage distribution. In other words, the monitoring data may be set so that the target memory cell is in the eighth state S8 or the first state S1 corresponding to the unprogrammed erased state S0. For example, Fig. 30BAs shown, the monitoring data may be set so that the first state S1 and the eighth state S8 may be arranged alternately, and the monitoring programming operation MPO may be performed based on such monitoring data. In this case, not only the vertical disturbance VDST of the target memory cell TMC in the eighth state S8 affected by the aggressor memory cell AMC may be increased, but also the lateral disturbance or horizontal disturbance HDST between the target memory cells TMC in the first state S1 and the eighth state S8 may be increased to further promote the degradation of the retention characteristics of the target memory cell TMC according to the exposure temperature, and the accuracy of the exposure temperature measurement may be improved.

[0194] For ease of illustration and description, Fig.29B and Fig. 30B It is shown that the memory cells connected to one word line WLn are set as target memory cells TMC, and the memory cells connected to two adjacent word lines WLn+1 and WLn-1 are set as aggressor memory cells AMC, but some embodiments are not limited thereto. According to some embodiments, the number of word lines corresponding to the target memory cells TMC and / or aggressor memory cells AMC may be determined in various ways. In addition, according to some embodiments, in order to reduce the deviation of the exposure temperature estimation and improve the accuracy, the memory cells connected to the plurality of word lines arranged at different physical positions may be set as the target memory cells TMC.

[0195] In some embodiments, memory cells included in a defective memory block of a nonvolatile memory device may be set as target memory cells TMC. Even if a memory block is determined to be a bad block, memory cells of some word lines connected to the bad block may operate normally. In this way, the bad block may be used to set the target memory cell TMC for estimating the exposure temperature without causing a reduction in available memory capacity.

[0196] Figures 28 to 30B Some embodiments of monitoring data of a specific mode are shown, but the embodiments are not limited thereto. According to some embodiments, the monitoring data may vary according to the power-off time point. In some embodiments, the monitoring data may be metadata backed up to the non-volatile memory device before the non-volatile memory device is powered off. Figure 1 As described above, the log technology can be used to maintain the consistency of the firmware metadata FMDT and the non-volatile metadata NVMDT. When the non-volatile memory device is powered off, a backup programming operation is performed to store the firmware metadata FMDT in the non-volatile memory device or to update the non-volatile metadata NVMDT based on the firmware metadata FMDT. In this way, by using the metadata that is basically backed up in the non-volatile memory device when the power is turned off as the monitoring data, a separate monitoring programming operation can be omitted.

[0197] Furthermore, in the case of variable monitoring data, when the power is turned off, the address of the monitoring data and the initial hold value of the monitoring data must be stored in the non-volatile memory device. Thereafter, when the non-volatile memory device is powered on, the exposure temperature can be estimated based on the ratio of the measured hold value to the stored initial hold value. In this case, the reference information RFI may include the ratio of the count value after exposure to the initial count value instead of Fig.13 The count values ​​or digital CNT, dCNT and NEB.

[0198] Fig.31 is a block diagram illustrating an autonomous driving device including a non-volatile memory device according to some embodiments.

[0199] Reference Fig.31 The autonomous driving device 3000 may include a driver (eg, including a circuit system) 3110 , a sensor 3120 , a storage unit 3130 , a controller (eg, including a processing circuit) 3140 , and a communication interface 3150 .

[0200] The driver 3110 may be, for example, a configuration for driving the autonomous driving device 3000, and may include various circuit systems. In the case where the autonomous driving device 3000 is implemented as a vehicle, the driver 3110 may include various circuit systems and / or components, such as, for example, an engine / motor 3111, a steering unit 3112, a brake unit 3113, etc.

[0201] The engine / motor 3111 may include any combination of an internal combustion engine, an electric motor, a steam locomotive, and a Stirling engine. For example, in the case where the autonomous driving device 3000 is a gas-electric hybrid vehicle, the engine / motor 3111 may be a gasoline engine and an electric motor. For example, the engine / motor 3111 may be configured to supply energy to the autonomous driving device 3000 to travel on a predetermined driving route.

[0202] The steering unit 3112 may be any combination of mechanisms included to control the direction of the autonomous driving device 3000. For example, when an obstacle is recognized while the autonomous driving device 3000 is traveling, the steering unit 3112 may change the direction of the autonomous driving device 3000. In the case where the autonomous driving device 3000 is a vehicle, the steering unit 3112 may be configured to turn the steering wheel clockwise or counterclockwise and change the direction of the autonomous driving device 3000 accordingly.

[0203] The brake unit 3113 may be any combination of mechanisms included to decelerate the autonomous driving device 3000. For example, the brake unit may use friction to reduce the speed of the wheels / tires. When an obstacle is identified while the autonomous driving device 3000 is traveling, the brake unit 3113 may be configured to decelerate or slow down the autonomous driving device 3000.

[0204] The driver 3110 may enable the automatic driving device 3000 to travel or run on the ground, but the embodiment is not limited thereto. The driver 3110 may include a flight propulsion unit, a propeller, a wing, etc., and may include various ship propulsion devices.

[0205] The sensor 3120 may include a plurality of sensors configured to sense information related to the surrounding environment of the autonomous driving device 3000. For example, the sensor 3120 may include at least one of an image sensor 3121, a depth sensor 3122, a lidar unit 3123, a radar unit 3124, an infrared sensor 3125, a global positioning system (GPS) 3126, a magnetic sensor 3127, and / or an accelerometer sensor 3128.

[0206] The image sensor 3121 may be configured to capture an image of an external object located outside the autonomous driving device 3000 or other data related to an external object located outside the autonomous driving device 3000. The captured image or other data related to the external device may be used as data for changing at least one of the speed and direction of the autonomous driving device 3000. The image sensor 3121 may include various types of sensors, such as a charge coupled device (CCD) and a complementary metal oxide semiconductor (CMOS). In addition, the depth sensor 3122 may acquire a depth for determining the distance between the autonomous driving device 3000 and the external object.

[0207] The laser radar unit 3123, the radar unit 3124, and the infrared sensor 3125 may each include a sensor configured to output a specific signal and sense an external object in the environment where the autonomous driving device 3000 is located. For example, the laser radar unit 3123 may include a laser light source and / or a laser scanner configured to radiate laser light and a detector configured to detect the reflection of the laser light. The radar unit 3124 may be a sensor configured to sense an object in the environment where the autonomous driving device 3000 is located using a wireless signal. In addition, the radar unit 3124 may be configured to sense the speed and / or direction of the object. The infrared sensor 3125 may be a sensor configured to sense an external object in the environment where the autonomous driving device 3000 is located using light of a wavelength in the infrared region.

[0208] The GPS 3126, the magnetic sensor 3127, and the accelerometer sensor 3128 may each include a sensor configured to acquire information related to the speed, direction, position, etc. of the autonomous driving device 3000. For example, information related to the current state of the autonomous driving device 3000 may be acquired, and the possibility of collision with an external object may be identified and / or estimated, etc. The GPS 3126 may be configured to receive the position of the autonomous driving device 3000 as latitude and altitude data via a satellite, and the magnetic sensor 3127 and the accelerometer sensor 3128 may be configured to identify the current state of the autonomous driving device 3000 based on the momentum of the autonomous driving device 3000.

[0209] The storage unit 3130 may be configured to store data required for the controller 3140 to perform various processes. For example, the storage unit 3130 may be implemented as an internal memory included in the controller 3140, such as ROM, RAM, etc., and may be implemented as a memory separated from the controller 3140. In this case, the storage unit 3130 may be implemented in the form of a memory embedded in the automatic driving device 3000, or may be implemented in the form of a memory that can be removed from the automatic driving device 3000 according to the use of the data storage unit. For example, data for driving the automatic driving device 3000 is stored in a memory embedded in the automatic driving device 3000, and data for the extended functions of the automatic driving device 3000 may be stored in a memory that can be separated from the automatic driving device 3000. The memory embedded in the automatic driving device 3000 may be implemented in the form of a non-volatile memory, a volatile memory, a flash memory, a hard disk drive (HDD), a solid state drive (SDD), etc., and the memory that can be removed from the automatic driving device 3000 may be implemented in the form of a memory card (e.g., a micro SD card, a USB memory), an external memory (e.g., a USB memory) that can be connected to a USB port, etc.

[0210] The communication interface 3150 may include various communication circuit systems and may be configured to facilitate communication between the autonomous driving device 3000 and an external device. For example, the communication interface 3150 may send driving information of the autonomous driving device 3000 to an external device and receive driving information of the autonomous driving device 3000 from an external device. For example, the communication interface 3150 may be configured to perform communication through various communication methods (such as infrared (IR) communication, wireless fidelity (WI-FI), Bluetooth, ZigBee, beacon, near field communication (NFC), WAN, Ethernet, IEEE 1394, HDMI, USB, MHL, AES / EBU, optical, coaxial, etc.). In some embodiments, the communication interface 3150 may be configured to communicate driving information through a server (not shown).

[0211] The controller 3140 may include a random access memory (RAM) 3141, a read only memory (ROM) 3142, a central processing unit (CPU) 3143, a battery management system (BMS) 3144, and a bus 3145. The RAM 3141, the ROM 3142, the CPU 3143, and the BMS 3144 may be connected to each other through the bus 3145. The controller 3140 may be implemented as a system on chip (SoC).

[0212] The RAM 3141 may be a memory for reading various instructions and the like related to the driving of the automatic driving device 3000 from the storage unit 3130. The ROM 3142 may store a set of instructions for system startup. In response to a start command being input to the automatic driving device 3000 and power being supplied, the CPU 3143 may copy the O / S stored in the storage unit 3130 to the RAM 3141 according to the command stored in the ROM 3142, and start the system by executing the O / S. If the startup is completed, the CPU 3143 performs various operations by copying various types of application programs stored in the storage unit 3130 to the RAM 3141 and executing the application programs copied to the RAM 3141. The controller 3140 may perform various operations using the modules stored in the storage unit 3130.

[0213] According to some embodiments, the storage unit 3130 may include an exposure temperature monitor ETM, which is used to perform the method of providing the exposure temperature of the non-volatile memory in the power-off state as described above. When the storage unit 3130 is powered on, the exposure temperature monitor ETM can provide the measured exposure temperature to the controller 3140. According to some embodiments, the measured exposure temperature can be directly provided to the battery management system 3144, which is configured to be as described in reference to Figure 1 The peripheral management controller SMC manages the battery BTT.

[0214] As described above, the storage device and the method of providing the exposure temperature according to some embodiments can reduce power consumption and enhance the performance of the battery by providing the exposure information in the power-off state using the retention characteristics of the non-volatile memory device without supplying power to the circuit for temperature monitoring in the power-off state. By using the exposure temperature in the power-off state, products containing temperature-sensitive components can be effectively managed and controlled.

[0215] Aspects of the present disclosure may be applied to any electronic device and system including a non-volatile memory device. For example, the described processes, devices, and systems may be applied to devices such as memory cards, solid-state drives (SSDs), embedded multimedia cards (eMMCs), universal flash memory (UFS), mobile phones, smart phones, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, camcorders, personal computers (PCs), server computers, workstations, laptop computers, digital televisions, set-top boxes, portable game consoles, navigation systems, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-books, virtual reality (VR) devices, augmented reality (AR) devices, server systems, automotive driving systems, and the like.

[0216] Although the present disclosure contains many specific implementation details, these details should not be interpreted as limiting the scope of what may be claimed. Specific features described in the present disclosure in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented individually in multiple implementations or in any suitable sub-combination. In addition, although features may be described above as working in a particular combination and even initially claimed as such, in some cases, one or more features from a combination may be deleted from the combination, and the combination may be a sub-combination or a variation of a sub-combination.

[0217] The foregoing is illustrative of some embodiments and should not be construed as limiting thereof. Although some embodiments have been described, those skilled in the art will readily appreciate that many modifications may be made in some embodiments without substantially departing from the scope of the present disclosure.

Claims

1. A method for providing an exposure temperature, comprising: obtaining reference information indicating a relationship between an exposure condition and a retention value, wherein the exposure condition includes an exposure temperature and an exposure time of a nonvolatile memory device, and wherein the retention value indicates a retention characteristic of the nonvolatile memory device; Before a power-off time point at which the nonvolatile memory device is powered off, writing monitoring data into a target memory cell included in the nonvolatile memory device; generating a measured retention value based on data from the target memory cell after a power-on time point at which the nonvolatile memory device is powered on; and A temperature to which the nonvolatile memory device is exposed when powered off is determined based on the reference information, the measured retention value, and an exposure time between the power-off time point and the power-on time point.

2. The method according to claim 1, wherein: The held values ​​that produce the measurements include: applying a monitoring voltage to a word line connected to the target memory cell to obtain a count value indicating the number of target memory cells having a threshold voltage higher than the monitoring voltage; and The count value is provided as a hold value of the measurement.

3. The method according to claim 1, wherein: The held values ​​that produce the measurements include: applying a first monitoring voltage to a word line connected to the target memory cell to obtain a first count value indicating a number of target memory cells having a threshold voltage higher than the first monitoring voltage; applying a second monitor voltage to a word line connected to the target memory cell to provide a second count value indicating a number of target memory cells having a threshold voltage higher than the second monitor voltage; and A difference between the first count value and the second count value is provided as a hold value of the measurement.

4. The method according to claim 1, wherein: The held values ​​that produce the measurements include: generating read data corresponding to at least a portion of the monitoring data by reading from the target memory cell; determining the number of error bits characterizing the read data; and The number of error bits is provided as a held value of the measurement.

5. The method according to claim 4, wherein: A plurality of data bits are written into the target memory cell, and wherein the read data corresponds to page data corresponding to the most significant bits of the plurality of data bits.

6. The method according to claim 1, comprising: A memory cell included in a defective memory block of the nonvolatile memory device is set as the target memory cell.

7. The method according to claim 1, wherein: The monitoring data includes metadata, and the metadata is backed up in the non-volatile memory device before the non-volatile memory device is powered off.

8. The method according to claim 1, wherein: The exposure conditions include a program-erase cycle of the target memory cell, and wherein a temperature to which the nonvolatile memory device is exposed is also determined based on the program-erase cycle of the target memory cell.

9. The method according to claim 1, comprising: Generate the reference information, wherein generating the reference information comprises: writing the monitoring data into a test memory cell included in a test nonvolatile memory device; exposing the test non-volatile memory device to test conditions in a test environment, the test conditions including a test temperature and a test time; and After exposing the test nonvolatile memory device to the test condition in the test environment, a retention value corresponding to the test condition is generated based on data from the test memory cell.

10. The method according to claim 9, wherein: The physical locations of the test memory cells in the test non-volatile memory device match the physical locations of the target memory cells in the non-volatile memory device.

11. The method according to claim 9, wherein: The operating conditions for writing the monitoring data into the test memory cell match the operating conditions for writing the monitoring data into the target memory cell, and wherein the operating conditions for producing a retention value corresponding to the test conditions match the operating conditions for producing the measured retention value.

12. The method according to claim 1, wherein: The reference information includes a reference table including a plurality of combinations of the exposure time, the holding value, and the exposure temperature.

13. The method according to claim 1, wherein: The reference information includes a function having inputs of the exposure time and the holding value, and an output of the exposure temperature.

14. The method according to claim 1, wherein: The reference information includes an artificial neural network having inputs of the exposure time and the hold value and an output of the exposure temperature.

15. The method according to claim 14, comprising: Generate the reference information, wherein generating the reference information comprises: generating training data including a plurality of combinations of the exposure time, the holding value, and the exposure temperature; and The artificial neural network is trained based on the training data.

16. The method according to claim 1, comprising: The monitoring data is set so that the target memory cell is programmed to a state corresponding to a highest threshold voltage distribution.

17. The method according to claim 1, comprising: Disposing an aggressor memory cell adjacent to the target memory cell; as well as The aggressor memory cells are maintained in an erased state.

18. A storage device, comprising: a nonvolatile memory device configured to store reference information indicating a relationship between an exposure condition and a retention value, wherein the exposure condition includes an exposure temperature and an exposure time of the nonvolatile memory device, and wherein the retention value indicates a retention characteristic of the nonvolatile memory device; and A storage controller configured to: Before a power-off time point at which the nonvolatile memory device is powered off, writing monitoring data into a target memory cell included in the nonvolatile memory device; generating a measured retention value based on data from the target memory cell after a power-on time point at which the nonvolatile memory device is powered on; and A temperature to which the nonvolatile memory device is exposed when powered off is determined based on the reference information, the measured retention value, and an exposure time between the power-off time point and the power-on time point.

19. The storage device according to claim 18, wherein: The nonvolatile memory device is a three-dimensional NAND flash memory device in which memory cells are stacked in a vertical direction.

20. A method of providing an exposure temperature, comprising: writing first monitoring data into a test memory cell included in a test nonvolatile memory device; exposing the test non-volatile memory device to test conditions in a test environment, the test conditions including a test temperature and a test time; generating a retention value corresponding to the test condition based on data from the test memory cell after the test nonvolatile memory device is exposed to the test condition; generating reference information based on the test time, the hold value, and the test temperature; Before a power-off time point at which the nonvolatile memory device is powered off, writing second monitoring data into a target memory cell included in the nonvolatile memory device; After a power-on time point when the nonvolatile memory device is powered on, a measured retention value is generated based on the data from the target memory cell, wherein the measured retention value includes at least one of the following: the number of target memory cells having a threshold voltage higher than the monitoring voltage, a number of target memory cells having a threshold voltage between a first monitor voltage and a second monitor voltage, and a number of error bits of data from the target memory cell; as well as A temperature to which the nonvolatile memory device is exposed when powered off is determined based on the reference information, the measured retention value, and an exposure time between the power-off time point and the power-on time point.

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