Data reading method of memory, memory controller and related equipment

Abstract

The invention provides a data reading method of a memory, a memory controller and related equipment, and relates to the technical field of data storage, and the method comprises the following steps: obtaining a reading instruction used for reading target data in a source memory; in a prefetching mode, if the target data does not hit the data from the source memory stored in the temporary memory, reading the target data from the source memory in response to the reading instruction, and loading a predetermined amount of data after the target data in the source memory to the temporary memory; in a prefetching mode, if the target data hits the data from the source memory stored in the temporary memory, the target data is read from the temporary memory in response to the reading instruction, and the data reading efficiency of the temporary memory is higher than the data reading efficiency of the source memory. According to the invention, the efficiency of reading data from the low-speed memory by the high-speed interface can be improved.

Description

Technical Field

[0001] The present application relates to the technical field of data storage, and in particular to a data reading method of a memory, a memory controller and related equipment. Background Art

[0002] Currently, when the central processing unit reads data from a low-speed memory based on a high-speed interface, it is limited by the reading rate of the low-speed memory, so that the data reading performance of the high-speed interface cannot be fully utilized, which in turn leads to the low actual efficiency of the central processing unit in reading and writing data.

[0003] That is to say, based on the data reading method provided by the related art, the efficiency of reading data from the low-speed memory through the high-speed interface is low. Summary of the invention

[0004] The purpose of the present application is to provide a memory data reading method, a memory controller and related equipment, which are used to solve the technical problem of low reading efficiency when reading data from a low-speed memory through a high-speed interface in the data reading method provided by the related art.

[0005] In a first aspect, an embodiment of the present application provides a method for reading data from a memory, the method comprising:

[0006] Obtaining a read instruction, wherein the read instruction is used to read target data in a source memory;

[0007] In the pre-fetch mode, if the target data does not hit the data from the source memory stored in the temporary memory, in response to the read instruction, read the target data from the source memory and load a predetermined amount of data after the target data in the source memory into the temporary memory;

[0008] In the pre-fetch mode, if the target data hits the data from the source memory stored in the temporary memory, the target data is read from the temporary memory in response to the read instruction,

[0009] The data reading efficiency of the temporary memory is higher than the data reading efficiency of the source memory.

[0010] In a second aspect, an embodiment of the present application further provides a memory controller, the memory controller comprising:

[0011] a first memory interface connected to the source memory;

[0012] a second memory interface connected to the temporary memory;

[0013] an access interface connected to the bus, used to obtain a read instruction, wherein the read instruction is used to read target data in the source memory;

[0014] In the prefetch mode, if the target data does not hit the data from the source memory stored in the temporary memory, in response to the read instruction, read the target data from the source memory through the access interface and the first memory interface, and load a predetermined amount of data after the target data in the source memory into the temporary memory through the first memory interface and the second memory interface;

[0015] In the pre-fetch mode, if the target data hits the data from the source memory temporarily stored in the temporary memory, in response to the read instruction, reading the target data from the temporary memory through the access interface and the second memory interface;

[0016] The data reading efficiency of the temporary memory is higher than the data reading efficiency of the source memory.

[0017] In a third aspect, an embodiment of the present application provides an electronic device, comprising a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements the steps of the method described in the first aspect.

[0018] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the method described in the first aspect are implemented.

[0019] In a fifth aspect, an embodiment of the present application provides a computer program product, comprising computer instructions, which, when executed by a processor, implement the steps of the method described in the first aspect.

[0020] In the present application, a temporary memory with a higher data reading rate is used to cache a predetermined amount of data in the source memory. After a read instruction is obtained, it is determined whether the target data to be read by the read instruction hits the data from the source memory stored in the temporary memory. If so, the target data is read from the temporary memory to circumvent the limitation of the data reading rate of the source memory and improve the actual reading efficiency of the target data. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a flowchart of a method for reading data from a memory provided in an embodiment of the present application;

[0022] Figure 2 This is a support provided by the embodiment of the present application. Figure 1The hardware architecture diagram of the data reading method shown;

[0023] Figure 3 It is a schematic diagram of changes in cached data in a temporary memory before and after data reading provided by an embodiment of the present application;

[0024] Figure 4 It is a schematic diagram of another change of cached data in a temporary memory before and after data reading provided by an embodiment of the present application;

[0025] Figure 5 This is a schematic diagram of another change of cached data in a temporary memory before and after data reading provided by an embodiment of the present application;

[0026] Figure 6 It is a schematic diagram of another change of cached data in a temporary memory before and after data reading provided by an embodiment of the present application;

[0027] Figure 7 is a structural schematic diagram of a memory controller provided by an embodiment of the present application;

[0028] Figure 8 It is a structural schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0029] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0030] See also Figure 1 , Figure 1 It is a flowchart of a method for reading data from a memory provided in an embodiment of the present application.

[0031] like Figure 1 As shown, the data reading method of the memory includes:

[0032] Step 101: Get a read instruction.

[0033] The read instruction is used to read target data in the source memory, and the target data can be understood as any data among multiple data stored in the source memory.

[0034] It should be understood that the target data may be a piece of data in the source memory, or may be a plurality of data with data addresses increasing continuously in the source memory.

[0035] Step 102: In prefetch mode, if the target data does not hit the data from the source memory stored in the temporary memory, then in response to the read instruction, the target data is read from the source memory, and a predetermined amount of data after the target data in the source memory is loaded into the temporary memory.

[0036] Step 103: In the pre-fetch mode, if the target data hits the data from the source memory stored in the temporary memory, the target data is read from the temporary memory in response to the read instruction.

[0037] The data reading efficiency of the temporary memory is higher than the data reading efficiency of the source memory.

[0038] The present application is configured with a prefetch mode and a non-prefetch mode, wherein in the prefetch mode, the data in the source memory is placed in the temporary memory as a cache in the manner shown in step 102 and step 103, so that when the target data hits the data from the source memory stored in the temporary memory, the target data is directly read from the temporary memory rather than the source memory, thereby circumventing the limitation of the data reading rate of the source memory and improving the actual reading efficiency of the target data.

[0039] In the non-prefetch mode, target data is read from the source memory in response to the read instruction.

[0040] Without loss of generality, the non-prefetch mode is a mode enabled by default, and whether to enter the prefetch mode is selected by configuring a mode register.

[0041] In some implementations, the pre-fetch mode and the non-pre-fetch mode may be switched manually or by setting a program.

[0042] In one example, the processing flow corresponding to the setting program may be:

[0043] Get data reading information;

[0044] In a case where the data read information indicates that a plurality of data are to be read from the source memory in sequence from low to high data addresses, the pre-fetch mode is enabled.

[0045] For example, when the chip starts, the process of the host loading data from the source memory can be understood as reading multiple data from the source memory in sequence according to the data address from low to high. Alternatively, in the network model training phase, the process of loading the training data set to the server can also be understood as reading multiple data from the source memory in sequence according to the data address from low to high.

[0046] Exemplarily, as mentioned above, when training an artificial intelligence model, the process of the central processing unit (CPU) reading the memory in ascending order according to the data address can be understood as reading multiple data from the source memory in sequence according to the data address from low to high. At this time, after the CPU reads a piece of data from the memory, it will perform corresponding algorithm processing. After the algorithm processing is completed, the CPU will continue to read the next piece of data from the memory. During the algorithm processing, by caching the next data that may be read in a temporary memory in advance, the reading rate of the next data can be accelerated to a certain extent, so as to achieve effective utilization of time resources during non-data reading and writing processing operations (such as the period of performing corresponding algorithm processing on the currently read data), so that the overall data reading and writing efficiency of the CPU during the model training process is significantly improved.

[0047] In one embodiment, the target data not hitting the data from the source memory stored in the temporary memory comprises:

[0048] If the operation indicated by the instruction preceding the read instruction is a write operation, it is considered that the target data accessed by the read instruction does not hit the data from the source memory stored in the temporary memory;

[0049] or,

[0050] If the read instruction is the first read instruction received after entering the prefetch mode, it is considered that the target data accessed by the read instruction misses the data from the source memory stored in the temporary memory;

[0051] or,

[0052] If the first address of the target data accessed by the read instruction does not fall within the address range of the data from the source memory stored in the temporary memory, it is considered that the target data accessed by the read instruction misses the data from the source memory stored in the temporary memory.

[0053] Among them, in the case where the operation indicated by the previous instruction of the read instruction is a write operation, it is determined that the target data does not hit the data from the source memory stored in the temporary memory, so as to read the target data from the source memory, thereby ensuring the consistency and security of data reading and writing, and avoiding data errors caused by confusion in read and write operations.

[0054] As for the case where the read instruction is the first read instruction received after entering the prefetch mode, since the temporary memory does not store the data from the source memory at this time, it is determined that the target data does not hit the data from the source memory stored in the temporary memory, so as to read the target data from the source memory, so as to avoid program errors caused by failure to read the target data from the temporary memory, and at the same time, utilize the time of reading the target data from the source memory to load a predetermined amount of data after the target data in the source memory into the temporary memory, thereby initializing the temporary memory.

[0055] In one embodiment, if the first address of the target data accessed by the read instruction falls within the address range of the data from the source memory stored in the temporary memory, it is considered that the target data accessed by the read instruction hits the data from the source memory stored in the temporary memory.

[0056] The first address of the target data read by the read instruction is the address of the data corresponding to the first address of the target data read by the read instruction in the source memory, the first address of the address range is the address of the earliest data from the source memory stored in the temporary memory in the source memory, and the last address of the address range is the address of the latest data from the source memory stored in the temporary memory in the source memory.

[0057] In one embodiment, if the target data hits the data from the source memory stored in the temporary memory, when the target data is read from the temporary memory in response to the read instruction, the data after the latest data stored in the temporary memory in the source memory are loaded into the temporary memory in sequence starting from the first address of the temporary memory in accordance with the address sequence until the data corresponding to the tail address of the target data accessed by the read instruction in the temporary memory is overwritten.

[0058] When reading the target data from the temporary storage, after reading the tail address of the temporary storage, the next address of the temporary storage to be read is the head address of the temporary storage.

[0059] When loading data into the temporary memory, after writing to the tail address of the temporary memory, the next address of the temporary memory to be written is the head address of the temporary memory.

[0060] The latest data stored in the temporary memory can be understood as: the data loaded from the source memory to the temporary memory at the latest; that is, the data whose data address in the source memory is the last among the multiple data stored in the temporary memory.

[0061] For example: if the multiple data stored in the temporary memory are data1 to data10, wherein the data addresses of data1 to data10 in the temporary memory are 1-10 respectively, and the data addresses of data1 to data10 in the source memory are also 1-10 respectively, then the data after the latest data stored in the temporary memory in the source memory is data11 at data address 11. When the target data accessed by the read instruction is data3, while responding to the read instruction to read data3 from the temporary memory, at the position where the data address of the temporary memory is 1, data11 taken out from the source memory is used to overwrite the data1 stored at the position. Similarly, at the position where the data address of the temporary memory is 2, data12 taken out from the source memory is used to overwrite the data2 stored at the position. At the position where the data address of the temporary memory is 3, data13 taken out from the source memory is used to overwrite the data3 stored at the position. After reading the target data data3, the multiple data stored in the temporary memory become data4-data13.

[0062] Through the above settings, when data is not read sequentially according to the data address in the source memory (such as skipping), it is not necessary to wait for the target data to be read before starting to update the data cache in the temporary memory. Instead, the data cache in the temporary memory can be updated during the target data reading process, thereby speeding up the data cache efficiency in the temporary memory and further improving the overall data reading efficiency.

[0063] It should be emphasized that starting to update the data cache in the temporary memory during the target data reading process should be understood as: starting to fetch data after the latest data stored in the temporary memory from the source memory at the same time as starting to read the target data.

[0064] In one embodiment, when reading the target data from the temporary storage, if the data in the address of the temporary storage to be read next is earlier than the data in the address of the temporary storage to be read currently, and the target data has not been read completely, it is necessary to wait until the data from the source storage is loaded into the address of the temporary storage to be read next.

[0065] The step of loading a predetermined amount of data after the target data in the source memory into the temporary memory is specifically as follows: loading a predetermined amount of data after the target data in the source memory into the temporary memory in sequence starting from the first address of the temporary memory in accordance with the address sequence,

[0066] The effective capacity of the temporary storage is configured to be equal to the predetermined capacity.

[0067] In this embodiment, in order to solve the problem of data address crossing boundaries that may exist in the process of reading target data, the above settings are used to ensure the integrity and consistency of the target data reading operation.

[0068] In one embodiment, when the data corresponding to the first address of the target data is read from the temporary memory in response to the read instruction, the data after the latest data stored in the temporary memory in the source memory is simultaneously loaded into the temporary memory starting from the first address of the temporary memory.

[0069] In this embodiment, through the above settings, it is not necessary to wait for the target data to be read before starting to update the data cache in the temporary storage device. Instead, the data cache in the temporary storage device can be updated during the target data reading process, thereby speeding up the data cache efficiency in the temporary storage device to further improve the overall data reading efficiency; and starting to update from the data after the latest data stored in the temporary storage device in the source storage device can also avoid invalid data update operations and save time for updating the data cache in the temporary storage device.

[0070] For ease of understanding, the following examples are provided. Figure 2 The system block diagram shown implements the solution described in the present application, the AHB bus is specifically an advanced high-performance bus (Advanced High-performance Bus), the pseudo static random access memory (PSRAM) can be understood as the aforementioned source memory, the static random access memory (SRAM) can be understood as the aforementioned temporary memory, and the aforementioned prefetch mode and non-prefetch mode can be configured through registers, specifically:

[0071] In non-prefetch mode, the AHB bus reads data from the PSRAM directly from the read FIFO.

[0072] In the prefetch mode, the data in the PSRAM is first written into the 1KB SRAM through the PSRAM interface module (the PSRAM interface module is responsible for the PSRAM interface timing conversion, data bit width conversion and other functions), the read FIFO module, and the SRAM interface module (the SRAM interface module is responsible for the SRAM interface timing conversion and other functions). If the current read data has been cached in the SRAM (that is, the aforementioned target data hits the M data in the temporary storage), the AHB bus reads the data directly from the SRAM.

[0073] When the register-controlled pre-read function is turned on, each time the AHB bus reads data from a PSRAM, the controller will automatically cache the 1KB of data after the PSRAM read address into the SRAM;

[0074] When AHB reads the next PSRAM address, the controller will determine the relationship between the current PSRAM address and the last PSRAM address. If the current PSRAM address hits the cache data in SRAM, the controller will directly read the corresponding data in SRAM to AHB.

[0075] It should be understood that Figure 2 Although the storage space of PSRAM is set to 64M bytes and the storage space of SRAM is set to 1K bytes, in actual applications, the storage space of the two can be adaptively adjusted based on actual needs, for example: 64M bytes can be modified to 128M bytes, 256M bytes; 1K bytes can be modified to 512 bytes, 2K bytes, etc.

[0076] In one example, if the target data hits the data from the source memory stored in the temporary memory, then in response to the read instruction, the process of reading the target data from the temporary memory may be as follows: Figure 3 As shown, Figure 3 In the example, before reading the target data, the data from the source memory stored in the temporary memory is data1-data1024. When the target data is data1-data16, the process of reading the target data is:

[0077] First, data1-data8 are read from the data address 0x000-0x007 in the temporary memory, and then data9-data16 are read from the data address 0x008-0x00f in the temporary memory. It should be noted that while data1 is read from the data address 0x000 in the temporary memory, a read operation is also performed on the source memory (starting from data1025) and overwriting the data in the temporary memory (starting from the address 0x000 of the temporary memory). Finally, data16 is read from the data address 0x00f in the temporary memory, that is, data1040 is finally taken out from the source memory and overwrites data16 at the data address 0x00f in the temporary memory. Since the rate of reading the temporary memory is greater than the rate of reading the source memory, there is no rate mismatch problem. It should be understood that, Figure 3 The data portion surrounded by the bold line is the data portion that is updated in the temporary storage during the process of reading the target data.

[0078] In another example, if the target data hits the data from the source memory stored in the temporary memory, then in response to the read instruction, the process of reading the target data from the temporary memory may be as follows: Figure 4 As shown, Figure 4 In the example, before reading the target data, the data from the source memory stored in the temporary memory is data1-data1024. When the target data is data17-data32, the process of reading the target data is:

[0079] First, data17-data24 are read from the data address 0x010-0x017 in the temporary memory, and then data25-data32 are read from the data address 0x018-0x01f in the temporary memory. It should be noted that while data17 is read from the data address 0x010 in the temporary memory, a read operation is also performed on the source memory (starting from data1025) and overwriting the data in the temporary memory (starting from address 0x000 in the temporary memory). Finally, data32 is read from the data address 0x01f in the temporary memory, that is, data1056 is finally taken out from the source memory and overwrites data32 at the data address 0x01f in the temporary memory. Since the rate of reading the temporary memory is greater than the rate of reading the source memory, there is no rate mismatch problem. It should be understood that, Figure 4 The data portion surrounded by the bold line is the data portion that is updated in the temporary storage during the process of reading the target data.

[0080] In another example, if the target data hits the data from the source memory stored in the temporary memory, then in response to the read instruction, the process of reading the target data from the temporary memory may be as follows: Figure 5 As shown, Figure 5 In the example, before reading the target data, the data from the source memory stored in the temporary memory is data1-data1024. When the target data is data1017-data1032, the process of reading the target data is:

[0081] First, data1017-data1024 is read from the data address 0x3f8-0x3ff in the temporary memory, and then data1025-data1032 is read from the data address 0x000-0x007 in the temporary memory (that is, after reading the tail address 0x3f8-0x3ff of the temporary memory, the next read position is the first address 0x000-0x007 of the temporary memory). Similar to the previous example, while reading data1017 from the data address 0x3f8 in the temporary memory, a read operation is also performed on the source memory (starting from data1025) and overwriting the data in the temporary memory (starting from the address 0x000 of the temporary memory). It should be noted that when reading data from the data address 0x000-0x007 in the temporary memory, it is necessary to wait for the data data1025-data1032 stored in the source memory to be written to the temporary memory before reading the data data1025-data1032. Since data1032 is finally read out from the data address 0x007 in the temporary memory, data2056 is finally taken out from the source memory and overwrites data1032 at the data address 0x007 in the temporary memory. It should be understood that Figure 5 The data portion surrounded by the bold line is the data portion that is updated in the temporary storage during the process of reading the target data.

[0082] Exemplarily, if the target data does not hit the data from the source memory stored in the temporary memory, then in response to the read instruction, the target data is read from the source memory, and after the reading is completed, a predetermined amount of data after the target data in the source memory is loaded into the temporary memory. The process can be as follows: Figure 6 As shown, Figure 6 In the example, before reading the target data, the data from the source memory stored in the temporary memory is data1-data1024. When the target data is data1040-data1056, the process of reading the target data is:

[0083] After reading data1040-data1056 from the source memory, data1057-data2080 taken out from the source memory will overwrite data1-data1024 in the temporary memory in sequence. It should be understood that Figure 6 The data portion surrounded by the bold line is the data portion that is updated in the temporary storage during the process of reading the target data.

[0084] Based on the above settings, by utilizing the characteristic that the reading rate of SRAM is much higher than the reading rate of PSRAM, the data reading efficiency of the AHB bus can be significantly improved when the AHB bus reads the continuously increasing address in the PSRAM.

[0085] In the simulation test, the pre-read SRAM was set to 512 bytes in size, and a total of 1922 PSRAM read operations were performed (reading continuously increasing addresses and 64 bytes each time). Statistics show that 62 of them were slow reads (reading 64 bytes requires 57 to 61 AHB clock cycles), and 1860 were fast reads (reading 64 bytes only requires 10 AHB clock cycles). It can be seen that 96.8% of the continuous PSRAM read operations are fast reads, which greatly improves the efficiency of AHB reading PSRAM continuously increasing addresses.

[0086] The present application also provides a memory controller, such as Figure 7 As shown, the memory controller 700 includes:

[0087] A first memory interface 701 connected to a source memory;

[0088] A second memory interface 702 connected to the temporary memory;

[0089] An access interface 703 connected to the bus, used to obtain a read instruction, wherein the read instruction is used to read target data in the source memory;

[0090] In the pre-fetch mode, if the target data does not hit the data from the source memory stored in the temporary memory, in response to the read instruction, the target data is read from the source memory through the access interface 703 and the first memory interface 701, and a predetermined amount of data after the target data in the source memory is loaded into the temporary memory through the first memory interface 701 and the second memory interface 702;

[0091] In the pre-fetch mode, if the target data hits the data from the source memory temporarily stored in the temporary memory, in response to the read instruction, the target data is read from the temporary memory through the access interface 703 and the second memory interface 702;

[0092] The data reading efficiency of the temporary memory is higher than the data reading efficiency of the source memory.

[0093] In one embodiment, in the non-prefetch mode, in response to the read instruction, the target data is read from the source memory through the access interface 703 and the first memory interface 701 .

[0094] In one embodiment, the target data not hitting the data from the source memory stored in the temporary memory comprises:

[0095] If the operation indicated by the instruction preceding the read instruction is a write operation, it is considered that the target data accessed by the read instruction does not hit the data from the source memory stored in the temporary memory; or,

[0096] If the read instruction is the first read instruction received after entering the pre-fetch mode, it is considered that the target data accessed by the read instruction does not hit the data from the source memory stored in the temporary memory; or,

[0097] If the first address of the target data accessed by the read instruction does not fall within the address range of the data from the source memory stored in the temporary memory, it is considered that the target data accessed by the read instruction misses the data from the source memory stored in the temporary memory.

[0098] In one embodiment, if the first address of the target data accessed by the read instruction falls within the address range of the data from the source memory stored in the temporary memory, it is considered that the target data accessed by the read instruction hits the data from the source memory stored in the temporary memory.

[0099] The first address of the target data read by the read instruction is the address of the data corresponding to the first address of the target data read by the read instruction in the source memory, the first address of the address range is the address of the earliest data from the source memory stored in the temporary memory in the source memory, and the last address of the address range is the address of the latest data from the source memory stored in the temporary memory in the source memory.

[0100] In one embodiment, if the target data hits the data from the source memory stored in the temporary memory, when the target data is read from the temporary memory in response to the read instruction through the access interface 703 and the second memory interface 702, the data after the latest data stored in the temporary memory in the source memory is loaded into the temporary memory in sequence starting from the first address of the temporary memory in accordance with the address sequence, through the first memory interface 701 and the second memory interface 702, until the data corresponding to the tail address of the target data accessed by the read instruction in the temporary memory is covered,

[0101] When reading the target data from the temporary storage, after reading the tail address of the temporary storage, the next address of the temporary storage to be read is the head address of the temporary storage.

[0102] When loading data into the temporary memory, after writing to the tail address of the temporary memory, the next address of the temporary memory to be written is the head address of the temporary memory.

[0103] In one embodiment, when the target data is read from the temporary memory through the access interface 703 and the second memory interface 702, if the data in the address of the temporary memory to be read next is earlier than the data in the address of the temporary memory to be read currently, and the target data has not been read completely, it is necessary to wait until the data from the source memory is loaded into the address of the temporary memory to be read next.

[0104] The method of loading a predetermined amount of data after the target data in the source memory into the temporary memory through the first memory interface 701 and the second memory interface 702 is as follows: loading a predetermined amount of data after the target data in the source memory into the temporary memory in sequence starting from the first address of the temporary memory in accordance with the address sequence through the first memory interface 701 and the second memory interface 702;

[0105] The effective capacity of the temporary storage is configured to be equal to the predetermined capacity.

[0106] In one embodiment, when the data corresponding to the first address of the target data is read from the temporary memory in response to the read instruction through the access interface 703 and the second memory interface 702, the data after the latest data stored in the temporary memory in the source memory is simultaneously loaded into the temporary memory starting from the first address of the temporary memory through the first memory interface 701 and the second memory interface 702.

[0107] In some embodiments, the working clock of the advanced high-performance bus can be 200MHz, and the bit width of 64 bits can be 1.6GB / s in read / write speed; the source memory 403 can be a pseudo static random access memory (PSRAM) with a working clock of 32MHz, a bit width of 8 bits, a read / write speed of 64MB / s, and a storage capacity of 64MB; the temporary memory 404 can be a static random access memory (SRAM) with a working clock of 200MHz, a bit width of 64 bits, a read / write speed of 1.6GB / s, and a storage capacity of 1KB;

[0108] In this implementation, the structure formed by the PSRAM, the PSRAM controller and the SRAM can be roughly understood as a large-capacity high-speed memory with a cache function.

[0109] A memory controller 700 provided in an embodiment of the present application can implement each process in the above-mentioned memory data reading method embodiment, and will not be described again here to avoid repetition.

[0110] Figure 8 A schematic block diagram of an example electronic device 800 that can be used to implement an embodiment of the present application is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workbenches, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present application described and / or required herein.

[0111] like Figure 8 As shown, the device 800 includes a computing unit 801, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 802 or a computer program loaded from a storage unit 808 to a random access memory (RAM) 803. In the RAM 803, various programs and data required for the operation of the device 800 can also be stored. The computing unit 801, the ROM 802, and the RAM 803 are connected to each other via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0112] A number of components in the device 800 are connected to the I / O interface 805, including: an input unit 806, such as a keyboard, a mouse, etc.; an output unit 807, such as various types of displays, speakers, etc.; a storage unit 808, such as a disk, an optical disk, etc.; and a communication unit 809, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 809 allows the device 800 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0113] The computing unit 801 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSP), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 801 performs the various methods and processes described above, such as a data reading method of a memory. For example, in some embodiments, the data reading method of a memory may be implemented as a computer software program, which is tangibly included in a machine-readable medium, such as a storage unit 808. In some embodiments, part or all of the computer program may be loaded and / or installed on the device 800 via the ROM 802 and / or the communication unit 809. When the computer program is loaded into the RAM 803 and executed by the computing unit 801, one or more steps of the data reading method of the memory described above may be executed. Alternatively, in other embodiments, the computing unit 801 may be configured to execute the memory data reading method in any other appropriate manner (for example, by means of firmware).

[0114] Various embodiments of the systems and techniques described above herein may be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0115] The program code for implementing the method of the present application can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, implements the functions / operations specified in the flow chart and / or block diagram. The program code can be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0116] In the context of the present application, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0117] As used herein, the term "machine-readable medium" refers to any computer program product, apparatus, and / or device (e.g., disk, optical disk, memory, programmable logic device (PLD)) for providing machine instructions and / or data to a programmable processor, including a machine-readable medium that receives machine instructions as a machine-readable signal. The term "machine-readable signal" refers to any signal for providing machine instructions and / or data to a programmable processor.

[0118] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0119] The systems and techniques described herein may be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), and the Internet.

[0120] A computer system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The relationship of client and server is generated by computer programs running on respective computers and having a client-server relationship with each other. The server may be a cloud server, a server of a distributed system, or a server combined with a blockchain.

[0121] The present application also provides a computer program product, including computer instructions, which, when executed by a processor, implement the above Figure 1 The various processes of the method embodiment shown can achieve the same technical effect, and will not be described again here to avoid repetition.

[0122] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this application can be executed in parallel, sequentially or in different orders, as long as the expected results of the technical solution disclosed in this application can be achieved, and this document is not limited here.

[0123] The above specific implementations do not constitute a limitation on the protection scope of this application. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of this application should be included in the protection scope of this application.

Claims

1. A method for reading data from a memory, characterized in that the method comprises: Obtaining a read instruction, wherein the read instruction is used to read target data in a source memory; In the pre-fetch mode, if the target data does not hit the data from the source memory stored in the temporary memory, in response to the read instruction, read the target data from the source memory and load a predetermined amount of data after the target data in the source memory into the temporary memory; In the pre-fetch mode, if the target data hits the data from the source memory stored in the temporary memory, the target data is read from the temporary memory in response to the read instruction, in, The data reading efficiency of the temporary memory is higher than the data reading efficiency of the source memory.

2. The method according to claim 1, characterized in that In the non-prefetch mode, the target data is read from the source memory in response to the read instruction.

3. The method according to claim 1, characterized in that The target data misses the data from the source memory stored in the temporary memory, including: If the operation indicated by the instruction preceding the read instruction is a write operation, it is considered that the target data accessed by the read instruction does not hit the data from the source memory stored in the temporary memory; or, If the read instruction is the first read instruction received after entering the pre-fetch mode, it is considered that the target data accessed by the read instruction does not hit the data from the source memory stored in the temporary memory; or, If the first address of the target data accessed by the read instruction does not fall within the address range of the data from the source memory stored in the temporary memory, it is considered that the target data accessed by the read instruction misses the data from the source memory stored in the temporary memory.

4. The method according to claim 1, characterized in that: If the first address of the target data accessed by the read instruction falls within the address range of the data from the source memory stored in the temporary memory, it is considered that the target data accessed by the read instruction hits the data from the source memory stored in the temporary memory, The first address of the target data read by the read instruction is the address of the data corresponding to the first address of the target data read by the read instruction in the source memory, the first address of the address range is the address of the earliest data from the source memory stored in the temporary memory in the source memory, and the last address of the address range is the address of the latest data from the source memory stored in the temporary memory in the source memory.

5. The method according to claim 1, characterized in that If the target data hits the data from the source memory stored in the temporary memory, when the target data is read from the temporary memory in response to the read instruction, the data after the latest data stored in the temporary memory in the source memory are loaded into the temporary memory in sequence starting from the first address of the temporary memory in accordance with the address sequence until the data corresponding to the tail address of the target data accessed by the read instruction in the temporary memory is overwritten, When reading the target data from the temporary storage, after reading the tail address of the temporary storage, the next address of the temporary storage to be read is the head address of the temporary storage. When loading data into the temporary memory, after writing to the tail address of the temporary memory, the next address of the temporary memory to be written is the head address of the temporary memory.

6. The method according to claim 5, characterized in that When reading the target data from the temporary storage, if the data in the address of the temporary storage to be read next is earlier than the data in the address of the temporary storage to be read currently, and the target data has not been read completely, it is necessary to wait until the data from the source storage is loaded into the address of the temporary storage to be read next, The step of loading a predetermined amount of data after the target data in the source memory into the temporary memory is specifically as follows: loading a predetermined amount of data after the target data in the source memory into the temporary memory in sequence starting from the first address of the temporary memory in accordance with the address sequence, The effective capacity of the temporary storage is configured to be equal to a predetermined capacity.

7. The method according to claim 5, characterized in that When responding to the read instruction to read the data corresponding to the first address of the target data from the temporary memory, the data after the latest data stored in the temporary memory in the source memory is simultaneously loaded into the temporary memory starting from the first address of the temporary memory.

8. A memory controller, characterized in that: It includes: a first memory interface connected to the source memory; a second memory interface connected to the temporary memory; an access interface connected to the bus, used to obtain a read instruction, wherein the read instruction is used to read target data in the source memory; In the prefetch mode, if the target data does not hit the data from the source memory stored in the temporary memory, in response to the read instruction, read the target data from the source memory through the access interface and the first memory interface, and load a predetermined amount of data after the target data in the source memory into the temporary memory through the first memory interface and the second memory interface; In the pre-fetch mode, if the target data hits the data from the source memory temporarily stored in the temporary memory, in response to the read instruction, reading the target data from the temporary memory through the access interface and the second memory interface; The data reading efficiency of the temporary memory is higher than the data reading efficiency of the source memory.

9. An electronic device, characterized in that: The method comprises a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the computer program implements the steps of the method according to any one of claims 1 to 7 when executed by the processor.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

11. A computer program product, characterized in that The method comprises computer instructions, which, when executed by a processor, implement the steps of the method according to any one of claims 1 to 7.

Images