Storage system based on CPU and FPGA heterogeneous platform

Abstract

The invention relates to a storage system based on a CPU and FPGA heterogeneous platform, and the system comprises a CPU processor module which is used for task scheduling, resource distribution and internal and external communication of the storage system; the FPGA calculation module supports the calculation capability of the storage system and is connected with the CPU processor module through a PCIe interface; the PCIe SWITCH module is used for supporting a PCI (Peripheral Component Interconnect Express) exchange function of a plurality of hosts; the disk storage module is connected with the PCIe SWITCH module through a PCIe interface; the FPGA calculation module is configured to be connected to the disk storage module through a PCIe interface; the FPGA calculation module is configured to receive image data through the LRM connector, and the image data is transmitted to the CPU processor module after being calculated and processed by the FPGA calculation module and is stored in the disk storage module.

Description

Technical Field

[0001] The present invention relates to the field of computers, and in particular to an improved storage system based on a CPU and FPGA heterogeneous platform. Background Art

[0002] Since the beginning of the 21st century, computer technology has developed rapidly, and there are increasingly higher speed requirements for image data storage, especially in the fields of aviation, rail transportation, energy and power, and various image acquisition.

[0003] Traditional computer storage technology is mainly designed with CPU processors and mostly uses mechanical hard disk storage, which occupies a large space, volume and weight, and is difficult to use in specific scenarios where the volume / space is small and the weight must be as light as possible, for example, in the configuration and application of space shuttles, drones, unmanned vehicles, other types of unmanned aerial vehicles and other equipment.

[0004] In addition, if a storage system designed with a single CPU architecture is not compatible with the FPGA platform, it cannot meet the requirements for fast and real-time storage of data, especially large amounts of data, and the scalability of this type of architecture is poor; if a single FPGA architecture is used, the FPGA processing performance is limited (which is different from CPU multi-threaded processing). Since the FPGA architecture has limited processing performance and is not compatible with the CPU platform and the Linux system, it cannot be developed in the Linux environment, which makes it difficult for designers to develop. The equipment and R&D costs of the existing FPGA platform are too high, so the cost performance of the existing equipment is low.

[0005] In view of the above problems, the inventors of the present invention propose a new and improved storage system based on a CPU and FPGA heterogeneous platform and an operation method thereof.

[0006] The information included in this background section of the present specification, including any references cited herein and any description or discussion thereof, is included for technical reference purposes only and is not to be construed as subject matter that will limit the scope of the present invention. Summary of the invention

[0007] The present invention is proposed in view of the above and other more concepts.

[0008] One of the main purposes of the present invention is to integrate and utilize the advantages of the CPU architecture and FPGA architecture platforms, and can be based on the 6U LRM design, so that the final designed system platform occupies a small volume and is light in weight, and can meet the requirements of specific scenarios. The system has the characteristics of flexible design, good scalability, high reliability and fast data storage speed, and can achieve the complementarity of software and logic development to greatly improve the system's performance of high computing power, high storage speed and large capacity in a small space.

[0009] In order to solve the above problems, according to the concept of one aspect of the present invention, a storage system based on a CPU and FPGA heterogeneous platform is proposed, which adopts a CPU+FPGA heterogeneous fusion platform, which not only integrates the multi-threaded processing capability of the CPU, but can also be developed based on the Linux operating system (the Linux operating system is flexible in design, well extensible, and stable in operating system), and is also compatible with the fast and real-time data processing performance of the FPGA architecture. For example, the CPU can adopt the Feiteng D2000 / 4 processor based on ARM, with rich PCIE and its peripheral resources. One end of the PCIE3.0 x16 can be interconnected with the FPGA architecture platform to ensure sufficient bandwidth (x16); the other end of the PCIE3.0 x16 can be interconnected with the PCIE SWITCH module, and then connected to the disk storage board (the disk storage module thereon).

[0010] According to one aspect of the present invention, there is provided a storage system based on a heterogeneous platform of CPU and FPGA, the storage system comprising: a CPU processor module, configured to be used for task scheduling, resource allocation and internal and external communication of the storage system; an FPGA computing module, configured to support the computing capability of the storage system and connected to the CPU processor module via a PCIe interface; a PCIe SWITCH module, configured to support multi-host PCI Express switching function; a disk storage module, configured to be connected to the PCIe SWITCH module via a PCIe interface; wherein the FPGA computing module is configured to be connected to the disk storage module via a PCIe interface; wherein the FPGA computing module is configured to receive image data via an LRM connector, transmit the image data to the CPU processor module after computing and processing by the FPGA computing module, and store the image data in the disk storage module; and the storage system implements data transmission between the FPGA computing module and the CPU processor module via an XDMA method.

[0011] According to one embodiment, the CPU processor module is connected to the FPGA computing module via a PCIe3.0 x16 interface, and is connected to the PCIe SWITCH module via a PCIe3.0 x16 interface.

[0012] According to one embodiment, the FPGA computing module includes: an FPGA controller, a communication module, a file management module, a PCIe control module and a DDR4 memory module; wherein the FPGA controller is configured to receive an external command through the communication module and perform high-speed reading of image data; wherein the FPGA controller is configured to create a file management system through the file management module after receiving a command to store data, and the file management system is configured to manage files and assist the FPGA controller in data management;

[0013] Wherein, the PCIe control module is configured to transfer data from the FPGA computing module to the CPU processor module; and the DDR4 memory module is configured to support the computing power of the FPGA controller to help achieve its high-speed reading of image data.

[0014] According to one embodiment, the FPGA controller receives external control commands and data through an optical port and a GTH high-speed interface.

[0015] According to one embodiment, the DDR4 memory module supports a rate of 1600 MHz to 2400 MHz and a capacity range of 8 GB to 64 GB.

[0016] According to one embodiment, the disk storage module is composed of multiple NVMe SSD hard disks, which are configured to support PCIe3.0 interface and use RAID5 technology to achieve data redundancy.

[0017] According to one embodiment, the PCIe SWITCH module is configured to support 64-Lane, 16-Port PCIe Gen3 switching functions.

[0018] According to one embodiment, the CPU processor module is configured with a Feiteng FT2000 / 4 high-performance processor, which integrates multiple 64-bit cores and a PCIe interface; and the FPGA computing module is configured with an FPGA logic chip XCVU3P, which supports PCIe3.0x16 IP hard core and supports mounting a DDR4 memory module.

[0019] According to an embodiment, the storage system includes an IPMI health management module for monitoring a real-time status of the storage system, wherein the real-time status includes at least one of a current, a voltage, a temperature, and a program loading status of the storage system.

[0020] According to one embodiment, the storage system includes a first 6U LRM board and a second 6U LRM board interconnected by an LRM connector, wherein the first 6U LRM board acts as a storage control board configured to install the CPU processor module, FPGA computing module and PCIe SWITCH module, and the second 6U LRM board acts as a disk storage board configured to install the disk storage module.

[0021] According to an embodiment, the storage system can be advantageously used in an airborne or vehicle-mounted device, for example, in at least one of an aircraft, a drone, and an unmanned vehicle.

[0022] The storage system of the present invention can be applied in the computer field, and is mainly used in the storage of various image data. It is particularly suitable for use in specific scenarios such as small, limited space and limited mass, including drones, unmanned vehicles and other devices with small spaces, etc.

[0023] The storage system of the present invention adopts a CPU and FPGA heterogeneous design, aiming to integrate the advantages of CPU and FPGA, improve system stability and scalability, and has a flexible design, which greatly reduces the development difficulty for designers.

[0024] The storage system device of the present invention can be designed with two 6U LRM boards to meet the usage requirements of small space occupation and light weight in specific scenarios.

[0025] The storage system device of the present invention can adopt four modules, such as CPU processor module, FPGA calculation module, PCIe SWITCH module and disk storage module, thus forming the functional requirements of this assembly: the CPU processor module is used as the core of the entire storage system, mainly responsible for task scheduling, resource allocation and internal and external communication; the FPGA calculation module is used for the data calculation and cache capacity of the system; the PCIe SWITCH module is used to provide expanded PCIE resources; the disk storage module is used for disk storage media;

[0026] The storage system device of the present invention can use XDMA mode to realize data transmission between FPGA and CPU-FT2000 / 4, so as to improve system throughput and enhance data transmission efficiency, with a total bandwidth of up to 128Gbps.

[0027] The storage system device of the present invention can solve the following specific technical problems:

[0028] 1) The storage system device of the present invention can have a large-capacity storage function and support a maximum storage of 128TB.

[0029] 2) The storage system device of the present invention can receive data from external devices through optical ports (4 transmit and 4 receive) and GTH high-speed interfaces (8 channels), with a maximum write speed of 40 Gbps.

[0030] 3) The storage system device of the present invention can transmit data externally and perform human-computer interaction (DP display) through a Gigabit network port and a USB3.0 interface.

[0031] 4) The storage system device of the present invention can be connected to an NVMe SSD hard disk via a PCIe3.0 x4 bus, and can realize a fast storage function of image data.

[0032] 5) The storage system device of the present invention can provide a system IPMI health management function through the MCU, which is used to provide equipment status monitoring and automatic overheating protection functions.

[0033] Compared with the prior art, one or more embodiments of the present invention can achieve at least some beneficial effects such as but not limited to the following:

[0034] (1) The present invention can adopt a CPU and FPGA heterogeneous platform storage system, which has the characteristics of flexible design, good scalability, high reliability and fast data storage. The CPU and FPGA heterogeneous platform design integrates and integrates the advantages of the CPU and FPGA platforms (for example, the CPU uses Feiteng FT2000 / 4 high-performance processor, and the FPGA uses VU series VU3P to support PCIe3.0 x16IP hard core and mount DDR4 memory 16GB size), and uses the CPU's resource allocation, task scheduling capabilities and FPGA's computing power to achieve flexible system design, good scalability, and greatly reduce the difficulty of development for designers, thereby reducing manpower and material costs.

[0035] (2) In some embodiments of the present invention, the storage system may adopt a 6U LRM architecture design to meet the requirements of small space occupation and light weight of storage devices in small specific scenarios such as aircraft, drones, and unmanned vehicles.

[0036] (3) In some embodiments of the present invention, a PCIe SWITCH module can be used to support up to 16-lane PortGen3 devices, and support up to 128TB SSD storage capacity without occupying space and light weight, and support RAID technology.

[0037] (4) In some embodiments of the present invention, an XDMA hard core can be used to implement data transmission between the FPGA and the CPU, with a total bandwidth of up to 128 Gbps (8 Gbps*16), which greatly improves system throughput and enhances data transmission efficiency.

[0038] (5) In some embodiments of the present invention, an IPMI health management module may be used to monitor the real-time status of the device (current, voltage, temperature and program loading status) and provide feedback to the user, thereby achieving human-computer interaction and improving the robustness of the system.

[0039] More embodiments of the present invention can also achieve other advantageous technical effects that are not listed one by one. These other technical effects may be partially described below and are predictable and understandable to those skilled in the art after reading the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The above features and advantages of these embodiments and other features and advantages and the manner in which they are achieved will become more apparent, and embodiments of the present invention may be better understood, by referring to the following description taken in conjunction with the accompanying drawings, in which:

[0041] Figure 1 The present invention is a schematic block diagram of an exemplary principle and configuration of a storage system based on a CPU and FPGA heterogeneous platform according to an embodiment of the present invention.

[0042] Figure 2 The present invention is a schematic block diagram of the architecture, functional modules and configuration of a storage system based on a CPU and FPGA heterogeneous platform according to an embodiment of the present invention.

[0043] Figure 3 A schematic processing flow chart of FPGA computing module configuration and data storage according to an embodiment of the present invention.

[0044] Figure 4 The present invention is a schematic transmission flow chart of image data storage between a storage system based on a CPU and FPGA heterogeneous platform and an external device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0045] In the following description of the drawings and specific embodiments, the details of one or more embodiments of the present invention will be described. Other features, objects and advantages of the present invention will be apparent from these descriptions, drawings and claims.

[0046] It should be understood that the illustrated and described embodiments are not limited in application to the details of the construction and arrangement of the components set forth in the following description or illustrated in the accompanying drawings. The illustrated embodiments may be other embodiments and may be implemented or executed in various ways. Each example is provided by explaining the disclosed embodiments rather than limiting them. In fact, it will be apparent to those skilled in the art that various modifications and variations may be made to the embodiments of the present invention without departing from the scope or essence of the present invention. For example, a feature illustrated or described as part of one embodiment may be used together with another embodiment to still produce another embodiment. Therefore, the present invention discloses such modifications and variations that fall within the scope of the appended claims and their equivalent elements.

[0047] Likewise, it is understood that the phrases and terms used herein are for descriptive purposes and should not be considered restrictive. The use of "include," "comprise," or "have" and variations thereof herein is intended to be open-ended to include the items listed thereafter and their equivalents and additional items.

[0048] The present invention will be described in more detail below with reference to specific embodiments of the present invention.

[0049] Figure 1 The present invention is a schematic block diagram of an exemplary principle and configuration of a storage system based on a CPU and FPGA heterogeneous platform according to an embodiment of the present invention.

[0050] like Figure 1 As shown, a storage system based on a CPU and FPGA heterogeneous platform according to an embodiment of the present invention may include two boards, such as a 6U LRM board, and the two boards are divided into a storage control board and a disk storage board, which are interconnected through an LRM connector. Figure 1 The storage system based on the CPU and FPGA heterogeneous platform of the embodiment shown may include four modules: a CPU processor module, an FPGA computing module, a PCIe SWITCH module, and a disk storage module. Figure 1 As shown schematically, among the first 6U LRM board and the second 6U LRM board interconnected by the LRM connector, the first 6U LRM board acts as a storage control board configured to install a CPU processor module, an FPGA computing module and a PCIeSWITCH module, while the second 6U LRM board acts as a disk storage board configured to install a disk storage module.

[0051] Among them, the first 6U LRM board is used as a storage control board, and its main function is to serve as the main control core and communicate with the outside world to process data. The second 6U LRM board is a disk storage board, and its main function is to store data. This configuration and design, on the one hand, considers that the design space of the 6U standard size is limited, and it is difficult for one board to accommodate many IC chips, so it is restricted by various factors such as space and heat dissipation; on the other hand, the design uses two boards, and the second 6U LRM board can be flexibly designed, and a specific disk storage board (for example, 8T~128TB) can be selected according to the use requirements, without rework and repeated design, and it is more flexible to use.

[0052] In a preferred embodiment of the present invention, the above-mentioned boards all use 6U LRM boards. The 6U LRM architecture is a domestic high-performance aerospace electronic connector standard, which is widely used in data centers, cloud computing, supercomputing and other fields. The design concept of the 6U LRM architecture is high speed, low latency and reliability, which can meet the needs of high load and high concurrency (maximum transmission rate 12.5Gbps). The 6U standard size is 160x233.35mm. Considering that the airborne and vehicle-mounted equipment storage system of the present invention will be used in some specific occasions, and it is used in scenarios with strict requirements on weight and space, such as space shuttles, vehicles, drones, etc., the use of 6U LRM boards is a particularly advantageous solution, as described below.

[0053] The advantages of using 6U LRM boards include: meeting the strict requirements in some narrow and specific scenarios of airborne and vehicle-mounted equipment such as aircraft, drones, and unmanned vehicles, such as the use requirements of small space and light weight for storage devices; while occupying a small space and being light, the use of 6U LRM boards can also meet the needs of large-capacity data storage, supporting, for example, a maximum of 128TB, etc.; boards using 6U LRM architecture can also be applied to SEM-D, SEM-E, and ASAAC modules, are industry-wide, and are widely used in the Internet, advanced industry, and military fields.

[0054] In the present invention, for example Figure 1 In the storage system based on the CPU and FPGA heterogeneous platform shown in the figure, the CPU processor module is the core of the entire storage system, which is mainly responsible for task scheduling, resource allocation, and internal and external communications, and allocates 1 group of PCIe3.0 x16 interfaces (or card slots) to connect to the FPGA computing module to use its powerful computing power for data processing, and allocates another group of PCIe3.0 x16 interfaces (or card slots) to connect to the PCIe SWITCH module to expand 10 PCIe3.0 x4 interfaces for connecting to the disk storage module (i.e., Figure 1The NVMe SSD hard drive shown in the figure can be used as a data storage medium, and 1 PCIe3.0 x1 is interconnected with the X100 bridge chip; externally, the X100 is mainly used to expand the mSATA interface, USB3.0 interface and DP display for data communication and human-computer interaction functions.

[0055] In the present invention, for example Figure 1 In the storage system based on the CPU and FPGA heterogeneous platform shown, the PCIe SWITCH module can support up to 64-Lane, 16-Port PCIe Gen3 switch devices, providing multi-host PCI Express switching functions, enabling users to connect multiple hosts to their respective endpoints through scalable, high-bandwidth, non-blocking interconnections to connect various applications, including servers, storage, communications, and graphics platforms. The Host upstream end of the present invention can be connected to the CPU via PCIe x16, and the Slave downstream port can lead to 10 PCIe x4 for connecting to disk storage modules (i.e., Figure 1 NVMe SSD hard drive shown).

[0056] In the present invention, for example Figure 1 In the storage system based on the CPU and FPGA heterogeneous platform shown in the figure, the FPGA computing module can mainly receive image data from the external LRM connector through its optical port (4 receive and 4 transmit) and 8-way GTH high-speed interface, and then it can be processed and transmitted to the CPU through its powerful computing power, and finally stored in the disk storage module.

[0057] In the present invention, for example Figure 1 In the storage system based on the CPU and FPGA heterogeneous platform shown, the disk storage module can be composed of 10 NVMe SSD hard disks, for example, and the PCIe3.0 x4 interface can be used to ensure its high-speed storage capability. The single disk capacity of the hard disk can be 8TB. ​​Therefore, the maximum device capacity of the storage system of this embodiment of the present invention defaults to 80TB (maximum support 128TB), which can be implemented using RAID5 technology.

[0058] Figure 2 The present invention is a schematic block diagram of the architecture and functional module configuration of a storage system based on a CPU and FPGA heterogeneous platform according to an embodiment of the present invention.

[0059] like Figure 2 As shown, the FPGA computing module may include an FPGA controller, a communication module, a file management module, a PCIe control module, and a DDR4 memory module. Figure 2 As shown, the data storage processing flow of the FPGA computing module may include the following:

[0060] 1) The FPGA controller receives control commands and image data from the outside through the optical port and 8-way GTH high-speed interface (communication module).

[0061] 2) After receiving the command to start storing data, the FPGA controller simultaneously starts to create a file management system through the file management module.

[0062] 3) The FPGA controller obtains computing power through the DDR4 memory module (DDR4 rate 2400Mhz, maximum support 3200Mhz) to achieve fast reading and writing functions of stored data. As an example, the DDR4 memory module may include a DDR4 SDRAM with a capacity in the range of 8GB-128GB, such as in the range of 16GB-128GB.

[0063] 4) Then, the FPGA controller transmits the read data to the CPU processor through the PCIe control module (PCIe bus), and finally stores it in the disk storage module (e.g. Figure 1 NVMe SSD hard drive shown in the figure).

[0064] Figure 3 The present invention is a schematic processing flow chart of FPGA computing module configuration and data storage of a storage system based on a CPU and FPGA heterogeneous platform according to an embodiment of the present invention.

[0065] like Figure 3 As shown, the CPU of the storage system based on the CPU and FPGA heterogeneous platform can use the Tianjin Feiteng FT2000 / 4 high-performance processor, which integrates four 64-bit FTC663 high-performance cores, with a main frequency of 2.6GHz, integrated 34-Lane PCIe3.0 interface (2 PCIe x16 and 1 x1 interface), 2 Gigabit Ethernet network ports, onboard 16GB of Changxin Technology's DDR4 memory particles, built-in password acceleration engine, integrated system-level security mechanism, and can meet the performance requirements and security and trust requirements in complex application scenarios. The functional bus communication process of each module of the storage system based on the CPU and FPGA heterogeneous platform is as follows:

[0066] 1) The CPU is connected to the PLX8764 PCIE bridge chip through PCIe3.0 x16, and expands 10 PCIE3.0 interfaces to the outside, and connects 10 8TB NVME solid-state drives of the disk storage module through the LRM connector.

[0067] 2) The CPU is connected to the XILINX Ultrascal-Plus FPGA logic chip XCVU3P through another set of PCIe3.0 x16, and expands 4 high-speed interfaces (optical port output) and 8 GTH high-speed interfaces.

[0068] 3) The CPU is connected to the X100 bridge chip through the PCIE X1 channel, providing 1 USB3.0, 2 USB2.0, DP display interface and mSATA hard disk interface for storing CPU system images.

[0069] 4) The CPU controls the power-on timing of the entire board, interface level conversion, and communication control logic with IPMI through a CPLD module such as Gowin Semiconductor;

[0070] 5) The storage system based on CPU and FPGA heterogeneous platform can provide IPMI service through MCU chip APM32F407, mainly providing equipment status monitoring for obtaining information such as voltage, current, temperature, FPGA loading status, optical module status, etc.; it also provides overheat protection program and automatic power-off protection when the module temperature is too high.

[0071] Among them, the x100 bridge chip integrates a low-power GPU, an NPU neural network accelerator, a 64-bit DDR4 / LPDDR4 video memory controller (supports up to 8GB, 2666MT / rate), 8-way PCIe3.0 x1, and numerous USB interfaces, SATA interfaces, DP interfaces, serial ports, GPIO and other peripherals; in addition, the storage system based on the CPU and FPGA heterogeneous platform can integrate the whole machine control functions, such as power on and off control, reset control, low power control and temperature detection.

[0072] The CPLD module can be designed and implemented through the LittleBee series chip GW1N-UV9PG256. It has rich logic resources, supports multiple I / O level standards, and has built-in block static random access memory, digital signal processing module, and phase-locked loop resources. In addition, it can embed Flash resources and is a non-volatile CPLD product with low power consumption, instant start, low cost, high security, small product size, rich package types, and convenient and flexible use.

[0073] The IPMI module can use the APM32F407RGT6 MCU chip of Jihai Micro as the core, based on the ARM Cortex-M4 core, with a 168Mhz operating speed, 1MB Flash and 192KB RAM size, providing rich peripheral (external device) interfaces, up to 51 GPIOs, 4 USARTs, 16-channel ADC acquisition and 2-channel DAC output, etc.

[0074] Figure 4 The present invention is a schematic transmission flow chart of image data storage between a storage system based on a CPU and FPGA heterogeneous platform and an external device according to an embodiment of the present invention.

[0075] like Figure 4 As shown in the figure, the storage system based on the heterogeneous platform of CPU and FPGA can use the XDMA hard core method to implement data transmission (DMA data transmission) between FPGA and CPU (such as CPU-FT2000 / 4). Generally speaking, in the PCIe bus, there are two ways for data interaction between devices: PIO (Programmed Input Output) and DMA (Direct Memory Access). The former PIO data transmission requires the participation of the host's CPU / FPGA, and each transmission operation is executed according to the I / O instruction. It is not efficient when transmitting large-scale data and occupies CPU / FPGA resources. The second DMA method is more suitable for application scenarios where a large amount of data is moved. This method does not require the CPU / FPGA to directly participate in the data interaction operation, reducing the utilization rate of the CPU / FPGA in the data transmission operation. In contrast, the XDMA method can integrate the two parts of PCIe3.0 hard core and DMA control, realize high-bandwidth and selectable decentralized aggregation DMA control of the above PCIe3.0 hard core module, and can select the AXI interface in the configuration to interact with user logic data.

[0076] XDMA is a high-performance configurable SG DMA hard core that can have three user interfaces: AXI Stream interface, AXI Lite interface, and AXI4 interface. The XDMA IP core is a secondary encapsulation of the PCIe hard core integrated in the FPGA, which has higher development efficiency. The XDMA hard core has the logical functions of the physical layer, data link layer, and transaction layer in the PCIe protocol. The XDMA IP core can be composed of two parts: a PCIe3.0 hard core module and a DMA control module. It can achieve high-bandwidth, selectable decentralized aggregation DMA control of the above PCIe3.0 hard core module, and the AXI interface can be selected in the configuration to interact with user logic data.

[0077] In addition, the XDMA hard core can also provide user logic interfaces such as configuration management interface, interrupt control signal and clock reset signal. The process of image data transmission between the external device and the storage system based on the CPU and FPGA heterogeneous platform through XDMA includes the following steps:

[0078] S1. The system (storage system based on CPU and FPGA heterogeneous platform) applies for memory space according to the size of data storage capacity (executed multiple times) and loads the data to be transmitted.

[0079] S2. Create descriptors based on the requested memory space and organize the descriptors into a complete linked list.

[0080] S3.DMA driver writes the first address of the linked list into the descriptor base address register of DMA hard core BAR1 space and applies for DMA request.

[0081] S4. Then, the DMA engine starts to obtain the descriptor.

[0082] S5. After the data transfer is completed, the DMA engine checks whether the current descriptor is the last one. If not, it obtains the next descriptor address and repeats the above steps.

[0083] S6. After the data transfer is completed, the DMA engine checks whether the current descriptor is the last one. If the current descriptor is the last one, an interrupt is initiated and the data transfer is completed.

[0084] The foregoing description of several embodiments of the present invention is presented for illustrative purposes. The foregoing description is not intended to be exhaustive, nor is it intended to limit the present invention to the precise steps and / or forms disclosed, and it is apparent that many modifications and variations may be made in light of the above teachings. The scope of the present invention and all equivalents are intended to be defined by the appended claims.

Claims

1. A storage system based on a CPU and FPGA heterogeneous platform, characterized in that: The storage system comprises: A CPU processor module configured to be used for task scheduling, resource allocation, and internal and external communications of the storage system; An FPGA computing module, which is configured to support the computing capability of the storage system and is connected to the CPU processor module via a PCIe interface; a PCIe SWITCH module configured to support multi-host PCI Express switching; and a disk storage module configured to be connected to the PCIe SWITCH module via a PCIe interface; Wherein, the FPGA computing module is configured to be connected to the disk storage module via a PCIe interface; The FPGA calculation module is configured to receive image data through the LRM connector, transmit the image data to the CPU processor module after calculation and processing by the FPGA calculation module, and store the image data in the disk storage module; and The storage system realizes data transmission between the FPGA computing module and the CPU processor module through XDMA.

2. The storage system according to claim 1, characterized in that: The CPU processor module is connected to the FPGA computing module via a PCIe3.0x16 interface, and is connected to the PCIeSWITCH module via a PCIe3.0 x16 interface.

3. The storage system according to claim 1, characterized in that: The FPGA computing module includes: an FPGA controller, a communication module, a file management module, a PCIe control module and a DDR4 memory module; Wherein, the FPGA controller is configured to receive external commands through the communication module and perform high-speed reading of image data; Wherein, the FPGA controller is configured to create a file management system through the file management module after receiving a command to store data, and the file management system is configured to manage files and assist the FPGA controller in data management; Wherein, the PCIe control module is configured to transfer data from the FPGA computing module to the CPU processor module; and The DDR4 memory module is configured to support the computing power of the FPGA controller to help achieve high-speed reading of image data.

4. The storage system according to claim 3, characterized in that: The FPGA controller receives external control commands and data through the optical port and the GTH high-speed interface.

5. The storage system according to claim 3, characterized in that: The DDR4 memory module supports a speed of 1600MHz to 2400MHz and a capacity range of 8GB to 64GB.

6. The storage system according to claim 1, characterized in that: The disk storage module is composed of multiple NVMe SSD hard disks, which are configured to support PCIe3.0 interface and use RAID5 technology to achieve data redundancy.

7. The storage system according to claim 1, characterized in that: The PCIe SWITCH module is configured to support 64-Lane, 16-Port PCIe Gen3 switching.

8. The storage system according to claim 1, characterized in that: The CPU processor module is configured with the Feiteng FT2000 / 4 high-performance processor, which integrates multiple 64-bit cores and PCIe interfaces; and the FPGA computing module is configured with the FPGA logic chip XCVU3P, which supports PCIe3.0 x16 IP hard core and supports mounting DDR4 memory modules.

9. The storage system according to claim 1, characterized in that: The storage system includes an IPMI health management module for monitoring a real-time status of the storage system, wherein the real-time status includes at least one of a current, a voltage, a temperature, and a program loading status of the storage system.

10. The storage system according to claim 1, characterized in that: The storage system includes a first 6U LRM board and a second 6U LRM board interconnected by an LRM connector, wherein the first 6U LRM board acts as a storage control board configured to install the CPU processor module, FPGA computing module and PCIe SWITCH module, and the second 6U LRM board acts as a disk storage board configured to install the disk storage module.

Images