Method for realizing 256-bit multiplier hardware optimization based on 33-bit multiplier

Abstract

The invention relates to chip hardware design, in particular to a 256-bit multiplier hardware optimization method based on a 33-bit multiplier, and the method comprises the following steps based on a Karatsuba-Ofman algorithm principle: constructing a 66bit multiplier by using a 33-bit multiplier; the method comprises the following steps: constructing a 130-bit multiplier on the basis of a 66-bit multiplier; the method comprises the following steps: constructing a 256-bit multiplier on the basis of a 130-bit multiplier; according to the technical scheme provided by the invention, the defect that the calculation speed cannot be improved while the area of the multiplier is reduced in the prior art can be effectively overcome.

Description

Technical Field

[0001] The invention relates to chip hardware design, and in particular to a hardware optimization method for realizing a 256-bit multiplier based on a 33-bit multiplier. Background Art

[0002] In chips, multipliers are used very frequently, and large-bit-width multipliers often occupy a large chip area and consume more computing time. A traditional approach is to directly call the multiplier generated by the synthesis tool. Such a multiplier has a large area, which will increase the chip manufacturing cost. For example, the comprehensive area of ​​a 256-bit multiplier based on a 22nm library of GlobalFoundry is about 90,000 μm 2 , the area is too large, which leads to an increase in chip manufacturing costs.

[0003] Another traditional approach is to use a small bit-width multiplier instead, trading time for area. For example, a 256-bit*256-bit multiplication can be completed based on a 32-bit multiplier, using 64 32-bit*32-bit multiplications combined with some storage and control logic. Then, a 256-bit*256-bit multiplication takes at least 64 clock cycles. This method can reduce the area of ​​the multiplier, but the calculation time increases significantly. Summary of the invention

[0004] 1. Technical issues to be resolved

[0005] In view of the above-mentioned shortcomings of the prior art, the present invention provides a hardware optimization method for implementing a 256-bit multiplier based on a 33-bit multiplier, which can effectively overcome the defect of the prior art that it is impossible to increase the calculation speed while reducing the multiplier area.

[0006] (II) Technical solution

[0007] To achieve the above objectives, the present invention is implemented through the following technical solutions:

[0008] The hardware optimization method for implementing a 256-bit multiplier based on a 33-bit multiplier is based on the Karatsuba-Ofman algorithm principle and the following steps are performed:

[0009] S1. Use 33-bit multiplier to build 66-bit multiplier;

[0010] S2. Build a 130-bit multiplier based on the 66-bit multiplier;

[0011] S3, build a 256-bit multiplier based on the 130-bit multiplier;

[0012] Among them, additional addition operations and subtraction operations are introduced into the above process, and optimization is performed by time-division multiplexing adders and subtractors.

[0013] Preferably, a 66-bit multiplier is constructed using a 33-bit multiplier in S1, including:

[0014] Assume that A and B are both 66-bit integers, then:

[0015] (A[65:33],A[32:0])*(B[65:33],B[32:0])=A[65:33]*B[65:33]<<66+

[0016] {[(A[65:33]+A[32:0])*(B[65:33]+B[32:0])]-(A[65:33]*B[65:33]+A[32:0]*B[32:0])}<<33+A[32:0]*B[32:0];

[0017] In hardware, A[65:33]*B[65:33]<<66+A[32:0]*B[32:0] is equivalent to the bit concatenation operation (A[65:33]*B[65:33],A[32:0]*B[32:0]), which can reduce one addition operation, that is, the following is obtained:

[0018] (A[65:33],A[32:0])*(B[65:33],B[32:0])=(A[65:33]*B[65:33],A[32: 0]*B[32:0])+{[(A[65:33]+A[32:0])*(B[65:33]+B[32:0])]-(A[65:33]*

[0019] B[65:33]+A[32:0]*B[32:0])}<<33;

[0020] Since there is only one 33-bit multiplier, it takes three clock cycles to complete the three multiplications in the above formula. At the same time, the following needs to be completed within these three clock cycles:

[0021] 2 33-bit additions, namely: A[65:33]+A[32:0] and B[65:33]+B[32:0];

[0022] 1 66-bit addition, i.e.: A[65:33]*B[65:33]+A[32:0]*B[32:0];

[0023] 1 68-bit subtraction, that is:

[0024] [(A[65:33]+A[32:0])*(B[65:33]+B[32:0])]-(A[65:33]*B[65:33]+

[0025] A[32:0]*B[32:0]);

[0026] 1 132-bit addition, that is:

[0027] (A[65:33]*B[65:33],A[32:0]*B[32:0])+{[(A[65:33]+A[32:0])*

[0028] (B[65:33]+B[32:0])]-(A[65:33]*B[65:33]+A[32:0]*B[32:0])}<<33;

[0029] Among them, A[65:33] represents the high 33 bits of A, A[32:0] represents the low 33 bits of A, B[65:33] represents the high 33 bits of B, and B[32:0] represents the low 33 bits of B.

[0030] Preferably, in S2, a 130-bit multiplier is constructed based on a 66-bit multiplier, including:

[0031] Assume that A and B are both 130-bit integers, then:

[0032] (A[129:65],A[64:0])*(B[129:65],B[64:0])=A[129:65]*B[129:65]<<130+{[(A[129:65]+A[64: 0])*(B[129:65]+B[64:0])]-(A[129:65]*B[129:65]+A[64:0]*B[64:0])}<<65+A[64:0]*B[64:0];

[0033] In hardware, A[129:65]*B[129:65]<<130+A[64:0]*B[64:0] is equivalent to the bit concatenation operation (A[129:65]*B[129:65],A[64:0]*B[64:0]), which can reduce one addition operation, that is, the following is obtained:

[0034] (A[129:65],A[64:0])*(B[129:65],B[64:0])=(A[129:65]*B[129:65],A[64:0]*B[64:0])+{[(A [129:65]+A[64:0])*(B[129:65]+B[64:0])]-(A[129:65]*B[129:65]+A[64:0]*B[64:0])}<<65;

[0035] All the multiplications in the above formula are completed by calling 66-bit multipliers, which requires 3 66-bit multipliers and takes 9 clock cycles. At the same time, it needs to be completed within these 9 clock cycles:

[0036] Two 65-bit additions, namely: A[129:65]+A[64:0] and B[129:65]+B[64:0];

[0037] 1 130-bit addition, i.e.: A[129:65]*B[129:65]+A[64:0]*B[64:0];

[0038] 1 132-bit subtraction, that is:

[0039] [(A[129:65]+A[64:0])*(B[129:65]+B[64:0])]-(A[129:65]*B[129:65]+A[64:0]*B[64:0]);

[0040] 1 260-bit addition, that is:

[0041] (A[129:65]*B[129:65],A[64:0]*B[64:0])+{[(A[129:65]+A[64:0])*

[0042] (B[129:65]+B[64:0])]-(A[129:65]*B[129:65]+A[64:0]*B[64:0])}<<65;

[0043] Among them, A[129:65] represents the high 65 bits of A, A[64:0] represents the low 65 bits of A, B[129:65] represents the high 65 bits of B, and B[64:0] represents the low 65 bits of B.

[0044] Preferably, in S3, a 256-bit multiplier is constructed based on a 130-bit multiplier, including:

[0045] Assume that A and B are both 256-bit integers, then:

[0046] (A[255:128],A[127:0])*(B[255:128],B[127:0])=A[255:128]*

[0047] B[255:128]<<256+{[(A[255:128]+A[127:0])*(B[255:128]+B[127:0] )]-(A[255:128]*B[255:128]+A[127:0]*B[127:0])}<<128+A[127:0]*

[0048] B[127:0];

[0049] In hardware, A[255:128]*B[255:128]<<256+A[127:0]*B[127:0] is equivalent to the bit concatenation operation (A[255:128]*B[255:128],A[127:0]*B[127:0]), which can reduce one addition operation, that is, the following is obtained:

[0050] (A[255:128],A[127:0])*(B[255:128],B[127:0])=(A[255:128]*

[0051] B[255:128],A[127:0]*B[127:0])+{[(A[255:128]+A[127:0])*(B[255:1 28]+B[127:0])]-(A[255:128]*B[255:128]+A[127:0]*B[127:0])}<<128;

[0052] All the multiplications in the above formula are completed by calling 130-bit multipliers, which requires 3 130-bit multipliers and takes 27 clock cycles. At the same time, it needs to be completed within these 27 clock cycles:

[0053] Two 128-bit additions, namely: A[255:128]+A[127:0] and B[255:128]+B[127:0];

[0054] 1 256-bit addition, i.e.: A[255:128]*B[255:128]+A[127:0]*B[127:0];

[0055] 1 258-bit subtraction, that is:

[0056] [(A[255:128]+A[127:0])*(B[255:128]+B[127:0])]-(A[255:128]*

[0057] B[255:128]+A[127:0]*B[127:0]);

[0058] 1 512-bit addition, that is:

[0059] (A[255:128]*B[255:128],A[127:0]*B[127:0])+{[(A[255:128]+

[0060] A[127:0])*(B[255:128]+B[127:0])]-(A[255:128]*B[255:128]+A[127:0]*B[127:0])}<<128;

[0061] Among them, A[255:128] represents the high 128 bits of A, A[127:0] represents the low 128 bits of A, B[255:128] represents the high 128 bits of B, and B[127:0] represents the low 128 bits of B.

[0062] Preferably, in the absence of 33-bit addition and 512-bit addition, at most only two additions are performed at the same time, so two 260-bit adders are provided, and the addition operations except the 33-bit addition and the 512-bit addition are completed by time-division multiplexing the two 260-bit adders;

[0063] For 33-bit addition, since the area of ​​a 33-bit adder is very small, a 33-bit adder is directly provided;

[0064] For 512-bit addition, we have:

[0065] (A[255:128]*B[255:128],A[127:0]*B[127:0])+{[(A[255:128]+

[0066] A[127:0])*(B[255:128]+B[127:0])]-(A[255:128]*B[255:128]+A[127:0]*B[127:0])}<<128;

[0067] From the above formula, we can see that 512-bit addition is a 512-bit number add0[511:0] plus a 258-bit number add1 shifted 128 bits to the left. The effective addition is only the 258-bit segment. After completing the 258-bit addition, it is determined whether there is a carry. If there is a carry, add0[511:385] needs to be added by 1. Otherwise, only 258-bit addition is performed. Then, a 260-bit adder can be used to complete the 512-bit addition.

[0068] Among them, add0[511:0] represents bits 0 to 511 of add0, and add0[511:385] represents bits 385 to 511 of add0;

[0069] Performing a 512-bit addition takes an extra clock cycle, so a 256-bit*256-bit multiplication ultimately takes 28 clock cycles.

[0070] Preferably, all subtraction operations are performed by time division multiplexing a 260-bit subtractor.

[0071] Preferably, the Karatsuba-Ofman algorithm works as follows:

[0072] For the multiplication of two n-bit integers x and y, let n = 21, x = x 1 2 l +x 0 , y=y 1 2 l +y 0 , then:

[0073] xy=(x 1 2 l +x 0 )*(y 1 2 l +y 0 )=x 1 y 1 2 2l +[(x 0 +x 1 )(y 0 +y 1 )-x 1 y 1 -x 0 y 0 ]2 l +x 0 y 0 ;

[0074] Among them, x 1 is the high l bits of integer x, x 0 is the lower l bits of the integer x, y 1 is the high 1 bits of integer y, 0 The lower l bits of the integer y;

[0075] As can be seen from the above formula, the multiplication of two n-bit integers x and y is completed through three l-bit integer multiplications, four additions and two subtractions.

[0076] (III) Beneficial effects

[0077] Compared with the prior art, the hardware optimization method for implementing a 256-bit multiplier based on a 33-bit multiplier provided by the present invention has the following beneficial effects:

[0078] 1) Based on the principle of Karatsuba-Ofman algorithm, a 256-bit large-bit-width multiplier is implemented using a 33-bit multiplier. It only takes 28 clock cycles to perform a 256-bit*256-bit multiplication. Compared with the traditional method based on a 32-bit multiplier, the calculation speed is faster and the calculation efficiency is higher;

[0079] 2) For the introduction of additional addition and subtraction operations, optimization is performed by time-division multiplexing adders and subtractors, while avoiding the use of 512-bit adders. Compared with the multipliers generated by traditional direct calls to synthesis tools, the chip area is smaller, which can effectively save chip manufacturing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0080] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0081] Figure 1 It is a schematic diagram of the process of the present invention;

[0082] Figure 2 Schematic diagram of the hardware structure of the 256-bit multiplier in the present invention;

[0083] Figure 3 It is a timing diagram of addition and subtraction operations in the 256-bit multiplier of the present invention;

[0084] Figure 4 It is the principle diagram of 512-bit addition in the present invention. DETAILED DESCRIPTION

[0085] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0086] The Karatsuba-Ofman algorithm works as follows:

[0087] For the multiplication of two n-bit integers x and y, let n = 21, x = x 1 2 l +x 0 , y=y 1 2 l +y 0 , then:

[0088] xy=(x 1 2 l +x 0 )*(y 1 2 l +y 0 )=x 1 y 1 2 2l +[(x 0 +x 1 )(y 0 +y 1 )-x 1 y 1 -x 0 y 0 ]2 l +x 0 y 0 ;

[0089] Among them, x 1 is the high l bits of integer x, x 0 is the lower l bits of the integer x, y 1 is the high 1 bits of integer y, 0 The lower l bits of the integer y;

[0090] As can be seen from the above formula, the multiplication of two n-bit integers x and y is completed through three l-bit integer multiplications, four additions and two subtractions.

[0091] A hardware optimization method for implementing a 256-bit multiplier based on a 33-bit multiplier, such as Figure 1 As shown, the following steps are performed based on the principle of Karatsuba-Ofman algorithm:

[0092] S1. Use the 33-bit multiplier to build a 66-bit multiplier, including:

[0093] Assume that A and B are both 66-bit integers, then:

[0094] (A[65:33],A[32:0])*(B[65:33],B[32:0])=A[65:33]*B[65:33]<<66+

[0095] {[(A[65:33]+A[32:0])*(B[65:33]+B[32:0])]-(A[65:33]*B[65:33]+A[32:0]*B[32:0])}<<33+A[32:0]*B[32:0];

[0096] In hardware, A[65:33]*B[65:33]<<66+A[32:0]*B[32:0] is equivalent to the bit concatenation operation (A[65:33]*B[65:33],A[32:0]*B[32:0]), which can reduce one addition operation, that is, the following is obtained:

[0097] (A[65:33],A[32:0])*(B[65:33],B[32:0])=(A[65:33]*B[65:33],A[32: 0]*B[32:0])+{[(A[65:33]+A[32:0])*(B[65:33]+B[32:0])]-(A[65:33]*

[0098] B[65:33]+A[32:0]*B[32:0])}<<33;

[0099] Since there is only one 33-bit multiplier, it takes three clock cycles to complete the three multiplications in the above formula. At the same time, the following needs to be completed within these three clock cycles:

[0100] 2 33-bit additions, namely: A[65:33]+A[32:0] and B[65:33]+B[32:0];

[0101] 1 66-bit addition, i.e.: A[65:33]*B[65:33]+A[32:0]*B[32:0];

[0102] 1 68-bit subtraction, that is:

[0103] [(A[65:33]+A[32:0])*(B[65:33]+B[32:0])]-(A[65:33]*B[65:33]+

[0104] A[32:0]*B[32:0]);

[0105] 1 132-bit addition, that is:

[0106] (A[65:33]*B[65:33],A[32:0]*B[32:0])+{[(A[65:33]+A[32:0])*

[0107] (B[65:33]+B[32:0])]-(A[65:33]*B[65:33]+A[32:0]*B[32:0])}<<33;

[0108] Among them, A[65:33] represents the high 33 bits of A, A[32:0] represents the low 33 bits of A, B[65:33] represents the high 33 bits of B, and B[32:0] represents the low 33 bits of B.

[0109] S2. Build a 130-bit multiplier based on the 66-bit multiplier, including:

[0110] Assume that A and B are both 130-bit integers, then:

[0111] (A[129:65],A[64:0])*(B[129:65],B[64:0])=A[129:65]*B[129:65]<<130+{[(A[129:65]+A[64: 0])*(B[129:65]+B[64:0])]-(A[129:65]*B[129:65]+A[64:0]*B[64:0])}<<65+A[64:0]*B[64:0];

[0112] In hardware, A[129:65]*B[129:65]<<130+A[64:0]*B[64:0] is equivalent to the bit concatenation operation (A[129:65]*B[129:65],A[64:0]*B[64:0]), which can reduce one addition operation, that is, the following is obtained:

[0113] (A[129:65],A[64:0])*(B[129:65],B[64:0])=(A[129:65]*B[129:65],A[64:0]*B[64:0])+{[(A [129:65]+A[64:0])*(B[129:65]+B[64:0])]-(A[129:65]*B[129:65]+A[64:0]*B[64:0])}<<65;

[0114] All the multiplications in the above formula are completed by calling 66-bit multipliers, which requires 3 66-bit multipliers and takes 9 clock cycles. At the same time, it needs to be completed within these 9 clock cycles:

[0115] Two 65-bit additions, namely: A[129:65]+A[64:0] and B[129:65]+B[64:0];

[0116] 1 130-bit addition, i.e.: A[129:65]*B[129:65]+A[64:0]*B[64:0];

[0117] 1 132-bit subtraction, that is:

[0118] [(A[129:65]+A[64:0])*(B[129:65]+B[64:0])]-(A[129:65]*B[129:65]+A[64:0]*B[64:0]);

[0119] 1 260-bit addition, that is:

[0120] (A[129:65]*B[129:65],A[64:0]*B[64:0])+{[(A[129:65]+A[64:0])*

[0121] (B[129:65]+B[64:0])]-(A[129:65]*B[129:65]+A[64:0]*B[64:0])}<<65;

[0122] Among them, A[129:65] represents the high 65 bits of A, A[64:0] represents the low 65 bits of A, B[129:65] represents the high 65 bits of B, and B[64:0] represents the low 65 bits of B.

[0123] S3. Build a 256-bit multiplier based on the 130-bit multiplier, including:

[0124] Assume that A and B are both 256-bit integers, then:

[0125] (A[255:128],A[127:0])*(B[255:128],B[127:0])=A[255:128]*

[0126] B[255:128]<<256+{[(A[255:128]+A[127:0])*(B[255:128]+B[127:0] )]-(A[255:128]*B[255:128]+A[127:0]*B[127:0])}<<128+A[127:0]*

[0127] B[127:0];

[0128] In hardware, A[255:128]*B[255:128]<<256+A[127:0]*B[127:0] is equivalent to the bit concatenation operation (A[255:128]*B[255:128],A[127:0]*B[127:0]), which can reduce one addition operation, that is, the following is obtained:

[0129] (A[255:128],A[127:0])*(B[255:128],B[127:0])=(A[255:128]*

[0130] B[255:128],A[127:0]*B[127:0])+{[(A[255:128]+A[127:0])*(B[255:1 28]+B[127:0])]-(A[255:128]*B[255:128]+A[127:0]*B[127:0])}<<128;

[0131] All the multiplications in the above formula are completed by calling 130-bit multipliers, which requires 3 130-bit multipliers and takes 27 clock cycles. At the same time, it needs to be completed within these 27 clock cycles:

[0132] Two 128-bit additions, namely: A[255:128]+A[127:0] and B[255:128]+B[127:0];

[0133] 1 256-bit addition, i.e.: A[255:128]*B[255:128]+A[127:0]*B[127:0];

[0134] 1 258-bit subtraction, that is:

[0135] [(A[255:128]+A[127:0])*(B[255:128]+B[127:0])]-(A[255:128]*

[0136] B[255:128]+A[127:0]*B[127:0]);

[0137] 1 512-bit addition, that is:

[0138] (A[255:128]*B[255:128],A[127:0]*B[127:0])+{[(A[255:128]+

[0139] A[127:0])*(B[255:128]+B[127:0])]-(A[255:128]*B[255:128]+A[127:0]*B[127:0])}<<128;

[0140] Among them, A[255:128] represents the high 128 bits of A, A[127:0] represents the low 128 bits of A, B[255:128] represents the high 128 bits of B, and B[127:0] represents the low 128 bits of B.

[0141] In the technical solution of the present application, the introduction of additional addition and subtraction operations is optimized by time-division multiplexing adders and subtractors.

[0142] 1) For the introduction of additional addition operations

[0143] like Figure 3 As shown, in the absence of 33-bit addition and 512-bit addition, at most only two additions are executed at the same time, so two 260-bit adders are provided, and the addition operations of 33-bit addition and 512-bit addition are completed by time-division multiplexing these two 260-bit adders;

[0144] For 33-bit addition, since the area of ​​a 33-bit adder is very small, a 33-bit adder is directly provided;

[0145] For 512-bit addition, we have:

[0146] (A[255:128]*B[255:128],A[127:0]*B[127:0])+{[(A[255:128]+

[0147] A[127:0])*(B[255:128]+B[127:0])]-(A[255:128]*B[255:128]+A[127:0]*B[127:0])}<<128;

[0148] From the above formula, we can see that 512-bit addition is a 512-bit number add0[511:0] plus a 258-bit number add1 shifted left by 128 bits. Figure 4 As shown, the effective addition is only the 258-bit section. After completing the 258-bit addition, determine whether there is a carry. If there is a carry, add0[511:385] needs to add 1, otherwise only 258-bit addition is performed, and the 260-bit adder can be used to complete the 512-bit addition.

[0149] Among them, add0[511:0] represents bits 0 to 511 of add0, and add0[511:385] represents bits 385 to 511 of add0;

[0150] Performing a 512-bit addition takes an extra clock cycle, so a 256-bit*256-bit multiplication ultimately takes 28 clock cycles.

[0151] 2) For introducing additional subtraction operations

[0152] All subtraction operations are performed by time-division multiplexing a 260-bit subtractor.

[0153] In the technical solution of this application, the hardware structure of the 256-bit multiplier is as follows: Figure 2 As shown. Among them, clk is the clock signal, reset_n is the reset signal, A and B are input data, input_vld is the input valid indication signal, C_vld is the output valid indication signal, and C_mult_256×256_wrapper is the multiplication result.

[0154] The overall area of ​​the 256-bit multiplier obtained by using the technical solution of this application is about 9000 μm 2 Compared with the multiplier generated by traditional direct call synthesis tools, the area is only 10% of that. The traditional method based on a 32-bit multiplier uses a multiplier with a comprehensive area of ​​about 10,000 μm. 2 , it takes at least 64 clock cycles to perform a 256-bit*256-bit multiplication. Compared with the traditional method based on one 32-bit multiplier, the 256-bit multiplier obtained by using the technical solution of the present application not only has a faster calculation speed, but also occupies a smaller chip area.

[0155] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements will not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for hardware optimization of a 256-bit multiplier based on a 33-bit multiplier, characterized in that: Based on the principle of Karatsuba-Ofman algorithm, the following steps are performed: S1. Use 33-bit multiplier to build 66-bit multiplier; S2. Build a 130-bit multiplier based on the 66-bit multiplier; S3. Build a 256-bit multiplier based on the 130-bit multiplier; Among them, additional addition operations and subtraction operations are introduced into the above process, and optimization is performed by time-division multiplexing adders and subtractors.

2. The method for hardware optimization of a 256-bit multiplier based on a 33-bit multiplier according to claim 1, characterized in that: In S1, a 66-bit multiplier is constructed using a 33-bit multiplier, including: Assume that A and B are both 66-bit integers, then: (A[65:33],A[32:0])*(B[65:33],B[32:0])=A[65:33]*B[65:33]<<66+{[(A[65:33]+A[32:0] )*(B[65:33]+B[32:0])]-(A[65:33]*B[65:33]+A[32:0]*B[32:0])}<<33+A[32:0]*B[32:0]; In hardware, A[65:33]*B[65:33]<<66+A[32:0]*B[32:0] is equivalent to the bit concatenation operation (A[65:33]*B[65:33],A[32:0]*B[32:0]), which can reduce one addition operation, that is, the following is obtained: (A[65:33],A[32:0])*(B[65:33],B[32:0])=(A[65:33]*B[65:33],A[32: 0]*B[32:0])+{[(A[65:33]+A[32:0])*(B[65:33]+B[32:0])]-(A[65:33]* B[65:33]+A[32:0]*B[32:0])}<<33; Since there is only one 33-bit multiplier, it takes three clock cycles to complete the three multiplications in the above formula. At the same time, the following needs to be completed within these three clock cycles: 2 33-bit additions, namely: A[65:33]+A[32:0] and B[65:33]+B[32:0]; 1 66-bit addition, i.e.: A[65:33]*B[65:33]+A[32:0]*B[32:0]; 1 68-bit subtraction, that is: [(A[65:33]+A[32:0])*(B[65:33]+B[32:0])]-(A[65:33]*B[65:33]+ A[32:0]*B[32:0]); 1 132-bit addition, that is: (A[65:33]*B[65:33],A[32:0]*B[32:0])+{[(A[65:33]+A[32:0])* (B[65:33]+B[32:0])]-(A[65:33]*B[65:33]+A[32:0]*B[32:0])}<<33; Among them, A[65:33] represents the high 33 bits of A, A[32:0] represents the low 33 bits of A, B[65:33] represents the high 33 bits of B, and B[32:0] represents the low 33 bits of B.

3. The method for hardware optimization of a 256-bit multiplier based on a 33-bit multiplier according to claim 2, characterized in that: In S2, a 130-bit multiplier is built on the basis of a 66-bit multiplier, including: Assume that A and B are both 130-bit integers, then: (A[129:65],A[64:0])*(B[129:65],B[64:0])=A[129:65]*B[129:65]<<130+{[(A[129:65]+A[64: 0])*(B[129:65]+B[64:0])]-(A[129:65]*B[129:65]+A[64:0]*B[64:0])}<<65+A[64:0]*B[64:0]; In hardware, A[129:65]*B[129:65]<<130+A[64:0]*B[64:0] is equivalent to the bit concatenation operation (A[129:65]*B[129:65],A[64:0]*B[64:0]), which can reduce one addition operation, that is, the following is obtained: (A[129:65],A[64:0])*(B[129:65],B[64:0])=(A[129:65]*B[129:65],A[64:0]*B[64:0])+{[(A [129:65]+A[64:0])*(B[129:65]+B[64:0])]-(A[129:65]*B[129:65]+A[64:0]*B[64:0])}<<65; All the multiplications in the above formula are completed by calling 66-bit multipliers, which requires 3 66-bit multipliers and takes 9 clock cycles. At the same time, it needs to be completed within these 9 clock cycles: Two 65-bit additions, namely: A[129:65]+A[64:0] and B[129:65]+B[64:0]; 1 130-bit addition, i.e.: A[129:65]*B[129:65]+A[64:0]*B[64:0]; 1 132-bit subtraction, that is: [(A[129:65]+A[64:0])*(B[129:65]+B[64:0])]-(A[129:65]*B[129:65]+A[64:0]*B[64:0]); 1 260-bit addition, that is: (A[129:65]*B[129:65],A[64:0]*B[64:0])+{[(A[129:65]+A[64:0])*(B [129:65]+B[64:0])]-(A[129:65]*B[129:65]+A[64:0]*B[64:0])}<<65; Among them, A[129:65] represents the high 65 bits of A, A[64:0] represents the low 65 bits of A, B[129:65] represents the high 65 bits of B, and B[64:0] represents the low 65 bits of B.

4. The method for hardware optimization of a 256-bit multiplier based on a 33-bit multiplier according to claim 3, characterized in that: In S3, a 256-bit multiplier is built on the basis of a 130-bit multiplier, including: Assume that A and B are both 256-bit integers, then: (A[255:128],A[127:0])*(B[255:128],B[127:0])=A[255:128]* B[255:128]<<256+{[(A[255:128]+A[127:0])*(B[255:128]+B[127:0] )]-(A[255:128]*B[255:128]+A[127:0]*B[127:0])}<<128+A[127:0]* B[127:0]； In hardware, A[255:128]*B[255:128]<<256+A[127:0]*B[127:0] is equivalent to the bit concatenation operation (A[255:128]*B[255:128],A[127:0]*B[127:0]), which can reduce one addition operation, that is, the following is obtained: (A[255:128],A[127:0])*(B[255:128],B[127:0])=(A[255:128]* B[255:128],A[127:0]*B[127:0])+{[(A[255:128]+A[127:0])*(B[255:1 28]+B[127:0])]-(A[255:128]*B[255:128]+A[127:0]*B[127:0])}<<128; All the multiplications in the above formula are completed by calling 130-bit multipliers, which requires 3 130-bit multipliers and takes 27 clock cycles. At the same time, it needs to be completed within these 27 clock cycles: Two 128-bit additions, namely: A[255:128]+A[127:0] and B[255:128]+B[127:0]; 1 256-bit addition, i.e.: A[255:128]*B[255:128]+A[127:0]*B[127:0]; 1 258-bit subtraction, that is: [(A[255:128]+A[127:0])*(B[255:128]+B[127:0])]-(A[255:128]* B[255:128]+A[127:0]*B[127:0]); 1 512-bit addition, that is: (A[255:128]*B[255:128],A[127:0]*B[127:0])+{[(A[255:128]+ A[127:0])*(B[255:128]+B[127:0])]-(A[255:128]*B[255:128]+A[127:0]*B[127:0])}<<128; Among them, A[255:128] represents the high 128 bits of A, A[127:0] represents the low 128 bits of A, B[255:128] represents the high 128 bits of B, and B[127:0] represents the low 128 bits of B.

5. The method for hardware optimization of a 256-bit multiplier based on a 33-bit multiplier according to claim 4, characterized in that: In the absence of 33-bit addition and 512-bit addition, at most only two additions are executed at the same time, so two 260-bit adders are provided. In addition to the addition of 33-bit addition and 512-bit addition, the addition operations are completed by time-division multiplexing these two 260-bit adders; For 33-bit addition, since the area of ​​a 33-bit adder is very small, a 33-bit adder is directly provided; For 512-bit addition, we have: (A[255:128]*B[255:128],A[127:0]*B[127:0])+{[(A[255:128]+ A[127:0])*(B[255:128]+B[127:0])]-(A[255:128]*B[255:128]+A[127:0]*B[127:0])}<<128; From the above formula, we can see that 512-bit addition is a 512-bit number add0[511:0] plus a 258-bit number add1 shifted 128 bits to the left. The effective addition is only the 258-bit segment. After completing the 258-bit addition, it is determined whether there is a carry. If there is a carry, add0[511:385] needs to be added by 1. Otherwise, only 258-bit addition is performed. Then, a 260-bit adder can be used to complete the 512-bit addition. Among them, add0[511:0] represents bits 0 to 511 of add0, and add0[511:385] represents bits 385 to 511 of add0; Performing a 512-bit addition takes an extra clock cycle, so a 256-bit*256-bit multiplication ultimately takes 28 clock cycles.

6. The method for hardware optimization of a 256-bit multiplier based on a 33-bit multiplier according to claim 5, characterized in that: All subtraction operations are performed by time-division multiplexing a 260-bit subtractor.

7. The method for hardware optimization of a 256-bit multiplier based on a 33-bit multiplier according to any one of claims 1 to 6, characterized in that: The Karatsuba-Ofman algorithm works as follows: For the multiplication of two n-bit integers x and y, let n = 21, x = x12 l +x0,y=y12 l +y0, then: xy=(x12 l +x0)*(y12 l +y0)=x1y12 2l +[(x0+x1)(y0+y1)-x1y1-x0y0]2 l +x0y0; Among them, x1 is the high l bits of integer x, x0 is the low l bits of integer x, y1 is the high l bits of integer y, and y0 is the low l bits of integer y; As can be seen from the above formula, the multiplication of two n-bit integers x and y is completed through three l-bit integer multiplications, four additions and two subtractions.

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