AI instruction extension execution method and device, equipment and storage medium

Abstract

The embodiment of the invention discloses an AI instruction extension execution method and device, equipment and a storage medium. The method comprises the following steps: acquiring an extended AI instruction sequence pre-configured by a user, and executing an extended AI instruction in the extended AI instruction sequence according to the extended AI instruction sequence; under the condition that any extended AI instruction is executed, calling pre-stored AI instruction configuration information from a general register or a local internal register according to instruction addressing information of a target field in the extended AI instruction; and executing the corresponding AI instruction according to the AI instruction configuration information. On the basis, by means of the extended AI instruction, the general register and the local internal register, one 32-bit instruction can accommodate more AI instruction configuration information, so that the miss rate of instruction cache is reduced, and the calculation efficiency is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of AI algorithm execution technology, and in particular, to an extended execution method, device, equipment and storage medium of AI instructions. Background Art

[0002] With the rapid development of artificial intelligence (AI) technology, RISC-V has become an ideal choice in the field of AI chips due to its openness, flexibility and high scalability. RISC-V supports user-defined instruction set extensions, allowing chip designers to customize AI accelerators according to specific needs to meet the rapidly changing needs of AI workloads while improving the performance and efficiency of AI computing.

[0003] When performing AI calculations, matrix acceleration instructions are usually used to achieve higher data reuse and reduce memory bandwidth requirements. However, due to the limited bit width of AI instructions, multiple loading and calculation AI instructions are required to achieve larger-scale matrix calculations. The increase in the number of required instructions will lead to an increase in the miss rate of the instruction cache and a decrease in computing efficiency. Summary of the invention

[0004] The embodiments of the present application provide an extended execution method, apparatus, device and storage medium for AI instructions to reduce the miss rate of instruction cache and improve computing efficiency.

[0005] In a first aspect, an embodiment of the present application provides an extended execution method of an AI instruction, the method comprising: Obtaining an extended AI instruction sequence pre-configured by a user, and executing the extended AI instructions in the extended AI instruction sequence according to the extended AI instruction sequence; When any extended AI instruction is executed, the pre-stored AI instruction configuration information is called from a general register or a local internal register according to the instruction addressing information of the target field in the extended AI instruction; Execute corresponding AI instructions according to AI instruction configuration information; According to the instruction addressing information of the target field in the extended AI instruction, the pre-stored AI instruction configuration information is called from the general register or the local internal register, including: Obtaining an index address in a first target field and a field value in a second target field; If the field value is the first preset field value, calling the pre-stored AI instruction configuration information from the index address of the general register; If the field value is the second preset field value, the pre-stored AI instruction configuration information is called from the index address of the local internal register.

[0006] Furthermore, the method also includes: Obtain the user's instruction configuration information, which includes multiple instruction information and sequence information. Each instruction information includes instruction type and field configuration information; For any instruction information, obtain the extended AI instruction template corresponding to the instruction type, and fill the field configuration information into the extended AI instruction template to obtain the extended AI instruction corresponding to the instruction information; The extended AI instructions are sorted according to the sequence information to obtain an extended AI instruction sequence.

[0007] Furthermore, the method also includes: Each time an instruction is executed, the instruction is parsed. If the parsed instruction is an extended AI instruction, it is determined that any extended AI instruction is executed.

[0008] Furthermore, the extended AI instructions are executed asynchronously by the AI ​​accelerator.

[0009] Furthermore, the method also includes: During the execution of any extended AI instruction, if a preset target operation is performed, a field value of a third target field in the extended AI instruction and a target register address in a fourth target field are obtained; If the field value of the third target field is the third preset field value, determining the general register as the target register; If the field value of the third target field is the fourth preset field value, determining the local internal register as the target register; Performs a preset target operation based on the target register address.

[0010] Further, the preset target operation is a write answer word operation.

[0011] In a second aspect, an embodiment of the present application provides an extended execution device for an AI instruction, the device comprising: A first execution module, configured to obtain an extended AI instruction sequence pre-configured by a user, and execute the extended AI instructions in the extended AI instruction sequence according to the extended AI instruction sequence; A calling module, used for calling pre-stored AI instruction configuration information from a general register or a local internal register according to instruction addressing information of a target field in the extended AI instruction when any extended AI instruction is executed; A second execution module, used to execute corresponding AI instructions according to AI instruction configuration information; The calling module is specifically used for: Obtaining an index address in a first target field and a field value in a second target field; If the field value is the first preset field value, calling the pre-stored AI instruction configuration information from the index address of the general register; If the field value is the second preset field value, the pre-stored AI instruction configuration information is called from the index address of the local internal register.

[0012] In a third aspect, an embodiment of the present application further provides an electronic device, the electronic device comprising: one or more processors; a storage device for storing one or more programs, When one or more programs are executed by one or more processors, the one or more processors implement an extended execution method of AI instructions as provided in any embodiment of the present application.

[0013] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium on which a computer program is stored, characterized in that when the program is executed by a processor, an extended execution method of the AI ​​instruction provided in any embodiment of the present application is implemented.

[0014] The technical solution of the embodiment of the present application obtains the extended AI instruction sequence pre-configured by the user, and executes the extended AI instruction in the extended AI instruction sequence according to the extended AI instruction sequence; when any extended AI instruction is executed, the pre-stored AI instruction configuration information is called from the general register or the local internal register according to the instruction addressing information of the target field in the extended AI instruction; and the corresponding AI instruction is executed according to the AI ​​instruction configuration information. Based on this, with the help of extended AI instructions, general registers and local internal registers, a 32-bit instruction can accommodate more AI instruction configuration information, thereby reducing the miss rate of the instruction cache and improving computing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A flowchart of the extended execution method of the AI ​​instruction provided in Example 1 of the present application.

[0016] Figure 2 A schematic diagram of the structure of an extended execution device for AI instructions provided in Example 2 of the present application.

[0017] Figure 3 A schematic diagram of the structure of an electronic device provided in Example 3 of the present application.

[0018] Figure 4 A schematic diagram of an extended AI instruction bit field provided in Example 1 of the present application. DETAILED DESCRIPTION

[0019] The present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for ease of description, only the parts related to the present application, rather than all structures, are shown in the accompanying drawings.

[0020] Embodiment 1: Figure 1 A flowchart of an extended execution method of an AI instruction provided in Embodiment 1 of the present application is shown as follows: Figure 1 As shown, the extended execution method of the AI ​​instruction provided in this embodiment can be applied to an extended execution platform of the AI ​​instruction carried on a device with data processing capability such as a computer, and can be used in conjunction with some application software to achieve a better experience. Specifically, the following steps may be included: Step 101: Acquire an extended AI instruction sequence pre-configured by a user, and execute the extended AI instructions in the extended AI instruction sequence according to the extended AI instruction sequence.

[0021] In this step, the extended AI instruction sequence includes multiple extended AI instructions with an execution order. When configuring and generating the extended AI instruction sequence, the user's instruction configuration information can be obtained first. The instruction configuration information includes multiple instruction information and sequence information. Each instruction information includes an instruction type and field configuration information.

[0022] Then, for any instruction information, obtain the extended AI instruction template corresponding to the instruction type, and fill the field configuration information into the extended AI instruction template to obtain the extended AI instruction corresponding to the instruction information; sort each extended AI instruction according to the sequence information to obtain the extended AI instruction sequence.

[0023] There may be multiple types of instructions. In a specific example, there may be a configuration instruction (CFG), a load operand A instruction (LDA), a load operand B instruction (LDB), a write back instruction (ST), and a continuous load instruction (CTN).

[0024] In general registers and local internal registers, the functions that can be configured by each instruction type can be configured through the set instruction, and each function can exist in the register in the form of AI instruction configuration information.

[0025] Specifically, CFG (configuration instruction), by sending this instruction, can achieve: (1) You can configure whether to enable the sparse acceleration function when loading data.

[0026] (2) The precision of the input data can be configured, including but not limited to FP64, FP32, FP16, BF16, FP8, etc.

[0027] (3) You can configure whether to enable the fast format conversion function, that is, no calculation is performed, and only the precision conversion of the input data is performed. When the fast format conversion is enabled, operand B does not need to be loaded.

[0028] (4) When the precision is FP8, the data format can be configured as E4M3 or E5M2.

[0029] (5) The rounding mode for dot product and accumulation operations of floating-point operands can be configured.

[0030] LDA (load operand A), by sending this instruction, operand A can be loaded from the local storage component and achieve: (1) The starting address of the instruction when accessing the local storage component can be configured.

[0031] (2) You can configure how many operands A the instruction loads in total.

[0032] (3) The address stride mode of this instruction can be configured. If more than one data is loaded, the hardware will automatically calculate the subsequent addresses. It supports address stride of zero, address stride of non-zero, and address stride of two dimensions.

[0033] (4) You can configure whether to perform a PADDING (zero padding) operation when loading operand A.

[0034] (5) The mask used by this instruction to load operand A can be configured. The width of the loaded vector is determined by the hardware design and is not configurable. Through the mask, redundant data can be set to zero to avoid contaminating the dot product result.

[0035] (6) You can configure whether the instruction writes a reply word and the address of the reply word.

[0036] (7) You can configure whether this instruction accumulates the dot product results.

[0037] LDB (load operand B), by sending this instruction, operand B can be loaded from the local storage component and achieve: (1) The starting address of the instruction when accessing the local storage component can be configured.

[0038] (2) The address stride mode of this instruction can be configured. If more than one data is loaded, the hardware will automatically calculate the subsequent addresses. It supports address stride of zero, address stride of non-zero, and one-dimensional stride.

[0039] (3) You can configure whether to perform a transposition operation on operand B when the instruction loads it.

[0040] (4) The mask used by this instruction when loading operand B can be configured. The width of the loaded vector is determined by the hardware design and is not configurable. Through the mask, the redundant data can be set to zero to avoid contaminating the dot product result.

[0041] (5) You can configure whether the instruction writes a reply word and the address of the reply word.

[0042] ST (write back instruction), by sending this instruction, the accumulated result can be written back to the local storage component and achieve: (1) The precision of the calculation result written back by the instruction can be configured, including but not limited to FP64, FP32, FP16, BF16, FP8, INT32, etc.

[0043] (2) You can configure whether the instruction performs scaling / offset operations on the accumulated results.

[0044] (3) You can configure how this instruction loads offset coefficients and scales sparsity.

[0045] (4) You can configure whether the calculation result written back by this instruction supports non-reduced numbers.

[0046] (5) You can configure how to handle overflow when the calculation result written back by this instruction exceeds the precision representation range.

[0047] (6) You can configure whether to enable the absolute maximum value statistics of the write-back result for this instruction.

[0048] (7) You can configure whether the instruction writes back the absolute maximum value and the write-back address.

[0049] (8) You can configure how many calculation results the instruction writes back, which entry in the accumulation result buffer 0 / 1 the calculation result is, and whether the buffer is cleared after the accumulation result is taken out.

[0050] (9) The starting address of this instruction when it is written back to the local storage component can be configured.

[0051] (10) The address stride mode of this instruction can be configured. If more than one data is loaded, the hardware will automatically calculate the subsequent addresses. It supports address stride of zero, address stride of non-zero, and one-dimensional stride.

[0052] (11) The address of the reply word written by this instruction can be configured.

[0053] CTN: (Continuous Load Instruction). By sending this instruction, the hardware can be notified to automatically execute LDA and LDB instructions multiple times. LDA and LDB can also be configured with the various functions mentioned above.

[0054] In addition, the extended AI instruction fields can be found in Figure 4 , Figure 4 A schematic diagram of an extended AI instruction bit field provided in Example 1 of the present application.

[0055] like Figure 4 As shown, xs1 / xs2 indicates the type of source register: the present invention uses two source registers, an internal register and a general register. The two registers store specific instruction configuration information rs2 and rs1 for AI calculation respectively. xs1 / xs2 is 0, indicating that instruction information rs2 is fetched from the internal register, and 1 indicates that instruction information rs1 is fetched from the general register. rs1 / rs2 indicates the index address of the source register: rs1 corresponds to the index address of the xs2 indication register, and rs2 corresponds to the index address of the xs1 indication register.

[0056] xd indicates the type of the target register: xd = 1 indicates the target operation is for a general register, xd = 0 indicates the target operation is for an internal register, and the target operation is usually to write a reply word. rd indicates the address of the target register.

[0057] Funct7 is used to indicate the function corresponding to the instruction: in the present invention, all AI instructions are set to a same fixed value.

[0058] In addition, this embodiment may set the operation code (opcode) as a custom operation code to avoid conflicts with future standard extensions.

[0059] It should be noted that an extended AI instruction template can be set for each instruction type, and the extended AI instruction template can be set as a specific extended AI instruction that is most commonly used for this type of instruction, so as to speed up the user's configuration of instruction sequences in common scenarios.

[0060] The functions of the above-mentioned types of instructions are all implemented by existing traditional AI instructions. The specific implementation methods can refer to relevant technologies and will not be described here. The user pre-fills the instruction configuration information corresponding to each function into a general register or a certain address in the local internal register through the set instruction, so that the instruction configuration information of the corresponding function can be directly obtained by addressing during subsequent execution, thereby realizing the function.

[0061] In addition, in this embodiment, each time an instruction is executed, the instruction is parsed, and if the parsed instruction is an extended AI instruction, it is determined that any extended AI instruction is executed. Since the funct7 field is set to a fixed value, the parsed funct7 field of the instruction is the fixed value, and the instruction can be determined to be an extended AI instruction.

[0062] Step 102: When any extended AI instruction is executed, the pre-stored AI instruction configuration information is called from a general register or a local internal register according to the instruction addressing information of the target field in the extended AI instruction.

[0063] In this step, the index address in the first target field and the field value in the second target field can be obtained; if the field value is the first preset field value, the pre-stored AI instruction configuration information is called from the index address of the general register; if the field value is the second preset field value, the pre-stored AI instruction configuration information is called from the index address of the local internal register.

[0064] The first target field may be xs1 / xs2 in the above specific example, and the second target field may be rs1 / rs2 in the above specific example. Based on these two fields, the AI ​​instruction configuration information corresponding to the extended AI instruction can be obtained from the register.

[0065] In addition, the extended AI instruction is executed asynchronously by the AI ​​accelerator. That is, when the extended AI instruction is executed, the subsequent steps can be handed over to the AI ​​accelerator.

[0066] Step 103: Execute the corresponding AI instruction according to the AI ​​instruction configuration information.

[0067] In this step, the AI ​​instruction configuration information includes AI instruction information that can realize a certain function, which can be a specific code, a code block, etc. By executing the code or the code block, the function can be realized.

[0068] In addition, during the execution of any extended AI instruction, if a preset target operation is performed, the field value of the third target field in the extended AI instruction and the target register address in the fourth target field are obtained; if the field value of the third target field is the third preset field value, the general register is determined as the target register; if the field value of the third target field is the fourth preset field value, the local internal register is determined as the target register; and the preset target operation is performed based on the target register address.

[0069] The third target field may be xd, and the fourth target field may be rd. The preset target operation may be a write answer word operation. If the AIE completes executing the current instruction, it may initiate a write answer word request to the internal register or the local storage component to inform the user that the asynchronous event is completed.

[0070] To further illustrate the extended execution process in this embodiment, the convolution algorithm may be taken as an example for illustration: First, initialize the configuration through CFG. Then, load the weight value vector (such as vector B0~B31) through LDB instruction before calculation, and enter the dot product array in pre-loaded form. The data at the same position on several convolution kernels can be deployed to the dot product array. The number of loaded vectors is consistent with the number of dot product units in the dot product array, which is determined by the hardware design.

[0071] Then load several eigenvalue vectors (such as vectors A0~A127) through the LDA instruction.

[0072] The first step of LDA: wait for the weight value vector to be loaded, and then deploy vector A0 to the dot product array. At this time, no calculation instructions are required, and AIE can automatically perform the dot product calculation of all weight vectors and eigenvalue vector A0. If the accumulation function of LDA is turned on, the hardware will add the dot product result to the data in the accumulation result buffer and store the addition result in the accumulation result buffer. Otherwise, the hardware directly stores the dot product result in the accumulation result buffer.

[0073] The second step of LDA: deploy vector A1 into the dot product array. AIE can automatically perform the same calculation operation as the first step. By analogy, an LDA can load multiple eigenvalue vectors, perform multiple dot products and accumulation operations. In addition, all loaded eigenvalue vectors can be mapped to the input feature map.

[0074] Through the ST instruction, the accumulated result can be taken out from the accumulated result buffer, and after scaling / offset operation and output format conversion according to the configuration, the result can be written back to the storage component. If the ST instruction opens the statistics and write back the absolute maximum value, the absolute maximum value of the calculated result can also be written back to the local storage component.

[0075] In addition, based on the method of this embodiment, several instruction sequences can be given to achieve different purposes: Sequence 1: CFG→CTN→ST, automatically configures multiple LDB / LDA, allowing the hardware to implement larger-scale dot product operations.

[0076] Sequence 2: LDB→LDA→LDA→LDA→ST, loading a large number of eigenvalues ​​while reusing weight values.

[0077] Sequence three: CFG→LDA→ST, turn on the fast format conversion and transcendental function mode. At this time, there is no need to load OPB, and DPA automatically assigns values ​​to OPB.

[0078] In this embodiment, an extended AI instruction sequence pre-configured by a user is obtained, and the extended AI instructions in the extended AI instruction sequence are executed according to the extended AI instruction sequence; when any extended AI instruction is executed, the pre-stored AI instruction configuration information is called from a general register or a local internal register according to the instruction addressing information of the target field in the extended AI instruction; and the corresponding AI instruction is executed according to the AI ​​instruction configuration information. Based on this, with the help of extended AI instructions, general registers and local internal registers, a 32-bit instruction can accommodate more AI instruction configuration information, thereby reducing the miss rate of the instruction cache and improving computing efficiency.

[0079] Embodiment 2: Figure 2 This is a schematic diagram of the structure of an extended execution device for AI instructions provided in the second embodiment of the present application. The extended execution device for AI instructions provided in the embodiment of the present application can execute the extended execution method for AI instructions provided in any embodiment of the present application, and has the corresponding functional modules and beneficial effects of the execution method. The device can be implemented in software and / or hardware, such as Figure 2 As shown, the extended execution device of the AI ​​instruction specifically includes: a first execution module 201, a calling module 202, and a second execution module 203.

[0080] The first execution module is used to obtain an extended AI instruction sequence pre-configured by a user, and execute the extended AI instructions in the extended AI instruction sequence according to the extended AI instruction sequence; A calling module, used for calling pre-stored AI instruction configuration information from a general register or a local internal register according to instruction addressing information of a target field in the extended AI instruction when any extended AI instruction is executed; The second execution module is used to execute the corresponding AI instruction according to the AI ​​instruction configuration information.

[0081] Embodiment three: Figure 3 A schematic diagram of the structure of an electronic device provided in Embodiment 3 of the present application is shown in FIG. Figure 3 As shown, the electronic device includes a processor 310, a memory 320, an input device 330 and an output device 340; the number of the processor 310 in the electronic device can be one or more. Figure 3 A processor 310 is taken as an example; the processor 310, the memory 320, the input device 330 and the output device 340 in the electronic device can be connected via a bus or other means. Figure 3 The example of connecting through bus is taken in the following.

[0082] The memory 320, as a computer-readable storage medium, can be used to store software programs, computer executable programs and modules, such as program instructions / modules corresponding to the extended execution method of the AI ​​instruction in the embodiment of the present invention. The processor 310 executes various functional applications and data processing of the electronic device by running the software programs, instructions and modules stored in the memory 320, that is, implements the extended execution method of the AI ​​instruction mentioned above: Obtaining an extended AI instruction sequence pre-configured by a user, and executing the extended AI instructions in the extended AI instruction sequence according to the extended AI instruction sequence; When any extended AI instruction is executed, the pre-stored AI instruction configuration information is called from a general register or a local internal register according to the instruction addressing information of the target field in the extended AI instruction; Execute the corresponding AI command according to the AI ​​command configuration information.

[0083] Furthermore, the method also includes: Obtain the user's instruction configuration information, which includes multiple instruction information and sequence information. Each instruction information includes instruction type and field configuration information; For any instruction information, obtain the extended AI instruction template corresponding to the instruction type, and fill the field configuration information into the extended AI instruction template to obtain the extended AI instruction corresponding to the instruction information; The extended AI instructions are sorted according to the sequence information to obtain an extended AI instruction sequence.

[0084] Furthermore, the method also includes: Each time an instruction is executed, the instruction is parsed. If the parsed instruction is an extended AI instruction, it is determined that any extended AI instruction is executed.

[0085] Further, according to the instruction addressing information of the target field in the extended AI instruction, the pre-stored AI instruction configuration information is called from the general register or the local internal register, including: Obtaining an index address in a first target field and a field value in a second target field; If the field value is the first preset field value, calling the pre-stored AI instruction configuration information from the index address of the general register; If the field value is the second preset field value, the pre-stored AI instruction configuration information is called from the index address of the local internal register.

[0086] Furthermore, the extended AI instructions are executed asynchronously by the AI ​​accelerator.

[0087] Furthermore, the method also includes: During the execution of any extended AI instruction, if a preset target operation is performed, a field value of a third target field in the extended AI instruction and a target register address in a fourth target field are obtained; If the field value of the third target field is the third preset field value, determining the general register as the target register; If the field value of the third target field is the fourth preset field value, determining the local internal register as the target register; Performs a preset target operation based on the target register address.

[0088] Further, the preset target operation is a write answer word operation.

[0089] The memory 320 may mainly include a program storage area and a data storage area, wherein the program storage area may store an operating system and at least one application required for a function; the data storage area may store data created according to the use of the terminal, etc. In addition, the memory 320 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device. In some instances, the memory 320 may further include a memory remotely arranged relative to the processor 310, and these remote memories may be connected to the electronic device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0090] Embodiment 4: Embodiment 4 of the present application further provides a storage medium containing computer executable instructions. When the computer executable instructions are executed by a computer processor, they are used to execute an extended execution method of an AI instruction. The method includes: Obtaining an extended AI instruction sequence pre-configured by a user, and executing the extended AI instructions in the extended AI instruction sequence according to the extended AI instruction sequence; When any extended AI instruction is executed, the pre-stored AI instruction configuration information is called from a general register or a local internal register according to the instruction addressing information of the target field in the extended AI instruction; Execute the corresponding AI command according to the AI ​​command configuration information.

[0091] Furthermore, the method also includes: Obtain the user's instruction configuration information, which includes multiple instruction information and sequence information. Each instruction information includes instruction type and field configuration information; For any instruction information, obtain the extended AI instruction template corresponding to the instruction type, and fill the field configuration information into the extended AI instruction template to obtain the extended AI instruction corresponding to the instruction information; The extended AI instructions are sorted according to the sequence information to obtain an extended AI instruction sequence.

[0092] Furthermore, the method also includes: Each time an instruction is executed, the instruction is parsed. If the parsed instruction is an extended AI instruction, it is determined that any extended AI instruction is executed.

[0093] Further, according to the instruction addressing information of the target field in the extended AI instruction, the pre-stored AI instruction configuration information is called from the general register or the local internal register, including: Obtaining an index address in a first target field and a field value in a second target field; If the field value is the first preset field value, calling the pre-stored AI instruction configuration information from the index address of the general register; If the field value is the second preset field value, the pre-stored AI instruction configuration information is called from the index address of the local internal register.

[0094] Furthermore, the extended AI instructions are executed asynchronously by the AI ​​accelerator.

[0095] Furthermore, the method also includes: During the execution of any extended AI instruction, if a preset target operation is performed, a field value of a third target field in the extended AI instruction and a target register address in a fourth target field are obtained; If the field value of the third target field is the third preset field value, determining the general register as the target register; If the field value of the third target field is the fourth preset field value, determining the local internal register as the target register; Performs a preset target operation based on the target register address.

[0096] Further, the preset target operation is a write answer word operation.

[0097] Of course, the storage medium containing computer executable instructions provided in the embodiments of the present application, whose computer executable instructions are not limited to the above method operations, can also execute related operations in the extended execution method of the AI ​​instructions provided in any embodiment of the present application.

[0098] Through the above description of the implementation method, the technicians in the relevant field can clearly understand that the present application can be implemented by means of software and necessary general hardware, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application can be essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as a computer floppy disk, read-only memory (ROM), random access memory (RAM), flash memory (FLASH), hard disk or optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, server, or network device, etc.) to execute the methods of each embodiment of the present application.

[0099] It is worth noting that in the embodiment of the above-mentioned search device, the various units and modules included are only divided according to functional logic, but are not limited to the above-mentioned division, as long as the corresponding functions can be achieved; in addition, the specific names of the functional units are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application.

[0100] Note that the above are only preferred embodiments of the present application and the technical principles used. Those skilled in the art will understand that the present application is not limited to the specific embodiments herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present application. Therefore, although the present application is described in more detail through the above embodiments, the present application is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present application, and the scope of the present application is determined by the scope of the appended claims.

Claims

1. An extended execution method of an AI instruction, characterized in that: The method comprises: Acquire an extended AI instruction sequence pre-configured by a user, and execute the extended AI instructions in the extended AI instruction sequence according to the extended AI instruction sequence; When any of the extended AI instructions is executed, calling the pre-stored AI instruction configuration information from a general register or a local internal register according to the instruction addressing information of the target field in the extended AI instruction; Execute the corresponding AI instruction according to the AI ​​instruction configuration information; The calling of pre-stored AI instruction configuration information from a general register or a local internal register according to the instruction addressing information of the target field in the extended AI instruction includes: Obtaining an index address in a first target field and a field value in a second target field; If the field value is a first preset field value, calling pre-stored AI instruction configuration information from the index address of the general register; If the field value is the second preset field value, the pre-stored AI instruction configuration information is called from the index address of the local internal register.

2. The method according to claim 1, characterized in that The method further comprises: Acquire the user's instruction configuration information, wherein the instruction configuration information includes multiple instruction information and sequence information, and each instruction information includes an instruction type and field configuration information; For any instruction information, obtain an extended AI instruction template corresponding to the instruction type, and fill the field configuration information into the extended AI instruction template to obtain the extended AI instruction corresponding to the instruction information; The extended AI instructions are sorted according to the sequence information to obtain an extended AI instruction sequence.

3. The method according to claim 1, characterized in that The method further comprises: Each time an instruction is executed, the instruction is parsed. If the instruction is parsed as an extended AI instruction, it is determined that any of the extended AI instructions has been executed.

4. The method according to claim 1, characterized in that: The extended AI instructions are asynchronously executed by the AI ​​accelerator.

5. The method according to claim 1, characterized in that The method further comprises: During the execution of any of the extended AI instructions, if a preset target operation is performed, obtaining a field value of a third target field in the extended AI instruction and a target register address in a fourth target field; If the field value of the third target field is a third preset field value, determining the general register as the target register; If the field value of the third target field is the fourth preset field value, determining the local internal register as the target register; The preset target operation is performed based on the target register address.

6. The method according to claim 5, characterized in that The preset target operation is a write answer word operation.

7. An extended execution device for AI instructions, characterized in that: The device comprises: A first execution module, configured to obtain an extended AI instruction sequence pre-configured by a user, and execute the extended AI instructions in the extended AI instruction sequence according to the extended AI instruction sequence; A calling module, configured to call pre-stored AI instruction configuration information from a general register or a local internal register according to instruction addressing information of a target field in the extended AI instruction when any of the extended AI instructions is executed; A second execution module, configured to execute the corresponding AI instruction according to the AI ​​instruction configuration information; The calling module is specifically used for: Obtaining an index address in a first target field and a field value in a second target field; If the field value is a first preset field value, calling pre-stored AI instruction configuration information from the index address of the general register; If the field value is the second preset field value, the pre-stored AI instruction configuration information is called from the index address of the local internal register.

8. An electronic device, characterized in that: include: one or more processors; a storage device for storing one or more programs, When the one or more programs are executed by the one or more processors, the one or more processors implement the extended execution method of the AI ​​instruction as described in any one of claims 1-6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the extended execution method of the AI ​​instruction as described in any one of claims 1 to 6 is implemented.

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