Control method of QLC memory, electronic equipment and readable storage medium

Abstract

The invention discloses a QLC memory control method, electronic equipment and a readable storage medium. The method comprises the following steps: identifying workload features by using a machine learning model; carrying out load evaluation according to the working load characteristics; and carrying out dynamic resource allocation according to a load evaluation result, wherein the resources comprise read-write resources, cache resources and I / O scheduling resources. In this way, the resource utilization rate and the system efficiency can be improved.

Description

Technical Field

[0001] The present application relates to the field of memory technology, and in particular to a control method, electronic device, and readable storage medium of a QLC memory. Background Art

[0002] As data center workloads become increasingly complex and diverse, traditional statically configured storage systems are difficult to adapt to different application requirements. QLC (Quad-Level Cell) storage excels in providing high-capacity and low-cost solutions, but faces challenges in write durability and performance. In a multi-tenant environment, resource contention and performance interference issues are prominent, and the manual configuration and tuning process is complex, resulting in high operation and maintenance costs. There is significant room for improvement in resource utilization and system efficiency of related storage systems. Summary of the invention

[0003] The control method, electronic device, and readable storage medium of the QLC memory provided in the present application can improve resource utilization and system efficiency.

[0004] In a first aspect, the present application provides a control method for a QLC memory, the method comprising: using a machine learning model to identify workload characteristics; performing load evaluation based on the workload characteristics; and dynamically allocating resources based on the load evaluation results, the resources including read-write resources, cache resources, and I / O scheduling resources.

[0005] Among them, performing load assessment according to workload characteristics includes: obtaining corresponding performance indicators according to the workload characteristics; and performing load assessment according to the performance indicators.

[0006] Among them, dynamic resource allocation is performed according to the load assessment results, including: resource stratification based on the load assessment results, hot data and access patterns to obtain hot data layers, cold data layers and archive layers; resource reallocation is performed according to the hot data layers, cold data layers and archive layers.

[0007] Among them, after dynamic resource allocation is performed according to the load evaluation result, it includes: delay analysis, throughput measurement and resource efficiency evaluation of the QLC memory.

[0008] The method further includes: receiving target data and performing a cache hit judgment on the target data; in response to a hit on the first cache, updating the data according to the first cache; in response to a hit on the second cache, updating the data according to the second cache; wherein the access speed of the first cache is greater than the access speed of the second cache; and in response to a cache miss, writing the target data to the QLC memory.

[0009] The method further includes: using a machine learning model to predict the data to be read; and calling the data to be read into the first cache.

[0010] Among them, using a machine learning model to predict the data to be read includes: obtaining historical access patterns and access frequencies; and building a machine learning model using historical access patterns and access frequencies.

[0011] After the data to be read is transferred into the first cache, the method includes: receiving a data read request; if the data corresponding to the data read request is located in the first cache, reading the data corresponding to the data read request from the first cache.

[0012] In a second aspect, the present application provides an electronic device, comprising a processor and a memory connected to the processor; the memory is used to store a computer program, and when the computer program is executed by the processor, it is used to implement the method provided in the first aspect.

[0013] In a third aspect, the present application provides a computer-readable storage medium for storing a computer program, which, when executed by a processor, is used to implement the method provided in the first aspect.

[0014] The beneficial effects of the present application are as follows: different from the prior art, the control method of the QLC memory, the electronic device, and the readable storage medium provided by the present application use a machine learning model to identify workload characteristics; perform load evaluation based on the workload characteristics; and dynamically allocate resources based on the load evaluation results. The resources include read-write resources, cache resources, and I / O scheduling resources, which can be dynamically adjusted to adapt to different application characteristics and resource allocation, thereby improving resource utilization and system efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. Among them: Figure 1 It is a flowchart of an embodiment of a control method of a QLC memory provided by the present application; Figure 2 It is a flowchart of another embodiment of the control method of the QLC memory provided by the present application; Figure 3 It is a flowchart of another embodiment of the control method of the QLC memory provided by the present application; Figure 4 It is a flowchart of another embodiment of the control method of the QLC memory provided by the present application; Figure 5This is a schematic diagram of an application scenario of a control method for a QLC memory provided by the present application; Figure 6 This is a schematic diagram of the dynamic address mapping module architecture provided by this application; Figure 7 It is a structural schematic diagram of an embodiment of an electronic device provided by the present application; Figure 8 It is a structural schematic diagram of an embodiment of a computer-readable storage medium provided by the present application. DETAILED DESCRIPTION

[0016] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It will be understood that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for ease of description, only some but not all structures related to the present application are shown in the drawings. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application.

[0017] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0018] As data center workloads become increasingly complex and diverse, traditional statically configured storage systems are difficult to adapt to different application requirements. QLC (quadruple-level cell) storage excels in providing high-capacity and low-cost solutions, but faces challenges in write durability and performance. In a multi-tenant environment, resource contention and performance interference issues are prominent, and the manual configuration and tuning process is complex, resulting in high operation and maintenance costs. Existing storage systems have significant room for improvement in resource utilization and system efficiency.

[0019] Based on this, the present application proposes to use a machine learning model to identify workload characteristics; perform load evaluation based on workload characteristics; and dynamically allocate resources based on the load evaluation results. Resources include read and write resources, cache resources, and I / O scheduling resources, which can be dynamically adjusted to adapt to different application characteristics and resource allocation, thereby improving resource utilization and system efficiency. For details, please refer to any of the following embodiments or any combination of the embodiments.

[0020] See also Figure 1 , Figure 1 1 is a flow chart of an embodiment of a control method for a QLC memory provided by the present application. The method comprises: Step 11: Use machine learning models to identify workload characteristics.

[0021] In some embodiments, the machine learning model can be trained in the following manner: Data collection: Continuously collect the IO operation logs of the QLC storage, capture read and write characteristics in real time, and record detailed IO indicators. In some embodiments, the IO indicator can be IOPS, I / O per second, that is, the number of I / Os that can be processed per second, which is used to measure the I / O processing capacity of the storage system. IO indicators can be bandwidth, response time, busyness, etc.

[0022] Preprocess the collected data, such as data cleaning and standardization, feature engineering, outlier processing, and data normalization.

[0023] Perform feature extraction on the preprocessed data, such as extracting IO pattern feature vectors, calculating statistical features, identifying workload features, and performing dimensionality reduction on features.

[0024] Use the extracted features to train the machine learning model. Specifically, it involves algorithm selection and model construction, as well as the division of training / test sets, cross-validation, and optimization of hyperparameters in the model.

[0025] After training, the model is evaluated. Specifically, performance indicator analysis, accuracy evaluation, confusion matrix, and model error analysis are performed. After the evaluation is passed, the machine learning model can be used for subsequent reasoning.

[0026] Real-time reasoning includes model deployment, which can be used to perform IO pattern analysis, performance monitoring, and workload feature prediction in real time.

[0027] Furthermore, performance feedback can be performed, such as collecting actual operation data, comparing predicted workload characteristics with actual workload characteristics, and identifying performance deviations and recording model errors. Then, the performance feedback data can be used to optimize the model. For example, the model can be adjusted according to the feedback data, incremental learning can be performed on the model, feature parameters can be dynamically updated, and algorithm parameters can be optimized. Furthermore, based on model iteration, data can be collected again during data collection, and the optimized model can be introduced to continuously improve performance.

[0028] Step 12: Perform load assessment based on workload characteristics.

[0029] Step 13: Dynamically allocate resources based on the load assessment results. Resources include read and write resources, cache resources, and I / O scheduling resources.

[0030] In some embodiments, the QLC storage is provided with an adaptive management engine, which uses a machine learning model to analyze IO patterns in real time and provide workload feature identification. A multi-level resource scheduling framework is provided to dynamically adjust resource allocation based on the workload feature prediction data of the machine learning model, giving full play to the high capacity advantage of QLC storage. A closed-loop performance management mechanism is used to achieve automated tuning and online policy updates to optimize performance.

[0031] In this embodiment, a machine learning model is used to identify workload characteristics; load assessment is performed based on the workload characteristics; and dynamic resource allocation is performed based on the load assessment results. Resources include read and write resources, cache resources, and I / O scheduling resources, which can be dynamically adjusted to adapt to different application characteristics and resource allocation, thereby improving resource utilization and system efficiency.

[0032] See also Figure 2 , Figure 2 1 is a flow chart of another embodiment of the control method of the QLC memory provided by the present application. The method comprises: Step 21: Use machine learning models to identify workload characteristics.

[0033] Step 22: Obtain corresponding performance indicators based on workload characteristics.

[0034] Step 23: Perform load assessment based on performance indicators.

[0035] In some embodiments, system load, performance indicators, and capacity utilization can be dynamically evaluated based on workload characteristics.

[0036] Step 24: Dynamically allocate resources based on the load assessment results. The resources include read-write resources, cache resources, and I / O scheduling resources.

[0037] In some embodiments, resource stratification is performed in combination with load assessment results, hot data, and access patterns to obtain a hot data layer, a cold data layer, and an archive layer; and resource reallocation is performed based on the hot data layer, the cold data layer, and the archive layer. For example, when reallocating resources, it is necessary to optimize I / O scheduling, data migration, and cache strategies based on the hot data layer, the cold data layer, and the archive layer.

[0038] In some embodiments, after dynamic resource allocation is performed based on the load evaluation results, latency analysis, throughput measurement, and resource efficiency evaluation are performed on the QLC memory. After latency analysis, throughput measurement, and resource efficiency evaluation are obtained, continuous monitoring and adjustment are performed.

[0039] In some embodiments, after the workload characteristics are obtained, data collection is performed. For example, read request tracking, write request tracking, and access frequency statistics are performed. Then, access pattern analysis is performed based on the collected data. After the analysis is completed, hot data identification is performed. For example, the frequency threshold is used to determine whether the data is hot data, and then the data heat level is divided, and then dynamic heat adjustment is performed. After the dynamic heat adjustment, data migration is required. High-frequency data is marked, and storage location allocation is prioritized, and low-frequency data is downgraded and migrated to its corresponding storage location. After data migration, the migration is evaluated, such as access delay analysis, storage efficiency evaluation, and hot data hit rate evaluation. Feedback optimization is performed based on these evaluation results, so as to optimize strategies such as frequency thresholds and storage resource allocation, and achieve closed-loop continuous optimization.

[0040] In this embodiment, the workload characteristics of the machine learning model are used to predict data and efficiently locate and manage hot data, reduce write amplification effects, and extend the QLC storage life. See also Figure 3 , Figure 3 1 is a flow chart of another embodiment of the control method of the QLC memory provided by the present application. The method comprises: Step 31: Receive target data and perform cache hit determination on the target data.

[0041] Step 32: In response to hitting the first cache, update data according to the first cache.

[0042] In some embodiments, the first cache may be a high-speed cache. In response to hitting the first cache, the target data is quickly read and written, and the data is updated to obtain corresponding performance data. At the same time, performance statistics may be performed, such as access frequency statistics, cache heat evaluation, cache hit rate analysis, and cache strategy adjustment.

[0043] Step 33: In response to hitting the second cache, update data according to the second cache.

[0044] The access speed of the first cache is greater than the access speed of the second cache.

[0045] In some embodiments, the second cache may be an intermediate cache. After hitting the second cache, the data is loaded and a thermal analysis is performed. Cache scheduling is performed based on the thermal analysis, and the cache of the target data may be adjusted based on the thermal analysis results. For example, if, according to the thermal analysis, the target data can be cached in the first cache, cache scheduling is performed to cache the target data in the first cache. If, according to the thermal analysis, the target data can be cached in the second cache, the target data is cached in the second cache.

[0046] Step 34: In response to a cache miss, write the target data to the QLC memory.

[0047] In some embodiments, if the cache is not hit, the data is written to the QLC memory in the write order, and performance monitoring and write pressure analysis are performed.

[0048] In the above process, performance statistics are performed based on the working process of the first cache, the second cache, and the miss cache. For example, access frequency statistics are performed, and then cache heat evaluation, cache hit rate analysis, and cache strategy adjustment are performed. Then, cache strategy optimization is performed based on performance statistics to achieve adaptive cache strategy adjustment, thereby changing the cache hit judgment logic in real time.

[0049] See also Figure 4 , Figure 4 1 is a flow chart of another embodiment of the control method of the QLC memory provided by the present application. The method comprises: Step 41: Use the machine learning model to predict the data to be read.

[0050] In some embodiments, the machine learning model can also be constructed by obtaining historical access patterns and access frequencies and utilizing historical access patterns and access frequencies.

[0051] Step 42: Load the data to be read into the first cache.

[0052] In some embodiments, after the data to be read is loaded into the first cache, a data read request is received; if the data corresponding to the data read request is located in the first cache, the data corresponding to the data read request is read from the first cache.

[0053] In this embodiment, a machine learning model is used to formulate a data prefetch strategy, such as determining the prefetch range, sorting the prefetch priority, and evaluating the prefetch overhead, so as to formulate a reasonable prefetch strategy. Then the prefetch strategy is issued. Then the prefetch strategy is executed in the QLC memory. Specifically, data is pre-read according to the prefetch strategy, the pre-read data is cached and performance is monitored at the same time. And performance evaluation is performed based on performance monitoring. Such as access hit rate analysis, delay reduction evaluation, and energy consumption overhead analysis. According to the performance evaluation results, the prefetch strategy is tuned. For example, dynamic adjustment of parameters, algorithm optimization of the machine learning model, and iterative update of the machine learning model. The whole process achieves closed-loop feedback.

[0054] In one application scenario, the workflow of QLC storage is: First, workload feature perception and analysis. Use machine learning models to continuously monitor and analyze IO patterns. Capture data access patterns, read and write features, and performance indicators in real time. Build dynamic workload feature maps.

[0055] Second, intelligent dynamic resource scheduling. Use a multi-level resource scheduling framework to allocate resources based on real-time workload characteristics. Dynamically adjust the read and write strategies of QLC storage to balance performance and lifespan. Intelligent cache allocation: Quickly adjust multi-level cache strategies based on data access popularity Third, intelligent management of hot data. Use machine learning algorithms to identify data access hot spots. Track data access frequency and patterns in real time. Dynamically adjust data layout to reduce write amplification effects.

[0056] The key technical innovations are: 1. Adaptive management engine enhancement: Introducing machine learning algorithms enables resource scheduling strategies to learn and evolve autonomously.

[0057] Build prediction models based on historical data to make performance and resource forecasts in advance.

[0058] Achieve closed-loop performance management and support online real-time updates of strategies.

[0059] Furthermore, workload feature recognition can capture and analyze IO access patterns in real time, identify application load types and features, and predict load change trends and build workload profiles.

[0060] Furthermore, intelligent resource scheduling can dynamically allocate resources based on workload characteristics, manage multi-dimensional resource quotas, isolate resources between tenants, and optimize system-level resource utilization.

[0061] Furthermore, the performance guarantee mechanism can perform fine-grained QoS control, performance bottleneck prediction, automated performance tuning, and SLA breach prevention.

[0062] 2. Intelligent data layout optimization: Dynamic and intelligent allocation of multi-level cache.

[0063] Data prefetching optimization algorithm: Predictive prefetching based on machine learning predicts the data that may be accessed in the future based on the access pattern, and loads the data that may be accessed into the cache in advance.

[0064] Key features of the system: adaptability, intelligence, efficiency and scalability.

[0065] Adaptability: The system can dynamically adjust according to the load.

[0066] Intelligence: Use machine learning to make smart decisions.

[0067] Efficiency: Optimize data storage and access performance.

[0068] Scalability: The architecture design supports flexible expansion.

[0069] Furthermore, the QLC cache optimization architecture can improve the performance of storage devices.

[0070] Improved parallelism: By distributing data to different logical units, conflicts in accessing storage devices are reduced, and multi-channel and multi-plane architectures are fully utilized to improve the parallelism of data reading and writing.

[0071] Random access optimization: Multi-channel and multi-plane structured storage organizes data into continuous storage blocks (through neighbor arrays, block address arrays, etc.), greatly reducing the performance loss caused by random access.

[0072] Furthermore, the query efficiency is improved by using adjacent point query and logical-to-physical mapping optimization.

[0073] Acceleration of neighbor point query: Use the offset array to quickly locate the storage location of neighbor points without linear scanning, greatly reducing the query time.

[0074] Logical-to-physical mapping optimization: Through the dynamic address mapping module and logical-physical mapping of the block address array, storage addresses are quickly generated to achieve efficient access.

[0075] Furthermore, sparse optimization and mapping are used to save storage space.

[0076] Sparse optimization: Multi-channel and multi-plane structured storage compresses data and only stores the actual edges and vertices, avoiding unnecessary storage waste.

[0077] Mapping updates save resources: Dynamically update the mapping of logical to physical addresses, reduce frequent physical write operations, and extend the service life of storage devices.

[0078] Furthermore, dynamic management of logical addresses and maintenance of data consistency can improve system stability.

[0079] Dynamic management of logical addresses: supports data migration, garbage collection, and wear leveling, and maintains the stability and consistency of logical addresses in high-frequency read and write scenarios.

[0080] Data consistency maintenance: Multi-channel and multi-plane structured storage ensures that the logical-to-physical mapping is updated with refresh operations to avoid access errors or data loss.

[0081] Furthermore, large-scale graphs are supported and compatible with storage hardware, making it highly scalable.

[0082] Large-scale graph support: Multi-channel and multi-plane structured storage can store and manage massive nodes and edges, while supporting distributed storage and easy expansion.

[0083] Compatible with storage hardware: Applicable to a variety of modern storage devices such as SSD and QLC flash memory, optimizing storage performance while adapting to different hardware environments.

[0084] In one application scenario, combined with Figure 5 To explain: The host sends a query request to the PCIe switch.

[0085] The switch performs routing queries and feeds back to the main control core.

[0086] The master control core reads the query attribute from the DRAM module.

[0087] Specifically, the vertex value is read from the structured data storage model, and the vertex starting position, offset array and index adjacency list are provided to obtain the neighbor array. Then the logical unit number is mapped, and then the storage block address is mapped in the dynamic address mapping module and the consistency is maintained to obtain the block address array. Then the physical storage address is generated in the address generation module, and then the logical address is refreshed and the mapping relationship in the dynamic address mapping module is updated.

[0088] Further, cache access is scheduled and data blocks are managed using a distributor. Thus, the QLC cache controller is used to access data from the QLC storage module and the QLC storage module returns the corresponding query data. The QLC cache controller returns the processing result to the main control core. The main control core outputs the query result to the host.

[0089] Furthermore, the dynamic address mapping module architecture is as follows Figure 6 As shown, the query task is input, the query is performed using the query queue module, and then the task scheduling module, block access module, page access module, page buffer module, LDPC error correction module, output buffer module, multiplication and addition module, and acceleration control module are used in sequence for processing, and the corresponding query results are output to the query result return module, and the query results are returned to the host through the dynamic address mapping module. Figure 6 In the process, multiple accelerators can be used to coordinate and query tasks can be processed in parallel through multi-threading, greatly improving processing performance. The LDPC error correction module can ensure high reliability of stored data. The queue and scheduling functions provided by the acceleration control module can quickly allocate query tasks and improve query efficiency. The computing tasks can be directly executed in the storage device, and the computing module can be embedded in the storage to reduce data movement. Multiple dynamic mapping modules are supported in the storage, which can adapt to large-scale storage needs while reducing system computing delays and bandwidth bottlenecks.

[0090] See also Figure 7 , Figure 71 is a schematic diagram of the structure of an embodiment of an electronic device provided by the present application. The electronic device 70 includes a processor 71 and a memory 72 connected to the processor 71; the memory 72 is used to store a computer program, and when the computer program is executed by the processor 71, it is used to implement the following method: Use machine learning models to identify workload characteristics; perform load assessment based on workload characteristics; and dynamically allocate resources based on load assessment results. Resources include read and write resources, cache resources, and I / O scheduling resources.

[0091] In some embodiments, when the computer program is executed by the processor 71, it is also used to implement the following method: obtaining corresponding performance indicators according to workload characteristics; and performing load evaluation according to the performance indicators.

[0092] In some embodiments, when the computer program is executed by the processor 71, it is also used to implement the following method: perform resource stratification based on load assessment results, hot data and access patterns to obtain a hot data layer, a cold data layer and an archive layer; and reallocate resources based on the hot data layer, the cold data layer and the archive layer.

[0093] In some embodiments, after dynamic resource allocation is performed according to the load evaluation result, the computer program, when executed by the processor 71, is also used to implement the following method: performing latency analysis, throughput measurement, and resource efficiency evaluation on the QLC memory.

[0094] In some embodiments, when the computer program is executed by the processor 71, it is also used to implement the following method: receiving target data and performing a cache hit judgment on the target data; in response to a hit in the first cache, updating the data according to the first cache; in response to a hit in the second cache, updating the data according to the second cache; wherein the access speed of the first cache is greater than the access speed of the second cache; in response to a cache miss, writing the target data to the QLC memory.

[0095] In some embodiments, when the computer program is executed by the processor 71, it is also used to implement the following method: using a machine learning model to predict the data to be read; and calling the data to be read into the first cache.

[0096] In some embodiments, when the computer program is executed by the processor 71, it is also used to implement the following methods: obtaining historical access patterns and access frequencies; and building a machine learning model using historical access patterns and access frequencies.

[0097] In some embodiments, after the data to be read is loaded into the first cache, the computer program, when executed by the processor 71, is also used to implement the following method: receiving a data read request; if the data corresponding to the data read request is located in the first cache, reading the data corresponding to the data read request from the first cache.

[0098] It can be understood that when the computer program is executed by the processor 71, it is also used to implement the method of any of the above embodiments.

[0099] See also Figure 8 , Figure 8 1 is a schematic diagram of a computer readable storage medium according to an embodiment of the present application. The computer readable storage medium 80 is used to store a computer program 81. When the computer program 81 is executed by a processor, it is used to implement the following method: Use machine learning models to identify workload characteristics; perform load assessment based on workload characteristics; and dynamically allocate resources based on load assessment results. Resources include read and write resources, cache resources, and I / O scheduling resources.

[0100] In some embodiments, when the computer program 81 is executed by the processor, it is also used to implement the following method: obtaining corresponding performance indicators according to workload characteristics; and performing load evaluation according to the performance indicators.

[0101] In some embodiments, when the computer program 81 is executed by the processor, it is also used to implement the following method: perform resource stratification based on load assessment results, hot data and access patterns to obtain a hot data layer, a cold data layer and an archive layer; and reallocate resources based on the hot data layer, the cold data layer and the archive layer.

[0102] In some embodiments, after dynamic resource allocation is performed according to the load evaluation result, the computer program 81, when executed by the processor, is further used to implement the following method: performing latency analysis, throughput measurement, and resource efficiency evaluation on the QLC memory.

[0103] In some embodiments, when the computer program 81 is executed by the processor, it is also used to implement the following method: receiving target data and performing a cache hit judgment on the target data; in response to a hit in the first cache, updating the data according to the first cache; in response to a hit in the second cache, updating the data according to the second cache; wherein the access speed of the first cache is greater than the access speed of the second cache; in response to a cache miss, writing the target data to the QLC memory.

[0104] In some embodiments, when the computer program 81 is executed by the processor, it is also used to implement the following method: using a machine learning model to predict the data to be read; and calling the data to be read into the first cache.

[0105] In some embodiments, when the computer program 81 is executed by the processor, it is also used to implement the following methods: obtaining historical access patterns and access frequencies; and building a machine learning model using historical access patterns and access frequencies.

[0106] In some embodiments, after the data to be read is loaded into the first cache, the computer program 81 is also used to implement the following method when executed by the processor: receiving a data read request; if the data corresponding to the data read request is located in the first cache, reading the data corresponding to the data read request from the first cache.

[0107] It can be understood that when the computer program 81 is executed by the processor, it is also used to implement the method of any of the above embodiments.

[0108] In summary, the control method, electronic device, and readable storage medium of the QLC memory provided by the present application use a machine learning model to identify workload characteristics; perform load evaluation based on the workload characteristics; and dynamically allocate resources based on the load evaluation results. Resources include read and write resources, cache resources, and I / O scheduling resources, which can be dynamically adjusted to adapt to different application characteristics and resource allocation, thereby improving resource utilization and system efficiency.

[0109] In the several embodiments provided in this application, it should be understood that the disclosed methods and devices can be implemented in other ways. For example, the device implementation described above is only illustrative, for example, the division of the modules or units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed.

[0110] If the integrated units in the above other embodiments are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) or a processor to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, RandomAccess Memory), disk or optical disk and other media that can store program codes.

[0111] The above description is only an implementation method of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A control method for a QLC memory, characterized in that: The method comprises: Identify workload characteristics using machine learning models; performing load assessment according to the workload characteristics; Dynamic resource allocation is performed based on the load evaluation results, and the resources include read-write resources, cache resources, and I / O scheduling resources.

2. The control method according to claim 1, characterized in that: The performing load assessment according to the workload characteristics includes: Acquire corresponding performance indicators according to the workload characteristics; A load assessment is performed based on the performance indicators.

3. The control method according to claim 1, characterized in that: The dynamically allocating resources according to the load evaluation result includes: Perform resource stratification based on the load assessment results, hot data, and access patterns to obtain a hot data layer, a cold data layer, and an archive layer; Resources are reallocated according to the hot data tier, the cold data tier, and the archive tier.

4. The control method according to claim 3, characterized in that: After the dynamic resource allocation is performed according to the load evaluation result, the following steps are included: The QLC memory is subjected to latency analysis, throughput measurement, and resource efficiency evaluation.

5. The control method according to claim 1, characterized in that: The method further comprises: Receiving target data, and performing cache hit determination on the target data; In response to hitting the first cache, updating data according to the first cache; In response to hitting the second cache, updating data according to the second cache; wherein the access speed of the first cache is greater than the access speed of the second cache; In response to a cache miss, the target data is written to the QLC memory.

6. The control method according to claim 5, characterized in that: The method further comprises: Predicting data to be read using the machine learning model; The to-be-read data is loaded into the first cache.

7. The control method according to claim 6, characterized in that: The using the machine learning model to predict the data to be read includes: Obtain historical access patterns and access frequencies; The machine learning model is constructed using the historical access pattern and the access frequency.

8. The control method according to claim 6, characterized in that: After the to-be-read data is loaded into the first cache, the method further comprises: Receive data read request; If the data corresponding to the data read request is located in the first cache, the data corresponding to the data read request is read from the first cache.

9. An electronic device, characterized in that: The electronic device comprises a processor and a memory connected to the processor; the memory is used to store a computer program, and when the computer program is executed by the processor, it is used to implement the method according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium is used to store a computer program, and when the computer program is executed by a processor, the computer program is used to implement the method according to any one of claims 1 to 8.

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