Method and system for single-channel SRIO time-sharing transmission of various data based on FPGA

Abstract

The invention provides a method and a system for single-channel SRIO time-sharing transmission of various data based on an FPGA. The method comprises the following steps: waiting for first type data and receiving and caching second type data at the same time; the first type of data is used for communicating with first target equipment, and the second type of data is used for communicating with second target equipment; when the first type of data is received, preferentially transmitting the first type of data to the first target device, and after the first type of data is transmitted, if the second type of data is cached, transmitting the second type of data to the second target device; the first type of data and the second type of data are output through the same transmission channel, the real-time requirement of communication with the first target device is ensured, the second type of data is transmitted in the idle period of the bus after the first type of data is transmitted, the bandwidth of the transmission channel is fully utilized, the overall data transmission efficiency is improved, and the data transmission efficiency is improved. Requirements of hardware resources are reduced, and system cost and complexity are reduced.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a method and system for transmitting multiple data in a single-channel SRIO time-sharing manner based on FPGA. Background Art

[0002] SRIO is the best interconnection method for current point-to-point embedded processors, DSPs, FPGAs and other cluster networks. It has a high transmission rate and is widely used in aircraft board-level and system-level devices.

[0003] The control processing board can realize functions such as command reception and information feedback from the integrated control machine, telemetry and data recorder. In the traditional way, the communication between the control processor of the aircraft and other equipment of the aircraft is point-to-point, which requires a dedicated communication path to be established between every two devices. This method leads to an increase in the number of connectors and cables in the aircraft, high procurement and assembly costs, and also increases the consumption of limited space in the aircraft. Summary of the invention

[0004] In view of the above-mentioned defects or deficiencies in the prior art, the present application aims to provide a method and system for transmitting multiple data in a time-sharing manner using a single-channel SRIO based on FPGA.

[0005] In a first aspect, the present application proposes a method for transmitting multiple data in a single-channel SRIO time-sharing manner based on FPGA, comprising the following steps:

[0006] Waiting for first type data and simultaneously receiving and buffering second type data; the first type data is used to communicate with a first target device, and the second type data is used to communicate with a second target device;

[0007] When the first type of data is received, it is preferentially transmitted to the first target device, and after the first type of data is transmitted, if the second type of data is cached, the second type of data is transmitted to the second target device; and the first type of data and the second type of data are both output through the same transmission channel.

[0008] According to the technical solution provided in the embodiment of the present application, the first type of data is DSP instructions and data information, the second type of data is image data input by the imager, the first target device is an integrated control machine, and the second target device is a data recorder.

[0009] According to the technical solution provided in the embodiment of the present application, after the first type of data transmission is completed, the following steps are also included:

[0010] Determine the bus state; the bus state at least includes an idle period and an occupied period;

[0011] If the second type of data is cached, transmitting it to the second target device specifically includes the following steps:

[0012] When the bus state is in the idle period, if the second type of data is cached, it is transmitted to the second target device.

[0013] According to the technical solution provided in the embodiment of the present application, the step of preferentially transmitting the first type of data to the first target device after receiving the first type of data specifically includes the following steps:

[0014] After receiving the DSP instruction and data information, the DSP instruction and data information are output to the optical module through SRIO, and the optical module outputs the DSP instruction and data information to the integrated control machine through optical fiber.

[0015] According to the technical solution provided in the embodiment of the present application, the transmitting the second type of data to the second target device specifically includes the following steps:

[0016] After receiving the image data input by the imager, the image data input by the imager is output to the optical module through SRIO, and the optical module outputs the image data input by the imager to the data recorder through the optical fiber.

[0017] According to the technical solution provided in the embodiment of the present application, before waiting for the first type of data and simultaneously receiving and caching the second type of data, the following steps are also included:

[0018] Initializing the optical module;

[0019] Waiting for the first type of data and simultaneously receiving and buffering the second type of data specifically includes the following steps:

[0020] After the optical module is initialized, it waits for the first type of data and simultaneously receives the second type of data, and caches the second type of data into a cache area.

[0021] According to the technical solution provided in the embodiment of the present application, if the second type of data is cached, transmitting the second type of data to the second target device specifically includes the following steps:

[0022] It is determined whether the second type of data is stored in the buffer area; if the second type of data is stored in the buffer area, the second type of data is read out from the buffer area and transmitted to the second target device.

[0023] In the second aspect, the present application proposes a system for transmitting multiple data in a time-sharing manner using a single-channel SRIO based on FPGA, which is used to implement the method for transmitting multiple data in a time-sharing manner using a single-channel SRIO based on FPGA as described above, including:

[0024] A control and processing board, the control and processing board includes an FPGA, the FPGA implements data interaction of the first type of data with the DSP through the EMIF bus, the FPGA receives the second type of data through the LVDS interface, and the control and processing board also includes an optical module; the FPGA is connected to the electrical interface end of the optical module;

[0025] A target device, wherein the target device at least includes the first target device and the second target device, and the first target device and the second target device are connected to the optical interface end of the optical module.

[0026] According to the technical solution provided in the embodiment of the present application, the FPGA is connected to the electrical interface end of the optical module through SPIO.

[0027] According to the technical solution provided in the embodiment of the present application, the first target device and the second target device are connected to the optical interface end of the optical module through optical fibers.

[0028] In summary, the present application proposes a method and system for time-sharing transmission of multiple data using a single-channel SRIO based on FPGA, including the following steps: waiting for first type data and simultaneously receiving and caching second type data; the first type data is used to communicate with a first target device, and the second type data is used to communicate with a second target device; when the first type data is received, it is preferentially transmitted to the first target device, and after the transmission of the first type data is completed, if the second type data is cached, the second type data is transmitted to the second target device; and both the first type data and the second type data are output through the same transmission channel.

[0029] Compared with the prior art, the beneficial effects of the present application are: the present application transmits multiple data in time-sharing through a single-channel SRIO, avoiding the waste of resources and complexity caused by setting up independent transmission channels for different types of data, giving priority to transmission after receiving the first type of data, ensuring the real-time requirements of communication with the first target device, and transmitting the second type of data during the idle period of the bus after the first type of data transmission is completed, making full use of the bandwidth of the transmission channel and improving the overall data transmission efficiency. At the same time, compared with the traditional communication between different devices, multiple dedicated communication paths are established, resulting in an increase in the number of aircraft connectors and cables, reducing the demand for hardware resources and reducing system cost and complexity. The solution based on FPGA has high flexibility and scalability, and can adapt to different application scenarios and demand changes. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A flowchart of the steps of the method for transmitting multiple data in a single-channel SRIO time-sharing manner based on FPGA provided in this application;

[0031] Figure 2 A schematic diagram of the structure of a system for transmitting multiple data in a time-sharing manner using a single-channel SRIO based on FPGA provided in this application;

[0032] Figure 3 A flowchart of the steps of an implementation method of a method for transmitting multiple data in a single-channel SRIO time-sharing manner based on FPGA provided in the present application.

[0033] The text annotations in the figure represent:

[0034] 1. Imager; 2. DSP; 3. FPGA; 4. Optical module; 5. Integrated control machine; 6. Data recorder. DETAILED DESCRIPTION

[0035] The present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the relevant invention, rather than to limit the invention. It is also necessary to explain that, for ease of description, only the parts related to the invention are shown in the accompanying drawings.

[0036] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0037] Example 1

[0038] As mentioned in the background technology, in order to solve the problems in the prior art, this application proposes a method for transmitting multiple data in a single-channel SRIO time-sharing manner based on FPGA, please refer to Figure 1 As shown, the following steps are included:

[0039] Waiting for first type data and simultaneously receiving and buffering second type data; the first type data is used to communicate with a first target device, and the second type data is used to communicate with a second target device;

[0040] When the first type of data is received, it is preferentially transmitted to the first target device, and after the first type of data is transmitted, if the second type of data is cached, the second type of data is transmitted to the second target device; and the first type of data and the second type of data are both output through the same transmission channel.

[0041] Now let's explain the English words that appear in the full text. FPGA (Field Programmable Gate Array) is a field programmable gate array. It is an integrated circuit that can be programmed to implement specific digital logic functions. FPGA has the characteristics of high flexibility, strong parallel processing capabilities, and reconfigurability. It is widely used in digital signal processing, communication, computer vision and other fields.

[0042] SRIO (Serial RapidIO): Serial RapidIO is a high-performance, low-latency interconnect technology that is primarily used for chip-to-chip communication in embedded systems. It supports multiple data transmission modes, including point-to-point and switching structures, and can achieve high-speed data transmission and processing.

[0043] DSP (Digital Signal Processor): Digital signal processor. A microprocessor specifically used for digital signal processing, with powerful digital signal processing capabilities, such as fast Fourier transform, filtering, compression, etc. It is widely used in audio, video, communications and other fields.

[0044] LVDS (Low-Voltage Differential Signaling): Low-voltage differential signal. It is a high-speed digital signal transmission technology that uses low-voltage differential signal transmission. It has the advantages of low power consumption, low noise, and high speed. It is often used in high-speed data transmission, such as in image transmission, communication and other fields.

[0045] Specifically, the time-sharing transmission of multiple data in this embodiment clarifies the correspondence between different types of data and different target devices, making data transmission more targeted and efficient. For example, the first type of data is used to communicate with the first target device, meeting the needs of the specific device for real-time data; the second type of data is used to communicate with the second target device, ensuring the accurate transmission and storage of specific data. This optimized communication method helps to improve the performance and reliability of the entire aircraft system.

[0046] The time-sharing transmission method is adopted to avoid conflicts and interferences between different types of data during transmission. At the same time, by caching the second type of data, it is ensured that it is transmitted at the right time, reducing the risk of data loss. FPGA has high stability and reliability, can ensure the accuracy and integrity of data transmission, and improve the overall reliability and stability of the system.

[0047] This implementation is based on the FPGA+DSP architecture of the control and processing circuit board and the optical module chip, and has significant beneficial effects in data transmission efficiency, system cost, inter-device communication and system reliability, and provides an efficient and reliable data transmission solution for application scenarios such as aircraft infrared seekers.

[0048] In a preferred embodiment, the first type of data is DSP instructions and data information, the second type of data is image data input by the imager, the first target device is an integrated control machine, and the second target device is a data recorder.

[0049] In a preferred embodiment, after the first type of data transmission is completed, the method further includes the following steps:

[0050] Determine the bus state; the bus state at least includes an idle period and an occupied period;

[0051] If the second type of data is cached, transmitting it to the second target device specifically includes the following steps:

[0052] When the bus state is in the idle period, if the second type of data is cached, it is transmitted to the second target device.

[0053] In a preferred embodiment, the step of preferentially transmitting the first type of data to the first target device after receiving the first type of data specifically includes the following steps:

[0054] After receiving the DSP instruction and data information, the DSP instruction and data information are output to the optical module through SRIO, and the optical module outputs the DSP instruction and data information to the integrated control machine through optical fiber.

[0055] In a preferred embodiment, the transmitting the second type of data to the second target device specifically comprises the following steps:

[0056] After receiving the image data input by the imager, the image data input by the imager is output to the optical module through SRIO, and the optical module outputs the image data input by the imager to the data recorder through the optical fiber.

[0057] In a preferred embodiment, before waiting for the first type of data and simultaneously receiving and buffering the second type of data, the method further includes the following steps:

[0058] Initializing the optical module;

[0059] Waiting for the first type of data and simultaneously receiving and buffering the second type of data specifically includes the following steps:

[0060] After the optical module is initialized, it waits for the first type of data and simultaneously receives the second type of data, and caches the second type of data into a cache area.

[0061] In a preferred embodiment, if the second type of data is cached, transmitting the second type of data to the second target device specifically includes the following steps:

[0062] It is determined whether the second type of data is stored in the buffer area; if the second type of data is stored in the buffer area, the second type of data is read out from the buffer area and transmitted to the second target device.

[0063] Example 2

[0064] Based on Example 1, this example proposes a system for transmitting multiple data in a single-channel SRIO time-sharing manner based on FPGA, which is used to implement the method for transmitting multiple data in a single-channel SRIO time-sharing manner based on FPGA as described in Example 1. Figure 2 As shown, including:

[0065] A control and processing board, the control and processing board includes an FPGA, the FPGA implements data interaction of the first type of data with the DSP through the EMIF bus, the FPGA receives the second type of data through the LVDS interface, and the control and processing board also includes an optical module; the FPGA is connected to the electrical interface end of the optical module;

[0066] A target device, wherein the target device at least includes the first target device and the second target device, and the first target device and the second target device are connected to the optical interface end of the optical module.

[0067] In a preferred embodiment, the FPGA is connected to the electrical interface terminal of the optical module via SPIO.

[0068] In a preferred embodiment, the first target device and the second target device are connected to the optical interface end of the optical module through optical fibers.

[0069] Specifically, please refer to Figure 3 As shown, it is a specific implementation method of the present application, and the specific process is as follows: after the control processing board is powered on and initialized, the FPGA receives the data written by the DSP through the EMIF for cache, and receives the image data written by the imager through the LVDS for cache. After receiving the DSP instruction, all the cached DSP data information is read out, converted into the data format specified by the SRIO protocol, and output to the optical module through the SRIO bus; during the idle period of the bus after sending the DSP data, if there is image data in the buffer, a packet of image data is read from the buffer according to the data format specified by the SRIO protocol, and output to the optical module through the SRIO bus; then determine whether it is necessary to send DSP data. If there is DSP data, the DSP data is sent first. If there is no DSP data, the image data continues to be sent until the image data buffer is cleared.

[0070] Through the above operation, the traditional method of using two SRIOs for the integrated control machine and the data recorder can be avoided, while the real-time response speed of communication with the integrated control machine can be guaranteed. This saves equipment hardware costs and aircraft space, and provides support for low-cost and miniaturized design.

[0071] This article uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and its core ideas of this application. The above is only the preferred implementation method of this application. It should be pointed out that due to the limitations of textual expression and the objective existence of infinite specific structures, ordinary technicians in this technical field can make several improvements, modifications or changes without departing from the principles of the present invention, and can also combine the above technical features in an appropriate manner; these improvements, modifications, changes or combinations, or the direct application of the inventive concept and technical solution to other occasions without improvement, should be regarded as the scope of protection of this application.

Claims

1. A method for transmitting multiple data in a single-channel SRIO time-sharing manner based on FPGA, characterized in that: The following steps are involved: Waiting for first type data and simultaneously receiving and buffering second type data; the first type data is used to communicate with a first target device, and the second type data is used to communicate with a second target device; When the first type of data is received, it is preferentially transmitted to the first target device, and after the first type of data is transmitted, if the second type of data is cached, the second type of data is transmitted to the second target device; and the first type of data and the second type of data are both output through the same transmission channel.

2. The method for transmitting multiple data in a single-channel SRIO time-sharing manner based on FPGA according to claim 1, characterized in that: The first type of data is DSP (2) instructions and data information, the second type of data is image data input by the imager (1), the first target device is an integrated control machine (5), and the second target device is a data recorder (6).

3. The method for transmitting multiple data in a single-channel SRIO time-sharing manner based on FPGA according to claim 1, characterized in that: After the first type of data transmission is completed, the method further comprises the following steps: Determine the bus state; the bus state at least includes an idle period and an occupied period; If the second type of data is cached, transmitting it to the second target device specifically includes the following steps: When the bus state is in the idle period, if the second type of data is cached, it is transmitted to the second target device.

4. The method for transmitting multiple data in a single-channel SRIO time-sharing manner based on FPGA according to claim 2, characterized in that: The method of preferentially transmitting the first type of data to the first target device after receiving the first type of data specifically includes the following steps: After receiving the DSP (2) instruction and data information, the DSP (2) instruction and data information are output to the optical module (4) through SRIO, and the optical module (4) outputs the DSP (2) instruction and data information to the integrated control machine (5) through optical fiber.

5. The method for transmitting multiple data in a single-channel SRIO time-sharing manner based on FPGA according to claim 2, characterized in that: The transmitting the second type of data to the second target device specifically comprises the following steps: After receiving the image data input by the imager (1), the image data input by the imager (1) is output to the optical module (4) via SRIO, and the optical module (4) outputs the image data input by the imager (1) to the data recorder (6) via optical fiber.

6. The method for transmitting multiple data in a single-channel SRIO time-sharing manner based on FPGA according to claim 4, characterized in that: Before waiting for the first type of data and simultaneously receiving and caching the second type of data, the following steps are also included: Initializing the optical module (4); Waiting for the first type of data and simultaneously receiving and buffering the second type of data specifically includes the following steps: After the optical module (4) is initialized, it waits for the first type of data and simultaneously receives the second type of data, and caches the second type of data into a cache area.

7. The method for transmitting multiple data in a single-channel SRIO time-sharing manner based on FPGA according to claim 6, characterized in that: If the second type of data is cached, transmitting the second type of data to the second target device specifically includes the following steps: It is determined whether the second type of data is stored in the buffer area; if the second type of data is stored in the buffer area, the second type of data is read out from the buffer area and transmitted to the second target device.

8. A system for transmitting multiple data in a time-sharing manner using a single-channel SRIO based on FPGA, for implementing the method for transmitting multiple data in a time-sharing manner using a single-channel SRIO based on FPGA (3) as claimed in any one of claims 1 to 7, characterized in that: include: A control and management processing board, the control and management processing board comprising an FPGA (3), the FPGA (3) realizing data interaction of the first type of data with the DSP (2) via an EMIF bus, the FPGA (3) receiving the second type of data via an LVDS interface, the control and management processing board further comprising an optical module (4); the FPGA (3) being connected to an electrical interface end of the optical module (4); A target device, the target device at least comprising the first target device and the second target device, the first target device and the second target device being connected to the optical interface end of the optical module (4).

9. The system for transmitting multiple data in a time-sharing manner using a single-channel SRIO based on FPGA according to claim 8, characterized in that: The FPGA (3) is connected to the electrical interface end of the optical module (4) via SPIO.

10. The system for transmitting multiple data in a time-sharing manner using a single-channel SRIO based on FPGA according to claim 8, characterized in that: The first target device and the second target device are connected to the optical interface end of the optical module (4) via optical fibers.

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