Writing method and device based on AXI bus interconnection matrix

Abstract

The invention provides a writing method and device based on an AXI bus interconnection matrix, and the method comprises the steps: responding to a writing operation request initiated by a master device to a slave device, and controlling a master device interface writing address channel to initiate a connection request to a slave device interface writing address channel; decoding the slave device interface applied to be accessed by the master device interface; if the decoding is successful, arbitrating a write address channel of the slave device interface; if the arbitration of the write address channel is passed, controlling the write data channel of the master device interface to initiate a connection request to the write data channel of the slave device interface, arbitrating the write data channel of the slave device interface, and obtaining write address information of the slave device; and if the write data channel arbitration passes, connecting the write data channel of the master device interface with the write data channel of the slave device interface, and controlling the slave device to initiate write data transmission to the master device according to the write address information. According to the embodiment of the invention, the write operation transmission efficiency is improved, and the limitation of the bus transmission performance is relieved.

Description

Technical Field

[0001] The present invention relates to the field of digital chip design, and in particular to a writing method and device based on an AXI bus interconnection matrix. Background Art

[0002] In the related technologies, as the scale of integrated circuit chips increases day by day, the functions and complexity of chips are improved, and the requirements for the processing speed performance of SOC (System on Chip) chips are getting higher and higher. As the central bridge connecting various modules, the internal bus of the chip has an important impact on the performance of the SOC system, especially in systems with multiple master devices and multiple slave devices. AXI (Advanced eXtensible Interface) is an on-chip bus for high performance, high bandwidth, and low latency in the AMBA (Advanced Microcontroller Bus Architecture) bus system proposed by ARM.

[0003] AXI is essentially a master-slave point-to-point interface protocol. The AXI protocol does not specify the specific implementation method of the bus interconnection matrix module. In the process of SOC chip design and implementation, designers need to design the bus interconnection matrix according to their needs or purchase ARM's interconnection matrix IP. In related technologies, either an independent arbitration method for read and write address channels is used, but the independence between address channels and data channels cannot be fully utilized, which will limit the bus transmission performance and fail to realize the advance transmission function of AXI; or a multi-level cascade method is used, but the interface conversion will consume clock cycles and increase transmission delay, which cannot meet the design requirements of high-performance SOC.

[0004] With respect to the above-mentioned problems existing in the related technologies, no efficient and accurate solutions have been found yet. Summary of the invention

[0005] The present invention provides a writing method and device based on an AXI bus interconnection matrix to solve the technical problems in related technologies.

[0006] According to one embodiment of the present invention, a writing method based on an AXI bus interconnection matrix is ​​provided, comprising: responding to a write operation request initiated by a master device to a slave device, controlling a write address channel of a master device interface to initiate a connection request to a write address channel of a slave device interface, wherein the system on chip SOC comprises a plurality of master devices and a plurality of slave devices, the master device is connected to the AXI bus via a master device interface, and the slave device is connected to the AXI bus via a slave device interface; decoding the slave device interface to which the master device interface applies for access; if the decoding is successful, arbitrating the write address channel of the slave device interface; if the write address channel arbitration passes, controlling the write data channel of the master device interface to initiate a connection request to the write data channel of the slave device interface, arbitrating the write data channel of the slave device interface, and obtaining the write address information of the slave device; if the write data channel arbitration passes, connecting the write data channel of the master device interface with the write data channel of the slave device interface, and controlling the slave device to initiate write data transmission to the master device according to the write address information.

[0007] According to another embodiment of the present invention, a writing device based on an AXI bus interconnection matrix is ​​provided, comprising: a control module, for responding to a write operation request initiated by a master device to a slave device, controlling a write address channel of a master device interface to initiate a connection request to a write address channel of a slave device interface, wherein the system on chip SOC comprises a plurality of master devices and a plurality of slave devices, the master device is connected to the AXI bus via a master device interface, and the slave device is connected to the AXI bus via a slave device interface; a decoding module, for decoding a slave device interface to which the master device interface applies for access; an arbitration module, for arbitrating the write address channel of the slave device interface if the decoding is successful; a processing module, for controlling the write data channel of the master device interface to initiate a connection request to the write data channel of the slave device interface if the write address channel arbitration passes, arbitrating the write data channel of the slave device interface, and acquiring the write address information of the slave device; a write operation module, for connecting the write data channel of the master device interface with the write data channel of the slave device interface if the write data channel arbitration passes, and controlling the slave device to initiate write data transmission to the master device according to the write address information.

[0008] According to another aspect of an embodiment of the present application, a storage medium is further provided, which includes a stored program, and the above steps are executed when the program is run.

[0009] According to another aspect of an embodiment of the present application, there is also provided an electronic device, including a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus; wherein: the memory is used to store computer programs; and the processor is used to execute the steps in the above method by running the program stored in the memory.

[0010] The embodiment of the present application also provides a computer program product including instructions, which, when executed on a computer, enables the computer to execute the steps in the above method.

[0011] Beneficial effects of the present invention:

[0012] 1. The AXI bus interconnection matrix system of the present invention provides a register configuration method for interface configuration and channel configuration of the AXI bus interconnection matrix. Compared with the hardened circuit configuration method of the prior art, it can realize flexible soft configuration of the modifiable access restrictions between master and slave devices of the AXI bus interconnection matrix, achieve the purpose of modifiable access, and effectively expand the application scenario scope of chip information security and functional safety.

[0013] 2. The AXI bus interconnection matrix system of the present invention provides a register configuration method for configuring the arbitration mechanism of the AXI bus interconnection matrix. The arbitration mechanism can be flexibly and softly configured to change the arbitration mechanism according to the register configuration. Compared with the hardened circuit configuration method of the prior art, it is more flexible and provides the possibility of changing the arbitration method after chip tape-out.

[0014] 3. The AXI bus interconnection matrix system of the present invention provides a channel-level task cache method. Compared with the entire burst transmission transaction cache or transmission data cache in the prior art, it occupies less storage resources of the interconnection matrix, is more efficient, and is accurate to each channel, giving full play to the advantages of independence between AXI bus channels.

[0015] 4. The address and data transmission of the write operation are independently arbitrated and transmitted, and channel-level task caching can be performed, which effectively improves the transmission efficiency of the write operation and thus effectively improves the chip performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of this application. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0017] Figure 1 is a hardware structure block diagram of a vehicle according to an embodiment of the present invention;

[0018] Figure 2 is a flow chart of a writing method based on an AXI bus interconnection matrix according to an embodiment of the present invention;

[0019] Figure 3 is a schematic diagram of an AXI bus interconnection matrix system according to an embodiment of the present invention;

[0020] Figure 4 is a schematic diagram of a configuration module in an embodiment of the present invention;

[0021] Figure 5 is a schematic diagram of the structure of an arbitration module in an embodiment of the present invention;

[0022] Figure 6 is an arbitration flow chart of the arbitration module in an embodiment of the present invention;

[0023] Figure 7 1 is a schematic diagram of a write operation transmission flow of an AXI bus interconnection matrix according to an embodiment of the present invention;

[0024] Figure 8 It is a structural block diagram of a writing device based on an AXI bus interconnection matrix according to an embodiment of the present invention. DETAILED DESCRIPTION

[0025] In order to enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only embodiments of a part of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work should fall within the scope of protection of the present application. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0026] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0027] Example 1

[0028] The method embodiment provided in the first embodiment of the present application can be executed in an onboard chip, a vehicle or a similar processing device. Taking running on a vehicle as an example, Figure 1 FIG. 1 is a hardware structure diagram of a vehicle according to an embodiment of the present invention. Figure 1 As shown, the vehicle may include one or more ( Figure 1Only one is shown in the figure) a processor 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data. Optionally, the above vehicle may also include a transmission device 106 and an input / output device 108 for communication functions. It can be understood by those skilled in the art that Figure 1 The structure shown is for illustration only and does not limit the structure of the above vehicle. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations shown.

[0029] The memory 104 can be used to store vehicle programs, for example, software programs and modules of application software, such as a vehicle program corresponding to a writing method based on an AXI bus interconnection matrix in an embodiment of the present invention. The processor 102 executes various functional applications and data processing by running the vehicle program stored in the memory 104, that is, implementing the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories may be connected to the vehicle via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0030] The transmission device 106 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by a communication provider of the vehicle. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0031] In this embodiment, a writing method based on an AXI bus interconnection matrix is ​​provided. Figure 2 is a flow chart of a writing method based on an AXI bus interconnection matrix according to an embodiment of the present invention, such as Figure 2 As shown, the process includes the following steps:

[0032] Step S202, in response to a write operation request initiated by the master device to the slave device, controlling the master device interface write address channel to initiate a connection request to the slave device interface write address channel, wherein the system on chip SOC includes multiple master devices and multiple slave devices, the master device is connected to the AXI bus through the master device interface, and the slave device is connected to the AXI bus through the slave device interface;

[0033] The master device of this embodiment includes a central processing unit CPU (Central Processing Unit), a direct memory access DMA (Direct Memory Access) device, and the slave device includes a static random access memory SRAM (Static Random-Access Memory) controller, a flash memory controller, and an advanced high-performance peripheral bus AXI-to-AHB (Advanced eXtensible Interface to Advanced High Performance Bus) bridge.

[0034] Step S204, decoding the slave device interface that the master device interface applies to access;

[0035] Step S206, if the decoding is successful, arbitrate the write address channel of the slave device interface;

[0036] Step S208, if the write address channel arbitration is passed, the write data channel of the master device interface is controlled to initiate a connection request to the write data channel of the slave device interface, arbitrate the write data channel of the slave device interface, and obtain the write address information of the slave device;

[0037] Step S210: If the write data channel arbitration is passed, the write data channel of the master device interface is connected to the write data channel of the slave device interface, and the slave device is controlled to initiate write data transmission to the master device according to the write address information.

[0038] Through the above steps, in response to the write operation request initiated by the master device to the slave device, the write address channel of the master device interface is controlled to initiate a connection request to the write address channel of the slave device interface, wherein the system on chip SOC includes multiple master devices and multiple slave devices, the master device is connected to the AXI bus through the master device interface, and the slave device is connected to the AXI bus through the slave device interface, the slave device interface to which the master device interface applies for access is decoded, if the decoding is successful, the write address channel of the slave device interface is arbitrated, if the write address channel arbitration passes, the write data channel of the master device interface is controlled to initiate a connection request to the write data channel of the slave device interface, the write data channel of the slave device interface is arbitrated, and the write address information of the slave device is obtained, if the write data channel arbitration passes, the write data channel of the master device interface is connected to the write data channel of the slave device interface, and the slave device is controlled to initiate write data transmission to the master device according to the write address information, which effectively expands the applicable scenario range of the AXI bus interconnection matrix, improves the write operation transmission efficiency, and thus improves the chip performance, makes full use of the independence between the address channel and the data channel, and removes the limitation of the bus transmission performance.

[0039] Figure 3 is a schematic diagram of an AXI bus interconnection matrix system according to an embodiment of the present invention. Figure 3 As shown, the process includes: m master device interfaces 30, n slave device interfaces 31, a configuration module 32, a decoding module 33, an arbitration module 34, and a cache module 35, wherein m and n are both positive integers greater than 0.

[0040] A master device interface 30, used to connect to a master device of a system on chip SOC, and the master device initiates a read / write operation to a slave device through the master device interface using a bus interconnection matrix system;

[0041] A slave device interface 31, used to connect to a slave device of the SOC, the slave device responding to a read / write operation using a bus interconnection matrix system through the slave device interface;

[0042] The master device interface is connected to an external master device, the slave device interface is connected to an external slave device, the master device initiates a read / write operation to the slave device using a bus interconnection matrix through the master device interface, and the slave device responds to the read / write operation using the bus interconnection matrix through the slave device interface.

[0043] Each master / slave interface has five independent channels, namely, write address channel (AW), write data channel (W), write reply channel (B), read address channel (AR), and read data channel (R); a channel of the master interface can only be connected to the same channel of the slave.

[0044] Due to AXI protocol restrictions, the number of master devices and slave devices, m and n, can be configured to be less than or equal to 16.

[0045] A configuration module 32, used to configure the connectivity relationship between the master device interface and the slave device interface, and to configure the arbitration strategy of the arbitration module using a register group;

[0046] A decoding module 33, used to decode the address information sent by the master device and determine the slave device interface corresponding to the access request;

[0047] When the master device initiates an access request (read / write operation) to the slave device, it carries the address information of the slave device to which access is requested.

[0048] The decoding module is connected to the read address channel and write address channel of the master-slave device interface, and includes two parts: read address decoding and write address decoding. During decoding, according to the slave device storage address table, the decoding module decodes the address information sent by the master device and obtains the slave device corresponding to the address information, that is, the slave device requested to access by the master device. The slave device storage address table is used to record the address space range of all slave devices. The address table is adjusted according to the interface configuration and channel configuration results to implement read and write access restrictions between master and slave devices. The decoding module sends the decoding result to the arbitrator of the slave device for arbitration.

[0049] The arbitration module 34, each channel of each slave device interface corresponds to an independent arbitrator, which is used to perform arbitration gating according to the arbitration strategy when receiving the application gating signals of multiple master device channels;

[0050] The cache module 35 is used to cache data for channel-level transmission tasks of the address channel and data channel of the master device during the access operation.

[0051] In one implementation of the present embodiment, decoding the slave device interface to which the master device interface applies for access includes: controlling the write address channel of the master device interface to send the address information of the slave device interface to which access is applied to a write address decoder; using the write address decoder to decode the address information to obtain a decoding result; determining whether the decoding result matches the address range table of the write address decoder; if the decoding result cannot match the address range table of the write address decoder, determining that the decoding is an error; if the decoding result matches the address range table of the write address decoder, determining that the decoding is successful.

[0052] In an arbitration example, arbitrating the write address channel of the slave device interface includes: controlling the master device interface to send an arbitration selection signal to the write address channel arbitrator of the slave device interface, the write address channel arbitrator responds to the arbitration selection signal, arbitrates the write address channel according to the configured arbitration mechanism, and returns the address channel arbitration result to the master device interface.

[0053] In an arbitration example, arbitrating a write data channel of a slave device interface includes: controlling the master device interface to send an arbitration selection signal to the write data channel arbitrator of the slave device interface, the write data channel arbitrator responds to the arbitration selection signal, arbitrates the write data channel according to the configured arbitration mechanism, and returns the data channel arbitration result to the master device interface.

[0054] In one implementation scenario, after arbitrating the write address channel of the slave device interface, it also includes: if the write address channel arbitration fails, determining whether there are other write address channel application strobe arbitration requests; if there are other write address channel application strobe arbitration requests and the current write address channel application strobe arbitration request fails, reading the write address channel connection request control information related to the master device interface and the first other slave device interface from the cache module, and caching the write address channel connection request control information related to the master device interface and the current slave device interface to the cache module, controlling the master device interface to initiate a write address channel connection request to the first other slave device interface, and arbitrating the write address channel of the first other slave device interface; if there are no other write address channel application strobe arbitration requests and the current write address channel application strobe arbitration request fails, controlling the master device interface to continue initiating a write address channel arbitration strobe request to the current slave device interface.

[0055] In one implementation scenario, after obtaining the write address information of the slave device, it also includes: determining whether there is an application for arbitration of other write address channels; if there is an application for arbitration of other write address channels and the application for arbitration of the current write address channel has passed and the write address transmission is completed, reading the write address channel connection request control information related to the master device interface and the second other slave device interface from the cache module, controlling the master device interface to initiate a write address channel connection request to the second other slave device interface, and arbitrating the write address channel of the second other slave device interface; if there is no application for arbitration of other write address channels and the application for arbitration of the current write address channel has passed and the write address transmission is completed, ending the write address transmission process.

[0056] In one implementation scenario, after arbitrating the write data channel of the slave device interface, it also includes: if the write data channel arbitration fails, determining whether there are other write data channel arbitration requests; if there are other write data channel arbitration requests and the current write data channel arbitration request fails, reading the write data channel connection request control information related to the master device interface and the third other slave device interface from the cache module, and caching the write data channel connection request control information related to the master device interface and the current slave device interface to the cache module, the master device interface initiates a write data channel connection request to the third other slave device interface, and arbitrates the write data channel of the third other slave device interface; if there are no other write data channel arbitration requests and the current write data channel arbitration request fails, controlling the master device interface to continue to initiate a write data channel arbitration request to the current slave device interface, and arbitrates the write data channel of the current slave device interface.

[0057] Optionally, after controlling the slave device to initiate write data transmission to the master device according to the address information, it also includes: determining whether there are requests for application for selection arbitration from other write data channels; if there are requests for application for selection arbitration from other write data channels and the current write data channel application for selection arbitration has passed and the write data transmission has been completed, then reading the write data channel connection request control information related to the master device interface and the third other slave device interface from the cache module, controlling the master device interface to initiate a write data channel connection request to the third other slave device interface, and arbitrating the write data channel of the third other slave device interface; if there are no requests for application for selection arbitration from other write data channels and the current write data channel application for selection arbitration has passed and the write data transmission has been completed, the write data transmission process is ended.

[0058] In one implementation scenario, after obtaining the write address information of the slave device, it also includes: determining whether there is an application for arbitration of other write address channels; if there is an application for arbitration of other write address channels and the application for arbitration of the current write address channel has passed and the write address transmission is completed, reading the write address channel connection request control information related to the master device interface and the second other slave device interface from the cache module, controlling the master device interface to initiate a write address channel connection request to the second other slave device interface, and arbitrating the write address channel of the second other slave device interface; if there is no application for arbitration of other write address channels and the application for arbitration of the current write address channel has passed and the write address transmission is completed, ending the write address transmission process.

[0059] In one implementation of this embodiment, each master device interface is configured with the following independent channels: a write address channel, a write data channel, a write reply channel, a read address channel, and a read data channel; each slave device interface is configured with the following independent channels: a write address channel, a write data channel, a write reply channel, a read address channel, and a read data channel; wherein the channel restrictions of the master device interface are interconnected with the same type of channels of the slave device interface.

[0060] For example, the write address channel of the master device interface can only be interconnected with the write address channel of the slave device interface, and cannot be interconnected with the write data channel, write reply channel, read address channel, and read data channel of the slave device interface.

[0061] In this embodiment, the configuration module includes: an interface configuration submodule, which is used to freely configure the connectivity between each master device interface and the slave device interface, and freely configure the restricted access between each master device interface and the slave device interface; a channel configuration submodule, which is used to freely configure the connectivity between each type of channel of each master device interface and the slave device interface, and freely configure the restricted access between each type of channel of each master device interface and the slave device interface; an arbitration configuration submodule, which is used to configure the arbitration mechanism of the arbitrator of each slave device interface, and configure the arbitration priority for different signals.

[0062] In the system of this embodiment, the configuration module includes three parts: interface configuration, channel configuration, and arbitration mechanism configuration. Interface configuration: used to freely configure the connectivity between all master device interfaces and slave device interfaces, restrict certain master device interfaces from accessing certain slave device interfaces, and cooperate with the decoding module to realize the free change from the fully connected matrix to the sparsely connected matrix, so as to achieve the effect of physical isolation between certain master and slave devices. Channel configuration: used to freely configure the connectivity between a certain type of channels of all master device interfaces and slave device interfaces, restrict the connectivity between certain master device interface channels and slave device interface channels, and cooperate with the decoding module to realize the read-only or write-only operation function between certain master and slave devices, so as to achieve the security access needs between certain master and slave devices. Arbitration configuration: used to configure the arbitration mechanism of the arbitrator of all slave devices, and configure the arbitration priority mechanism according to the different situations of each slave device. The arbitrators of each channel of the slave device are independent, which can realize that the master device channel priorities corresponding to the read and write channels of the same slave device are different, so as to achieve the purpose of precise control.

[0063] In one example, the interface configuration submodule is configured with an interface register group, which includes n registers, each register corresponds to a slave device, each register has m bits, each bit number corresponds to a master device, and the configurable value of each bit number includes: a first flag bit and a second flag bit, wherein the first flag bit is used to represent free access with the corresponding master device, and the second flag bit is used to represent access restrictions with the corresponding master device.

[0064] The interface configuration submodule determines which slave devices the master device can access, and cooperates with the decoding module to achieve physical isolation between the master device and some slave devices; the interface configuration is achieved by configuring the interface register group IREG, which contains n registers ireg1, ireg2…iregn, corresponding to slave device 1, slave device 2…slave device n respectively; each ireg register has m bits {i1, i2,…im}, corresponding to master device 1, master device 2…master device m respectively; the accessibility between the master device and the slave device is set by configuring the value of the register.

[0065] For example, the first bit i1 of the interface register ireg1 is configured to be 1 and the second bit i2 is configured to be 0, which means that the master device 1 can access the slave device 1, but the master device 2 cannot access the slave device 1. The configuration of other interface registers is similar.

[0066] In an example, the channel configuration submodule is configured with a channel register group, which includes n registers, each register corresponding to a slave device; each register has 5 channel registers, corresponding to a read address channel, a read data channel, a write address channel, a write data channel, and a write reply channel, respectively, each channel register has m bits, each bit number corresponds to a master device, and the configurable value of each bit number includes: a third flag bit and a fourth flag bit, wherein the third flag bit is used to represent free access with the corresponding master device, and the fourth flag bit is used to represent access restrictions with the corresponding master device.

[0067] The channel configuration submodule determines whether the read and write channels of the master device and the slave devices can be interconnected based on the interface configuration, so as to realize the master device's read-only access, write-only access or both read and write access to certain slave devices. The read channel includes the read address channel AR and the read data channel R, and the write channel includes the write address channel AW, the write data channel W and the write reply channel B. The channel configuration is realized by configuring the channel register group CREG. The channel register group CREG contains n register groups creg1, creg2...cregn, corresponding to slave device 1, slave device 2...slave device n respectively. Each creg register group has 5 channel registers ar, r, aw, w, b, corresponding to the read address channel, read data channel, write address channel, write data channel and write reply channel respectively. Each channel register has m bits {c1, c2,...cm}, corresponding to master device 1, master device 2...master device m respectively. The readability and writability between the master device and the slave device are set by configuring the value of the channel register.

[0068] For example, to set the master device 1 to be only readable but not writable to the slave device 1 and the master device 2 to be only writable but not readable to the slave device 1, the following configuration is made: configure the first bit c1 of the channel register ceg1.ar to be 1 and the second bit c2 to be 0, the first bit c1 of the channel register ceg1.r to be 1 and the second bit c2 to be 0, the first bit c1 of the channel register ceg1.aw to be 0 and the second bit c2 to be 1, the first bit c1 of the channel register ceg1.w to be 0 and the second bit c2 to be 1, the first bit c1 of the channel register ceg1.b to be 0 and the second bit c2 to be 1, and the channel register configurations for other read and write restriction scenarios between the master and slave devices can be deduced accordingly.

[0069] Figure 4 It is a schematic diagram of a configuration module in an embodiment of the present invention, including an interface configuration register group IREG (ireg1-iregn), a channel configuration register group CREG (creg1-cregn), an arbitration configuration register group AREG (areg1-aregn), and an arbitration priority configuration register PREG (preg1-pregn).

[0070] In an example, the arbitration configuration submodule is configured with an arbitration register group, which includes n register groups, each register group corresponds to a slave device; each register group has 5 channel arbitration registers, corresponding to a read address channel, a read data channel, a write address channel, a write data channel, and a write reply channel; each channel arbitration register has k bits, and each bit number corresponds to an arbitration mechanism.

[0071] In one example, k=4, and the four arbitration mechanisms are: fixed priority, round-robin priority, combined priority, and adaptive priority, where the adaptive priority is used to indicate that the priority order of the corresponding master device is adjusted in real time according to the frequency of the master device applying for arbitration within a fixed time period.

[0072] In the above example, the arbitration mechanism of the arbitrator includes four modes, namely, fixed priority, cyclic priority, combined priority, and adaptive priority. The fixed priority is that all master devices are sorted in a fixed order, and the master device in the front order has a high priority and is given priority when applying for arbitration; the cyclic priority is that all master devices are in a cyclic order, and the master device that applies for selection and passes arbitration in the current round has the lowest priority in the next round of arbitration, and the priority order of the master devices in the initial state is arranged according to the initial set master device order; the group priority is that all master devices are divided into multiple priority groups, each group is sorted in a fixed order, and arbitration is performed between groups in a fixed priority manner. The master devices in each group have the same priority, and arbitration is performed within the group in a cyclic priority manner; the adaptive priority is to adjust the priority order of the master devices in real time according to the frequency of master devices applying for arbitration within a fixed time period, and the master device with a high frequency has a high priority. The priority order is adjusted once after each time period, and the priority order of the master devices in the initial state is arranged according to the initial set master device order.

[0073] In an example, the arbitration configuration submodule is configured with a channel priority register group, each register group corresponds to a slave device; each register group has 5 channel priority registers, corresponding to a read address channel, a read data channel, a write address channel, a write data channel, and a write reply channel, respectively; each channel priority register has m bits for storing a sequence of length m, each element of the sequence corresponds to a master device, and the order of the m elements in the sequence corresponds to the arbitration priority order of the m master devices.

[0074] The arbitration configuration submodule configures the arbitration mechanism of the arbitrators of all slave devices, and configures the arbitration priority mechanism according to the different situations of each slave device corresponding to the master device. The configuration is divided into two parts. The first part is to configure the arbitration mechanism of each arbitrator, that is, to select one of the four arbitration mechanisms such as fixed priority, round-robin priority, combined priority, and adaptive priority; the second part is to configure the priority order of each arbitrator corresponding to the master device, that is, to determine the priority of all master devices that have the authority to access the slave device. The arbitrators of each channel of the slave device are independent, which can realize different master device channel priorities corresponding to the read and write channels of the same slave device, so as to achieve the purpose of precise control. The configuration of the channel arbitrator arbitration mechanism is achieved by configuring the arbitration register group AREG. The arbitration register group AREG contains n register groups areg1, areg2...aregn, corresponding to slave device 1, slave device 2...slave device n respectively; each areg register group has 5 channel arbitration registers ar, r, aw, w, b, corresponding to the read address channel, read data channel, write address channel, write data channel, write reply channel respectively; each channel arbitration register has 4 bits {a1, a2,...a4}, corresponding to four arbitration mechanisms such as fixed priority, round-robin priority, combined priority, and adaptive priority respectively; the arbitration mechanism of the channel arbitrator is set by configuring the value of the channel arbitration register. For example, if the arbitration mechanism of the read address channel arbitrator of slave device 1 is set to round-robin priority, the third bit a3 of the areg1.ar register is configured to be 1, and the remaining bits are all 0. The arbitration mechanism configuration of other slave device channel arbitrators can be deduced in the same way. The master device priority order corresponding to the channel arbiter is realized by configuring the channel priority register group PREG. The channel priority register group PREG contains n register groups preg1, preg2...pregn, corresponding to slave device 1, slave device 2...slave device n respectively; each preg register group has 5 channel priority registers ar, r, aw, w, b, corresponding to the read address channel, read data channel, write address channel, write data channel, write reply channel respectively; each channel priority register has m bits, and p1, p2,...pm correspond to master device 1, master device 2...master device m respectively; by configuring p1, p2 , …pm in the priority register to set the arbitration priority order of master device access. For example, preg1.ar={p2,p1,…pm} means that the arbitration priority order of master device access corresponding to the write address channel of slave device 1 is p2,p1,…pm, that is, master device 2 has the highest priority, master device 1 has the second highest priority, …master device m has the lowest priority; the configuration of the arbitration priority order of master device access of other slave device channels can be deduced in the same way. The arbitration priority order is used to configure the order of master devices with fixed priority, as well as the initial order of master devices with cyclic priority, combined priority and adaptive priority mechanism.

[0075] The arbitration module is equipped with an independent arbitrator for each channel of each slave device interface, which can realize independent arbitration of each channel connection request. The arbitrator of a slave device channel only allows one master device channel of the same type to communicate with the slave device channel at a certain time. Each arbitrator determines the master device channel with the right to participate in arbitration based on the configuration module interface configuration and channel configuration results. Each arbitrator determines the arbitration priority order of the master device channel with the right to participate in arbitration based on the results of the configuration module arbitration configuration. When the arbitrator of the slave device channel receives the application selection signal from the master device channel, it performs arbitration selection according to the priority order.

[0076] The arbitrator performs arbitration based on the arbitration mechanism pre-configured by the configuration module, including four modes: fixed priority, round-robin priority, combined priority, and adaptive priority.

[0077] In one implementation of this embodiment, the arbitration module configures the following channel arbiters for each slave device interface: a write address channel arbiter, a read address channel arbiter, a write data channel arbiter, a read data channel arbiter, and a write reply channel arbiter.

[0078] Figure 5 FIG. 1 is a schematic diagram of the structure of the arbitration module in an embodiment of the present invention. Figure 5 As shown, as an embodiment of the present invention, an arbitration module structure of an AXI bus interconnection matrix is ​​provided, in which the arbitration module is equipped with an independent arbitrator for each channel of each slave device interface, that is, each slave device has a write address channel AW arbitrator, a read address channel AR arbitrator, a write data channel W arbitrator, a read data channel R arbitrator, and a write reply channel B arbitrator, which can realize independent arbitration of each channel connection request.

[0079] Figure 6 This is an arbitration flow chart of the arbitration module in an embodiment of the present invention, which provides an arbitration method flow of an AXI bus interconnection matrix. The arbitrator of a slave device channel only allows one master device channel to communicate with the slave device channel at a certain time. The arbitration process steps of the channel arbitrator are as follows:

[0080] S61, when multiple master devices simultaneously initiate use requests to a slave device channel, the slave device channel arbitrator starts arbitration;

[0081] S62, the channel arbitrator determines the master device channel with the right to participate in arbitration according to the configuration module interface configuration and the channel configuration result;

[0082] S63, the channel arbitrator determines the arbitration mechanism and the arbitration priority order of the master device channels having the right to participate in the arbitration according to the result of the arbitration configuration of the configuration module;

[0083] S64: The channel arbitrator performs arbitration according to the arbitration mechanism and arbitration priority order, determines the master device with priority, and the arbitration ends.

[0084] The cache module of this embodiment is used for channel-level transmission task cache of the read / write address channel and the read / write data channel of the master device during the read / write operation.

[0085] In the system of this embodiment, the cache information of the transmission task includes the following fields: cache information category, master device interface number, slave device interface number, cache task code, wherein the cache information category is used to indicate the channel type, and the cache task code is used to indicate the task identifier of the transmission task initiated by the master device to the slave device.

[0086] The transmission task cache information includes the cache information category (read address, write address, read data, write data), the master device interface number (which master device initiated the read and write operation), the slave device interface number (the slave device object of the read and write operation), and the cache task code (used to distinguish multiple task caches initiated by a master device to the same slave device).

[0087] Optionally, the channel-level transmission tasks include: a read address channel transmission task, a read data channel transmission task, a write address channel transmission task, and a write data channel transmission task.

[0088] When the master device performs advance transmission, out-of-order transmission, or the arbitration application fails during the read and write operations, the transmission task cache for the read and write operations is required. During the read operation, there is a read address channel transmission task cache and a read data channel transmission task cache; during the write operation, there is a write address channel transmission task cache and a write data channel transmission task cache; since the write reply channel is for the reply of the entire burst transmission transaction, the channel occupancy time is short and there is no need for transmission task cache. The transmission task cache information includes the cache information category (read address, write address, read data, write data), the master device interface number (which master device initiated the read and write operation), the slave device interface number (the slave device object of the read and write operation), and the cache task code (used to distinguish multiple task caches initiated by a master device to the same slave device).

[0089] The cache module of this embodiment only caches the transmission task, rather than the data required to be transmitted by the transmission task, so the amount of cached information is relatively small, and the cache module occupies little storage resources.

[0090] Compared with the entire burst transfer transaction cache or transfer data cache of the prior art, the channel-level task cache method proposed in this embodiment occupies less storage resources of the interconnection matrix, is more efficient, and is accurate to each channel, giving full play to the advantages of independence between AXI bus channels.

[0091] Optionally, obtaining the write address information of the slave device includes: connecting the write address channel of the master device interface with the write address channel of the slave device interface; initiating write address information transmission from the master device to the slave device based on the write address channel; after the transmission is completed, closing the connection relationship between the write address channel of the master device interface and the write address channel of the slave device interface.

[0092] In one example, after controlling the slave device to initiate write data transmission to the master device according to the write address information, it also includes: controlling the write reply channel of the master device interface to initiate a connection request to the write reply channel of the slave device interface; controlling the master device interface to send an arbitration selection signal to the write reply channel arbitrator of the slave device interface to arbitrate the write reply channel; if the arbitration is passed, connecting the write reply channel of the master device interface with the write reply channel of the slave device interface, and controlling the slave device to initiate a write reply transmission to the master device according to the write data completion information; after the write reply transmission is completed, closing the connection relationship between the write reply channel of the master device interface and the write reply channel of the slave device interface.

[0093] Figure 7 1 is a schematic diagram of the transmission flow of the write operation of the AXI bus interconnection matrix in an embodiment of the present invention. As an embodiment of the present invention, a write operation working method flow of the AXI bus interconnection matrix is ​​provided. The working method steps of the master device initiating the write operation are as follows:

[0094] S01) Master device M j The master device interface MI of the bus interconnection matrix j And from the device interface SI k To slave device S k Initiate a write operation request (j, k are positive integers, j≤m, k≤n, m, n are the number of master devices and slave devices respectively, the same below), and execute step S02.

[0095] S02) Main device interface MI j Write address channel AW_MI j To the slave device interface SI k Write address channel AW_SI k Initiate a connection request and set the address channel connection request flag AW j [k-1] = 1 (AW j Register represents the master device interface MI j The write address channel applies for arbitration request status, AW j The bit width is the same as the number of slave device interfaces. If the k-1th position is 1, it means that the master device interface MI j Need to apply for connection arbitration request to the kth slave device interface write address channel), the master device interface MI j Write address channel AW_MI jSend the address range information to the write address decoder DECR_W_MI j Decode and execute step S03.

[0096] S03) The write address decoder starts decoding and determines the decoder decoding result. If the decoder address range table cannot match, the write address decoder sends a signal to the master device interface MI. j Returns decoding error signal, master device interface MI j To the master device M j Returns a transmission error signal and sets the flag AW j [k-1] = 0, the transmission is completed, and the process returns to step S01 to perform the next transmission cycle; if the write address decoder successfully decodes the master device interface MI j The slave device interface SI that is requested to be accessed k , then execute step S04.

[0097] S04) Main device interface MI j To the slave device interface SI k Write address channel arbiter arb_AW_SI k Send an arbitration selection signal, the arbitrator arbitrates according to the configured arbitration mechanism and sends a signal to the master device interface MI j Return arbitration result RE_arb_AW_SI k If RE_arb_AW_SI k =1 means passing arbitration, then the write data channel connection request flag W is set j [k-1] = 1(W j Register represents the master device interface MI j The write data channel applies for arbitration request status, W j The bit width is the same as the number of slave device interfaces. If the k-1th position is 1, it means that the master device interface MI j It is necessary to apply for a connection arbitration request to the kth slave device interface write data channel, and set the write address channel connection request flag AW j [k-1] = 0, and execute step S05 and step S06 simultaneously; if RE_arb_AW_SI k =0, that is, the arbitration is not passed, and step S07 is executed.

[0098] S05) Main device interface MI j Write data channel W_MI j To the slave device interface SI k Write data channel W_SI k Initiate a connection request, the main device interface MI j To the slave device interface SI k Write data channel arbiter arb_W_SIk Send arbitration selection signal from device interface SI k Write data channel arbiter arb_W_SI k Arbitrate according to the configured arbitration mechanism and send the MI to the master interface j Return arbitration result RE_arb_W_SI k If RE_arb_W_SI k =1 means passing arbitration, then write reply channel connection request flag B j [k-1] = 1(B j Register represents the master device interface MI j The write reply channel applies for arbitration request status, B j The bit width is the same as the number of slave device interfaces. If the k-1th position is 1, it means that the master device interface MI j It is necessary to apply for a connection arbitration request to the kth slave device interface write reply channel), and then execute steps S08 and S10 simultaneously; if RE_arb_W_SI k =0 and fails to pass arbitration, then execute step S09.

[0099] S06) According to the write address channel arbitration signal RE_arb_AW_SI k =1, the system will host the device interface MI j Write address channel AW_MI j Interface with slave device SI k Write address channel AW_SI k Connect, the master device M j Through the main device interface MI j And from the device interface SI k To the slave device S k Initiate the transmission of write address information; after the transmission is completed, the system closes the main device interface MI j Write address channel AW_MI j Interface with slave device SI k Write address channel AW_SI k The connectivity relationship between them sets the write address channel arbitration status RE_arb_AW_SI k =0, the write address transmission process ends and step S07 is executed.

[0100] S07) Determine the write address channel arbitration request status register flag AW j [k-1] and AW j The value of [y-1] (y is any positive integer except k, and x≤n):

[0101] ①If AW j [k-1] = 1 and AWj [x-1]=1, then the master device interface MI j There is a slave device interface SI k And other slave device interface write address channel connection requirements, but at this time the slave device interface SI k The write address channel of the master device is temporarily unavailable. Priority is given to connecting to other slave device interfaces and reading the master device interface MI from the cache module. j Interface with slave device SI y The relevant write address channel connection request control information and the master device interface MI j Interface with slave device SI k The related write address channel connection request control information is cached to the cache module, the main device interface MI j Start to send data to slave device interface SI y A write address channel connection request is initiated, the parameter k in step S04 (and subsequent steps related to step S04, such as steps S05 and S06, etc.) is replaced with y, and then step S04 is executed.

[0102] ②If AW j [k-1] = 1 and AW j [x-1]=0, then the master device interface MI j Only from device interface SI k Write address channel connection requirements, master device interface MI j Continue to the slave device interface SI k Initiate a write address channel arbitration strobe request, that is, do not change the parameters and execute step S04.

[0103] ③If AW j [k-1] = 0 and AW j [y-1]=1, then the master device interface MI j Except for the slave device interface SI k Other slave device interface write address channel connection requirements, read the master device interface MI from the cache module j Interface with slave device SI y Related write address channel connection request control information, master device interface MI j Start to send data to slave device interface SI y A write address channel connection request is initiated, that is, the parameter k in step S04 (and subsequent steps related to step S04, such as steps S05 and S06, etc.) is replaced with y, and then step S04 is executed.

[0104] ④If AW j [k-1] = 0 and AW j [y-1] = 0, master device interface MI jIf there is no connection requirement with all slave device interface write address channels, the transmission is completed and the process returns to step S01 to execute the next transmission cycle.

[0105] S08) According to the write data channel arbitration signal RE_arb_W_SI k =1, the system will host the device interface MI j Write data channel W_MI j Interface with slave device SI k Write data channel W_SI k According to the write address control information received in step S06, from device S k Through the slave device interface SI k And the main device interface MI j To the master device M j Initiate write data transmission; after the transmission is completed, the system closes the main device interface MI j Write data channel W_MI j Interface with slave device SI k Write data channel W_SI k The connection relationship between them sets the arbitration signal RE_arb_W_SI k =0, set flag bit W j [k-1]=0, the write data transmission process ends; execute step S09.

[0106] S09) Determine the write data channel arbitration request status register flag bit W j [k-1] and W j The value of [x-1] (x is any positive integer except k, and x≤n):

[0107] ①If W j [k-1] = 1 and W j [x-1]=1, then the master device interface MI j There is a slave device interface SI k And other slave device interface write data channel connection requirements, but at this time the slave device interface SI k The write data channel of the master device is temporarily unavailable. Priority is given to connecting to other slave device interfaces and reading the master device interface MI from the cache module. j Interface with slave device SI x The relevant write data channel connection request control information and the master device interface MI j Interface with slave device SI k The relevant write data channel connection request control information is cached to the cache module, the master device interface MI j Start to send data to slave device interface SI xA write data channel connection request is initiated, the parameter k in step S05 (and subsequent steps related to step S05, such as step S08, etc.) is replaced with x, and then step S05 is executed.

[0108] ②If W j [k-1] = 1 and W j [x-1]=0, then the master device interface MI j Only from device interface SI k Write data channel connection requirements, master device interface MI j Continue to the slave device interface SI k A write data channel arbitration strobe request is initiated, that is, the parameters are not changed and step S05 is executed.

[0109] ③If W j [k-1] = 0 and W j [x-1]=1, then the master device interface MI j Except for the slave device interface SI k Other slave device interfaces write data channel connection requirements, read the master device interface MI from the cache module j Interface with slave device SI x Related write data channel connection request control information, master device interface MI j Start to send data to slave device interface SI x A write data channel connection request is initiated, that is, the parameter k in step S05 (and subsequent steps related to step S05, such as step S08, etc.) is replaced with x, and then step S05 is executed.

[0110] ④If W j [k-1] = 0 and W j [x-1] = 0, master device interface MI j If there is no connection requirement with all slave device interface write data channels, the transmission is completed, and the process returns to step S01 to execute the next transmission cycle.

[0111] S10) Main device interface MI j Write reply channel B_MI j To the slave device interface SI k Write reply channel B_SI k Initiate a connection request, the main device interface MI j To the slave device interface SI k Write reply channel arbiter arb_B_SI k Send arbitration selection signal from device interface SI k Write reply channel arbiter arb_B_SI k Arbitrate according to the configured arbitration mechanism and send the MI to the master interfacej Return arbitration result RE_arb_B_SI k If RE_arb_B_SI k =1, that is, arbitration is passed, then step S11 is executed; if RE_arb_B_SI k =0 and fails to pass arbitration, then step S10 is executed again.

[0112] S11) According to the write reply channel arbitration signal RE_arb_B_SI k =1, the system will host the device interface MI j Write reply channel B_MI j Interface with slave device SI k Write reply channel B_SI k According to the write data completion information received in step S08, the slave device S k Through the slave device interface SI k And the main device interface MI j To the master device M j Initiate a write reply transmission; after the transmission is completed, the system closes the master device interface MI j Write reply channel B_MI j Interface with slave device SI k Write reply channel B_SI k The connection relationship between them sets the arbitration signal RE_arb_B_SI k =0, set flag bit B j [k-1]=0, the write reply transmission process ends; return to step S01 to execute the next round of transmission cycle.

[0113] The channel-level task cache method proposed in this embodiment occupies less storage resources of the interconnection matrix, is more efficient, and is accurate to each channel, compared with the entire burst transmission transaction cache or transmission data cache of the prior art, giving full play to the advantages of independence between AXI bus channels. This embodiment proposes a specific implementation method for write operations, in which the address and data transmission of write operations are independently arbitrated and transmitted independently, and channel-level task cache can be performed, which effectively expands the scope of applicable scenarios of the AXI bus interconnection matrix, improves the transmission efficiency of write operations, and thus improves chip performance.

[0114] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, a magnetic disk, or an optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present invention.

[0115] Example 2

[0116] In this embodiment, a writing device based on an AXI bus interconnection matrix is ​​also provided, which is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0117] Figure 8 is a structural block diagram of a writing device based on an AXI bus interconnection matrix according to an embodiment of the present invention, such as Figure 8 As shown, the device comprises:

[0118] A first control module 80 is used to respond to a write operation request initiated by a master device to a slave device, and control a master device interface write address channel to initiate a connection request to a slave device interface write address channel, wherein the system on chip SOC includes a plurality of master devices and a plurality of slave devices, the master device is connected to the AXI bus via a master device interface, and the slave device is connected to the AXI bus via a slave device interface;

[0119] A decoding module 82, used for decoding the slave device interface that the master device interface applies to access;

[0120] An arbitration module 84, configured to arbitrate the write address channel of the slave device interface if the decoding is successful;

[0121] The processing module 86 is used to control the write data channel of the master device interface to initiate a connection request to the write data channel of the slave device interface if the write address channel arbitration is passed, arbitrate the write data channel of the slave device interface, and obtain the write address information of the slave device;

[0122] The write operation module 88 is used to connect the write data channel of the master device interface with the write data channel of the slave device interface if the write data channel arbitration is passed, and control the slave device to initiate write data transmission to the master device according to the write address information.

[0123] Optionally, the decoding module includes: a control unit, used to control the write address channel of the master device interface to send the address information of the slave device interface applying for access to the write address decoder; a decoding unit, used to use the write address decoder to decode the address information to obtain a decoding result; a judgment unit, used to judge whether the decoding result matches the address range table of the write address decoder; a determination unit, used to determine that a decoding error is present if the decoding result does not match the address range table of the write address decoder; and determine that the decoding is successful if the decoding result matches the address range table of the write address decoder.

[0124] Optionally, the arbitration module includes: an arbitration unit, used to control the master device interface to send an arbitration request selection signal to the write address channel arbitrator of the slave device interface, the write address channel arbitrator responds to the arbitration request selection signal, arbitrates the write address channel according to the configured arbitration mechanism, and returns the address channel arbitration result to the master device interface.

[0125] Optionally, the processing module includes: an arbitration unit, used to control the master device interface to send an arbitration request selection signal to the write data channel arbitrator of the slave device interface, the write data channel arbitrator responds to the arbitration request selection signal, arbitrates the write data channel according to the configured arbitration mechanism, and returns the data channel arbitration result to the master device interface.

[0126] Optionally, the device also includes: a first judgment module, used to judge whether there are other write address channel application selection arbitration requests after the arbitration module arbitrates the write address channel of the slave device interface, if the write address channel arbitration fails; a second control module, used to read the write address channel connection request control information related to the master device interface and the first other slave device interface from the cache module if there are other write address channel application selection arbitration requests and the current write address channel application selection arbitration request fails, and cache the write address channel connection request control information related to the master device interface and the current slave device interface to the cache module, control the master device interface to initiate a write address channel connection request to the first other slave device interface, and arbitrate the write address channel of the first other slave device interface; if there are no other write address channel application selection arbitration requests and the current write address channel application selection arbitration request fails, control the master device interface to continue to initiate a write address channel arbitration selection request to the current slave device interface.

[0127] Optionally, the processing module includes: a connecting unit, used to connect the write address channel of the master device interface with the write address channel of the slave device interface; an initiating unit, used to initiate the transmission of write address information from the master device to the slave device based on the write address channel; and a closing unit, used to close the connection relationship between the write address channel of the master device interface and the write address channel of the slave device interface after the transmission is completed.

[0128] Optionally, the device also includes: a second judgment module, used to judge whether there are requests for application of arbitration for other write address channels after the processing module obtains the write address information of the slave device; a third control module, used to read the write address channel connection request control information related to the master device interface and the second other slave device interface from the cache module if there are requests for application of arbitration for other write address channels and the current write address channel application of arbitration for arbitration has passed and the write address transmission has been completed, control the master device interface to initiate a write address channel connection request to the second other slave device interface, and arbitrate the write address channel of the second other slave device interface; if there are requests for application of arbitration for other write address channels and the current write address channel application of arbitration for arbitration has passed and the write address transmission has been completed, end the write address transmission process.

[0129] Optionally, the device also includes: a third judgment module, which is used to judge whether there are other write data channel arbitration requests after the processing module arbitrates the write data channel of the slave device interface, if the write data channel arbitration fails; a fourth control module, which is used to read the write data channel connection request control information related to the master device interface and the third other slave device interface from the cache module if there are other write data channel arbitration requests and the current write data channel arbitration request fails, and cache the write data channel connection request control information related to the master device interface and the current slave device interface to the cache module, the master device interface initiates a write data channel connection request to the third other slave device interface, and arbitrates the write data channel of the third other slave device interface; if there are no other write data channel arbitration requests and the current write data channel arbitration request fails, control the master device interface to continue to initiate a write data channel arbitration request to the current slave device interface, and arbitrate the write data channel of the current slave device interface.

[0130] Optionally, the device also includes: a fourth judgment module, used to judge whether there is an application for selection arbitration request for other write data channels after the write operation module controls the slave device to initiate write data transmission to the master device according to the address information; a fifth control module, used to read the write data channel connection request control information related to the master device interface and the third other slave device interface from the cache module if there is an application for selection arbitration request for other write data channels and the current write data channel application for selection arbitration has passed and the write data transmission has been completed, control the master device interface to initiate a write data channel connection request to the third other slave device interface, and arbitrate the write data channel of the third other slave device interface; if there is no application for selection arbitration request for other write data channels and the current write data channel application for selection arbitration has passed and the write data transmission has been completed, end the write data transmission process.

[0131] Optionally, the device also includes: a sixth control module, which is used to control the write reply channel of the master device interface to initiate a connection request to the write reply channel of the slave device interface after the write operation module controls the slave device to initiate write data transmission to the master device according to the write address information; a seventh control module, which is used to control the master device interface to send an arbitration selection signal to the write reply channel arbitrator of the slave device interface to arbitrate the write reply channel; a write reply module, which is used to connect the write reply channel of the master device interface with the write reply channel of the slave device interface if the arbitration is passed, and control the slave device to initiate a write reply transmission to the master device according to the write data completion information; and a closing module, which is used to close the connection relationship between the write reply channel of the master device interface and the write reply channel of the slave device interface after the write reply transmission is completed.

[0132] It should be noted that the above modules can be implemented by software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0133] Example 3

[0134] An embodiment of the present invention further provides a storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0135] Optionally, in this embodiment, the storage medium may be configured to store a computer program for performing the following steps:

[0136] S1, responding to a write operation request initiated by a master device to a slave device, controlling a master device interface write address channel to initiate a connection request to a slave device interface write address channel, wherein the system on chip SOC includes multiple master devices and multiple slave devices, the master device is connected to the AXI bus through the master device interface, and the slave device is connected to the AXI bus through the slave device interface;

[0137] S2, decoding the slave device interface that the master device interface requests to access;

[0138] S3, if the decoding is successful, arbitrating the write address channel of the slave device interface;

[0139] S4, if the write address channel arbitration is passed, controlling the write data channel of the master device interface to initiate a connection request to the write data channel of the slave device interface, arbitrating the write data channel of the slave device interface, and obtaining the write address information of the slave device;

[0140] S5, if the write data channel arbitration is passed, connecting the write data channel of the master device interface with the write data channel of the slave device interface, and controlling the slave device to initiate write data transmission to the master device according to the write address information.

[0141] Optionally, in this embodiment, the above-mentioned storage medium may include but is not limited to: a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and other media that can store computer programs.

[0142] An embodiment of the present invention further provides an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0143] Optionally, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0144] Optionally, in this embodiment, the processor may be configured to perform the following steps through a computer program:

[0145] S1, responding to a write operation request initiated by a master device to a slave device, controlling a master device interface write address channel to initiate a connection request to a slave device interface write address channel, wherein the system on chip SOC includes multiple master devices and multiple slave devices, the master device is connected to the AXI bus through the master device interface, and the slave device is connected to the AXI bus through the slave device interface;

[0146] S2, decoding the slave device interface that the master device interface requests to access;

[0147] S3, if the decoding is successful, arbitrating the write address channel of the slave device interface;

[0148] S4, if the write address channel arbitration is passed, controlling the write data channel of the master device interface to initiate a connection request to the write data channel of the slave device interface, arbitrating the write data channel of the slave device interface, and obtaining the write address information of the slave device;

[0149] S5, if the write data channel arbitration is passed, connecting the write data channel of the master device interface with the write data channel of the slave device interface, and controlling the slave device to initiate write data transmission to the master device according to the write address information.

[0150] Optionally, the specific examples in this embodiment may refer to the examples described in the above embodiments and optional implementation modes, and this embodiment will not be described in detail here.

[0151] The above is only a preferred implementation of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A writing method based on an AXI bus interconnection matrix, characterized in that: include: In response to a write operation request initiated by a master device to a slave device, control a master device interface write address channel to initiate a connection request to a slave device interface write address channel, wherein the system on chip SOC includes multiple master devices and multiple slave devices, the master device is connected to the AXI bus through the master device interface, and the slave device is connected to the AXI bus through the slave device interface; Decode the slave device interface that the master device interface requests to access; If the decoding is successful, arbitrating the write address channel of the slave device interface; If the write address channel arbitration is passed, the write data channel of the master device interface is controlled to initiate a connection request to the write data channel of the slave device interface, arbitrate the write data channel of the slave device interface, and obtain the write address information of the slave device; If the write data channel arbitration is passed, the write data channel of the master device interface is connected to the write data channel of the slave device interface, and the slave device is controlled to initiate write data transmission to the master device according to the write address information.

2. The method according to claim 1, characterized in that: Decoding the slave device interface that the master device interface requests to access includes: Control the master device interface write address channel to send the address information of the slave device interface applying for access to the write address decoder; Decoding the address information using the write address decoder to obtain a decoding result; Determining whether the decoding result matches the address range table of the write address decoder; If the decoding result cannot match the address range table of the write address decoder, it is determined that the decoding is wrong; if the decoding result matches the address range table of the write address decoder, it is determined that the decoding is successful.

3. The method according to claim 1, characterized in that Arbitrating the write address channel of the slave device interface includes: The master device interface is controlled to send an arbitration selection signal to the write address channel arbitrator of the slave device interface. The write address channel arbitrator responds to the arbitration selection signal, arbitrates the write address channel according to the configured arbitration mechanism, and returns the address channel arbitration result to the master device interface.

4. The method according to claim 1, characterized in that: Arbitrating the write data channel of the slave device interface includes: The master device interface is controlled to send an arbitration selection signal to the write data channel arbitrator of the slave device interface, and the write data channel arbitrator responds to the arbitration selection signal, arbitrates the write data channel according to the configured arbitration mechanism, and returns the data channel arbitration result to the master device interface.

5. The method according to claim 1, characterized in that After arbitrating the write address channel of the slave device interface, the method includes: If the write address channel arbitration fails, determine whether there are other write address channels that have applied for strobe arbitration requests; If there are other write address channel gating arbitration requests and the current write address channel gating arbitration request fails, read the write address channel connection request control information related to the master device interface and the first other slave device interface from the cache module, cache the write address channel connection request control information related to the master device interface and the current slave device interface to the cache module, control the master device interface to initiate a write address channel connection request to the first other slave device interface, and arbitrate the write address channel of the first other slave device interface; If there is no application strobe arbitration request for other write address channels and the current application strobe arbitration request for the write address channel fails, the master device interface is controlled to continue to initiate a write address channel arbitration strobe request to the current slave device interface.

6. The method according to claim 1, characterized in that Acquiring the write address information of the slave device includes: Connecting the write address channel of the master device interface to the write address channel of the slave device interface; Initiate transmission of write address information from the master device to the slave device based on the write address channel; After the transmission is completed, the connection relationship between the write address channel of the master device interface and the write address channel of the slave device interface is closed.

7. The method according to claim 1, characterized in that After acquiring the write address information of the slave device, the method further includes: Determine whether there is a request for strobe arbitration from other write address channels; If there are other write address channel strobe arbitration requests and the current write address channel strobe arbitration request has passed and the write address transmission is completed, read the write address channel connection request control information related to the master device interface and the second other slave device interface from the cache module, control the master device interface to initiate a write address channel connection request to the second other slave device interface, and arbitrate the write address channel of the second other slave device interface; If there is no request for strobe arbitration from other write address channels and the current write address channel has passed the strobe arbitration and completed the write address transmission, the write address transmission process ends.

8. The method according to claim 1, characterized in that After arbitrating the write data channel of the slave device interface, the method further includes: If the write data channel arbitration fails, determine whether there are other write data channels that have applied for strobe arbitration requests; If there are other write data channel strobe arbitration requests, and the current write data channel strobe arbitration request is not passed, then read the write data channel connection request control information related to the master device interface and the third other slave device interface from the cache module, and cache the write data channel connection request control information related to the master device interface and the current slave device interface to the cache module, the master device interface initiates a write data channel connection request to the third other slave device interface, and arbitrates the write data channel of the third other slave device interface; If there is no other write data channel applying for strobe arbitration request and the current write data channel applying for strobe arbitration request fails, the control master device interface continues to initiate a write data channel arbitration strobe request to the current slave device interface to arbitrate the write data channel of the current slave device interface.

9. The method according to claim 1, characterized in that: After controlling the slave device to initiate write data transmission to the master device according to the address information, the method further includes: Determine whether there is a request for strobe arbitration from other write data channels; If there are other write data channel strobe arbitration requests and the current write data channel strobe arbitration request has passed and the write data transmission has been completed, read the write data channel connection request control information related to the master device interface and the third other slave device interface from the cache module, control the master device interface to initiate a write data channel connection request to the third other slave device interface, and arbitrate the write data channel of the third other slave device interface; If there is no request for strobe arbitration from other write data channels and the current write data channel has passed the strobe arbitration and completed the write data transmission, the write data transmission process ends.

10. The method according to claim 1, characterized in that After controlling the slave device to initiate write data transmission to the master device according to the write address information, the method further includes: Control the write reply channel of the master device interface to initiate a connection request to the write reply channel of the slave device interface; Control the master device interface to send an arbitration selection signal to the write reply channel arbitrator of the slave device interface to arbitrate the write reply channel; If the arbitration is successful, the write reply channel of the master device interface is connected to the write reply channel of the slave device interface, and the slave device is controlled to initiate a write reply transmission to the master device according to the write data completion information; After the write reply transmission is completed, the connection relationship between the write reply channel of the master device interface and the write reply channel of the slave device interface is closed.

11. A writing device based on an AXI bus interconnection matrix, characterized in that: include: A first control module is used to respond to a write operation request initiated by a master device to a slave device, and control a master device interface write address channel to initiate a connection request to a slave device interface write address channel, wherein the system on chip SOC includes a plurality of master devices and a plurality of slave devices, the master device is connected to an AXI bus via a master device interface, and the slave device is connected to the AXI bus via a slave device interface; A decoding module, used for decoding the slave device interface that the master device interface applies to access; An arbitration module, used for arbitrating the write address channel of the slave device interface if the decoding is successful; A processing module, configured to control the write data channel of the master device interface to initiate a connection request to the write data channel of the slave device interface if the write address channel arbitration is passed, arbitrate the write data channel of the slave device interface, and obtain the write address information of the slave device; The write operation module is used to connect the write data channel of the master device interface with the write data channel of the slave device interface if the write data channel arbitration is passed, and control the slave device to initiate write data transmission to the master device according to the write address information.

12. A storage medium, characterized in that: The storage medium stores a computer program, wherein the computer program is configured to execute the method according to any one of claims 1 to 10 when executed.

13. An electronic device comprising a memory and a processor, characterized in that: A computer program is stored in the memory, and the processor is configured to run the computer program to perform the method according to any one of claims 1 to 10.

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