A brain wave measurement circuit

Abstract

The present application discloses a brain wave measurement circuit, which relates to the field of brain wave measurement technology. The brain wave measurement circuit comprises: an electrode probe, a first amplifier circuit, a first low-pass filter, a second amplifier circuit, a second low-pass filter, a first notch filter, a first debiasing circuit, a third low-pass filter, a third amplifier circuit, a fourth low-pass filter, a second notch filter, a second debiasing circuit, a fifth low-pass filter, a fourth amplifier circuit, a sixth low-pass filter, a first adder and a first ADC sampling circuit connected in sequence; the amplifier circuit amplifies the brain voltage signal, the low-pass filter filters the brain voltage signal, the notch filter filters the 50Hz signal in the brain voltage signal, and after the first adder removes the negative signal, the first ADC sampling circuit samples the brain voltage signal after the negative signal is removed once to obtain the first sampled brain wave signal. The present application improves the measurement accuracy of the brain wave signal.

Description

Technical Field

[0001] The present application relates to the technical field of brain wave measurement, and in particular to a brain wave measurement circuit. Background Art

[0002] There are some difficult and complicated medical diseases, such as stroke, epilepsy, attention deficit disorder, etc. In the diagnosis and treatment of these diseases, it is necessary to collect the patient's brain wave signals for the doctor's reference. However, due to the myoelectric interference of the human brain, the measurement accuracy of brain wave signals is low.

[0003] Therefore, a circuit is needed to improve the accuracy of brain wave signal measurement. Summary of the invention

[0004] The purpose of this application is to provide a brain wave measurement circuit to solve the problem of low measurement accuracy of brain wave signals.

[0005] To achieve the above objectives, this application provides the following solutions:

[0006] The present application provides a brain wave measurement circuit, comprising: an electrode probe, a first amplifying circuit, a first low-pass filter, a second amplifying circuit, a second low-pass filter, a first notch filter, a first debiasing circuit, a third low-pass filter, a third amplifying circuit, a fourth low-pass filter, a second notch filter, a second debiasing circuit, a fifth low-pass filter, a fourth amplifying circuit, a sixth low-pass filter, a first adder and a first ADC sampling circuit connected in sequence; the electrode probe is connected to the brain;

[0007] The electrode probe is used to collect original brain voltage signals;

[0008] The first amplifier circuit is used to amplify the original brain voltage signal to obtain a once-amplified brain voltage signal;

[0009] The first low-pass filter is used to filter the once-amplified brain voltage signal to obtain a once-filtered brain voltage signal;

[0010] The second amplifier circuit is used to amplify the brain voltage signal after the primary filtering to obtain a brain voltage signal after the secondary amplification;

[0011] The second low-pass filter is used to filter the second-amplified brain voltage signal to obtain a second-filtered brain voltage signal;

[0012] The first notch filter is used to filter out the 50 Hz signal in the brain voltage signal after the secondary filtering to obtain the brain voltage signal after the primary notch;

[0013] The first de-biasing circuit is used to use a primary bias signal to correct the brain voltage signal after the primary notch to obtain a brain voltage signal after the primary de-biasing;

[0014] The third low-pass filter is used to filter the brain voltage signal after the first debiasing to obtain a brain voltage signal after thrice filtering;

[0015] The third amplifier circuit is used to amplify the brain voltage signal after thrice filtering to obtain a thrice amplified brain voltage signal;

[0016] The fourth low-pass filter is used to filter the brain voltage signal after thrice amplification to obtain a brain voltage signal after fourth filtering;

[0017] The second notch filter is used to filter out the 50 Hz signal in the brain voltage signal after the fourth filtering to obtain the brain voltage signal after the second notch;

[0018] The second de-biasing circuit is used to use the secondary bias signal to positively correct the brain voltage signal after the secondary notch to obtain the brain voltage signal after the secondary de-biasing;

[0019] The fifth low-pass filter is used to filter the brain voltage signal after the second debiasing to obtain a brain voltage signal after five filtering;

[0020] The fourth amplifier circuit is used to amplify the brain voltage signal after five filtering to obtain a brain voltage signal after four amplification;

[0021] The sixth low-pass filter is used to filter the brain voltage signal after the fourth amplification to obtain the brain voltage signal after the sixth filtering;

[0022] The first adder is used for removing negative signals from the brain voltage signal after six filterings to obtain a brain voltage signal after one negative signal removal;

[0023] The first ADC sampling circuit is used to sample the brain voltage signal after one negative removal to obtain a first sampled brain wave signal.

[0024] Optionally, the brain wave measurement circuit further includes: a second adder and a second ADC sampling circuit; the second adder is connected to the first de-biasing circuit, and the second ADC sampling circuit is connected to the second adder;

[0025] The second adder is used to remove the negative signal in the brain voltage signal after the primary de-biasing to obtain the brain voltage signal after the secondary de-negation;

[0026] The second ADC sampling circuit is used to sample the brain voltage signal after secondary de-negation to obtain a second sampled brain wave signal.

[0027] Optionally, the brain wave measurement circuit further includes: a third adder and a third ADC sampling circuit; the third adder is connected to the second de-biasing circuit, and the third ADC sampling circuit is connected to the third adder;

[0028] The third adder is used to remove the negative signal in the brain voltage signal after the second de-biasing to obtain the brain voltage signal after the third de-biasing;

[0029] The third ADC sampling circuit is used to sample the brain voltage signal after three times of de-negation to obtain a third sampled brain wave signal.

[0030] Optionally, the brain wave measurement circuit further includes: a reference voltage generating circuit; the first adder, the second adder and the third adder are respectively connected to the reference voltage generating circuit;

[0031] The reference voltage generating circuit is used to generate reference voltages required by the first adder, the second adder and the third adder.

[0032] Optionally, the first amplifying circuit and the second amplifying circuit are jointly composed of a dual operational amplifier, four resistors and two capacitors.

[0033] Optionally, the first notch filter and the second notch filter each include: 2 dual operational amplifiers, 13 resistors and 3 capacitors.

[0034] Optionally, the first de-biasing circuit and the third amplifying circuit are jointly composed of 2 dual operational amplifiers, 8 resistors and 3 capacitors;

[0035] The second de-biasing circuit and the fourth amplifying circuit are jointly composed of two dual operational amplifiers, eight resistors and three capacitors.

[0036] Optionally, the first adder comprises: 1 dual operational amplifier, 5 resistors and 2 capacitors;

[0037] The second adder and the third adder are composed of a dual operational amplifier, 10 resistors and 4 capacitors.

[0038] Optionally, the reference voltage generating circuit includes: 1 dual operational amplifier and 5 capacitors.

[0039] Optionally, the first low-pass filter, the second low-pass filter, the third low-pass filter, the fourth low-pass filter, the fifth low-pass filter and the sixth low-pass filter each include: a resistor and a capacitor connected in parallel.

[0040] According to the specific embodiments provided in this application, this application discloses the following technical effects:

[0041] The present application discloses a brain wave measurement circuit, which is sequentially connected to an electrode probe, a first amplifier circuit, a first low-pass filter, a second amplifier circuit, a second low-pass filter, a first notch filter, a first debiasing circuit, a third low-pass filter, a third amplifier circuit, a fourth low-pass filter, a second notch filter, a second debiasing circuit, a fifth low-pass filter, a fourth amplifier circuit, a sixth low-pass filter, a first adder and a first ADC sampling circuit; the amplifier circuit amplifies the brain voltage signal, the low-pass filter filters the brain voltage signal, the notch filter filters the 50Hz signal in the brain voltage signal, and after the first adder removes the negative signal, the first ADC sampling circuit samples the brain voltage signal after the negative signal is removed once to obtain a first sampled brain wave signal. The present application sets a debiasing circuit and a first adder to reduce the interference of electromyographic signals and improve the measurement accuracy of brain wave signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0043] Figure 1 A schematic diagram of a brain wave measurement circuit flow chart provided in an embodiment of the present application;

[0044] Figure 2 It is a schematic diagram of the structure of an electrode probe, a first amplifier circuit, a first low-pass filter, a second amplifier circuit and a second low-pass filter;

[0045] Figure 3 is a schematic diagram of the structure of the first notch filter;

[0046] Figure 4 It is a schematic diagram of the structures of a first de-biasing circuit, a third low-pass filter, a third amplifying circuit and a fourth low-pass filter;

[0047] Figure 5 is a schematic diagram of the structure of the second notch filter;

[0048] Figure 6is a schematic structural diagram of a second de-biasing circuit, a fifth low-pass filter, a fourth amplifying circuit and a sixth low-pass filter;

[0049] Figure 7 is a schematic diagram of the structure of a first adder;

[0050] Figure 8 is a schematic diagram of the structure of the second adder and the third adder;

[0051] Fig. 9 Schematic diagram of the reference voltage generation circuit structure.

[0052] Reference numerals:

[0053] Electrode probe-1, first amplifier circuit-2, first low-pass filter-3, second amplifier circuit-4, second low-pass filter-5, first notch filter-6, first de-biasing circuit-7, third low-pass filter-8, third amplifier circuit-9, fourth low-pass filter-10, second notch filter-11, second de-biasing circuit-12, fifth low-pass filter-13, fourth amplifier circuit-14, sixth low-pass filter-15, first adder-16, first ADC sampling circuit-17, second adder-18, second ADC sampling circuit-19, third adder-20, third ADC sampling circuit-21, reference voltage generating circuit-22. DETAILED DESCRIPTION

[0054] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0055] The purpose of this application is to provide a brain wave measurement circuit, aiming to improve the measurement accuracy of brain wave signals.

[0056] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0057] In an exemplary embodiment, Figure 1As shown, a brain wave measurement circuit is provided, comprising: an electrode probe 1, a first amplifier circuit 2, a first low-pass filter 3, a second amplifier circuit 4, a second low-pass filter 5, a first notch filter 6, a first de-biasing circuit 7, a third low-pass filter 8, a third amplifier circuit 9, a fourth low-pass filter 10, a second notch filter 11, a second de-biasing circuit 12, a fifth low-pass filter 13, a fourth amplifier circuit 14, a sixth low-pass filter 15, a first adder 16 and a first ADC sampling circuit 17 connected in sequence; the electrode probe 1 is connected to the brain.

[0058] The electrode probe 1 is used to collect raw brain voltage signals.

[0059] The first amplifier circuit 2 is used to amplify the original brain voltage signal to obtain an amplified brain voltage signal.

[0060] The first low-pass filter 3 is used to filter the once-amplified brain voltage signal to obtain a once-filtered brain voltage signal.

[0061] The second amplifier circuit 4 is used to amplify the brain voltage signal after the primary filtering to obtain a brain voltage signal after the secondary amplification.

[0062] The second low-pass filter 5 is used to filter the brain voltage signal after the second amplification to obtain the brain voltage signal after the second filtering.

[0063] The first notch filter 6 is used to filter out the 50 Hz signal in the brain voltage signal after the secondary filtering to obtain the brain voltage signal after the primary notch.

[0064] The first de-biasing circuit 7 is used to use a primary bias signal to positively correct the brain voltage signal after the primary notch, so as to obtain a brain voltage signal after the primary de-biasing.

[0065] The third low-pass filter 8 is used to filter the brain voltage signal after the first de-biasing to obtain a brain voltage signal after the third filtering.

[0066] The third amplifier circuit 9 is used to amplify the brain voltage signal after thrice filtering to obtain a thrice amplified brain voltage signal.

[0067] The fourth low-pass filter 10 is used to filter the brain voltage signal after thrice amplification to obtain a brain voltage signal after quadruple filtering.

[0068] The second notch filter 11 is used to filter out the 50 Hz signal in the brain voltage signal after the fourth filtering to obtain the brain voltage signal after the second notch.

[0069] The second de-biasing circuit 12 is used to use the secondary bias signal to positively correct the brain voltage signal after the secondary notch to obtain the brain voltage signal after the secondary de-biasing.

[0070] The fifth low-pass filter 13 is used to filter the brain voltage signal after the second debiasing to obtain a brain voltage signal after the fifth filtering.

[0071] The fourth amplifier circuit 14 is used to amplify the brain voltage signal after five filtering to obtain a brain voltage signal after four amplification.

[0072] The sixth low-pass filter 15 is used to filter the brain voltage signal after the fourth amplification to obtain a brain voltage signal after the sixth filtering.

[0073] The first adder 16 is used to remove negative signals from the brain voltage signal after six filterings to obtain a brain voltage signal after one negative signal removal.

[0074] The first ADC sampling circuit 17 is used to sample the brain voltage signal after the negative voltage is removed once to obtain a first sampled brain wave signal.

[0075] Because the ADC sampling circuit can only collect positive signals, it enters an adder before entering the ADC sampling circuit. After voltage division, it is ensured to meet the input requirements of the ADC sampling circuit before being input to the input pin of the ADC sampling circuit.

[0076] As an optional implementation, the brain wave measurement circuit further includes: a second adder 18 and a second ADC sampling circuit 19 ; the second adder 18 is connected to the first de-biasing circuit 7 , and the second ADC sampling circuit 19 is connected to the second adder 18 .

[0077] The second adder 18 is used to remove the negative signal in the brain voltage signal after the primary de-biasing to obtain the brain voltage signal after the secondary de-biasing.

[0078] The second ADC sampling circuit 19 is used to sample the brain voltage signal after the second negative removal to obtain a second sampled brain wave signal.

[0079] As an optional implementation, the brain wave measurement circuit further includes: a third adder 20 and a third ADC sampling circuit 21 ; the third adder 20 is connected to the second de-biasing circuit 12 , and the third ADC sampling circuit 21 is connected to the third adder 20 .

[0080] The third adder 20 is used to remove the negative signal in the brain voltage signal after the second de-biasing to obtain the brain voltage signal after the third de-biasing.

[0081] The third ADC sampling circuit 21 is used to sample the brain voltage signal after three times of negative elimination to obtain a third sampled brain wave signal.

[0082] Specifically, the brain wave measurement circuit also includes: a display; a first adder 16, a second adder 18 and a third adder 20 are respectively connected to the display.

[0083] When necessary, the first sampled brain wave signal, the second sampled brain wave signal and the third sampled brain wave signal can be compared and analyzed through the display.

[0084] As an optional implementation, the brain wave measurement circuit further includes: a reference voltage generating circuit 22; the first adder 16, the second adder 18 and the third adder 20 are respectively connected to the reference voltage generating circuit 22.

[0085] The reference voltage generating circuit 22 is used to generate reference voltages required by the first adder 16 , the second adder 18 and the third adder 20 .

[0086] As an optional implementation, the first amplifier circuit 2 and the second amplifier circuit 4 are jointly composed of a dual operational amplifier, four resistors and two capacitors.

[0087] As an optional implementation, the first notch filter 6 and the second notch filter 11 each include: 2 dual operational amplifiers, 13 resistors and 3 capacitors.

[0088] As an optional implementation, the first de-biasing circuit 7 and the third amplifying circuit 9 are jointly composed of two dual operational amplifiers, eight resistors and three capacitors.

[0089] The second de-biasing circuit 12 and the fourth amplifying circuit 14 are jointly composed of two dual operational amplifiers, eight resistors and three capacitors.

[0090] As an optional implementation, the first adder 16 includes: 1 dual operational amplifier, 5 resistors and 2 capacitors.

[0091] The second adder 18 and the third adder 20 are both composed of a dual operational amplifier, 10 resistors and 4 capacitors.

[0092] As an optional implementation, the reference voltage generating circuit 22 includes: 1 dual operational amplifier and 5 capacitors.

[0093] As an optional implementation, the first low-pass filter 3, the second low-pass filter 5, the third low-pass filter 8, the fourth low-pass filter 10, the fifth low-pass filter 13 and the sixth low-pass filter 15 each include: a resistor and a capacitor connected in parallel.

[0094] Specifically, the structures of the electrode probe, the first amplifier circuit, the first low-pass filter, the second amplifier circuit and the second low-pass filter are as follows: Figure 2 As shown. Among them, CN1 represents the electrode probe, and the electrode probe is a programmable communication interface (Programmable Communication Interface, PCOM); D1 and D2 are transient voltage suppressor diodes (Transient Voltage Suppressor, TVS) protection circuits, the first amplifier circuit includes: resistor R22, capacitor C8 and the left side of the dual operational amplifier U2, the first low-pass filter includes: resistor R12 and capacitor C4, the second amplifier circuit includes: the right side of the dual operational amplifier U2, resistor R13, resistor R14, resistor R32 and capacitor C9, the second low-pass filter includes: resistor R9 and capacitor C1. The original brain voltage signal collected by the electrode probe is directly input to the positive input terminal A+ of the first amplifier circuit, and the reference input terminal is output to the negative input terminal A- of the first amplifier circuit through resistor R31. The original brain voltage signal V input to the first amplifier circuit in and the brain voltage signal V after the first amplification output by the first amplifier circuit out The expression of the relationship between is: V out =V in × (R22 + R8) / R8. (R22 + R8) / R8 is the magnification of the first amplifier circuit. The brain voltage signal after the first amplification is input to the positive input terminal B+ of the second amplifier circuit through the first low-pass filter, and the output terminal BO outputs the brain voltage signal after the second amplification. The brain voltage signal after the second amplification passes through the second low-pass filter to obtain the brain voltage signal after the second filtering. The cutoff frequency of the first low-pass filter and the second low-pass filter are both 1.8KHz. Among them, the sizes of resistors R7, R27, R8, R12, R9, R13, and R32 are all 1K ohms, the sizes of resistors R22 and R14 are all 100K ohms, and the sizes of capacitors C8, C9, C1, and C4 are all 100nF.

[0095] The structure of the first notch filter is as follows Figure 3As shown, it includes: 2 dual operational amplifiers (U3 and U1), 13 resistors (R5, R15, R28, R30, R33, R10, R16, R2, R6, R1, R11, R17, R18) and 3 capacitors (C7, C3, C2). The brain voltage signal after secondary filtering is input into the first notch filter through the resistor R9 of the second low-pass filter and the resistor R15 of the first notch filter for processing to obtain the brain voltage signal after primary notch. Among them, the size of resistors R5, R15, R28, R30, and R33 are all 49.9K ohms, the size of resistors R10 and R2 are all 20.6K ohms, the size of resistors R16 and R6 are all 3.16M ohms, the size of resistors R1, R17, and R18 are all 12.1K ohms, the size of capacitors C7 and C3 are all 1nF, and the size of capacitor C2 is all 0.1nF.

[0096] The first debiasing circuit, the third low-pass filter, the third amplifier circuit and the fourth low-pass filter are structured as follows: Figure 4 As shown. Among them, the first de-biasing circuit includes: resistor R3, resistor R21, resistor R23, resistor R4, resistor R19, capacitor C10, capacitor C11, dual operational amplifier U15 and the left side of dual operational amplifier U4. The third low-pass filter includes: resistor R24 ​​and capacitor C6. The third amplifier circuit includes: the right side of the dual operational amplifier U4, resistor R25, resistor R26, resistor R34 and capacitor C12. The fourth low-pass filter includes: resistor R20 and capacitor C5. The brain voltage signal after the first notch is input into the first de-biasing circuit, the third low-pass filter, the third amplifier circuit and the fourth low-pass filter in turn through the resistor R11 of the first notch filter and the resistor R4 of the first de-biasing circuit for processing to obtain the brain voltage signal AOUT after four filtering. The cut-off frequencies of the third low-pass filter and the fourth low-pass filter are both 100Hz.

[0097] The structure of the second notch filter is as follows Figure 5As shown. The second notch filter includes: 2 dual operational amplifiers (U7 and U6), 13 resistors (R39, R43, R54, R55, R56, R41, R44, R36, R40, R35, R42, R45, R46) and 3 capacitors (C53, C51, C50). The brain voltage signal AOUT after the fourth filtering is input into the second notch filter through the resistor R20 of the fourth low-pass filter and the resistor R43 of the second notch filter for processing, and the brain voltage signal after the second notch is obtained. Among them, the resistors R39, R43, R54, R55, and R56 are all 49.9K ohms, the resistors R41 and R36 are all 20.6K ohms, the resistors R44 and R40 are all 3.16M ohms, the resistors R35, R45, and R46 are all 12.1K ohms, the capacitors C53 and C51 are all 1nF, and the capacitor C50 is 0.1nF. The second notch filter is set to prevent the first notch filter from filtering out the 50Hz waveform due to the excessive amplitude, and the back-end adder and amplifier belong to the conditioning circuit of the second notch filter signal output.

[0098] The structures of the second debiasing circuit, the fifth low-pass filter, the fourth amplifying circuit and the sixth low-pass filter are as follows: Figure 6 As shown. Among them, the second de-biasing circuit includes: resistor R37, resistor R94, resistor R95, resistor R100, resistor R101, capacitor C201, capacitor C202, dual operational amplifier U17 and the left side of dual operational amplifier U16. The fifth low-pass filter includes: resistor R96 and capacitor C200. The fourth amplifier circuit includes: the right side of the dual operational amplifier U16, resistor R97, resistor R98, resistor R99 and capacitor C203. The sixth low-pass filter includes: resistor R38 and capacitor C199. The brain voltage signal after the second notch is input into the second de-biasing circuit, the fifth low-pass filter, the fourth amplifier circuit and the sixth low-pass filter in turn through the resistor R42 of the second notch and the resistor R100 of the second de-biasing circuit for processing, and the brain voltage signal AOUT2 after six filtering is obtained. The cut-off frequencies of the fifth low-pass filter and the sixth low-pass filter are both 40Hz.

[0099] The structure of the first adder is as follows Figure 7As shown. The first adder includes: 1 dual operational amplifier (U8), 5 resistors (R58, R50, R47, R48, R2) and 2 capacitors (C52, C153). The brain voltage signal AOUT2 after six filtering is input into the first adder through the resistor R38 of the sixth low-pass filter and the resistor R50 of the first adder for processing, and the brain voltage signal DAOUT2 after one negative removal is obtained and transmitted to the first ADC sampling circuit. Among them, the size of resistors R58, R50, R48, and R2 are all 10K ohms, the size of resistor R47 is 1K ohm, the size of capacitor C153 is 470nF, and the size of capacitor C52 is 1μF.

[0100] The structures of the second adder and the third adder are as follows: Figure 8 As shown. The second adder and the third adder are jointly composed of 1 dual operational amplifier, 10 resistors and 4 capacitors. Among them, the second adder includes: resistor R65, resistor R29, resistor R53, resistor R66, resistor R49, capacitor C58, capacitor C61 and the right side of the dual operational amplifier U9. The third adder includes: resistor R61, resistor R62, resistor R63, resistor R52, resistor R64, capacitor C59, capacitor C60 and the left side of the dual operational amplifier U9. The brain voltage signal OUT after secondary de-negation is input into the second adder through the resistor R21 of the first de-biasing circuit and the resistor R66 of the second adder for processing, and the brain voltage signal DCOUT1 after secondary de-negation is obtained and transmitted to the second ADC sampling circuit. The brain voltage signal OUT2 after tertiary de-negation is input into the third adder through the resistor R94 of the second de-biasing circuit and the resistor R62 of the third adder for processing, and the brain voltage signal DCOUT2 after tertiary de-negation is obtained and transmitted to the third ADC sampling circuit.

[0101] The reference voltage generation circuit structure is as follows Fig. 9 The reference voltage generating circuit includes: a dual operational amplifier U10 and five capacitors (C70, C71, C75, C78, ​​C79) to generate a reference voltage VREF.

[0102] The model of each resistor in this application is R0402; the model of each capacitor is C0402; the model of each dual operational amplifier is AD8662ARMZ.

[0103] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0104] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0105] This article uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the circuit and its core ideas of this application. At the same time, for those skilled in the art, according to the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A brain wave measurement circuit, characterized in that: The brain wave measurement circuit comprises: an electrode probe, a first amplifier circuit, a first low-pass filter, a second amplifier circuit, a second low-pass filter, a first notch filter, a first debiasing circuit, a third low-pass filter, a third amplifier circuit, a fourth low-pass filter, a second notch filter, a second debiasing circuit, a fifth low-pass filter, a fourth amplifier circuit, a sixth low-pass filter, a first adder and a first ADC sampling circuit connected in sequence; the electrode probe is connected to the brain; The electrode probe is used to collect original brain voltage signals; The first amplifier circuit is used to amplify the original brain voltage signal to obtain a once-amplified brain voltage signal; The first low-pass filter is used to filter the once-amplified brain voltage signal to obtain a once-filtered brain voltage signal; The second amplifier circuit is used to amplify the brain voltage signal after the primary filtering to obtain a brain voltage signal after the secondary amplification; The second low-pass filter is used to filter the second-amplified brain voltage signal to obtain a second-filtered brain voltage signal; The first notch filter is used to filter out the 50 Hz signal in the brain voltage signal after the secondary filtering to obtain the brain voltage signal after the primary notch; The first de-biasing circuit is used to use a primary bias signal to correct the brain voltage signal after the primary notch to obtain a brain voltage signal after the primary de-biasing; The third low-pass filter is used to filter the brain voltage signal after the first debiasing to obtain a brain voltage signal after thrice filtering; The third amplifier circuit is used to amplify the brain voltage signal after thrice filtering to obtain a thrice amplified brain voltage signal; The fourth low-pass filter is used to filter the brain voltage signal after thrice amplification to obtain a brain voltage signal after fourth filtering; The second notch filter is used to filter out the 50 Hz signal in the brain voltage signal after the fourth filtering to obtain the brain voltage signal after the second notch; The second de-biasing circuit is used to use the secondary bias signal to positively correct the brain voltage signal after the secondary notch to obtain the brain voltage signal after the secondary de-biasing; The fifth low-pass filter is used to filter the brain voltage signal after the second debiasing to obtain a brain voltage signal after five filtering; The fourth amplifier circuit is used to amplify the brain voltage signal after five filtering to obtain a brain voltage signal after four amplification; The sixth low-pass filter is used to filter the brain voltage signal after the fourth amplification to obtain the brain voltage signal after the sixth filtering; The first adder is used for removing negative signals from the brain voltage signal after six filterings to obtain a brain voltage signal after one negative signal removal; The first ADC sampling circuit is used to sample the brain voltage signal after the negative voltage is removed once to obtain a first sampled brain wave signal; The brain wave measurement circuit further includes: a second adder and a second ADC sampling circuit; the second adder is connected to the first de-biasing circuit, and the second ADC sampling circuit is connected to the second adder; The second adder is used to remove the negative signal in the brain voltage signal after the primary de-biasing to obtain the brain voltage signal after the secondary de-negation; The second ADC sampling circuit is used to sample the brain voltage signal after secondary de-negation to obtain a second sampled brain wave signal.

2. The brain wave measurement circuit according to claim 1, characterized in that: The brain wave measurement circuit further includes: a third adder and a third ADC sampling circuit; the third adder is connected to the second de-biasing circuit, and the third ADC sampling circuit is connected to the third adder; The third adder is used to remove the negative signal in the brain voltage signal after the second de-biasing to obtain the brain voltage signal after the third de-biasing; The third ADC sampling circuit is used to sample the brain voltage signal after three times of de-negation to obtain a third sampled brain wave signal.

3. The brain wave measurement circuit according to claim 2, characterized in that: The brain wave measurement circuit further includes: a reference voltage generating circuit; the first adder, the second adder and the third adder are respectively connected to the reference voltage generating circuit; The reference voltage generating circuit is used to generate reference voltages required by the first adder, the second adder and the third adder.

4. The brain wave measurement circuit according to claim 1, characterized in that: The first amplifier circuit and the second amplifier circuit are both composed of a dual operational amplifier, four resistors and two capacitors.

5. The brain wave measurement circuit according to claim 1, characterized in that: The first notch filter and the second notch filter each include: 2 dual operational amplifiers, 13 resistors and 3 capacitors.

6. The brain wave measurement circuit according to claim 1, characterized in that: The first de-biasing circuit and the third amplifying circuit are jointly composed of two dual operational amplifiers, eight resistors and three capacitors; The second de-biasing circuit and the fourth amplifying circuit are jointly composed of two dual operational amplifiers, eight resistors and three capacitors.

7. The brain wave measurement circuit according to claim 3, characterized in that: The first adder includes: a dual operational amplifier, five resistors and two capacitors; The second adder and the third adder are composed of a dual operational amplifier, 10 resistors and 4 capacitors.

8. The brain wave measurement circuit according to claim 3, characterized in that: The reference voltage generating circuit includes: a dual operational amplifier and five capacitors.

9. The brain wave measurement circuit according to claim 3, characterized in that: The first low-pass filter, the second low-pass filter, the third low-pass filter, the fourth low-pass filter, the fifth low-pass filter and the sixth low-pass filter each include: a resistor and a capacitor connected in parallel.

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