First chip, chip assembly, replaceable accessory and communication method

Abstract

The invention provides a first chip, a chip assembly, a replaceable accessory and a communication method, the first chip is used for being in communication connection with a host device and a second chip, the host device is used for sending task instructions, the task instructions comprise a first instruction and a second instruction, and the first chip is used for sending the task instructions to the second chip when the first instruction sent by the host device is received. Stopping sending the first control signal to the second chip, so that the second chip is in an abnormal working state, and the first chip responds to the first instruction; and when a second instruction sent by the host equipment is received, a first control signal is sent to the second chip, so that the second chip is in a normal working state, and the second chip responds to the second instruction. The second chip can directly respond to the second instruction, the first chip does not need to forward the second instruction, and the first chip does not need to carry out protocol conversion and other related operations, so that the response speed of the chip assembly can be improved.

Description

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on December 30, 2023, with application number 202311874032.X and application name “A patch chip, a patch chip assembly and an imaging box”, the entire contents of which are incorporated by reference in this application. Technical Field

[0002] The present application relates to the field of communication technology, and in particular to a first chip, a chip assembly, a replaceable accessory and a communication method. Background Art

[0003] In order to enrich the characteristics of the host device, the host device is often used in combination with some peripheral replaceable accessories. When replaceable accessories are used on the host device, the host device often needs to authenticate the source of the replaceable accessories. The replaceable accessories often include a chip for identity authentication, and the chip stores authentication information. In addition, the chip also stores information such as the usage history or service life of the replaceable accessories. The host device can be an image forming device, a mobile terminal, a computer and other devices, and correspondingly, the replaceable accessories can be modules containing chips such as consumable boxes, headphones, batteries, and peripherals.

[0004] For environmental and economic reasons, the market hopes to reuse those replaceable accessories that have been used but not completely scrapped. For example, replace the consumable parts in the replaceable accessories to repair these used replaceable accessories. If the service life information recorded in the chip cannot be modified, it is often necessary to replace the used chip (old chip) on the replaceable accessory at the same time. However, the old chip is not completely unusable. If the old chip is directly replaced and discarded, it is not friendly to the environment; if the old chip is used directly, some data in the old chip may no longer be recognized by the host device, resulting in abnormal replaceable accessories.

[0005] Based on this, a solution combining an old chip and a patch chip is provided in the related technology, and a chip component composed of an old chip and a patch chip responds to the instructions sent by the host device. Specifically, the patch chip is directly connected to the host device for communication, and the old chip is indirectly connected to the host device for communication through the patch chip. When the host device sends a first instruction (an instruction that requires the patch chip to respond), the patch chip directly processes the first instruction and sends the first response data to the host device without the participation of the old chip. When the host device sends a second instruction (an instruction that requires the old chip to respond), the patch chip forwards the second instruction to the old chip, and the old chip processes the second instruction and sends the second response data to the patch chip, and the patch chip then sends the second response data to the host device. In other words, part of the instructions sent by the host device are responded to by the old chip, and the other part of the instructions are responded to by the patch chip.

[0006] However, the patch chip, as the host of the old chip, needs to perform protocol conversion on the second response data after receiving the second response data from the old chip, and then, as the slave of the host device, send the processed second response data to the host device. The protocol conversion process will take a long time, and the overall response of the chip component is relatively slow. In some host devices that require a high chip response speed, the existing chip components are difficult to meet the response speed requirements of the host device.

[0007] It should be pointed out that the information disclosed in the background technology section of this application is only intended to deepen the understanding of the general background technology of this application, and should not be regarded as an admission or suggestion in any form that the information constitutes prior art already known to those skilled in the art. Summary of the invention

[0008] The present application provides a first chip, a chip assembly, a replaceable accessory and a communication method, so as to solve the problem in the prior art that the chip assembly after adding a patch chip cannot meet the response speed requirements of some host devices for the replaceable accessory.

[0009] In the first aspect, an embodiment of the present application provides a first chip, which is used to communicate and connect with a host device and a second chip respectively, and the host device is used to send task instructions, and the task instructions include a first instruction and a second instruction. The first chip is used to: when receiving the first instruction sent by the host device, stop sending a first control signal to the second chip, so that the second chip is in an abnormal working state, and the first chip responds to the first instruction; when receiving the second instruction sent by the host device, send a first control signal to the second chip, so that the second chip is in a normal working state, and the second chip responds to the second instruction; wherein, in the abnormal working state, the second chip cannot respond to the task instruction sent by the host device.

[0010] In a possible implementation, the abnormal working state is a low voltage state, and the working voltage value of the low voltage state is lower than the working voltage value of the normal working state.

[0011] In a possible implementation manner, the abnormal working state is a power-off state.

[0012] In a possible implementation, the first chip is further used to: when receiving a second instruction sent by the host device, switch from a first power consumption state to a second power consumption state, and the power consumption of the first power consumption state is greater than the power consumption of the second power consumption state in at least part of the time interval.

[0013] In a possible implementation, the first chip is further used to: maintain the second power consumption state when receiving the second instruction sent by the host device again; and switch from the second power consumption state to the first power consumption state when receiving the first instruction sent by the host device.

[0014] In one possible implementation, the first chip responds to the first instruction, including: the first chip sends first response data to the host device, the first response data is reset data stored in the first chip, the reset data corresponds to invalid data in the second chip, the reset data is data after resetting the invalid data in the second chip, and the reset data is in a valid state.

[0015] In a possible implementation, the first response data includes remaining service life data.

[0016] In a possible implementation, the second chip responding to the second instruction includes: the second chip sending second response data to the host device, where the second response data is data stored in the second chip for authentication and / or encryption.

[0017] In a second aspect, an embodiment of the present application provides a chip assembly, comprising: a first chip as described in any one of the first aspects; a second chip; wherein the first chip and the second chip are communicatively connected.

[0018] In a third aspect, an embodiment of the present application provides a replaceable accessory, which is used to be detachably installed on a host device, and the replaceable accessory includes: the chip assembly described in the second aspect.

[0019] In a fourth aspect, an embodiment of the present application provides a communication method, which is applied to a first chip, wherein the first chip is used to communicate with a host device and a second chip respectively, and the host device is used to send task instructions, wherein the task instructions include a first instruction and a second instruction, and the method includes: when receiving the first instruction sent by the host device, stopping sending a first control signal to the second chip, so that the second chip is in an abnormal working state, and the first chip responds to the first instruction; when receiving the second instruction sent by the host device, sending a first control signal to the second chip, so that the second chip is in a normal working state, and the second chip responds to the second instruction; wherein, in the abnormal working state, the second chip cannot respond to the task instruction sent by the host device.

[0020] In the embodiment of the present application, when the task instruction sent by the host device is the first instruction, the response channel between the second chip and the host device is controlled to be disconnected, and the first chip responds to the first instruction; when the task instruction sent by the host device is the second instruction, the response channel between the second chip and the host device is controlled to be connected, and the second chip responds to the second instruction. Since the second chip can directly respond to the second instruction without forwarding by the first chip, there is no need for the first chip to perform related operations such as protocol conversion, so the response speed of the chip component can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0022] Figure 1 It is a structural block diagram of a communication system in the related art;

[0023] Figure 2 is a structural block diagram of another communication system in the related art;

[0024] Figure 3 A structural block diagram of a communication system provided in an embodiment of the present application;

[0025] Figure 4 A schematic diagram of the physical connection relationship of a communication system provided in an embodiment of the present application;

[0026] Figure 5 A schematic diagram of the physical connection relationship of another communication system provided in an embodiment of the present application;

[0027] Figure 6 A schematic diagram of the physical connection relationship of another communication system provided in an embodiment of the present application;

[0028] Figure 7 A schematic diagram of the physical connection relationship of another communication system provided in an embodiment of the present application;

[0029] Figure 8 A schematic diagram of the physical connection relationship of another communication system provided in an embodiment of the present application;

[0030] Fig. 9 A schematic diagram of the physical connection relationship of another communication system provided in an embodiment of the present application;

[0031] Fig.10A schematic diagram of the physical connection relationship of another communication system provided in an embodiment of the present application;

[0032] Fig.11 A schematic diagram of the physical connection relationship of another communication system provided in an embodiment of the present application;

[0033] Fig.12 A schematic diagram of the physical connection relationship of another communication system provided in an embodiment of the present application;

[0034] Fig.13 A schematic diagram of the physical connection relationship of another communication system provided in an embodiment of the present application;

[0035] Fig.14 A schematic diagram of the physical connection relationship of another communication system provided in an embodiment of the present application;

[0036] Fig.15 A schematic diagram of the physical connection relationship of another communication system provided in an embodiment of the present application;

[0037] Fig.16 A schematic diagram of the physical connection relationship of another communication system provided in an embodiment of the present application;

[0038] Fig.17 A schematic diagram of the physical connection relationship of another communication system provided in an embodiment of the present application;

[0039] Fig.18 A flow chart of a communication method provided in an embodiment of the present application;

[0040] Fig.19 A schematic diagram of another communication method flow chart provided in an embodiment of the present application;

[0041] Fig. 20 A structural block diagram of a chip component provided in an embodiment of the present application;

[0042] Fig.21 A structural block diagram of another chip component provided in an embodiment of the present application;

[0043] Fig. 22 A structural block diagram of another chip component provided in an embodiment of the present application;

[0044] Fig.23 A structural block diagram of a replaceable accessory provided in an embodiment of the present application. DETAILED DESCRIPTION

[0045] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0046] It should be clear that the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0047] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0048] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0049] To facilitate understanding, the concepts involved in the embodiments of the present application are first explained below.

[0050] Old chip: the original chip on the replaceable accessory. In some possible implementations, the old chip may also be called "used chip", "original chip" or "second chip";

[0051] Patch chip: A newly added chip on a replaceable accessory. In some possible implementations, the patch chip may also be called a "regeneration chip", "grafted chip" or "first chip".

[0052] See also Figure 1 , is a structural block diagram of a communication system in the related technology. Figure 1 As shown, the communication system includes a host device 100 and a replaceable accessory 200. Exemplarily, the host device 100 may be an image forming device, a mobile terminal, a computer or the like, and correspondingly, the replaceable accessory 200 may be a consumable box, an earphone, a battery, a peripheral or the like.

[0053] Specifically, the replaceable accessory 200 includes an old chip 211, and the old chip 211 is connected to the host device 100 through a first information transmission channel 301. It can be understood that the old chip 211 and the host device 100 can send and receive data through the first information transmission channel 301.

[0054] In some possible implementations, the old chip 211 stores identity data, encryption data, remaining service life data, etc. The host device 100 can authenticate the replaceable accessory 200 through the identity data, realize encrypted communication between the host device 100 and the old chip 211 through the encryption data, and determine the remaining service life of the replaceable accessory 200 through the remaining service life data. Normally, the initial value of the remaining service life data is the maximum value (for example, 100%), and as the replaceable accessory 200 is used, the remaining service life data gradually decreases to the minimum value (for example, 0). It can be understood that when the remaining service life data decreases to the minimum value, it usually means that the replaceable accessory 200 is no longer available, and the replaceable accessory 200 needs to be replaced.

[0055] Exemplarily, the host device 100 is an image forming apparatus, and correspondingly, the replaceable accessory 200 is a consumable box, and the remaining service life data is the remaining consumable amount. It can be understood that the initial value of the remaining consumable amount is usually 100%, and as the consumable box is used, the recording material (for example, toner or ink) in the consumable box gradually decreases until it reaches 0. When the remaining consumable amount in the consumable box is 0, it means that the recording material in the consumable box has been exhausted, and the consumable box needs to be replaced so that the image forming apparatus can continue to perform the image forming operation.

[0056] For environmental protection and economic considerations, the market hopes to reuse the used but not completely scrapped replaceable accessories 200. For example, the recording materials are refilled in the consumable box to repair these used consumable boxes. However, the repaired consumable box may give wrong results when performing some tasks. For example, when the consumable box is refilled with recording materials and used again, the data in the old chip 211 on the consumable box has not changed, resulting in the old chip 211 on the consumable box being unable to provide accurate information such as the remaining consumables. Specifically, even if the recording materials are refilled in the consumable box, the image forming device may still prompt that the consumables are insufficient, thereby causing the consumable box to be unusable. At the same time, the user cannot accurately obtain the information on the remaining consumables, which affects the user experience. That is, after the replaceable accessory 200 is repaired, some of the data in the old chip 211 may not match the repaired replaceable accessory 200, thereby causing the replaceable accessory 200 to be unusable and affecting the user experience.

[0057] At the same time, since the programs and data in the old chip 211 are usually fixed and cannot be modified by a third party, the old chip 211 often needs to be replaced synchronously after the replaceable accessory 200 is repaired. However, the data in the old chip 211 is not completely unusable. For example, the identity data and encryption data in the old chip 211 can still be used. In this case, directly replacing and discarding the old chip 211 is not environmentally friendly.

[0058] In view of the above problem, one solution in the related art is to set a patch chip between the host device 100 and the old chip 211, so that part of the instructions sent by the host device 100 (instructions that the old chip 211 can respond to) are responded to by the old chip 211, and the other part of the instructions (instructions that the old chip 211 cannot respond to) are responded to by the patch chip. While retaining the old chip 211, the normal use of the replaceable accessory 200 can be achieved. The working principle of the patch chip is described in detail below with reference to the accompanying drawings.

[0059] See also Figure 2 , is a structural block diagram of another communication system in the related art. Figure 2 As shown, the communication system Figure 1 The difference of the communication system shown is that the replaceable accessory 200 includes a chip assembly 210 consisting of a patch chip 212 and an old chip 211. The host device 100 is connected to the patch chip 212 through a second information transmission channel 302, and the patch chip 212 is connected to the old chip 211 through a third information transmission channel 303. In other words, the patch chip 212 is directly connected to the host device 100, and the old chip 211 is indirectly connected to the host device 100 through the patch chip 212.

[0060] When the host device 100 sends a first instruction (an instruction that requires the patch chip 212 to respond), the patch chip 212 directly processes the first instruction and sends the first response data to the host device 100 without the participation of the old chip 211. When the host device 100 sends a second instruction (an instruction that requires the old chip 211 to respond), the patch chip 212 forwards the second instruction to the old chip 211, and the old chip 211 processes the second instruction and sends the second response data to the patch chip 212, and the patch chip 212 then sends the second response data to the host device 100.

[0061] However, the patch chip 212, as the host of the old chip 211, needs to perform protocol conversion on the second response data after receiving the second response data from the old chip 211, and then, as the slave of the host device 100, send the processed second response data to the host device 100. The protocol conversion process will consume a relatively long time, and the overall response of the chip component 210 is relatively slow. In some host devices 100 that have higher requirements on chip response speed, the existing chip component 210 is difficult to meet the response speed requirements of the host device 100.

[0062] In addition, the process of protocol conversion and forwarding of the second response data by the patch chip 212 will bring additional power consumption. Compared with the replaceable accessory 200 with only the old chip 211, the replaceable accessory 200 with the patch chip 212 consumes more power and cannot meet the power consumption requirements of some host devices 100 for the replaceable accessory 200.

[0063] See also Figure 3 , is a structural block diagram of a communication system provided in an embodiment of the present application. Figure 3 As shown, the communication system Figure 2 The difference of the communication system shown is that a fourth information transmission channel 304 is also provided between the host device 100 and the old chip 211, and the host device 100 and the old chip 211 can directly send and receive data through the fourth information transmission channel 304. Specifically, the host device 100 can send the task instruction to the patch chip 212 through the second information transmission channel 302, and send the task instruction to the old chip 211 through the fourth information transmission channel 304. That is to say, both the patch chip 212 and the old chip 211 can directly receive the task instruction sent by the host device 100. Further, if the task instruction is a first instruction, the patch chip 212 processes the first instruction and sends the first response data to the host device 100 through the second information transmission channel 302; if the task instruction is a second instruction, the old chip 211 processes the second instruction and sends the second response data to the host device 100 through the fourth information transmission channel 304. Since the second response data does not need to be forwarded by the patch chip 212, the response speed of the chip component 210 can be improved.

[0064] In addition, in the embodiment of the present application, since the patch chip 212 can directly respond to the first instruction and the old chip 211 can directly respond to the second instruction (the patch chip 212 does not need to perform protocol conversion and forwarding on the second response data), the power consumption of the chip component 210 in responding to the first instruction and the second instruction is not much different from the power consumption of a single old chip in responding to the first instruction and the second instruction in the prior art. Therefore, when the chip component 210 is applied to the host device 100, it can meet the power consumption requirements of the host device 100.

[0065] As described above, the programs and data in the old chip 211 are usually fixed and cannot be modified by a third party. Therefore, according to the program setting of the old chip 211, when it receives the task instruction, it usually responds to the task instruction. However, when the task instruction is the first instruction, if the old chip 211 responds to the first instruction, it will interfere with the first response data of the patch chip 212, resulting in the host device 100 being unable to receive the correct first response data. Therefore, the patch chip 212 should also control the response capability of the old chip 211. Specifically, the old chip 211 needs to work based on the first control signal output by the patch chip 212 through the third information transmission channel 303. When the patch chip 212 receives the first instruction sent by the host device 100, it stops sending the first control signal to the old chip 211, so that the old chip 211 is in an abnormal working state. In the abnormal working state, the old chip 211 cannot respond to the task instruction sent by the host device 100, thereby avoiding the interference of the old chip 211 with the first response data of the patch chip 212. When the patch chip 212 receives the second instruction sent by the host device 100 , it sends a first control signal to the old chip 211 , so that the old chip 211 is in a normal working state, and the old chip 211 can respond to the second instruction.

[0066] It should be pointed out that Figure 1-Figure 3 The first information transmission channel 301, the second information transmission channel 302, the third information transmission channel 303 and the fourth information transmission channel 304 are only used to represent the information interaction relationship between different functional units, not the physical connection relationship between different functional units. The physical connection relationship between different functional units will be described in detail below.

[0067] See also Figure 4 , is a schematic diagram of the physical connection relationship of a communication system provided in an embodiment of the present application. Figure 4 As shown, the host device 100 includes a first end 100A and a second end 100B, the patch chip 212 includes a first end 212A, a second end 212B and a third end 212C, and the old chip 211 includes a first end 211A and a second end 211B. The first end 100A of the host device 100 is electrically connected to the first end 212A of the patch chip 212, and a first line is formed between the first end 100A of the host device 100 and the first end 212A of the patch chip 212. The second end 100B of the host device 100 is electrically connected to the second end 212B of the patch chip 212, and a second line is formed between the second end 100B of the host device 100 and the second end 212B of the patch chip 212. The third end 212C of the patch chip 212 is electrically connected to the first end 211A of the old chip 211, and the second end 211B of the old chip 211 is electrically connected to the first line.

[0068] In an embodiment of the present application, the host device 100 may send a task instruction through the first end 100A, and the task instruction includes a first instruction and a second instruction. Among them, the first instruction is an instruction that requires the patch chip 212 to respond. Specifically, the task corresponding to the first instruction may be a task that the patch chip 212 can accurately execute and the old chip 211 does not have the ability to execute. For example, the task corresponding to the first instruction is to provide consumables remaining information. Since the old chip 211 cannot provide correct consumables remaining information, the task needs to be executed by the patch chip 212. The second instruction is an instruction that requires the old chip 211 to respond. Specifically, the task corresponding to the second instruction may be a task that the old chip 211 can accurately execute and the patch chip 212 does not have the ability to execute. For example, the task corresponding to the second execution is that the old chip 211 completes authentication with the host device 100. To execute the task, it is necessary to send identity information or encryption information to the host device 100, and the identity information or encryption information is stored in the old chip 211, so the task needs to be executed by the old chip 211.

[0069] Understandably, according to Figure 4 According to the connection relationship shown, both the patch chip 212 and the old chip 211 can receive the task instruction sent by the host device 100, and after the patch chip 212 and the old chip 211 receive a task instruction at the same time, the patch chip 212 determines and controls which chip executes the task instruction. Specifically, when the patch chip 212 determines that the task instruction is the first instruction, the third end 212C of the patch chip 212 stops sending the first control signal to the first end 211A of the old chip 211, so that the old chip 211 is in an abnormal working state, and the old chip 211 cannot respond to the first instruction. At the same time, the patch chip 212 responds to the first instruction. Specifically, the patch chip 212 parses the first instruction, executes the task corresponding to the first instruction, and then sends the first response data to the host device 100 through the first end 212A and / or the second end 212B of the patch chip 212. When the patch chip 212 determines that the task instruction is the second instruction, the third terminal 212C of the patch chip 212 sends a first control signal to the first terminal 211A of the old chip 211, so that the old chip 211 is in a normal working state, and the old chip 211 responds to the second instruction. Specifically, the old chip 211 parses the second instruction, executes the task corresponding to the second instruction, and then sends the second response data to the host device 100 through the second terminal 211B of the old chip 211. It can be understood that in the embodiment of the present application, the patch chip 212 controls the response capability of the old chip 211 to the task instruction by controlling the old chip 211 to receive or not receive the first control signal.

[0070] It should be noted that when the patch chip 212 and the old chip 211 do not execute the task instructions sent by the host device 100, the third end 212C of the patch chip 212 can maintain the state of sending the first control signal to the first end 211A of the old chip 211, so that when the host device 100 sends the task instructions, the old chip 211 can receive the task instructions sent by the host device 100.

[0071] In a possible implementation, the first terminal 100A of the host device 100 is also used to output a first voltage, and the second terminal 100B of the host device 100 is also used to output a second voltage. Correspondingly, the first terminal 212A and the second terminal 212B of the patch chip 212 can also receive the first voltage and the second voltage output by the first terminal 100A and the second terminal 100B of the host device 100, respectively, and the patch chip 212 can be powered by the first voltage and the second voltage, so that the patch chip 212 can be powered on and work normally. In a specific implementation, the first voltage is a power supply voltage, and the second voltage is a ground voltage; or the first voltage is a ground voltage, and the second voltage is a power supply voltage.

[0072] Since the second end 211B of the old chip 211 is electrically connected to the first line, the second end 211B of the old chip 211 can receive the first voltage output by the first end 100A of the host device 100. If the old chip 211 is to be powered on and work normally, the first end 211A of the old chip 211 also needs to receive the second voltage. Therefore, by controlling the output voltage of the third end 212C of the patch chip 212, the response capability of the old chip 211211 can be controlled. Specifically, when the third end 212C of the patch chip 212 outputs the second voltage, the old chip 211 receives the first voltage and the second voltage at the same time, and the old chip 211 can be powered on and work normally (in a normal working state), and then can respond to the task instruction sent by the host device 100; when the third end 212C of the patch chip 212 does not output the second voltage, the old chip 211 cannot receive the first voltage and the second voltage at the same time, and the old chip 211 cannot be powered on and work normally (in an abnormal working state), and then cannot respond to the task instruction sent by the host device 100. It can be understood that in this application scenario, the first control signal mentioned above is the second voltage.

[0073] It can be understood that in the embodiment of the present application, the ports between different functional units (host device 100, patch chip 212 and old chip 211) can transmit both data and voltage, that is, the power lines and data lines between different functional units are shared. Of course, those skilled in the art can also set independent power lines between different functional units according to actual needs, that is, only use Figure 4 The port shown in the figure transmits data, and the embodiment of the present application does not impose any specific limitation on this.

[0074] See also Figure 5 , is a schematic diagram of the physical connection relationship of another communication system provided in an embodiment of the present application. Figure 5 As shown, the embodiments of the present application are Figure 4 The difference of the illustrated embodiment is that the second end 211B of the old chip 211 is electrically connected to the second line. Specifically, the host device 100 includes a first end 100A and a second end 100B, the patch chip 212 includes a first end 212A, a second end 212B and a third end 212C, and the old chip 211 includes a first end 211A and a second end 211B. Among them, the first end 100A of the host device 100 is electrically connected to the first end 212A of the patch chip 212, and a first line is formed between the first end 100A of the host device 100 and the first end 212A of the patch chip 212. The second end 100B of the host device 100 is electrically connected to the second end 212B of the patch chip 212, and a second line is formed between the second end 100B of the host device 100 and the second end 212B of the patch chip 212. The third end 212C of the patch chip 212 is electrically connected to the first end 211A of the old chip 211 , and the second end 211B of the old chip 211 is electrically connected to the second line.

[0075] In the embodiment of the present application, the host device 100 can send a task instruction through the second end 100B, and the task instruction includes a first instruction and a second instruction. Figure 5According to the connection relationship shown, both the patch chip 212 and the old chip 211 can receive the task instruction sent by the host device 100, and after the patch chip 212 and the old chip 211 receive a task instruction at the same time, the patch chip 212 determines and controls which chip executes the task instruction. Specifically, when the patch chip 212 determines that the task instruction is the first instruction, the third end 212C of the patch chip 212 stops sending the first control signal to the first end 211A of the old chip 211, so that the old chip 211 is in an abnormal working state, and the old chip 211 cannot respond to the first instruction. At the same time, the patch chip 212 responds to the first instruction. Specifically, the patch chip 212 parses the first instruction, executes the task corresponding to the first instruction, and then sends the first response data to the host device 100 through the first end 212A and / or the second end 212B of the patch chip 212. When the patch chip 212 determines that the task instruction is the second instruction, the third terminal 212C of the patch chip 212 sends a first control signal to the first terminal 211A of the old chip 211, so that the old chip 211 is in a normal working state, and the old chip 211 responds to the second instruction. Specifically, the old chip 211 parses the second instruction, executes the task corresponding to the second instruction, and then sends the second response data to the host device 100 through the second terminal 211B of the old chip 211. It can be understood that in the embodiment of the present application, the patch chip 212 controls the response capability of the old chip 211 to the task instruction by controlling the old chip 211 to receive or not receive the first control signal.

[0076] It should be noted that when the patch chip 212 and the old chip 211 do not execute the task instructions sent by the host device 100, the third end 212C of the patch chip 212 can maintain the state of sending the first control signal to the first end 211A of the old chip 211, so that when the host device 100 sends the task instructions, the old chip 211 can receive the task instructions sent by the host device 100.

[0077] In a possible implementation, the first terminal 100A of the host device 100 is also used to output a first voltage, and the second terminal 100B of the host device 100 is also used to output a second voltage. Accordingly, the first terminal 212A and the second terminal 212B of the patch chip 212 can respectively receive the first voltage and the second voltage output by the first terminal 100A and the second terminal 100B of the host device 100, and the patch chip 212 can be powered by the first voltage and the second voltage, so that the patch chip 212 can be powered on and work normally. In a specific implementation, the first voltage is a power supply voltage, and the second voltage is a ground voltage; or the first voltage is a ground voltage, and the second voltage is a power supply voltage.

[0078] Since the second end 211B of the old chip 211 is electrically connected to the second line, the second end 211B of the old chip 211 can receive the second voltage output by the second end 100B of the host device 100. If the old chip 211 is to be powered on and work normally, the first end 211A of the old chip 211 needs to receive the first voltage. Therefore, by controlling the output voltage of the third end 212C of the patch chip 212, the response capability of the old chip 211211 can be controlled. Specifically, when the third end 212C of the patch chip 212 outputs the first voltage, the old chip 211 receives the first voltage and the second voltage at the same time, and the old chip 211 can be powered on and work normally (in a normal working state), and then can respond to the task instruction sent by the host device 100; when the third end 212C of the patch chip 212 does not output the first voltage, the old chip 211 cannot receive the first voltage and the second voltage at the same time, and the old chip 211 cannot be powered on and work normally (in an abnormal working state), and then cannot respond to the task instruction sent by the host device 100. It can be understood that in this application scenario, the first control signal mentioned above is a first voltage.

[0079] It can be understood that in the embodiment of the present application, the ports between different functional units (host device 100, patch chip 212 and old chip 211) can transmit both data and voltage, that is, the power lines and data lines between different functional units are shared. Of course, those skilled in the art can also set independent power lines between different functional units according to actual needs, that is, only use Figure 5 The port shown in the figure transmits data, and the embodiment of the present application does not impose any specific limitation on this.

[0080] See also Figure 6 , is a schematic diagram of the physical connection relationship of another communication system provided in an embodiment of the present application. Figure 6 As shown, the embodiments of the present application are Figure 4The difference of the illustrated embodiment is that the patch chip 212 further includes a voltage adjustment module 320 and a processing module 310. The first output terminal 310A of the processing module 310 is electrically connected to the third terminal 212C of the patch chip 212, and the second output terminal 310B of the processing module 310 is electrically connected to the third terminal 212C of the patch chip 212 through the voltage adjustment module 320. When receiving the first instruction sent by the host device 100, the signal output by the second output terminal 310B of the processing module 310 is processed by the voltage adjustment module 320, and then the second control signal is output, that is, the second control signal is sent to the third terminal 212C of the patch chip 212, and the first terminal 211A of the old chip 211 receives the second control signal. At this time, the old chip 211 is in an abnormal working state, so that the old chip 211 cannot respond to the first instruction. When receiving the second instruction sent by the host device 100, the first output terminal 310A of the processing module 310 sends a first control signal to the third terminal 212C of the patch chip 212, and the first terminal 211A of the old chip 211 receives the first control signal. At this time, the old chip 211 is in a normal working state, and the old chip 211 can respond to the first instruction.

[0081] In one possible implementation, when the first terminal 211A of the old chip 211 receives the second control signal, the old chip 211 is in a low voltage state (the low voltage state is a type of abnormal working state). In the low voltage state, although the old chip 211 cannot respond to the task instruction, the old chip 211 still remains powered on, and at least part of the data stored in the old chip 211 will not be lost. In this way, when the old chip 211 receives the first control signal again, the at least part of the data is still stored in the old chip 211, and the old chip 211 can execute the task that requires the at least part of the data. In some possible implementations, the at least part of the data can be a temporary variable, for example, a session key.

[0082] In a possible implementation, the first terminal 100A of the host device 100 is also used to output a first voltage, and the second terminal 100B of the host device 100 is also used to output a second voltage. Correspondingly, the first terminal 212A and the second terminal 212B of the patch chip 212 can also receive the first voltage and the second voltage output by the first terminal 100A and the second terminal 100B of the host device 100, respectively, and the patch chip 212 can be powered by the first voltage and the second voltage, so that the patch chip 212 can be powered on and work normally. In a specific implementation, the first voltage is a power supply voltage, and the second voltage is a ground voltage; or the first voltage is a ground voltage, and the second voltage is a power supply voltage.

[0083] In addition, since the second end 211B of the old chip 211 is electrically connected to the first line, the second end 211B of the old chip 211 can receive the first voltage output by the first end 100A of the host device 100. If the old chip 211 is to be powered on and work normally, the first end 211A of the old chip 211 needs to receive the second voltage. Therefore, by controlling the output voltage of the third end 212C of the patch chip 212, the response capability of the old chip 211211 can be controlled. Specifically, when receiving the first instruction sent by the host device 100, the signal output by the second output end 310B of the processing module 310 is processed by the voltage adjustment module 320 and outputs the third voltage, that is, the first end 211A of the old chip 211 receives the third voltage. Among them, the voltage difference between the first voltage and the third voltage is less than the voltage difference between the first voltage and the second voltage, then the voltage difference between the first end 211A and the second end 211B of the old chip 211 is less than the voltage difference required for normal power-on operation, resulting in the old chip 211 being in a low voltage state, and the old chip 211 cannot respond to the first instruction. However, at this time, the old chip 211 is still in a powered-on state, and at least part of the data stored in the old chip 211 will not be lost. When receiving the second instruction sent by the host device 100, the first output terminal 310A of the processing module 310 outputs the second voltage, that is, the first end 211A of the old chip 211 receives the second voltage. At this time, the voltage difference between the first end 211A and the second end 211B of the old chip 211 is the voltage difference required for normal operation, so the old chip 211 is in a normal working state, and the old chip 211 can respond to the second instruction. It can be understood that in this application scenario, the first control signal described above is the second voltage, and the second control signal described above is the third voltage.

[0084] See also Figure 7 , is a schematic diagram of the physical connection relationship of another communication system provided in an embodiment of the present application. Figure 7 As shown, the embodiments of the present application are Figure 5The difference of the illustrated embodiment is that the patch chip 212 further includes a voltage adjustment module 320 and a processing module 310. The first output terminal 310A of the processing module 310 is electrically connected to the third terminal 212C of the patch chip 212, and the second output terminal 310B of the processing module 310 is electrically connected to the third terminal 212C of the patch chip 212 through the voltage adjustment module 320. When receiving the first instruction sent by the host device 100, the signal output by the second output terminal 310B of the processing module 310 is processed by the voltage adjustment module 320, and then the second control signal is output, that is, the second control signal is sent to the third terminal 212C of the patch chip 212, and the first terminal 211A of the old chip 211 receives the second control signal. At this time, the old chip 211 is in an abnormal working state, so that the old chip 211 cannot respond to the first instruction. When receiving the second instruction sent by the host device 100, the first output terminal 310A of the processing module 310 sends a first control signal to the third terminal 212C of the patch chip 212, and the first terminal 211A of the old chip 211 receives the first control signal. At this time, the old chip 211 is in a normal working state, and the old chip 211 can respond to the first instruction.

[0085] In one possible implementation, when the first terminal 211A of the old chip 211 receives the second control signal, the old chip 211 is in a low voltage state (the low voltage state is a type of abnormal working state). In the low voltage state, although the old chip 211 cannot respond to the task instruction, the old chip 211 still remains powered on, and at least part of the data stored in the old chip 211 will not be lost. In this way, when the old chip 211 receives the first control signal again, the at least part of the data is still stored in the old chip 211, and the old chip 211 can execute the task that requires the at least part of the data. In some possible implementations, the at least part of the data can be a temporary variable, for example, a communication key.

[0086] In a possible implementation, the first terminal 100A of the host device 100 is also used to output a first voltage, and the second terminal 100B of the host device 100 is also used to output a second voltage. Correspondingly, the first terminal 212A and the second terminal 212B of the patch chip 212 can also receive the first voltage and the second voltage output by the first terminal 100A and the second terminal 100B of the host device 100, respectively, and the patch chip 212 can be powered by the first voltage and the second voltage, so that the patch chip 212 can be powered on and work normally. In a specific implementation, the first voltage is a power supply voltage, and the second voltage is a ground voltage; or the first voltage is a ground voltage, and the second voltage is a power supply voltage.

[0087] In addition, since the second end 211B of the old chip 211 is electrically connected to the second line, the second end 211B of the old chip 211 can receive the second voltage output by the first end 100A of the host device 100. If the old chip 211 is to be powered on and work normally, the first end 211A of the old chip 211 needs to receive the first voltage. Therefore, by controlling the output voltage of the third end 212C of the patch chip 212, the response capability of the old chip 211211 can be controlled. Specifically, when receiving the first instruction sent by the host device 100, the signal output by the second output end 310B of the processing module 310 is processed by the voltage adjustment module 320 and outputs the fourth voltage, that is, the first end 211A of the old chip 211 receives the fourth voltage. Among them, the voltage difference between the fourth voltage and the second voltage is less than the voltage difference between the first voltage and the second voltage, then the voltage difference between the first end 211A and the second end 211B loaded on the old chip 211 is less than the voltage difference required for normal power-on operation, resulting in the old chip 211 being in a low voltage state, and the old chip 211 cannot respond to the first instruction. However, at this time, the old chip 211 is still in a powered-on state, and at least part of the data stored in the old chip 211 will not be lost. When receiving the second instruction sent by the host device 100, the first output terminal 310A of the processing module 310 outputs the first voltage, that is, the first end 211A of the old chip 211 receives the first voltage. At this time, the voltage difference between the first end 211A and the second end 211B loaded on the old chip 211 is the voltage difference required for normal operation, so the old chip 211 is in a normal working state, and the old chip 211 can respond to the second instruction. It can be understood that in this application scenario, the first control signal described above is the first voltage, and the second control signal described above is the fourth voltage.

[0088] In a possible implementation, the voltage adjustment module 320 includes a resistor device and / or a semiconductor device, which is not specifically limited in the embodiment of the present application.

[0089] See also Figure 8 , is a schematic diagram of the physical connection relationship of another communication system provided in an embodiment of the present application. Figure 8 As shown, the embodiments of the present application are Figure 4 The difference of the illustrated embodiment is that the patch chip 212 further includes a transfer terminal 212D, and the first terminal 212A of the patch chip 212 is electrically connected to the transfer terminal 212D. It is understandable that when the first terminal 212A of the patch chip 212 is electrically connected to the transfer terminal 212D, the second terminal 211B of the old chip 211 can be electrically connected to the first circuit through the electrical connection with the transfer terminal 212D of the patch chip 212, so as to facilitate the assembly of the old chip 211 and the patch chip 212.

[0090] In a possible implementation, the electrical connection between the first end 212A of the patch chip 212 and the adapter end 212D specifically includes: the first end 212A of the patch chip 212 and the adapter end 212D are electrically connected inside the patch chip 212. That is to say, when designing the patch chip 212, the electrical connection between the first end 212A of the patch chip 212 and the adapter end 212D is achieved through the internal circuit of the patch chip 212. It can be understood that, compared with "achieving the electrical connection between the first end 212A of the patch chip 212 and the adapter end 212D through a connecting wire outside the patch chip 212", the embodiment of the present application can reduce the connecting wires outside the patch chip 212, so that the circuit of the chip assembly composed of the patch chip 212 and the old chip 211 is simpler.

[0091] In a possible implementation, the third end 212C and the transition stage 212D of the patch chip 212 are located on one side of the patch chip 212 ( Figure 8 The first end 212A and the second end 212B of the patch chip 212 are located on the other side of the patch chip 212 ( Figure 8 According to this arrangement, the old chip 211 can be connected to one side of the patch chip 212, and the other side of the patch chip 212 is used to connect to the host device 100, so that the structure of the chip assembly composed of the patch chip 212 and the old chip 211 is more compact. Of course, those skilled in the art can also set other port arrangements on the patch chip 212 according to actual needs, and the embodiment of the present application does not specifically limit this.

[0092] It should be pointed out that according to Figure 8 As shown in the connection relationship, when the old chip 211 sends the second response data to the host device 100 through the second end 211B, the second response data passes through the inside of the patch chip 212, but it only uses the line between the first end 212A and the adapter end 212D of the patch chip 212 to realize data transmission, and the patch chip 212 does not need to process and forward the second response data.

[0093] For other contents of the embodiments of this application, please refer to Figure 4 For the sake of brevity, the description of the illustrated embodiment will not be repeated here.

[0094] See also Fig. 9 , is a schematic diagram of the physical connection relationship of another communication system provided in an embodiment of the present application. Fig. 9 As shown, the embodiments of the present application are Figure 5The difference of the illustrated embodiment is that the patch chip 212 further includes a transfer terminal 212D, and the second terminal 212B of the patch chip 212 is electrically connected to the transfer terminal 212D. It is understandable that when the second terminal 212B of the patch chip 212 is electrically connected to the transfer terminal 212D, the second terminal 211B of the old chip 211 can be electrically connected to the second circuit through the electrical connection with the transfer terminal 212D of the patch chip 212, so as to facilitate the assembly of the old chip 211 and the patch chip 212.

[0095] In a possible implementation, the electrical connection between the second end 212B of the patch chip 212 and the adapter end 212D specifically includes: the second end 212B of the patch chip 212 and the adapter end 212D are electrically connected inside the patch chip 212. That is to say, when designing the patch chip 212, the electrical connection between the second end 212B of the patch chip 212 and the adapter end 212D is achieved through the internal circuit of the patch chip 212. It can be understood that, compared with "achieving the electrical connection between the second end 212B of the patch chip 212 and the adapter end 212D through a connecting wire outside the patch chip 212", the embodiment of the present application can reduce the connecting wires outside the patch chip 212, so that the circuit of the chip assembly composed of the patch chip 212 and the old chip 211 is simpler.

[0096] In a possible implementation, the third end 212C and the transition stage 212D of the patch chip 212 are located on one side of the patch chip 212 ( Figure 8 The first end 212A and the second end 212B of the patch chip 212 are located on the other side of the patch chip 212 ( Figure 8 According to this arrangement, the old chip 211 can be connected to one side of the patch chip 212, and the other side of the patch chip 212 is used to connect to the host device 100, so that the structure of the chip assembly composed of the patch chip 212 and the old chip 211 is more compact. Of course, those skilled in the art can also set other port arrangements on the patch chip 212 according to actual needs, and the embodiment of the present application does not specifically limit this.

[0097] It should be pointed out that according to Fig. 9 As shown in the connection relationship, when the old chip 211 sends the second response data to the host device 100 through the second end 211B, the second response data passes through the inside of the patch chip 212, but it only uses the line between the second end 212B of the patch chip 212 and the adapter end 212D to realize data transmission, and the patch chip 212 does not need to process and forward the second response data.

[0098] For other contents of the embodiments of this application, please refer to Figure 5For the sake of brevity, the description of the illustrated embodiment will not be repeated here.

[0099] See also Fig.10 , is a schematic diagram of the physical connection relationship of another communication system provided in an embodiment of the present application. Fig.10 As shown, in the embodiment of the present application, the second end 211B of the old chip 211 is electrically connected to the first end 212A of the patch chip 212 through a connecting line, so as to realize the electrical connection between the second end 211B of the old chip 211 and the first line. Compared with setting the adapter end 212D on the patch chip 212, this solution is easier to implement.

[0100] For other contents of the embodiments of this application, please refer to Figure 4 For the sake of brevity, the description of the illustrated embodiment will not be repeated here.

[0101] See also Fig.11 , is a schematic diagram of the physical connection relationship of another communication system provided in an embodiment of the present application. Fig.11 As shown, in the embodiment of the present application, the second end 211B of the old chip 211 is electrically connected to the second end 212B of the patch chip 212 through a connecting line, so as to realize the electrical connection between the second end 211B of the old chip 211 and the second circuit. Compared with setting the adapter terminal 212D on the patch chip 212, this solution is easier to implement.

[0102] For other contents of the embodiments of this application, please refer to Figure 5 For the sake of brevity, the description of the illustrated embodiment will not be repeated here.

[0103] See also Fig.12 , is a schematic diagram of the physical connection relationship of another communication system provided in an embodiment of the present application. Fig.12 As shown, in the embodiment of the present application, the second end 211B of the old chip 211 is electrically connected to the first end 100A of the host device 100 through a connecting line, so as to realize the electrical connection between the second end 211B of the old chip 211 and the first line. In the embodiment of the present application, the second end 211B of the old chip 211 is directly electrically connected to the host device 100 without passing through the patch chip 212, which can improve the stability of the electrical connection.

[0104] For other contents of the embodiments of this application, please refer to Figure 4 For the sake of brevity, the description of the illustrated embodiment will not be repeated here.

[0105] See also Fig.13 , is a schematic diagram of the physical connection relationship of another communication system provided in an embodiment of the present application. Fig.13As shown, in the embodiment of the present application, the second end 211B of the old chip 211 is electrically connected to the second end 100B of the host device 100 through a connecting line, so as to realize the electrical connection between the second end 211B of the old chip 211 and the second line. In the embodiment of the present application, the second end 211B of the old chip 211 is directly electrically connected to the host device 100 without passing through the patch chip 212, which can improve the stability of the electrical connection.

[0106] For other contents of the embodiments of this application, please refer to Figure 5 For the sake of brevity, the description of the illustrated embodiment will not be repeated here.

[0107] See also Fig.14 , is a schematic diagram of the physical connection relationship of another communication system provided in an embodiment of the present application. Fig.14 As shown, the embodiments of the present application are Figure 8 The difference of the illustrated embodiment is that a first switch S1 is further provided inside the patch chip 212, and the second end 212B of the patch chip 212 is electrically connected to the third end 212C of the patch chip 212 through the first switch S1. It can be understood that the second end 212B and the third end 212C of the patch chip 212 can be controlled to switch between electrical connection and electrical insulation through the first switch S1. Specifically, when the first switch S1 is closed, the second end 212B and the third end 212C of the patch chip 212 are electrically connected; when the first switch S1 is opened, the second end 212B and the third end 212C of the patch chip 212 are electrically insulated.

[0108] When the patch chip 212 receives the first instruction sent by the host device 100, the first switch S1 is controlled to be opened, and the second end 212B and the third end 212C of the patch chip 212 are electrically insulated, so that the third end 212C of the patch chip 212 stops sending the first control signal to the first end 211A of the old chip 211, and sets the old chip 211 to an abnormal working state, and the old chip 211 cannot respond to the first instruction. When the patch chip 212 receives the second instruction sent by the host device 100, the first switch S1 is controlled to be closed, and the second end 212B and the third end 212C of the patch chip 212 are electrically connected, so that the third end 212C of the patch chip 212 sends the first control signal to the first end 211A of the old chip 211, and sets the old chip 211 to a normal working state, and the old chip 211 can respond to the second instruction. It can be understood that when the first end 212A of the patch chip 212 receives the first voltage and the second end 212B of the patch chip 212 receives the second voltage, the first control signal is the second voltage.

[0109] It should be pointed out that in addition to simple switches, those skilled in the art may also use other devices to achieve switching between electrical connection and electrical insulation between the second end 212B and the third end 212C of the patch chip 212 according to actual needs, and the embodiments of the present application do not impose specific restrictions on this.

[0110] For other contents of the embodiments of this application, please refer to Figure 8 For the sake of brevity, the description of the illustrated embodiment will not be repeated here.

[0111] See also Fig.15 , is a schematic diagram of the physical connection relationship of another communication system provided in an embodiment of the present application. Fig.15 As shown, the embodiments of the present application are Fig. 9 The difference of the illustrated embodiment is that a second switch S2 is further provided inside the patch chip 212, and the first end 212B of the patch chip 212 is electrically connected to the third end 212C of the patch chip 212 through the second switch S2. It can be understood that the first end 212A and the third end 212C of the patch chip 212 can be controlled to switch between electrical connection and electrical insulation through the second switch S2. Specifically, when the second switch S2 is closed, the first end 212A and the third end 212C of the patch chip 212 are electrically connected; when the second switch S2 is opened, the first end 212A and the third end 212C of the patch chip 212 are electrically insulated.

[0112] When the patch chip 212 receives the first instruction sent by the host device 100, the second switch S2 is controlled to be opened, and the first end 212A and the third end 212C of the patch chip 212 are electrically insulated, so that the third end 212C of the patch chip 212 stops sending the first control signal to the first end 211A of the old chip 211, and sets the old chip 211 to an abnormal working state, and the old chip 211 cannot respond to the first instruction. When the patch chip 212 receives the second instruction sent by the host device 100, the second switch S2 is controlled to be closed, and the first end 212A and the third end 212C of the patch chip 212 are electrically connected, so that the third end 212C of the patch chip 212 sends the first control signal to the first end 211A of the old chip 211, and sets the old chip 211 to a normal working state, and the old chip 211 can respond to the second instruction. It can be understood that in the embodiment of the present application, when the first end 212A of the patch chip 212 receives the first voltage and the second end 212B of the patch chip 212 receives the second voltage, the first control signal is the first voltage.

[0113] It should be pointed out that in addition to simple switches, those skilled in the art may also use other devices to achieve switching between electrical connection and electrical insulation between the first end 212A and the third end 212C of the patch chip 212 according to actual needs, and the embodiments of the present application do not impose specific limitations on this.

[0114] For other contents of the embodiments of this application, please refer to Fig. 9 For the sake of brevity, the description of the illustrated embodiment will not be repeated here.

[0115] See also Fig.16 , is a schematic diagram of the physical connection relationship of another communication system provided in an embodiment of the present application. Fig.16 As shown, the embodiments of the present application are Figure 4 The difference of the embodiment shown is that the patch chip 212 further includes a voltage adjustment module 320, a processing module 310 and a transfer terminal 212D. For details about the voltage adjustment module 320 and the processing module 310, please refer to Figure 6 For details about the "transfer terminal 212D", please refer to Figure 8 For the sake of brevity, the description of the illustrated embodiment will not be repeated here.

[0116] In addition, in the embodiment of the present application, the voltage adjustment module 320 is a diode. When current flows through the diode, a voltage difference is generated at both ends of the diode, thereby achieving voltage adjustment of the output signal of the second output terminal 310B of the processing module 310. In addition, when the diode is forward-conducted, the voltage difference between its two ends can be basically kept stable, so that the voltage received by the old chip 211 can be kept stable.

[0117] It should be pointed out that Fig.16 This is only an exemplary description of the voltage adjustment module 320 in the embodiment of the present application, and should not be used as a limitation on the protection scope of the present application. For example, the number of diodes can also be multiple, and multiple diodes can be connected in series or in parallel. Those skilled in the art can adjust the type, number and connection relationship between diodes according to actual needs, and the embodiment of the present application does not impose specific restrictions on this. In addition, in addition to diodes, those skilled in the art can also use other devices to achieve the function of voltage adjustment, such as resistor devices, other semiconductor devices other than diodes, or a combination of resistor devices and semiconductor devices, etc., and the embodiment of the present application does not impose specific restrictions on this.

[0118] See also Fig.17 , is a schematic diagram of the physical connection relationship of another communication system provided in an embodiment of the present application. Fig.17 As shown, the embodiments of the present application are Figure 5 The difference of the embodiment shown is that the patch chip 212 further includes a voltage adjustment module 320, a processing module 310 and a transfer terminal 212D. For details about the voltage adjustment module 320 and the processing module 310, please refer to Figure 7For details about the "transfer terminal 212D", please refer to Fig. 9 For the sake of brevity, the description of the illustrated embodiment will not be repeated here.

[0119] In addition, in the embodiment of the present application, the voltage adjustment module 320 is a diode. When current flows through the diode, a voltage difference is generated at both ends of the diode, thereby realizing voltage adjustment of the output signal of the second output terminal 310B of the processing module 310. Of course, in addition to the diode, those skilled in the art can also use other devices to realize the function of voltage adjustment, such as a resistor device, other semiconductor devices other than the diode, or a combination of a resistor device and a semiconductor device, etc., and the embodiment of the present application does not make specific restrictions on this.

[0120] Corresponding to the above embodiment, the embodiment of the present application also provides a communication method.

[0121] See also Fig.18 , is a flow chart of a communication method provided in an embodiment of the present application. The method can be applied to Figure 3-Figure 17 The communication system shown in Fig.18 As shown, it mainly includes the following steps.

[0122] Step S1801 : the host device 100 sends a task instruction to the patch chip 212 and the old chip 211 .

[0123] Understandably, according to Figure 3-Figure 17 The connection relationship among the host device 100, the patch chip 212 and the old chip 211 in the communication system shown is such that when the host device 100 sends a task instruction, both the patch chip 212 and the old chip 211 can receive the task instruction.

[0124] Step S1802: The patch chip 212 determines whether the task instruction is the first instruction or the second instruction.

[0125] As described above, after the replaceable part 200 is repaired, a portion of the data in the old chip 211 does not match the repaired replaceable part 200 (e.g., remaining service life data, etc.); another portion of the data still matches the repaired replaceable part 200 (e.g., identity data, encryption data, etc.). For ease of explanation, the data in the old chip 211 that does not match the repaired replaceable part 200 is referred to as "invalid data"; the data in the old chip 211 that still matches the repaired replaceable part 200 is referred to as "valid data".

[0126] Normally, after the replaceable accessory 200 is repaired, the invalid data in the old chip 211 will be reset, and the generated reset data will be stored in the patch chip 212. In the subsequent work process, the patch chip 212 will respond to the instructions associated with the invalid data. In addition, since the valid data in the old chip 211 can still be used, there is no need to reset the valid data in the old chip 211. In the subsequent work, the old chip 211 will still respond to the instructions associated with the valid data. It can be understood that "instructions associated with invalid data" are instructions that require the patch chip 212 to respond, and this type of instruction is referred to as the "first instruction" in this article; "instructions associated with valid data" are instructions that require the old chip 211 to respond, and this type of instruction is referred to as the "second instruction" in this article.

[0127] As mentioned above, the programs and data in the old chip 211 are usually fixed and cannot be modified by a third party. Therefore, in the embodiment of the present application, "resetting the invalid data in the old chip 211" does not directly modify the invalid data in the old chip 211, but generates reset data corresponding to the invalid data, and stores the generated reset data in the patch chip 212, and the invalid data in the old chip 211 remains unchanged. It can be understood that the reset data in the patch chip 212 is in a valid state. Exemplarily, the remaining service life data in the old chip 211 is "0", and the remaining service life data "0" in the old chip 211 is invalid data. After resetting the remaining service life data to "100%", the remaining service life data "100%" is stored in the patch chip 212. The remaining service life data "100%" in the patch chip 212 is reset data, and it can be understood that the reset data is in a valid state.

[0128] When the patch chip 212 receives the task instruction, it first needs to determine whether the received task instruction is the first instruction or the second instruction. In a specific implementation, the patch chip 212 can determine whether the task instruction is the first instruction or the second instruction after receiving part of the data in the task instruction sent by the host device 100; or determine whether the task instruction is the first instruction or the second instruction after receiving all the data in the task instruction sent by the host device 100.

[0129] Exemplarily, the task instruction includes a field for marking the instruction type. It is understandable that when the field is located at the front end or the middle of the task instruction, the patch chip 212 can determine whether the task instruction is the first instruction or the second instruction after receiving part of the data in the task instruction sent by the host device 100 (including the data of the field for marking the instruction type). When the field is located at the end of the task instruction, the patch chip 212 needs to receive all the data in the task instruction sent by the host device 100 before the patch chip 212 can determine whether the task instruction is the first instruction or the second instruction.

[0130] It is understandable that the patch chip 212 determines whether the task instruction is the first instruction or the second instruction based on part of the data, which can improve the response speed of the patch chip 212.

[0131] Step S1803: If the task instruction sent by the host device 100 is the first instruction, stop sending the first control signal to the old chip 211, so that the old chip 211 is in an abnormal working state.

[0132] It is understandable that when the task instruction sent by the host device 100 is the first instruction, the patch chip 212 needs to respond, that is, the patch chip 212 needs to send the first response data to the host device 100. However, according to the program setting in the old chip 211, the old chip 211 will respond to the task instruction after receiving the task instruction (whether it is the first instruction or the second instruction). In other words, after receiving the first instruction, the old chip 211 will also output the corresponding response data. The response data output by the old chip 211 usually interferes with the first response data output by the patch chip 212, thereby causing the host device 100 to fail to receive the correct first response data. Therefore, in the embodiment of the present application, when the patch chip 212 determines that the task instruction sent by the host device 100 is the first instruction, it stops sending the first control signal to the old chip 211. When the old chip 211 does not receive the first control signal, the old chip 211 will enter an abnormal working state, so that the old chip 211 cannot respond to the task instruction sent by the host device 100, thereby avoiding the old chip 211 from outputting interference data.

[0133] During normal operation, the patch chip 212 usually maintains the state of sending the first control signal to the old chip 211, so that the old chip 211 has the ability to receive the task instruction sent by the host device 100, that is, the current patch chip 212 is in the state of sending the first control signal to the old chip 211. Therefore, in the embodiment of the present application, "stop sending the first control signal to the old chip 211" is specifically: the patch chip 212 switches from "the state of sending the first control signal to the old chip 211" to "the state of stopping sending the first control signal to the old chip 211". Of course, in other application scenarios, the current patch chip 212 may also be in the state of stopping sending the first control signal to the old chip 211, and accordingly, "stop sending the first control signal to the old chip 211" is specifically: keep stopping sending the first control signal to the old chip 211.

[0134] Normally, after determining that the task instruction sent by the host device 100 is the first instruction, the patch chip 212 will immediately stop sending the first control signal to the old chip 211. As described above, the patch chip 212 has different timings for determining the task instruction (after receiving all or part of the data in the task instruction, determining whether the task instruction is the first instruction or the second instruction), resulting in different timings for stopping sending the first control signal to the old chip 211, and further resulting in different data received by the old chip 211, which are discussed separately below.

[0135] In one case, after receiving part of the data in the task instruction sent by the host device 100, the patch chip 212 determines that the task instruction sent by the host device 100 is the first instruction, and immediately stops sending the first control signal to the old chip 211. It can be understood that at this time, the old chip 211 has not received all the data in the task instruction, that is, the old chip 211 has not received the complete first instruction, so that the old chip 211 cannot generate response data corresponding to the first instruction, thereby avoiding the old chip 211 from outputting interference data.

[0136] In another case, after receiving all the data in the task instruction sent by the host device 100, the patch chip 212 determines that the task instruction sent by the host device 100 is the first instruction, and immediately stops sending the first control signal to the old chip 211. It can be understood that at this time, the old chip 211 has received all the data in the task instruction, that is, the old chip 211 has received the complete first instruction. However, since the patch chip 212 stops sending the first control signal to the old chip 211, the old chip 211 is in an abnormal working state. Therefore, even if the old chip 211 receives the complete first instruction, it cannot perform corresponding data processing, thereby avoiding the old chip 211 from outputting interference data.

[0137] It is understandable that after receiving part of the data in the task instruction sent by the host device 100 , the patch chip 212 stops sending the first control signal to the old chip 211 , so that the old chip 211 processes less data, thereby reducing the power consumption of the entire chip assembly 210 .

[0138] In some possible implementations, the abnormal working state is a low-voltage state, and the working voltage value in the low-voltage state is lower than the working voltage value in the normal working state. In the low-voltage state, although the old chip 211 cannot respond to the task instruction, the old chip 211 still remains powered on, and at least part of the data stored in the old chip 211 will not be lost. In this way, when the old chip 211 receives the first control signal again, at least part of the data is still stored in the old chip 211, and the old chip 211 can execute the task that requires at least part of the data. In some possible implementations, at least part of the data can be a temporary variable, for example, a session key. The following is an explanation in conjunction with a specific application scenario.

[0139] In one application scenario, when encrypted communication is required between the host device 100 and the chip assembly 210, the old chip 211 generates a session key and encrypts communication with the host device 100 based on the session key. The session key is usually a temporary variable stored in the old chip 211. If the host device 100 directly controls the power off of the old chip 211 when sending the first instruction, the session key will be lost. When the host device 100 sends the second instruction again, the session key needs to be regenerated, which increases the data processing capacity of the old chip 211.

[0140] In addition, the session key is usually generated based on the encryption seed and count value stored in the old chip 211. According to the program setting of the old chip 211, after it is powered on again, the count value will default to +1, which will cause the session key to change after powering on again. In other words, if the host device 100 directly controls the old chip 211 to power off when sending the first instruction, then after switching to the second instruction again, the old chip 211 is controlled to power on again, which will cause the session key in the old chip 211 to change. It can be understood that after the session key in the old chip 211 is changed, the old chip 211 cannot decrypt and identify the second instruction sent by the host device 100, which will cause communication abnormality.

[0141] On the contrary, in the embodiment of the present application, when the host device 100 sends the first instruction, the old chip 211 is controlled to enter a low voltage state (keep powered on), which can avoid the loss of the session key stored in the old chip 211. When the host device 100 sends the second instruction again, the old chip 211 can directly use the temporarily stored session key to perform encrypted communication with the host device 100. It can be understood that this solution is particularly suitable for application scenarios where the first instruction and the second instruction are frequently switched and encrypted communication is required.

[0142] For the specific implementation of "abnormal working state is low voltage state", please refer to the above Figure 6 and Figure 7 For the sake of brevity, the description of the illustrated embodiment will not be repeated here.

[0143] In some possible implementations, the abnormal working state is a power-off state, that is, by controlling the old chip 211 to be powered off, the old chip 211 is prevented from responding to the task instruction sent by the host device 100 .

[0144] In the embodiment of the present application, since the old chip 211 is in a power-off state while the patch chip 212 is processing the first instruction, that is, the power consumption of the old chip 211 is 0 at this time, the overall power consumption of the chip assembly 210 is substantially the same as the power consumption of a single patch chip 212, that is, the solution can further reduce the overall power consumption of the chip assembly 210. Therefore, the solution is particularly suitable for application scenarios with high power consumption requirements.

[0145] For the specific implementation of "abnormal working state is power-off state", please refer to the above Fig.14 and Fig.15 For the sake of brevity, the description of the illustrated embodiment will not be repeated here.

[0146] Step S1804 : the patch chip 212 sends first response data to the host device 100 .

[0147] In the embodiment of the present application, if the patch chip 212 determines that the task instruction sent by the host device 100 is the first instruction, the patch chip 212 sends the first response data to the host device 100, that is, the patch chip 212 responds to the first instruction. In a specific implementation, the first response data is usually the reset data stored in the patch chip 212, and the reset data is the data after the invalid data in the old chip 211 is reset. It can be understood that the reset data is in a valid state.

[0148] Exemplarily, the remaining service life data stored in the old chip 211 is "0" (invalid data), and the remaining service life data stored in the patch chip 212 is "100%" (reset data). When the first instruction sent by the host device 100 to the chip component 210 is a remaining service life data acquisition instruction, the patch chip 212 sends "100%" to the host device 100 to indicate that the current remaining service life of the replaceable accessory 200 is 100%.

[0149] It is understandable that, with the use of the replaceable accessory 200, the reset data in the patch chip 212 will also change accordingly, but the invalid data in the old chip 211 will generally not change. Exemplarily, the remaining service life data stored in the patch chip 212 is "100%", and with the use of the replaceable accessory 200, the reset data in the patch chip 212 may gradually decrease, for example, to 99%, 98%, 97%, etc. However, since the remaining service life data "0" in the old chip 211 is already the minimum value, the remaining service life data in the two chips will generally not change with the use of the replaceable accessory 200.

[0150] Step S1805: If the task instruction sent by the host device 100 is the second instruction, a first control signal is sent to the old chip 211, so that the old chip 211 is in a normal working state.

[0151] It can be understood that when the task instruction sent by the host device 100 is the second instruction, the old chip 211 needs to respond, so the first control signal is sent to the old chip 211 to put the old chip 211 in a normal working state.

[0152] As described above, during normal operation, the patch chip 212 usually maintains a state of sending a first control signal to the old chip 211, so that the old chip 211 has the ability to receive task instructions sent by the host device 100, that is, the current patch chip 212 is in a state of sending a first control signal to the old chip 211. Therefore, in an embodiment of the present application, "sending a first control signal to the old chip 211" is specifically: maintaining a state of sending a first control signal to the old chip 211. Of course, in other application scenarios, the current patch chip 212 may also be in a state of stopping sending the first control signal to the old chip 211, and accordingly, "sending a first control signal to the old chip 211" is specifically: the patch chip 212 switches from "stopping the state of sending the first control signal to the old chip 211" to "sending the first control signal to the old chip 211".

[0153] Step S1806 : the old chip 211 sends second response data to the host device 100 .

[0154] In an embodiment of the present application, if the patch chip 212 determines that the task instruction sent by the host device 100 is the second instruction, a first control signal is sent to the old chip 211, so that the old chip 211 is in a normal working state. According to the program setting in the old chip 211, the old chip 211 can send second response data to the host device 100 after receiving the second instruction. It can be understood that the patch chip 212 will no longer respond to the second instruction at this time. It should be pointed out that the old chip 211 can directly send the second response data to the host device 100 without the need for forwarding by the patch chip 212, and there is no need for the patch chip 212 to perform related operations such as protocol conversion. Therefore, the response speed of the chip component 210 can be improved.

[0155] In a specific implementation, the second response data is usually data for authentication and / or encryption stored in the old chip 211, such as identity data and / or encryption data, etc. The identity data may include a serial number, etc., and the encryption data may include an encryption seed and a count value corresponding to the encryption seed, etc.

[0156] Exemplarily, Table 1 shows the encrypted data stored in the old chip 211 .

[0157] Table 1:

[0158]

[0159]

[0160] As shown in Table 1, the encrypted data includes multiple groups of encryption seeds and count values. Each encryption seed corresponds to a count value, and the count value is used to record the number of times the encryption seed is accessed. The initial value of the count value is usually 0. Each time the encryption seed is accessed, the count value corresponding to the encryption seed is increased by 1. Exemplarily, the count value corresponding to the encryption seed [3D E0 66C1] is [00FE], that is, the number of times the encryption seed [3D E0 66C1] is accessed is [00FE]. When the encryption seed [3D E0 66C1] is accessed again, the count value [00FE] corresponding to it is increased by 1, and the updated count value is [00FF]. In the embodiment of the present application, since the count value corresponding to the encryption seed stored in the old chip 211 has not reached the maximum value, the encrypted data stored in the old chip 211 is still available, that is, valid data.

[0161] It should be noted that Table 1 is only an exemplary description of the encryption seed and count value in the embodiment of the present application. In practical applications, the old chip 211 may store more or less encryption seeds and count values, and the embodiment of the present application does not make specific restrictions on this.

[0162] When the second instruction sent by the host device 100 to the chip assembly 210 is an encrypted data acquisition instruction, the old chip 211 sends a set of encryption seeds and count values ​​to the host device 100. The host device 100 generates a session key based on at least the encryption seed and the count value, and sends the session key to the patch chip 212 and the old chip 211. Thereafter, the patch chip 212 and the old chip 211 can perform encrypted communication with the host device 100 based on the session key. In addition, in the process of generating the session key, the host device 100 may also need to use other data, such as a random number, etc., which is not specifically limited in the embodiment of the present application.

[0163] In a possible application scenario, if the count value corresponding to the encryption seed stored in the old chip 211 reaches the maximum value, the encrypted data stored in the old chip 211 becomes unavailable. At this time, the encrypted data in the old chip 211 is invalid data, and the encrypted data needs to be reset, and the reset encrypted data is stored in the patch chip 212, and then the patch chip 212 responds to the instructions related to the encrypted data in the subsequent work process. That is to say, in the embodiment of the present application, the reset data stored in the patch chip 212 may also include encrypted data. The response process of the chip component 210 to the reset encrypted data can be referred to the above description, and for the sake of brevity, it will not be repeated here.

[0164] In the embodiment of the present application, when the task instruction sent by the host device 100 is the first instruction, the old chip 211 is controlled to enter an abnormal working state, and the patch chip 212 responds to the first instruction; when the task instruction sent by the host device 100 is the second instruction, the old chip 211 is controlled to enter a normal working state, and the old chip 211 responds to the second instruction. Since the old chip 211 can directly respond to the second instruction without the need for the patch chip 212 to forward it, there is no need for the patch chip 212 to perform related operations such as protocol conversion, so the response speed of the chip component 210 can be improved.

[0165] In addition, in the embodiment of the present application, since the old chip 211 can directly respond to the second instruction, the patch chip 212 does not need to perform related operations such as forwarding and protocol conversion, and therefore the power consumption of the chip component 210 can be reduced.

[0166] See also Fig.19 , is a flow chart of another communication method provided in an embodiment of the present application. Fig.19 As shown, the embodiments of the present application are Fig.18 The difference of the illustrated embodiment is that the following steps are included after step S1805.

[0167] Step S1901: the patch chip 212 switches from a first power consumption state to a second power consumption state.

[0168] In an embodiment of the present application, if the patch chip 212 determines that the task instruction sent by the host device 100 is a second instruction, that is, an instruction that requires the old chip 211 to respond, it switches from the first power consumption state to the second power consumption state. Among them, the power consumption of the first power consumption state is greater than the power consumption of the second power consumption state. In other words, if the patch chip 212 determines that the task instruction sent by the host device 100 is an instruction that requires the old chip 211 to respond, it reduces its own power consumption, and then reduces the power consumption of the entire chip component 210, meeting the power consumption requirements of the host device 100 for the chip component 210. In a specific implementation, in the second power consumption state, the patch chip 212 can reduce power consumption by reducing the working main frequency; or, turn off some energy-consuming modules in the patch chip 212 to reduce power consumption.

[0169] It can be understood that the patch chip 212 is in the second power consumption state, and when the second instruction sent by the host device 100 is received again, the patch chip 212 continues to maintain the second power consumption state. When the first instruction sent by the host device 100 is received, the patch chip 212 switches from the second power consumption state to the first power consumption state, so that the patch chip 212 can respond to the first instruction normally.

[0170] Corresponding to the above embodiment, the embodiment of the present application further provides a patch chip. The specific content of the patch chip can be found in the description of the above embodiment, and will not be repeated here for the sake of brevity.

[0171] Corresponding to the above embodiment, the embodiment of the present application further provides an old chip. The specific content of the old chip can be found in the description of the above method embodiment, and will not be repeated here for the sake of brevity.

[0172] Corresponding to the above embodiment, the embodiment of the present application also provides a chip component.

[0173] See also Fig. 20 , is a structural block diagram of a chip component provided in an embodiment of the present application. Fig. 20 As shown, the chip assembly 210 includes a patch chip 212 and an old chip 211, and the patch chip 212 and the old chip 211 are in communication connection. The specific contents of the patch chip 212 and the old chip 211 can be found in the description of the above embodiment, and will not be repeated here for the sake of brevity.

[0174] See also Fig.21 , is a structural block diagram of another chip component provided in an embodiment of the present application. Fig.21 As shown, the embodiments of the present application are Figure 7The difference of the illustrated embodiment is that a power consumption configuration unit is further provided in the patch chip 212 .

[0175] In some application scenarios, the host device 100 usually requires that the power consumption of the chip component 210 is constant and within a preset range. In the response scheme of the chip component 210 to the task instruction provided in the embodiment of the present application, the chip component 210 needs to switch between different working states according to the type of task instruction. Specifically, when the task instruction is a first instruction, the patch chip 212 responds to the first instruction; when the task instruction is a second instruction, the old chip 211 responds to the second instruction. Since the chip component 210 switches between different working states, it will cause power consumption fluctuations, which may cause the host device 100 to believe that the chip component 210 on the communication bus is abnormal, making the chip component 210 unable to work normally.

[0176] To address this problem, the embodiment of the present application sets a power consumption configuration unit in the chip assembly 210. The power consumption configuration unit can adjust its own power consumption to keep the power consumption of the chip assembly 210 within a preset power consumption range, thereby meeting the power consumption requirements of the host device 100 for the chip assembly 210. Specifically, when the power consumption of the patch chip 212 and the old chip 211 increases, the power consumption of the chip assembly 210 is reduced; when the power consumption of the patch chip 212 and the old chip 211 decreases, the power consumption of the chip assembly 210 is increased. Through the above control method, the power consumption of the chip assembly 210 is kept within the preset power consumption range.

[0177] In a specific implementation, the power consumption configuration unit may include a variable resistor, and the patch chip 212 may control the size of the variable resistor to adjust the power consumption of the power consumption configuration unit. Of course, those skilled in the art may set other types of power consumption configuration units according to actual needs, and the present application embodiment does not specifically limit this.

[0178] See also Fig. 22 , is a structural block diagram of another chip component provided in an embodiment of the present application. Fig. 22 As shown, the embodiments of the present application are Fig.21 The difference of the illustrated embodiment is that the power consumption configuration unit is arranged outside the patch chip 212. That is, the power consumption configuration unit can be arranged inside or outside the patch chip 212, and the embodiment of the present application does not impose any specific limitation on this.

[0179] Corresponding to the above embodiment, the embodiment of the present application also provides a replaceable accessory.

[0180] See also Fig.23 , is a structural block diagram of a replaceable accessory provided in an embodiment of the present application. Fig.23As shown, the replaceable accessory 200 includes a chip assembly 210. The specific content of the chip assembly 210 can refer to the description of the above embodiment, and for the sake of simplicity, it will not be repeated here.

[0181] Corresponding to the above embodiment, the embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium may store a program, wherein when the program is running, the device where the computer-readable storage medium is located may be controlled to execute some or all of the steps in the above method embodiment. In a specific implementation, the computer-readable storage medium may be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM).

[0182] Corresponding to the above-mentioned embodiment, the embodiment of the present application further provides a computer program product, which includes executable instructions. When the executable instructions are executed on a computer, the computer executes some or all of the steps in the above-mentioned method embodiment.

[0183] In the embodiments of the present application, "at least one" refers to one or more, and "plurality" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent the existence of A alone, the existence of A and B at the same time, and the existence of B alone. Among them, A and B can be singular or plural. The character " / " generally indicates that the previous and subsequent associated objects are in an "or" relationship. "At least one of the following" and similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b and c can be represented by: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple.

[0184] Those of ordinary skill in the art will appreciate that the various units and algorithm steps described in the embodiments disclosed herein can be implemented in a combination of electronic hardware, computer software, and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0185] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0186] In several embodiments provided in the present application, if any function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc., various media that can store program codes.

[0187] The above is only a specific implementation of the present application. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. The protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A first chip, the first chip is used to communicate with a host device and a second chip respectively, the host device is used to send a task instruction, the task instruction includes a first instruction and a second instruction, characterized in that: The first chip is used for: When receiving a first instruction sent by the host device, stop sending a first control signal to the second chip, so that the second chip is in an abnormal working state, and the first chip responds to the first instruction; When receiving a second instruction sent by the host device, sending a first control signal to the second chip, so that the second chip is in a normal working state, and the second chip responds to the second instruction; Wherein, in the abnormal working state, the second chip cannot respond to the task instruction sent by the host device.

2. The first chip according to claim 1, characterized in that: The abnormal working state is a low voltage state, and the working voltage value of the low voltage state is lower than the working voltage value of the normal working state.

3. The first chip according to claim 2, characterized in that: The abnormal working state is a power-off state.

4. The first chip according to claim 1, characterized in that: The first chip is also used for: When receiving a second instruction sent by the host device, the first power consumption state is switched to the second power consumption state, and the power consumption of the first power consumption state is greater than the power consumption of the second power consumption state in at least a part of the time interval.

5. The first chip according to claim 4, characterized in that: The first chip is also used for: When receiving a second instruction sent by the host device again, maintaining the second power consumption state; When a first instruction sent by the host device is received, the second power consumption state is switched to the first power consumption state.

6. The first chip according to any one of claims 1 to 5, characterized in that: The first chip responding to the first instruction includes: The first chip sends first response data to the host device, the first response data is reset data stored in the first chip, the reset data corresponds to the invalid data in the second chip, the reset data is data after resetting the invalid data in the second chip, and the reset data is in a valid state.

7. The first chip according to claim 6, characterized in that: The first response data includes remaining useful life data.

8. The first chip according to any one of claims 1 to 5, characterized in that: The second chip responding to the second instruction includes: The second chip sends second response data to the host device, where the second response data is data stored in the second chip for authentication and / or encryption.

9. A chip assembly, characterized in that: include: The first chip according to any one of claims 1 to 8; The second chip; The first chip and the second chip are communicatively connected.

10. A replaceable accessory, the replaceable accessory being used to be detachably mounted on a host device, characterized in that: The replaceable accessories include: The chip assembly as claimed in claim 9.

11. A communication method, applied to a first chip, wherein the first chip is used to communicate with a host device and a second chip respectively, and the host device is used to send a task instruction, wherein the task instruction includes a first instruction and a second instruction, characterized in that: The method comprises: When receiving a first instruction sent by the host device, stop sending a first control signal to the second chip, so that the second chip is in an abnormal working state, and the first chip responds to the first instruction; When receiving a second instruction sent by the host device, sending a first control signal to the second chip, so that the second chip is in a normal working state, and the second chip responds to the second instruction; Wherein, in the abnormal working state, the second chip cannot respond to the task instruction sent by the host device.

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