Offset cause reduction for localization constraints

Abstract

The invention relates to offset cause reduction for localization constraints. In one example, a control binary sequence (CBS) determined during simulation of a design under test (DUT) is obtained. The simulation includes the use of a constrained random stimulus generator (CRSG) biased by a coverage bias. The CBS includes a first enable bit corresponding to a respective constraint problem solved by the CRSG and biased by the coverage bias, and triggers a specified message during the emulation in accordance with the first enable bit. A simplified CBS is constructed having a second enable bit, which is a subset of the first enable bit. A simulation result generated by re-simulating the DUT is obtained. The re-simulation includes, for each constraint problem, a solution step of selectively recovering the CRSG, the solution step being performed during the simulation when a corresponding bit of the simplified CBS is an enable bit. And when the simulation result comprises the specified message, distributing the simplified CBS as a triggering CBS for triggering the specified message.

Description

Technical Field

[0001] The present disclosure relates to functional verification of circuit designs, and more particularly, to positioning constraints that can trigger specified messages during simulation of the design. Background Art

[0002] Designing a circuit can be an arduous process, especially for today's complex system-on-chip (SoC) circuits. Designs are often thoroughly tested to ensure functionality, specifications, and reliability. Performing these tests prior to tapeout and manufacturing is important because of the high cost and complexity of tapeout and manufacturing. Manufacturing circuits that do not meet the necessary specifications, do not operate as expected, and / or are unreliable can result in significant wasted costs. Summary of the invention

[0003] An example is a method. A control binary sequence determined during simulation of a design under test (DUT) is obtained. The simulation of the DUT is based on using a constrained random stimulus generator and a coverage biaser that biases the constrained random stimulus generator. The control binary sequence includes a first enable bit, which corresponds to a corresponding constraint problem solved by the constrained random stimulus generator and biased by the coverage biaser, and triggers a specified message according to the first enable bit during the simulation of the DUT. A simplified control binary sequence with a second enable bit is constructed by one or more processors, and the second enable bit is a subset of the first enable bit. A simulation result generated by re-simulating the DUT is obtained. Re-simulating the DUT includes: for each constraint problem in the constraint problem, selectively restoring the solution step of the constrained random stimulus generator for the corresponding constraint problem, and the solution step is performed during the simulation of the DUT when the corresponding bit of the simplified control binary sequence is an enable bit in the second enable bit. Determine whether the simulation result includes the specified message. When the simulation result includes the specified message, assign the simplified control binary sequence as a trigger control binary sequence that triggers the specified message.

[0004] Another example is a non-transient computer-readable medium. The non-transient computer-readable medium includes stored instructions. These instructions, when executed by one or more processors, cause one or more processors to: obtain a control binary sequence determined during simulation of a design under test (DUT), construct a simplified control binary sequence, obtain a simulation result generated by re-simulating the DUT, determine whether the simulation result includes a specified message, and when the simulation result includes a specified message, assign the simplified control binary sequence as a trigger control binary sequence that triggers the specified message. The simulation DUT is based on using a constrained random stimulus generator and a coverage biaser that biases the constrained random stimulus generator. The control binary sequence includes a first enable bit, which corresponds to a corresponding constraint problem solved by the constrained random stimulus generator and biased by the coverage biaser, and triggers the specified message according to the first enable bit during the simulation of the DUT. The simplified control binary sequence has a second enable bit, which is a subset of the first enable bit. Resimulating the DUT includes: for each constraint problem in the constraint problem, selectively restoring a solution step of the constrained random stimulus generator for the corresponding constraint problem, which solution step is performed when the corresponding bit of the simplified control binary sequence is an enable bit in the second enable bit during simulation of the DUT.

[0005] Another example is a non-transitory computer-readable medium. The non-transitory computer-readable medium includes stored instructions. These instructions, when executed by one or more processors, cause the one or more processors to: obtain an original control binary sequence generated during simulation of a design under test (DUT); start an index range with an upper index and a lower index; and iterate until (A) an index set is determined so that re-simulating the DUT based on the simplified control binary sequence triggers a specified message, or (B) a termination condition is reached: determine the lowest upper index in the index range and the highest lower index in the index range, collect the lowest upper index and the highest lower index in the index set, and set the upper index to be one less than the lowest upper index, and set the lower index to be one greater than the highest lower index. The simulation DUT is based on stimulus values ​​generated using a constrained random stimulus generator and a coverage biaser that biases the constrained random stimulus generator. The simulation DUT generates an original control binary sequence. The original control binary sequence includes a first enable bit, which corresponds to a corresponding constraint problem solved by the constrained random stimulus generator, and triggers a specified message according to the first enable bit during simulation of the DUT. The simplified control binary sequence has a second enable bit, and each of the second enable bits corresponds to a corresponding enable bit in the first enable bits at a corresponding index in the index set. In an iteration, the specified message is triggered by a re-simulation of the DUT based on the first control binary sequence. The first control binary sequence has a third enable bit, and each of the third enable bits corresponds to a corresponding enable bit in the first enable bits at a corresponding index in the index set, or at a corresponding index in a range from a highest lower index to a lowest upper index. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of the embodiments of the present disclosure. The accompanying drawings are used to provide knowledge and understanding of the embodiments of the present disclosure, and do not limit the scope of the present disclosure to these specific embodiments. In addition, the drawings are not necessarily drawn to scale.

[0007] Figure 1 A functional verification environment implemented on a computer system according to some examples is illustrated.

[0008] Figure 2 Based on some examples used to implement Figure 1 Pseudocode for the usage model of the constraint debugger.

[0009] Figure 3 A method for determining a trigger control binary sequence according to some examples.

[0010] Figure 4A , Figure 4B and Figure 4C A method for determining a trigger control binary sequence according to some examples.

[0011] Figure 5A , Figure 5B and Figure 5C is pseudo code for determining a trigger control binary sequence according to some examples.

[0012] Figure 6 is a method of locating one or more constraints that may trigger a specified message according to some examples.

[0013] Figure 7 Depicted are flow diagrams of various processes used during the design and fabrication of integrated circuits, according to some examples.

[0014] Figure 8 Depicted is a diagram of an example computer system in which some examples may operate. DETAILED DESCRIPTION

[0015] Various aspects of the present disclosure relate to bias cause reduction for positioning constraints. During the design process of a circuit or system, functional verification of a design under test (DUT) can be performed to test whether the DUT operates as expected. In this functional verification, stimulation can be used as input to the DUT during the simulation of the operation of the DUT so that a user can observe the functionality of the DUT generated by the stimulation. Generally, comprehensive functional verification can include simulating the operation of the DUT using a large number of stimulation sets, wherein the stimulation sets are diverse to cover many possible usage scenarios. A random number generator can be used to generate a set of random values ​​for the stimulation set; however, the stimulation set to be input into the DUT during the simulation must satisfy some constraints. A constraint solver can use random values ​​to solve the constraint problem and generate a stimulation set to be input into the DUT during the simulation. The constraints may include errors, or although not errors, may lead to rare or unwanted results, which may be due to incorrect constraint definitions by the user. During the simulation of the DUT, the constraints may trigger error messages or some other messages that may be of interest to the user. Because the traces captured during simulation contain a large amount of data (e.g., stimulus values ​​for simulation cycles, where the number of stimulus values ​​and / or simulation cycles can each be large), identifying the root cause of an error message or other message can be a time-consuming task. Currently, identifying the root cause is a manual process. It may take days for an experienced test engineer to identify the constraint that caused the error message or other message when reviewing the trace data. The manual process may require multiple iterations of replaying the simulation of the DUT to change one or more of the stimulus values ​​to identify the root cause. However, the speed of technological development is driving the desire to reduce the time used for these tests and any resulting debugging or redesign.

[0016] As described in more detail below, the constraint solver may also be biased by a coverage biaser to generate stimulus value sets that expose more of the stimulus space available for simulation. Such biasing may expose rarer situations that may result in triggering even more error messages or other messages. Such biasing may create more trace data than an experienced engineer can manually review to identify root causes.

[0017] According to some examples described herein, a trigger control binary sequence is determined, which has an enable bit, which is a true subset of the enable bit of the original control binary sequence. During the original simulation, the constraint solver of the constrained random stimulus generator solves the constraint problem to generate a stimulus value for simulating the DUT. The constraint solver obtains a random value from the random number generator of the constrained random stimulus generator for solving the constraint problem, and is biased by the coverage biaser when solving the constraint problem. The original control binary sequence can have an enable bit and a disable bit. The original control binary sequence has an enable (disable) bit, which corresponds to the bias (not biased) of the coverage biaser of the corresponding constraint problem to the constraint solver, and the corresponding constraint problem causes the triggering of a specified message during the original simulation. Therefore, the original control binary sequence is determined during the original simulation of the DUT, and the original simulation of the DUT triggers a specified message, which may be an error message or some other message of interest.

[0018] A simplified control binary sequence with an enable bit corresponding to a subset of the enable bits of the original control binary sequence is constructed. The simplified control binary sequence can be iteratively reconstructed until the simplified control binary sequence has a reduced (e.g., minimum) number of enable bits sufficient to trigger a specified message generated by simulating the DUT using the simplified control binary sequence to selectively enable the recovery of the solution step of the constraint random stimulus generator for each constraint problem corresponding to the enable bit of the simplified control binary sequence, and disable the recovery of the solution step for each constraint problem corresponding to the disable bit of the simplified control binary sequence. In some examples, the recovery of the solution step of the constraint random stimulus generator for a given constraint problem includes: enabling an override biaser to bias the constraint solver, and recovering the state of the random number generator for the corresponding constraint problem (e.g., RNG state), which is the state of the random number generator when the corresponding constraint problem was solved in the original simulation. The disabling solution step may include disabling the override biaser, disabling the recovery state of the random number generator, or both. The trigger control binary sequence can then be set equal to a simplified control binary sequence, which is a reduced (e.g., minimum) number of enable bits sufficient to trigger a specified message generated by simulating the DUT using the trigger control binary sequence to selectively enable and disable the recovery solution step.

[0019] Using the original control binary sequence, a first trace of the simulation of the DUT that triggers the specified message is obtained, and a second trace of the simulation of the DUT without the specified message is obtained. The first trace can be obtained from the original simulation. The second trace can be obtained by disabling the solution step of the corresponding constraint problem corresponding to the enable bit in the trigger control binary sequence. Any difference in the stimulus value in the first trace and the second trace for the corresponding simulation cycle can indicate which (which) constraints triggered the specified message. Any different constraints that affect the stimulus value may be the root cause of triggering the specified message.

[0020] In some examples, the state of the random number generator before solving the corresponding constraint problem is stored in a storage device (such as a database) during the original simulation. For any rerun simulation, the random number generator can restore its state to the state stored before solving the corresponding constraint problem. Restoring this state can allow the determination of generating stimulus values ​​between the original simulation and the rerun simulation, which can lead to equal stimulus values ​​when all other conditions (e.g., including whether the coverage biaser is enabled) are equal. In some examples, during the rerun of the simulation, the state of the random number generator is restored for each constraint problem that the constraint solver is solving. In such examples, a simplified (or triggered) control binary sequence can be used to selectively enable or disable the bias of the coverage biaser to the constraint solver. In some examples, the state of the random number generator is enabled based on a simplified (or triggered) control binary sequence for the constraint problem that the constraint solver is required to solve during the rerun of the simulation. In such an example, the constraint solver can be biased by the coverage biaser for each constraint problem to be solved during the rerun of the simulation.

[0021] In some examples, simulation results (e.g., including any trigger messages) of simulating a DUT (e.g., rerunning a simulation of the DUT) based on a simplified control binary sequence are stored in a storage device (such as a database). The simulation results are stored together with the simplified control binary sequence or an indication thereof. If the simulation results are used for any subsequent processing, the simulation results can be retrieved from the storage device instead of redundantly rerunning the simulation of the DUT based on the same simplified control binary sequence. This can avoid repeated and redundant processing.

[0022] In some examples, a binary search method is implemented to identify the enable bit of the simplified control binary sequence. In other examples, other search methods can be implemented, such as a linear search method, a brute force method, etc.

[0023] The technical advantages of the present disclosure include, but are not limited to, an efficient automated computer system that reduces the enable bits of a control binary sequence so that the stimulus value that triggers a specified message and the constraints thereby can be located. By locating the stimulus value and the constraints, it can be helpful to identify the constraints that trigger the specified message. The number of simulation runs required to identify and locate the constraints that trigger the message can be significantly reduced, with each simulation run being based on a calculated simplified binary sequence. Reducing the number of simulation runs can reduce the amount of computing resources required to identify the constraints, and can free up computing resources for other tasks or jobs. This computer system can be easily scaled to analyze large control binary sequences. The functionality of this computer system can extend beyond faults to other behaviors to achieve various debugging insights. In addition, the engineering time required to identify constraints can be greatly reduced. Implementing the techniques described herein may be relatively easy to use because these techniques can be implemented seamlessly and may not require additional input or infrastructure. These and other benefits and advantages can be achieved through the various examples described herein.

[0024] Figure 1 A functional verification environment 100 implemented on a computer system 102 according to some examples is illustrated. The functional verification environment 100 includes a debugging tool 112 executable on the computer system 102. The debugging tool 112 includes a simulator 122, a problem generator 124, a random number generator 126, a constraint solver 128, a coverage biaser 130, a simulation monitor 132, and a constraint debugger 134. The debugging tool 112 is implemented as instructions stored on a non-transitory computer readable medium that are executable by one or more processors of the computer system 102. Although Figure 1 One computer system 102 is illustrated in FIG. 1 , but debugging tool 112 may be distributed across multiple computer systems.

[0025] Similarly, each of the simulator 122, the problem generator 124, the random number generator 126, the constraint solver 128, the coverage biaser 130, the simulation monitor 132, and the constraint debugger 134 can be implemented as instructions stored on a non-transitory computer-readable medium that can be executed by one or more processors of the computer system 102. Each of the simulator 122, the problem generator 124, the random number generator 126, the constraint solver 128, the coverage biaser 130, the simulation monitor 132, and the constraint debugger 134 can be a subset of the instructions (e.g., instruction modules) of the debugging tool 112. The simulator 122, the problem generator 124, the random number generator 126, the constraint solver 128, the coverage biaser 130, the simulation monitor 132, and the constraint debugger 134 can be stored on the same computer system 102 (e.g., instruction modules). Figure 1The instructions implementing the debugging tool 112, which includes the simulator 122, the problem generator 124, the random number generator 126, the constraint solver 128, the coverage biaser 130, the simulation monitor 132, and the constraint debugger 134, when executed by one or more processors, perform the corresponding functionality described herein.

[0026] The simulator 122 simulates the operation of a design under test (DUT). A DUT is a circuit design being designed and tested for the purpose of manufacturing the circuit represented by the circuit design. The simulator 122 receives a DUT file 152, which includes an electronic (e.g., digital) representation of the DUT. The DUT file 152 may include a hardware description language (HDL) description (such as Verilog, etc.), a register transfer level (RTL) description, a gate level description, a layout level description, etc. of the DUT. The simulator 122 uses stimulus values ​​of signals output from the constraint solver 128 to simulate the operation of the DUT of the DUT file 152.

[0027] The problem generator 124 generates a constraint problem to be solved. The problem generator 124 receives a constraint file 154. The constraint file 154 includes declarative statements of constraints for various signals, for which stimulus values ​​for simulation will be generated. For example, any constraint can limit the upper and / or lower bounds of a given signal, require logical relationships between multiple signals, etc. The constraint can be or include a dynamic constraint based on the state of the DUT during simulation. The problem generator 124 can also observe the state of the DUT during simulation by the simulator 122. The problem generator 124 can dynamically expand the constraints based on the state of the DUT during simulation. If any such constraints are included in the constraint file 154, the problem generator 124 converts the constraints into a form readable by the constraint solver 128 and dynamically expands the constraints to generate a constraint problem. The problem generator 124 outputs the constraint problem to the constraint solver 128.

[0028] The random number generator 126 generates random values, which the constraint solver 128 can use as seed values. The random values ​​are output from the random number generator 126 to the constraint solver 128. The constraint solver 128 can query the random number generator 126 to generate and output random values. The random number generator 126 may appear to be non-deterministic and randomized. However, if the state of the random number generator 126 is known at the time of the query, the generated random value can be deterministic based on the state. As described later, the state of the random number generator 126 at the time of the query can be stored, and when the simulation is to be rerun, the state can be restored to the random number generator 126. Therefore, when the state has been restored, the random numbers generated by the random number generator 126 can be deterministically reproduced during the rerun of the simulation. As described later, during the rerun of the simulation, the state of the random number generator 126 can be selectively enabled or disabled for a given constraint problem.

[0029] The constraint solver 128 receives the constraint problem and the random value. Based on the received constraint problem and the random value, the constraint solver 128 generates a stimulus value of the signal within the constraint of the constraint file 154. The constraint solver 128 can solve the constraint problem based on the command in the user test bench. The constraint solver 128 can solve one or more constraint problems during the simulation cycle, or may not solve the constraint problem during the simulation cycle. The constraint solver 128 can be or include a constraint satisfiability solver. The generated stimulus value is applied to the corresponding driver to simulate the operation of the DUT through the simulator 122.

[0030] Although the problem generator 124, the random number generator 126, and the constraint solver 128 are illustrated and described as separate components, they may be collectively referred to as a constrained random stimulus generator 136. The constrained random stimulus generator 136 may perform the above-described functionality or similar functionality of the problem generator 124, the random number generator 126, and the constraint solver 128. In other examples, the constrained random stimulus generator may be implemented in different ways.

[0031] The coverage biaser 130 operates with the constraint solver 128 to bias a process (e.g., a constraint satisfiability solver process) implemented by the constraint solver 128 to force one or more values. The coverage biaser 130 may implement a machine learning process to identify coverage within a mathematical space available for stimulus values, and bias the process implemented by the constraint solver 128 to force values ​​to diversify the stimulus values ​​generated. Biasing the constraint solver 128 by the coverage biaser 130 may cause the constraint solver 128 to expose more of the mathematical space available for stimulus values, which may result in an increased chance of exposing errors, rare behaviors, or other conditions of interest during simulation. In some examples, the coverage biaser 130 implementing the machine learning process may be trained based on multiple simulations (e.g., different simulations) so that when the coverage biaser 130 determines, for example, that the constraint solver 128 can converge on a possible set of repeated stimulus values, the coverage biaser 130 may bias the process implemented by the constraint solver 128. During the original simulation, biasing by the coverage biaser 130 may be enabled for each constraint problem, and during a rerun of the simulation, biasing by the coverage biaser 130 may be selectively enabled or disabled.

[0032] The simulation monitor 132 observes the state of the random number generator 126, the generated stimulus value output by the constraint solver 128 (e.g., as an input to the simulator 122), and the state of the DUT during the simulation by the simulator 122. The simulation monitor 132 creates an operation record of the debugging tool 112 and writes it to the debugging database 142. The record may include a trace of the simulation, the state of the random number generator 126 for the corresponding constraint problem, and a control binary sequence determined for the constraint problem. The trace may include stimulus values ​​for the corresponding simulation cycle and any message generated by the simulation monitor 132 based on observing the simulation. The simulation monitor 132 is configured to observe the state of the DUT during the simulation, and create a message when the state of the DUT and / or the simulation is in some conditions of interest. Such a message may be created when a fatal error message (e.g., UVM_FATAL message), a non-fatal error message (e.g., UVM_ERROR message or SystemVerilog assertion (SVA) fault message), or any rare condition (e.g., line, branch, cover box, design state, etc.) or a condition of interest to the user occurs. In some examples, the message may be any regular expression defined and specified by a user, such as part of a test bench.

[0033] According to some examples, during the original simulation of the DUT, an original control binary sequence is created and stored. The original control binary sequence includes bits corresponding to the corresponding constraint problems. The original control binary sequence includes an enable bit, which corresponds to the corresponding constraint problem biased by the coverage biaser 130, and triggers a specified message according to the enable bit during the original simulation. The original control binary sequence is created during the original simulation by determining an enable bit or a disable bit for each constraint problem solved by the constraint solver 128 and biased by the coverage biaser 130 during the original simulation. Whether a given bit of the original control binary sequence is an enable bit or a disable bit is determined by whether the coverage biaser 130 biases the constraint solver 128 during solving the corresponding problem. In some examples, a logic "0" in the control binary sequence can indicate a disable bit for the corresponding constraint problem solved by the coverage biaser 130 without bias, and a logic "1" can indicate an enable bit for the corresponding constraint problem solved by the coverage biaser 130 with bias. Simulation monitor 132 and / or constraint debugger 134 may create an original control binary sequence during the original simulation and may store the original control binary sequence in a storage device such as debug database 142 .

[0034] The constraint debugger 134 typically determines a trigger control binary sequence. The trigger control binary sequence has enable bits that are a subset (e.g., a true subset) of the enable bits of the original control binary sequence. The trigger control binary sequence has enable bits that are a reduced (e.g., minimal) number of enable bits relative to the original control binary sequence and are sufficient to trigger a specified message when a simulation of the DUT is rerun using the trigger control binary sequence.

[0035] Typically, in some examples, the constraint debugger 134 accesses the original control binary sequence determined and stored during the original simulation, and iteratively builds the simplified control binary sequence until the simplified control binary sequence has a reduced (e.g., minimum) number of enable bits sufficient to trigger a specified message generated by simulating the DUT using the simplified control binary sequence. The trigger control binary sequence can then be set equal to the simplified control binary sequence.

[0036] In a rerun of the simulation, a simplified or triggered control binary sequence may be used to selectively enable or disable the recovery of the solution steps of the constraint random stimulus generator 136 for the corresponding constraint problem, which were performed during the original simulation of the DUT. Selectively enabling / disabling the recovery solution steps may affect the bias used to solve the corresponding constraint problem. Selectively enabling / disabling the recovery solution steps may include selectively enabling / disabling the bias of the overlay biaser 130 to the constraint solver 128, restoring the state of the random number generator 126, or both. In some examples, based on whether the corresponding bit of the simplified or triggered control binary sequence is an enable bit or a disable bit, the bias performed by the overlay biaser 130 is selectively enabled or disabled for a given constraint problem. In some examples, when querying the seed value for the constraint problem, the bias may be affected by the state of the random number generator 126, and in such an example, whether to restore the state of the random number generator 126 for a given constraint problem is based on whether the corresponding bit of the simplified or triggered control binary sequence is an enable bit or a disable bit. Other methods of determining the trigger control binary sequence may be implemented.

[0037] The constraint problem with the corresponding enable bit in the trigger control binary sequence indicates a reduced portion of the trace, which locates the cause of triggering the specified message during the simulation. For example, in order to obtain the first trace, the constraint debugger 134 can access the trace from the original simulation and / or use the original control binary sequence to make the simulator 122 rerun the simulation of the DUT. In addition, in order to obtain the second trace, the constraint debugger 134 can use the non-trigger control binary sequence to make the simulator 122 rerun the simulation of the DUT. The non-trigger control binary sequence has a disable bit corresponding to the enable bit of the trigger control binary sequence. Using the non-trigger control binary sequence, the constraint solver 128 generates stimulus values ​​for the constraint problem corresponding to the disable bit of the non-trigger control binary sequence without being biased by the coverage biaser 130 and / or without restoring the state of the random number generator 126. The constraint debugger 134 can compare the first trace and the second trace, and identify which stimulus values ​​in the corresponding simulation cycle are different. Different stimulus values ​​indicate which (which) constraints may cause the specified message. Any constraints that affect the identified stimulus values ​​may be the cause and may be identified by constraint debugger 134. With the stimulus values, and thus the constraints, identified, a user may more easily identify issues with randomized constraints that cause a specified message to be triggered.

[0038] To rerun the simulation, constraint debugger 134 accesses the records in debug database 142. Constraint debugger 134 reads the constructed control binary sequence (e.g., simplified control binary sequence and / or trigger control binary sequence) from debug database 142. According to implementations in some examples, constraint debugger 134 may then cause coverage biaser 130 to be selectively enabled or disabled for constraint issues and / or enable or disable recovery of the state of random number generator 126 for constraint issues.

[0039] In an example where the biasing performed by the overlay biaser 130 is enabled or disabled, when the constraint solver 128 is required to solve a constraint problem, the constraint debugger 134 reads the stored state of the random number generator 126 and causes the random number generator 126 to be restored to the read state. The stored state of the random number generator 126 was stored at the beginning of the corresponding constraint problem during the original simulation. When the state of the random number generator 126 is restored and the overlay biaser 130 implements a given control binary sequence for enabling / disabling the biasing of the constraint solver 128, the constraint solver 128 outputs the generated stimulus values ​​(generated in operation using the random number generator 126, the problem generator 124, and the overlay biaser 130) to the simulator 122, and the simulator 122 uses the generated stimulus values ​​to simulate the operation of the DUT.

[0040] In an example of enabling or disabling the restoration of the state of the random number generator 126, when the constraint solver 128 is required to solve a constraint problem, the constraint debugger 134 determines whether to restore the state of the random number generator for the given constraint problem based on a given control binary sequence. When the corresponding bit of the control binary sequence is an enable bit, the constraint debugger 134 reads the stored state of the random number generator 126 and causes the random number generator 126 to be restored to the read state. When the corresponding bit of the control binary sequence is a disable bit, the constraint debugger 134 does not restore the state of the random number generator 126. Based on the random value output by the random number generator 126 (e.g., the restoration state or the non-restoration state), the constraint solver 128 outputs the generated stimulus value (generated in operation using the random number generator 126, the problem generator 124, and the coverage biaser 130 of the bias constraint solver 128) to the simulator 122, and the simulator 122 uses the generated stimulus value to simulate the operation of the DUT.

[0041] The simulation monitor 132 will send any message <msg>The constraint debugger 134 may write any simplified control binary sequence that triggers the specified message to the debug database 142. The simulation monitor 132 and / or the constraint debugger 134 may write the simulation results (including any messages triggered by rerunning the simulation) to the debug database 142. The simulation results may be written in a manner corresponding to a given control binary sequence that is used to rerun the simulation. Subsequently, the constraint debugger 134 may read the simulation results written to the debug database 142 based on the given control binary sequence, thereby avoiding rerunning the simulation based on the given control binary sequence.

[0042] Although control binary sequences including enable bits and disable bits are described herein, the control binary sequence may be any abstraction that tracks which constraint problems lead to triggering a specified message. For example, the control binary sequence may not be an actual bit corresponding to a corresponding constraint problem, but rather an index or set of numbers corresponding to or identifying the corresponding constraint problem that leads to triggering a specified message. The control binary sequence may take many forms.

[0043] Figure 2 Pseudo code for implementing a usage model of the constraint debugger 134 according to some examples is illustrated. At line 201, an environment including source files is compiled, which generates an executable binary file. At line 202, the binary file is executed to simulate the DUT. By "<enable_cb> ", the coverage biaser 130 is enabled to operate in simulation. The coverage biaser 130 creates the original control binary sequence during simulation. After compilation and simulation, the constraint debugger 134 is executed by executing lines 203 to 207. The execution of the constraint debugger 134 includes a loop at lines 203 to 207, which reruns the simulation at line 204. In the rerun of the simulation, by "<enable_cb_rerun> " enables the overlay biaser 130. The loop includes a user runtime switch for constraining debugging. The user runtime switch at line 205 indicates the record to be debugged, which is Figure 2 In the diagram, it is "+ntb_solver_bias_debug_record= <dbg>”. When another user runs at line 206, the switch indicates the type of specified message identified for debugging, which is Figure 2 In the diagram, it is "+ntb_solver_bias_debug_regex= <desmsg>At line 207, a condition for terminating the loop is indicated, which in this example is that the status flag of the record is equal to "DONE" (eg, <dbg> / dbg.status=DONE) or the resource threshold has been met.

[0044] Figure 3 A method 300 for determining a trigger control binary sequence according to some examples is illustrated. Constraint debugger 134 implements the operations of method 300 and / or causes the operations of method 300 to be implemented in some examples.

[0045] At 302, a control binary sequence (ta) that actually triggers the specified message is read, such as from a database. For convenience, the control binary sequence (ta) that actually triggers the specified message is referred to as the "actual control binary sequence (ta)" hereinafter. At 302, the actual control binary sequence (ta) may be the original control binary sequence generated during the original simulation, as described above.

[0046] At 304, it is determined whether an end condition has been reached. The end condition can be or include any of a plurality of conditions and any logical combination of a plurality of conditions. For example, the end condition can include whether the status flag of the record indicates that the method 300 has been completed (e.g., is set to "DONE", such as Figure 2 ). The end condition may be whether the method 300 has run for a specified time or whether a specified amount of resources has been used. The end condition may also be or include a logical OR and / or a logical AND of different conditions. Different methods for determining a trigger control binary sequence according to other examples may implement different conditions.

[0047] At 306, a control binary sequence (tp) that may potentially trigger a specified message is constructed based on the actual control binary sequence (ta). For convenience, the control binary sequence (tp) that may potentially trigger a specified message is referred to as a "potential control binary sequence (tp)" hereinafter. In this example, the enable bit in the potential control binary sequence (tp) is a subset (e.g., a true subset) of the enable bit in the actual control binary sequence (ta). All other bits in the potential control binary sequence (tp) are disable bits. The potential control binary sequence (tp) is a simplified control binary sequence. Method 300 can implement any of a variety of methods at 306 to determine which bits of the potential control binary sequence (tp) are enabled and which bits of the potential control binary sequence (tp) are disabled when constructing the potential control binary sequence (tp). Such methods include binary search methods, linear search methods, and brute force (e.g., all possible combinations) methods. The example binary search method is described in detail later.

[0048] At 308, simulation results based on potential control binary sequences (tp) are obtained. In some examples, simulation based on potential control binary sequences (tp) may have occurred previously in previous iterations. In this case, the simulation results can be stored (e.g., cached) in a database such as (e.g., debug database 142). If the simulation results are stored, the simulation results are read at 308. This can avoid repeating the previous simulation, thereby reducing processing time and reducing resource usage. If the simulation results are not stored (e.g., when method 300 does not store such results, or if the simulation based on potential control binary sequences (tp) did not occur previously), the simulation results can be obtained by rerunning the simulation of the DUT using the potential control binary sequence (tp), so as to selectively restore the solution steps of the constrained random stimulus generator 136 for the corresponding constraint problem for each constraint problem, which are performed during the original simulation of the DUT. Selectively restoring the solution step can include enabling / disabling the state of the overlay biaser 130 and / or enabling / disabling the recovery random number generator 126. As previously noted, when the potential control binary sequence (tp) enables / disables the overlay biaser 130, the state of the random number generator 126 from the original simulation is read, such as from the debug database 142, and the random number generator 126 is restored to the read state for subsequent simulation during 308. When the potential control binary sequence (tp) enables / disables the state of the random number generator 126, the overlay biaser 130 is enabled during simulation. As previously described, the simulation monitor 132 can create records and can monitor what messages (if any) are triggered during simulation. Any messages observed by the simulation monitor 132 will be transmitted from the simulation monitor 132 to the constraint debugger 134.

[0049] At 310, it is determined whether the specified message is in the obtained simulation results. The specified message may be specified, for example, in the user test bench, hard-coded in the constraint debugger 134, or by another mechanism. If it is determined that the specified message is not included in the obtained simulation results, the method 300 loops back to 304. If it is determined that the specified message is included in the obtained simulation results, at 312, the actual control binary sequence (ta) is set equal to the potential control binary sequence (tp). After the actual control binary sequence (ta) is set equal to the potential control binary sequence (tp), the actual control binary sequence (ta) can be written to, for example, the debugging database 142. Then, the method 300 loops back to 304.

[0050] If it is determined at 304 that the end condition has been reached, then at 314 the actual control binary sequence (ta) is written (e.g., if not previously written). At 314, the actual control binary sequence (ta) is the trigger control binary sequence. It is noteworthy that, as an example, the determination at 304 is shown as being located in the flow of the loop. Such a determination may be located elsewhere in the logic flow of the loop, such as depending on the end condition.

[0051] In a subsequent iteration, at 306, an attempt is made to construct the potential control binary sequence (tp) as a subset of the enable bits of the actual control binary sequence (ta) that is a different subset of the enable bit subset of the potential control binary sequence (tp) of the immediately preceding iteration. As noted above, subsequent iterations may construct the same potential control binary sequence (tp) as constructed in some previous iterations. In some examples, if the potential control binary sequence (tp) cannot be constructed at 306, a status flag may be set to indicate that the method 300 should be completed, which may cause the method 300 to be completed at 304 as an end condition.

[0052] In some examples, the conditions and results of each rerun of the simulation occurring at 308 (e.g., for an iteration of the method 300) may be made available to the user on a video display unit (e.g., via a graphical user interface (GUI)) by the constraint debugger 134. The GUI generated by the constraint debugger 134 may display selectable line items for each rerun of the simulation. User selection of a line item (e.g., via a cursor control device, such as a mouse) may display, via the GUI, trace information for the corresponding rerun of the simulation, the potential control binary sequence (tp) used in the corresponding rerun, and / or the state of the random number generator 126. Thus, in such an example, the rerun of the simulation at 308 includes storing the trace, the potential control binary sequence (tp), and the state of the random number generator 126 (such as in the debug database 142). The user may be allowed to modify any stimulus values ​​of the trace, the potential control binary sequence (tp), and / or the state of the random number generator 126, and rerun the simulation of the DUT using the modified data.

[0053] Figure 4A , Figure 4B , Figure 4C , Figure 5A , Figure 5B ,and Figure 5C Illustrated are methods 400A, 400B, 400C (collectively, method 400 ) and pseudocode for determining a trigger control binary sequence according to some examples. FIG. 5A to FIG. 5C Shows the implementation FIG. 4A to FIG. 4C Example pseudo code of method 400. FIG. 4A to FIG. 4C Method 400 and FIG. 5A to FIG. 5C The pseudocode of implements a binary search method (eg, called the binary search simplification (bsr) method) according to some examples. FIG. 4A to FIG. 4C Method 400 and FIG. 5A to FIG. 5C The pseudo code may be implemented by the constraint debugger 134 .

[0054] Method 400 may rely on a monotonic property to identify a reduced (e.g., minimal) subset of enable bits for triggering a control binary sequence. For the monotonic property, assume that if a true subset of the enable bits of a control binary sequence Y causes a specified message to be triggered, then a superset of the enable bits of a control binary sequence X also causes a specified message to be triggered, where Conversely, if a superset of the enable bits of the control binary sequence X does not cause the specified message to be triggered, then a proper subset of the enable bits of the control binary sequence Y does not cause the specified message to be triggered either. The monotonic property may lead to the observation that adding enable bits to the control binary sequence does not prevent the triggering of the specified message, and some enable bits in the control binary sequence may not be necessary to trigger the specified message. Therefore, the enable bits that are not necessary to trigger the specified message can be disabled so that the specified message is triggered by the remaining enable bits. If a scenario occurs where this monotonic property does not hold, a simplified control binary sequence can still be determined; however, the simplified control binary sequence may not have the minimum set of enable bits.

[0055] Typically, method 400 identifies an index of an enable bit of an original control binary sequence that is sufficient to trigger a specified message from a simulation of a DUT, the simulation of which uses the enable bit identified by the index. Method 400 conceptually searches within an iterative range. Within the search range, a corresponding lowest upper index and a corresponding highest lower index are determined. (Multiple) lowest upper indexes and (multiple) highest lower indexes indicate enable bits of the original control binary sequence within the search range that are sufficient to trigger a specified message from the simulation of the DUT. Iteratively, a continuous range within the lowest upper index and the highest lower index in the previous iteration is searched until no other ranges are available for search. It is noteworthy that the lowest upper index of a range may be equal to the highest lower index of the range. (Multiple) lowest upper indexes and (multiple) highest lower indexes are collected in a set.

[0056] As illustrated, method 400 starts a range of indices spanning the original control binary sequence (e.g., indicated by the lower index (j) starting at zero and the upper index (k) starting at N-1), and starts the index set (psi) empty. Method 400 searches for the lowest upper index in the range and searches for the highest lower index in the range. The identified lowest upper index and highest lower index satisfy three conditions:

[0057] (1) The specified message is triggered by a simulation of the DUT using a simplified control binary sequence having an enable bit corresponding to an enable bit of the original control binary sequence at a corresponding index in the index set, or at a corresponding index from the highest lower index to the lowest upper index;

[0058] (2) specifying that the message is not triggered by simulation of the DUT using a simplified control binary sequence having an enable bit corresponding to an enable bit of the original control binary sequence at a corresponding index in the index set, or at a corresponding index from the highest lower index plus one to the lowest upper index; and

[0059] (3) The specified message is not triggered by simulation of the DUT using a simplified control binary sequence having an enable bit corresponding to the enable bit of the original control binary sequence at the corresponding index in the index set, or at the corresponding index from the highest lower index to the lowest upper index minus one.

[0060] Then, method 400 collects the highest lower index and the lowest upper index in the index set, and sets the range to be from the highest lower index plus one to the lowest upper index minus one. Then, method 400 iterates back to search for the lowest upper index in the range, and searches for the highest lower index in the range.

[0061] The iteration of method 400 continues until the specified message is triggered by the simulation of the DUT using a simplified control binary sequence, wherein the simplified control binary sequence has an enable bit corresponding to the enable bit of the original control binary sequence at the corresponding index in the index set. When no other range is available for searching (for example, when the highest lower index and the lowest upper index collected in the index set in an iteration are within a range), or when the range to be searched in the iteration does not include any enable bits that trigger the specified message, this condition may occur. Method 400 illustrates how to implement this condition. When this condition is reached, the status flag in the record can be set to "DONE (completed)", which can trigger the completion of the iteration of method 400, although not shown. When (multiple) iterations are completed, the simplified control binary sequence is the trigger control binary sequence. Additional conditions for completion may be included, such as when a threshold value of runtime or resources used is met or exceeded.

[0062] refer to Figure 4A At 402, the actual control binary sequence (ta) is read. The actual control binary sequence (ta) has N bits. The actual control binary sequence (ta) is Figure 5A The actual control binary sequence (ta) at 402 and row 502 is the original control binary sequence.

[0063] At 404, the lower index variable (j) is set equal to zero; the upper index variable (k) is set equal to N-1; and the index variable set (psi) is defined as empty. The variables j, k, and psi are respectively Figure 5A The variables j and k indicate the range to be searched.

[0064] At 406, it is determined whether psi is not null. If psi is null, the method 400 proceeds to Figure 4B 432 in. If it is determined that psi is not empty, then at 408, a potential control binary sequence (tp) is constructed based on the actual control binary sequence (ta) and psi. Any potential control binary sequence (tp) described in method 400 is a simplified control binary sequence. At 410, a simulation result based on the potential control binary sequence (tp) constructed at 408 is obtained. At 412, it is determined whether a specified message is included in the simulation result obtained at 410. If the specified message is included, then at 414, the actual control binary sequence (ta) is set equal to the potential control binary sequence (tp), and the actual control binary sequence (ta) is written at 416. The actual control binary sequence (ta) at 416 is a trigger control binary sequence. Method 400 is completed when 416 is executed.

[0065] The conditional statement at 406 is Figure 5A 408. Line 509 implements the operation of 408. At line 509, a potential control binary sequence (tp) is constructed by calling constructTp() based on each index contained in psi and without other indexes (for example, without any enable bit in the range from j to k). The function call rerunSim() at line 510 implements the operation of 410. The function call rerunSim() enables the simulation results of the simulation using the potential control binary sequence (tp) to be obtained, which may include rerunning the simulation based on the potential control binary sequence (tp). The if conditional statement at line 510 implements the conditional statement at 412. The conditional if statement at line 510 determines whether the function call rerunSim() returns a specified message. <desmsg>Lines 511, 512, and 520 implement the operations of 414 and 416.

[0066] Usually, reference Figure 4A and Figure 5A , the determination at line 406 and the corresponding conditional if statement at line 508 determine whether psi includes any index. In the initial iteration of the loop (e.g., the while loop starting at line 507 and ending at line 519), psi is empty, and the operations at 408, 410, 412, 414 and at lines 509 to 512 are omitted.

[0067] When reaching 414 and line 511, method 400 determines that the range of the original control binary sequence to be searched in the iteration does not include any enable bit that triggers the specified message. If psi includes any index (e.g., is not empty), it is determined whether the range of the actual control binary sequence (ta) from j to k includes any index of the enable bit that causes the specified message to be triggered. A potential control binary sequence (tp) is constructed based on psi without considering j and k, and simulation results are obtained based on the potential control binary sequence (tp). Therefore, if the specified message is obtained or returned, the potential control binary sequence (tp) has an enable bit sufficient to trigger the specified message at the index contained in psi, and a bit in the range from j to k is not required to trigger the specified message. Therefore, method 400 has identified the enable bit as being in the trigger control binary sequence (e.g., by the (multiple) indexes collected in psi) and is about to be completed.

[0068] refer to Figure 5B , provides the definition of the function call constructTp() in pseudocode form as an example. As indicated, the function call constructTp() Figure 5A , and is called elsewhere. At line 531, the function call constructTp() passes psi, a lower range index (range_lower), and an upper range index (range_upper) as input parameters. When no range is included when constructing the potential control binary sequence (tp), the parameters range_lower and range_upper can be null values, as shown at line 509. At line 535, the potential control binary sequence (tp) is started to zero for N bits (e.g., with indexes from 0 to N-1). At line 536, for each index contained in psi, the bits of the potential control binary sequence (tp) at the index contained in psi are set equal to the bits of the actual control binary sequence (ta) at the corresponding index contained in psi. At line 537, a conditional if statement determines whether a null value is passed for one or both of range_lower and range_upper. If yes (e.g., such as when in Figure 5A ), then lines 538 and 539 are omitted (e.g., the potential control binary sequence (tp) is not constructed based on the range). If non-null values ​​are passed for range_lower and range_upper, then at lines 538 and 539, the bits of the potential control binary sequence (tp) at the indexes in the range from range_lower to range_upper are iteratively set equal to the bits of the actual control binary sequence (ta) at the corresponding indexes in the range from range_lower to range_upper. At line 541, the potential control binary sequence (tp) is returned.

[0069] continue Figure 5B , provides the definition of the function call rerunSim() in pseudocode form as an example. As indicated, the function call rerunSim() Figure 5A , and is called elsewhere. At line 544, the function call rerunSim() passes the potential control binary sequence (tp) as an input parameter. At line 545, the conditional if statement checks whether a previous control binary sequence that is the same as the potential control binary sequence (tp) has been previously simulated and has a stored (e.g., cached) simulation result. If so, the cached simulation result is returned at line 546. If not, the state of the random number generator 126 is restored to the stored state at line 547. Restoration of the state of the random number generator 126 includes reading the state from a storage device (such as a debug database 142) and writing the read state to the random number generator 126. At line 548, as indicated by the potential control binary sequence (tp), the DUT is simulated with the overlay bias 130 enabled. At line 549, the simulation result is returned, which can be a specified message <desmsg>.

[0070] The definition of the function call rerunSim() uses a potential control binary sequence (tp) to selectively enable and disable the bias of the constraint solver 128 by the override biaser 130. In such an example, to solve each constraint problem to be solved by the constraint solver 128, the state of the random number generator 126 is restored to the corresponding state of the random number generator 126 when the corresponding constraint problem was solved during the original simulation. In other examples, the definition of the function call rerunSim() can enable the bias of the constraint solver 128 by the override biaser 130 for each constraint problem to be solved by the simulation. In such an example, the function call rerunSim() can use a potential control binary sequence (tp) to selectively enable and disable the restoration of the state of the random number generator 126 to solve the corresponding constraint problem.

[0071] Return to reference Figure 4A If (a) psi is empty as determined at 406 (e.g., "no" branch), or (b) psi is not empty as determined at 406 (e.g., "yes" branch) and the specified message is not included in the obtained simulation results as determined at 412, then method 400 returns to Figure 4A Continue to 418 before Figure 4B and Figure 4C Typically, Figure 4B The operation determines and sets k, and Figure 4C The operation of determines and sets j, as will be described later. Figure 4B Determine and set the lowest upper index of the range to k, so that the specified message is triggered when simulating using a potential control binary sequence (tp) constructed using an index set that is the union of the range and psi. Similarly, 4C identifies and sets the highest lower index of the range to j, so that the specified message is triggered when simulating using a potential control binary sequence (tp) constructed using an index set that is the union of the range and psi. In addition, when constructing a potential control binary sequence (tp) that causes the specified message to be triggered, Figure 4B and Figure 4C Update the actual control binary sequence (ta).

[0072] At 418, psi collects j and k within psi. psi is the union of psi, j, and k. The union is Figure 5A At line 515 of . At 420, it is determined whether j is equal to k or equal to k-1. If so, the actual control binary sequence (ta) is written at 416, as described above. The determination of 420 at line 516, when true, causes the while loop to be interrupted to write the actual control binary sequence (ta) at line 520. Typically, when j is equal to k or k1, the iteration of the loop has identified the same index or adjacent indexes, so that there is no range between j and k for subsequent iterations of the loop to search. Therefore, the loop is exited and the actual control binary sequence (ta) is written.

[0073] When j is neither equal to k nor equal to k-1, at 422, j is incremented by one and k is decremented by one. The operation then loops back to 406. Incrementing j and decrementing k are Figure 5A , and the operation loops back to the beginning of the while loop defined at line 507. Typically, when the operation reaches 422 and lines 517 and 518, the bits of the actual control binary sequence (ta) in the range identified by j and k and at the index in psi are sufficient to trigger the specified message; however, the range j+1 to k-1 has not yet been searched to remove any indexes that may not be required to trigger the specified message. A subsequent iteration of the loop (starting at 406 and line 507) searches the range j+1 to k-1. This iterative method continues until the range j+1 to k-1 (or j to k associated with a subsequent iteration) does not include the bits required to trigger the specified message (as determined by 412 and line 510), or until no ranges remain to be analyzed (as determined by 420 and line 516).

[0074] Go to Figure 4B , determine and set k. Figure 4A At 432 after 406 or 412, the lower range check index variable (lower_check) is set equal to j; the upper range check index variable (upper_check) is set equal to k; and the last check index variable (last_check) is set equal to k. This operation sets the outer boundary of the range to be searched for k (e.g., from j to k). At 434, it is determined whether lower_check is greater than upper_check. If not, then at 436, the next check index variable (next_check) is set to the rounded-down integer of the midpoint between lower_check and upper_check (e.g., roundDown((lower_check+upper_check) / 2)).

[0075] At 438, a potential control binary sequence (tp) is constructed based on the actual control binary sequence (ta), psi, and the range from j to next_check. At 440, a simulation result based on the potential control binary sequence (tp) constructed at 438 is obtained. At 442, it is determined whether a specified message is included in the simulation result obtained at 440. If the specified message is included, at 444, the actual control binary sequence (ta) is set equal to the potential control binary sequence (tp). Then, at 446, upper_check is set equal to next_check-1, and last_check is set equal to next_check. If it is determined at 442 that the specified message is not included, lower_check is set equal to next_check+1 at 448. After 446 and 448, the operation loops back to 434. If it is determined at 434 that lower_check is greater than upper_check, k is set equal to last_check at 450, and the operation continues to Figure 4C Of the 462.

[0076] Figure 4B The operation is performed by Figure 5A Line 513 and Figure 5C The function call bsrUpper() is implemented in Figure 5A At line 513 of , k is set equal to the return value of the function call bsrUpper(), where j and k are passed as various parameters.

[0077] refer to Figure 5C , the definition of the function call bsrUpper() is provided in pseudocode form as an example. At line 561, the function call bsrUpper() passes lower_check, upper_check, and last_check as input parameters. Figure 5A The function bsrUpper() is called at line 513 to set lower_check equal to j, upper_check equal to k, and last_check equal to k, as shown in Figure 4B 432. Return to Figure 5C , line 562 includes a conditional if state that determines whether lower_check is greater than upper_check, which implements Figure 4B 434. At line 563, last_check is returned, where line 513 sets k equal to the return value of the function call bsrUpper(), thus implementing Figure 4B of 450.

[0078] At line 564, next_check is set to implement Figure 4B 436. At line 565, the potential control binary sequence (tp) is constructed by calling the function constructTp(), where the input parameters are psi, j as range_lower, and next_check as range_upper, which implements Figure 4B 438. The functionality of the function call constructTp() is described above in Figure 5B In the function call constructTp() at line 565, Figure 5B The range of the potential control binary sequence (tp) constructed based on the actual control binary sequence (ta) at lines 538 and 539 is from j to next_check.

[0079] Then, at line 566, the function calls rerunSim() so that the simulation results based on the potential control binary sequence (tp) are returned, which implements Figure 4B 440. The functionality of the function call rerunSim() is described above in Figure 5B The conditional if statement at line 566 determines whether the function call rerunSim() returns a specified message <desmsg>, which realizes Figure 4B 442. If the specified message is returned, the potential control binary sequence (tp) includes an enable bit at an index contained in psi and at an index within the range j to next_check, which is sufficient to trigger the specified message. Therefore, if the specified message is returned, then at line 567, the actual control binary sequence (ta) is set equal to the potential control binary sequence (tp), which implements Figure 4B 444. In addition, if the specified message is returned, the function call bsrUpper() is recursively called at line 568, where next_check-1 is passed as upper_check and next_check is passed as last_check. Line 568 implements Figure 4B The functionality of 446 in and the loop from 446 to 434. If the specified message is not returned, the function call bsrUpper() is recursively called at line 570 and next_check+1 is passed as lower_check. Line 570 implements Figure 4B The functionality of 448 and the cycle from 448 to 434.

[0080] generally, Figure 4B and Figure 5C The illustrated binary search method analyzes the range in which the lowest upper index may reside, and searches the range using a binary search until the lowest upper index is identified. The range is the range from lower_check to upper_check, which is initially from j to k. The binary search divides the range into a lower half and an upper half by determining next_check (e.g., which is typically halfway between lower_check and upper_check), and determining whether the lowest upper index exists in a given half. Figure 4B and Figure 5C In the simulation, the lower half is analyzed for the lowest upper index by constructing a potential control binary sequence (tp) based on the range from j to next_check and rerunning the simulation based on the potential control binary sequence (tp). Based on the monotonic property, if the specified message is triggered when the simulation is rerun, the lowest upper index exists in the lower half, and the lower half will be further searched for the lowest upper index. The upper half can be discarded because it is not needed to trigger the specified message. On the contrary, if the specified message is not triggered when the simulation is rerun, the lowest upper index does not exist in the lower half, and the upper half will be searched for the lowest upper index. Each half is searched recursively until the range from lower_check to upper_check includes no more than one index. The result of such a search is:

[0081] (1) a potential control binary sequence (tp) constructed based on psi and a range from j to k+1 (where k is set in 450) triggers a specified message when used in the simulation;

[0082] (2) a potential control binary sequence (tp) constructed based on psi and a range from j to k (where k is set in 450) triggers a specified message when used in a simulation; and

[0083] (3) The potential control binary sequence (tp) constructed based on psi and a range from j to k-1 (where k is set in 450) does not trigger the specified message when used in the simulation.

[0084] Go to Figure 4C , determine and set j. Figure 4B At 462, following 450, lower_check is set equal to j; upper_check is set equal to k; and last_check is set equal to j. This operation sets the outer boundary of the range to be searched for j (e.g., from j to k). At 464, it is determined whether lower_check is greater than upper_check. If not, then at 466, next_check is set to the rounded-down integer of the midpoint between lower_check and upper_check (e.g., roundDown((lower_check+upper_check) / 2)).

[0085] At 468, a potential control binary sequence (tp) is constructed based on the actual control binary sequence (ta), psi, and a range from next_check to k. At 470, a simulation result based on the potential control binary sequence (tp) constructed at 468 is obtained. At 472, it is determined whether a specified message is included in the simulation result obtained at 470. If the specified message is included, at 474, the actual control binary sequence (ta) is set equal to the potential control binary sequence (tp). Then, at 476, lower_check is set equal to next_check+1, and last_check is set equal to next_check. If it is determined at 472 that the specified message is not included, upper_check is set equal to next_check-1 at 478. After 476 and 478, the operation loops back to 464. If it is determined at 464 that lower_check is greater than upper_check, j is set equal to last_check at 470, and the operation continues to Figure 4A 418 of them.

[0086] Figure 4A The operation is performed by Figure 5A Line 514 and Figure 5C The function call bsrLower() is implemented in Figure 5A At line 514 of , j is set equal to the return value of the function call bsrLower(), where j and k are passed as various parameters.

[0087] refer to Figure 5C , provides the definition of the function call bsrLower() in pseudocode form as an example. At line 573, the function call bsrLower() passes lower_check, upper_check, and last_check as input parameters. Figure 5A The function bsrLower() is called at line 514 to set lower_check equal to j, upper_check equal to k, and last_check equal to j, as shown in FIG. Figure 4C 462. Return to Figure 5C , line 574 includes a conditional if state that determines whether lower_check is greater than upper_check, which implements Figure 4C At line 575, last_check is returned, where line 514 sets j equal to the return value of the function call bsrLower(), thus implementing Figure 4C of 480.

[0088] At line 576, next_check is set to implement Figure 4C 466. At line 577, the potential control binary sequence (tp) is constructed by calling the function constructTp(), where the input parameters are psi, next_check as range_lower, and k as range_upper, which implements Figure 4C 468. The functionality of the function call constructTp() is described above in Figure 5B In the function call constructTp() at line 577, Figure 5B The range of the potential control binary sequence (tp) constructed based on the actual control binary sequence (ta) at lines 538 and 539 is from next_check to k.

[0089] Then, at line 578, the function calls rerunSim() so that the simulation results based on the potential control binary sequence (tp) are returned, which implements Figure 4C 470. The functionality of the function call rerunSim() is described above in Figure 5B The conditional if statement at line 578 determines whether the function call rerunSim() returns the specified message <desmsg>, which achieves Figure 4C 472. If the specified message is returned, the potential control binary sequence (tp) includes an enable bit at an index contained in psi and at an index within the range next_check to k, which is sufficient to trigger the specified message. Therefore, if the specified message is returned, then at line 579, the actual control binary sequence (ta) is set equal to the potential control binary sequence (tp), which implements Figure 4C 474. In addition, if the specified message is returned, the function call bsrLower() is recursively called at line 580, where next_check+1 is passed as lower_check and next_check is passed as last_check. Line 580 implements Figure 4C The functionality of 476 in and the loop from 476 to 464. If the specified message is not returned, the function call bsrLower() is recursively called at line 582 and next_check-1 is passed as upper_check. Line 582 implements Figure 4C The functionality of 478 and the cycle from 478 to 464.

[0090] generally, Figure 4B and Figure 5C The illustrated binary search method analyzes the range in which the highest lower index may reside, and searches the range using a binary search until the highest lower index is identified. The range is the range from lower_check to upper_check, which is initially from j to k. The binary search divides the range into a lower half and an upper half by determining next_check (e.g., which is typically halfway between lower_check and upper_check), and determining whether the highest lower index exists in a given half. Figure 4C and Figure 5C In the simulation, the upper part is analyzed for the highest lower index by constructing a potential control binary sequence (tp) based on the range from next_check to k and rerunning the simulation based on the potential control binary sequence (tp). Based on the monotonic property, if the specified message is triggered when the simulation is rerun, the highest lower index exists in the upper part, and the upper part will be further searched for the highest lower index. The lower part can be discarded because it is not needed to trigger the specified message. On the contrary, if the specified message is not triggered when the simulation is rerun, the highest lower index does not exist in the upper part, and the lower part will be searched for the highest lower index. Each half is searched recursively until the range from lower_check to upper_check includes no more than one index. The result of such a search is:

[0091] (1) a potential control binary sequence (tp) constructed based on psi and a range from j-1 to k (where j is set in 480) triggers a specified message when used in the simulation;

[0092] (2) a potential control binary sequence (tp) constructed based on psi and a range from j to k (where j is set in 480) triggers a specified message when used in the simulation; and

[0093] (3) The potential control binary sequence (tp) constructed based on psi and the range from j+1 to k (where j is set in 480) does not trigger the specified message when used in the simulation.

[0094] To illustrate FIG. 4A to FIG. 4C and FIG. 5A to FIG. 5C , assuming that the original control binary sequence (e.g., the actual control binary sequence (ta) read at 402) has 10 bits, and among these bits, the enable bits at indexes 0, 5, and 6 are sufficient to trigger the specified message. Figure 5A-5C The pseudo code indicates that Figure 4A-4C For the sake of brevity, the description of the execution of some lines may be omitted, but it should be understood that such execution will occur.

[0095] Through the operation of lines 503 to 505, initially, j equals 0; k equals 9; and psi is null. Since psi is null, execution enters the while loop at line 507 and branches to line 513. Table 1 below shows the values ​​of various variables when line 513 is executed in the first iteration of the while loop.

[0096]

[0097] Item 1 of Table 1 shows the values ​​of j, k, and psi before executing row 513. Item 2 of Table 1 shows the state of the variables when the function call bsrUpper() is called for the first time. In the first call, next_check is 4 (calculated at row 564), so that the range (at row 565) of the potential control binary sequence (tp) is 0 to 4. Since the potential control binary sequence (tp) does not include the position of the actual control binary sequence (ta) at index 5 and 6, the specified message (at row 566) will not be triggered when performing the simulation based on the potential control binary sequence (tp). Therefore, the lower half of the range (0:4) can be excluded from further searching the lowest upper index, and bsrUpper() (at row 570) is called recursively with lower_check being 5, as shown in item 3 of Table 1.

[0098] In the second call, next_check is 7 (calculated at line 564), so that the range of the potential control binary sequence (tp) is constructed (at line 565) from 0 to 7. Since the potential control binary sequence (tp) includes the bits of the actual control binary sequence (ta) at indexes 0, 5, and 6, the specified message is triggered when the simulation based on the potential control binary sequence (tp) is performed (at line 566). Therefore, the upper half of the range (8:9) can be excluded from further searching for the lowest upper index, and bsrUpper() is recursively called with upper_check of 6 and last_check of 7 (at line 568), as shown in entry 4 of Table 1.

[0099] In the third call, next_check is 5 (calculated at line 564), so that the range of the potential control binary sequence (tp) is constructed (at line 565) from 0 to 5. Since the potential control binary sequence (tp) does not include the bits of the actual control binary sequence (ta) at indexes 5 and 6, the specified message is not triggered when the simulation based on the potential control binary sequence (tp) is performed (at line 566). Therefore, the lower half of the range (5:5) can be excluded from further searching for the lowest upper index, and bsrUpper() is recursively called with lower_check of 6 (at line 570), as shown in entry 5 of Table 1.

[0100] In the fourth call, next_check is 6 (calculated at line 564), so that the range of the potential control binary sequence (tp) constructed (at line 565) is 0 to 6. Since the potential control binary sequence (tp) includes the bits of the actual control binary sequence (ta) at indexes 0, 5, and 6, the specified message is triggered when the simulation based on the potential control binary sequence (tp) is performed (at line 566). Therefore, the range (7:7) can be excluded from further searching for the lowest upper index, and bsrUpper() is recursively called with upper_check of 5 and last_check of 6 (at line 568), as shown in entry 6 of Table 1.

[0101] In the fifth call, lower_check is greater than upper_check, which causes last_check to be returned. last_check in the fifth call is 6, which causes k to be set equal to 6 in entry 6 of Table 1.

[0102] Table 2 below shows the values ​​of various variables when line 514 is executed in the first iteration of the while loop.

[0103]

[0104] The entry 1 of table 2 shows the value of j, k and psi before executing row 514. The entry 2 of table 2 shows the state of variables when the function is called bsrLower() for the first time. In the first call, next_check is 3 (calculated at row 576), so that the range (at row 577) of building potential control binary sequence (tp) is 3 to 6. Because potential control binary sequence (tp) does not include the position of actual control binary sequence (ta) at index 0, the specified message (at row 578) will not be triggered when performing the simulation based on potential control binary sequence (tp). Therefore, the upper half (3:6) of the range can be excluded from further searching the highest lower index, and bsrLower() (at row 582) is called recursively with upper_check being 2, as shown in the entry 3 of table 2.

[0105] In the second call, next_check is 1 (calculated at line 576), so that the range of the potential control binary sequence (tp) is constructed (at line 577) from 1 to 6. Since the potential control binary sequence (tp) does not include the bit of the actual control binary sequence (ta) at index 0, the specified message is not triggered when the simulation based on the potential control binary sequence (tp) is performed (at line 578). Therefore, the upper half of the range (1:2) can be excluded from further searching for the highest lower index, and bsrLower() is recursively called with upper_check being 0 (at line 582), as shown in entry 4 of Table 2.

[0106] In the third call, next_check is 0 (calculated at line 576), so that the range of the potential control binary sequence (tp) is constructed (at line 577) from 0 to 6. Since the potential control binary sequence (tp) includes the bits of the actual control binary sequence (ta) at indexes 0, 5, and 6, the specified message is triggered when the simulation based on the potential control binary sequence (tp) is performed (at line 578). Therefore, bsrLower() is recursively called with lower_check being 1 and last_check being 0 (at line 580), as shown in entry 5 of Table 2.

[0107] In the fourth call, lower_check is greater than upper_check, which causes last_check to be returned. last_check in the fourth call is 0, which causes j to be set equal to 0 in entry 5 of Table 2.

[0108] Then, in the first iteration of the while loop, psi collects j and k so that psi is {0,6} (at line 515). The if statement at line 516 does not cause the while loop to break. Then, k is decremented to 5 (at line 517); j is incremented to 1 (at line 518); and the second iteration of the while loop begins.

[0109] In the second iteration, psi is not empty, so lines 509 and 510 are executed. Since psi is equal to {0,6}, the constructed potential control binary sequence (tp) (at line 509) includes the bits of the actual control binary sequence (ta) at indexes 0 and 6. Since the potential control binary sequence (tp) does not include the bit of the actual control binary sequence (ta) at index 5, the specified message is not triggered when the simulation based on the potential control binary sequence (tp) is performed (at line 510). Therefore, the execution of lines 511 and 512 is omitted, and the interruption of the while loop (at line 512) is not executed.

[0110] Table 3 below shows the values ​​of various variables when line 513 is executed in the second iteration of the while loop.

[0111]

[0112] Item 1 of Table 3 shows the values ​​of j, k, and psi before executing row 513. Item 2 of Table 3 shows the state of variables when the function is called bsrUpper() for the first time. In the first call, next_check is 3 (calculated at row 564), so that the range (at row 565) of constructing the potential control binary sequence (tp) is 1 to 3 (wherein the index is contained in psi{0,6}). Since the potential control binary sequence (tp) does not include the position of the actual control binary sequence (ta) at index 5, the specified message (at row 566) will not be triggered when performing the simulation based on the potential control binary sequence (tp). Therefore, the lower half of the range (1:3) can be excluded from further searching the lowest upper index, and bsrUpper() (at row 570) is called recursively with lower_check being 4, as shown in item 3 of Table 3.

[0113] In the second call, next_check is 4 (calculated at line 564), so that the range of the potential control binary sequence (tp) is constructed (at line 565) from 1 to 4 (where the index is contained in psi{0,6}). Since the potential control binary sequence (tp) does not include the bit of the actual control binary sequence (ta) at index 5, the specified message is not triggered when performing the simulation based on the potential control binary sequence (tp) (at line 566). Therefore, the lower half of the range (4:4) can be excluded from further searching for the lowest upper index, and bsrUpper() is recursively called with lower_check of 5 (at line 570), as shown in entry 4 of Table 3.

[0114] In the third call, next_check is 5 (calculated at line 564), so that the range of the potential control binary sequence (tp) constructed (at line 565) is 1 to 5 (where the index is contained in psi{0,6}). Since the potential control binary sequence (tp) includes the bits of the actual control binary sequence (ta) at indexes 0, 5, and 6, the specified message is triggered when the simulation based on the potential control binary sequence (tp) is performed (at line 566). bsrUpper() is recursively called with upper_check of 4 and last_check of 5 (at line 568), as shown in entry 5 of Table 3.

[0115] In the fourth call, lower_check is greater than upper_check, which causes last_check to be returned. last_check in the fourth call is 5, which causes k to be set equal to 5 in entry 5 of Table 3.

[0116] Table 4 below shows the values ​​of various variables when line 514 is executed in the second iteration of the while loop.

[0117]

[0118]

[0119] The entry 1 of table 4 shows the values ​​of j, k, and psi before executing row 514. The entry 2 of table 4 shows the state of the variables when the function is called bsrLower() for the first time. In the first call, next_check is 3 (calculated at row 576), so that the range (at row 577) of the potential control binary sequence (tp) is 3 to 5 (wherein the index is contained in psi{0,6}). Since the potential control binary sequence (tp) includes the position of the actual control binary sequence (ta) at index 0, 5, and 6, a specified message (at row 578) is triggered when performing the simulation based on the potential control binary sequence (tp). Therefore, the lower half (1:2) of the range can be excluded from further searching for the highest lower index, and bsrLower() is called recursively (at row 580) with lower_check being 4 and last_check being 3, as shown in the entry 3 of table 4.

[0120] In the second call, next_check is 4 (calculated at line 576), so that the range of potential control binary sequence (tp) constructed (at line 577) is 4 to 5 (where the index is contained in psi{0,6}). Since the potential control binary sequence (tp) includes the bits of the actual control binary sequence (ta) at indexes 0, 5, and 6, the specified message is triggered when the simulation based on the potential control binary sequence (tp) is performed (at line 578). Therefore, the range (3:3) can be excluded from further searching for the highest lower index, and bsrLower() is recursively called with lower_check of 5 and last_check of 4 (at line 580), as shown in entry 4 of Table 4.

[0121] In the third call, next_check is 5 (calculated at line 576), so that the range of potential control binary sequence (tp) is constructed (at line 577) from 5 to 5 (where the index is contained in psi{0,6}). Since the potential control binary sequence (tp) includes the bits of the actual control binary sequence (ta) at indexes 0, 5, and 6, the specified message is triggered (at line 578) when the simulation based on the potential control binary sequence (tp) is performed. Therefore, the range (4:4) can be excluded from further searching for the highest lower index, and bsrLower() is recursively called with lower_check of 5 and last_check of 5 (at line 580), as shown in entry 5 of Table 4.

[0122] In the fourth call, lower_check is greater than upper_check, which causes last_check to be returned. last_check in the fourth call is 5, which causes j to be set equal to 5 at entry 5 of Table 4.

[0123] Then, in the second iteration of the while loop, psi collects j and k so that psi is {0,5,6} (at line 515). Since j is equal to k, the if statement at line 516 causes the while loop to break. The actual control binary sequence (ta) is then written at line 520.

[0124] To further explain FIG. 4A to FIG. 4C and FIG. 5A to FIG. 5C , assuming that the actual control binary sequence (ta) has 10 bits, and among these bits, the enable bits at indexes 0 and 6 are sufficient to trigger the specified message. As described in the previous example, execution occurs through the first iteration of the while loop (e.g., including the execution indicated by Tables 1 and 2). In the second iteration, psi is not empty, so lines 509 and 510 are executed. Since psi is equal to {0,6}, the constructed potential control binary sequence (tp) (at line 509) includes the bits of the actual control binary sequence (ta) at indexes 0 and 6. Since the potential control binary sequence (tp) includes the bits of the actual control binary sequence (ta) at indexes 0 and 6, the specified message is triggered when the simulation based on the potential control binary sequence (tp) is performed (at line 510). Therefore, the execution of lines 511 and 512 occurs. The actual control binary sequence (ta) is set equal to the potential control binary sequence (tp) (at line 511), and the interruption of the while loop is executed (at line 512). The actual control binary sequence (ta) is then written at line 520.

[0125] Various modifications may be made to the method 400 and pseudocode. For example, a linear search, a brute force search, or another search method may be implemented in place of the binary search described above. For example, a linear search may explore all indices of the current lower index as the lowest upper index, and explore all indices of the current upper index as the highest lower index. A brute force search may construct all 2 of the N bit control binary sequences. N permutations and search these permutations. In addition, binary search can be implemented in a manner different from that described above. For example, the highest lower index can be identified before the lowest upper index is identified.

[0126] The above binary search method can be executed with a running time of the order of Nlog(N) or less (e.g., O(Nlog(N))). Figure 5A The execution of the function calls bsrUpper() and bsrLower() at lines 513 and 514 in can be executed in a running time of the order of log(N) or less. The iteration of the while loop starting at line 507 can be executed in a running time of the order of N. Figure 5A The implemented method and the corresponding function definition can be executed together with a running time of the order of Nlog(N) or less (e.g., O(Nlog(N))). If a linear search method is implemented, the running time can be N 2 or less (e.g., O(N 2 )). If a brute force approach is implemented, the running time can be 2 N or less (e.g., O(2 N )). Storing the previous results of rerunning the simulation (e.g., caching the simulation results) can avoid the processing for rerunning the simulation, which can improve runtime performance. For example, in the context of the above example, the results of rerunning the simulation for entry 5 of Table 1 can be stored (e.g., cached), and the results of rerunning the simulation for entry 4 of Table 2 and the results of rerunning the simulation for entry 4 of Table 3 can be accessed. As indicated by these entries in the tables, the potential control binary sequence (tp) is constructed in a range from 0 to 6. Accessing the stored results in entry 4 of each of Tables 2 and 3 avoids rerunning the simulation for these entries.

[0127] Figure 6 The method 600 of locating one or more constraints that can trigger a specified message according to some examples. At 602, a first trace is obtained from a simulation of a DUT based on an original control binary sequence that triggers the specified message. The first trace can be obtained from the original simulation of the DUT, or from replaying the simulation of the DUT using the original control binary sequence. The first trace includes stimulus values ​​for a corresponding simulation cycle.

[0128] At 604, a second trace is obtained from the simulation of the DUT using a non-triggered control binary sequence based on the triggered control binary sequence and without triggering the specified message. The non-triggered control binary sequence is determined based on the triggered control binary sequence. The triggered control binary sequence can be obtained by FIG. 4A to FIG. 4C The method 400 is determined. Other methods can be used to obtain the triggered control binary sequence. The non-triggered control binary sequence is an original control binary sequence, in which the bit corresponding to the enable bit in the triggered control binary sequence is a disable bit. The enable bit of the triggered control binary sequence can be used to mask the corresponding bit of the original control binary sequence as a disable bit. The non-triggered control binary sequence is used during the simulation of the DUT to selectively enable and disable the solution step of the constraint random stimulus generator for each constraint problem corresponding to the enable bit of the non-triggered control binary sequence, and to restore the solution step for each constraint problem corresponding to the disable bit of the non-triggered control binary sequence. Selectively enabling and disabling the solution step according to the non-triggered control binary sequence may cause the specified message to not be triggered when simulating the DUT. The second trace includes the stimulus value for the corresponding simulation cycle.

[0129] At 606, one or more stimulus values ​​that differ between the first trace and the second trace for corresponding simulation cycles are identified. A trace may include values ​​for many stimuli for a given simulation cycle. When the corresponding values ​​of the same stimulus in the same simulation cycle of the first trace and the second trace are different, the stimulus may indicate that the constraint affecting the stimulus is the cause of a specified message generated by the simulation of the DUT. The number of stimuli identified as a result of method 600 may be reduced, thereby facilitating faster debugging of constraints.

[0130] Two use cases illustrate the effectiveness of implementing the constraint debugger 134 as described above. The first use case includes 110 random problem instances in a fault trace. The above methods 400, 600 are implemented to identify a trigger control binary sequence indicating a reduced portion of the trace and to identify one or more constraints that may trigger a specified message. As a baseline, the constraint debugger 134 is used to identify a trigger control binary sequence indicating a reduced portion of the trace and to identify one or more constraints that may trigger a specified message. Figure 4A-4C The run time for the binary search method to identify the trigger control binary sequence is upper bounded by 110*log(110) runs (e.g., for simulation reruns), which is approximately 746 runs. In this example, 16 runs were able to determine the trigger control binary sequence. Of these 16 runs, fault messages were observed in 11 runs, and no fault messages were observed in 5 runs. The 11 runs in which the fault message was observed averaged 2.7 seconds per run, and the 5 runs in which the fault message was not observed averaged 20 seconds per run. The total run time to determine the trigger control binary sequence was 129 seconds. In comparison, an experienced test engineer may take two to three days to identify the root cause of the fault message.

[0131] In this use case, by implementing Figure 4A-4C By using the binary search method of the present invention, the number of enabled bits in the trigger control binary sequence is reduced from 110 (e.g., the number corresponding to a random problem) to 1. In addition, the number of different stimulus values ​​between the fault trace (simulated based on the trigger control binary sequence) and the transfer trace (simulated without bias) is reduced from 94 to 7. The reduced set of value differences permits easier pinpointing of the root cause of the fault.

[0132] The second use case includes 331 random problem instances in the fault trace. The above methods 400, 600 are implemented to identify trigger control binary sequences that indicate a reduced portion of the trace and to identify one or more constraints that may trigger a specified message. Figure 4A-4C The run time for the binary search method to identify the trigger control binary sequence is upper bounded by 331*log(331) runs (e.g., for simulation reruns), which is approximately 2771 runs. In this example, 20 runs were able to determine the trigger control binary sequence. Of these 20 runs, fault messages were observed in 12 runs, and no fault messages were observed in 8 runs. The 12 runs in which fault messages were observed averaged 7 seconds per run, and the 8 runs in which no fault messages were observed averaged 7 seconds per run. The total run time to determine the trigger control binary sequence was 140 seconds.

[0133] In this use case, by implementing Figure 4A-4C By using the binary search method of the present invention, the number of enabled bits in the actual control binary sequence (ta) is reduced from 331 (e.g., the number corresponding to a random problem) to 1. In addition, the number of different stimulus values ​​between the fault trace (simulated based on the triggered control binary sequence) and the transfer trace (simulated without bias) is reduced from 251 to 6. The reduced set of value differences allows easier pinpointing of the root cause of the fault.

[0134] Figure 7 A set of example processes 700 used during the design, verification, and manufacture of an article such as an integrated circuit is illustrated to convert and verify design data and instructions representing the integrated circuit. Each of these processes can be constructed and enabled as multiple modules or operations. The term "EDA" represents the term "electronic design automation". These processes begin with creating a product concept 710 using information provided by a designer, which is converted to create an article using a set of EDA processes 712. When the design is complete, the design is taped out 734, at which time the artwork (e.g., geometric pattern) of the integrated circuit is sent to a manufacturing plant to manufacture a mask set, which is then used to manufacture the integrated circuit. After taping out, the semiconductor chip is manufactured 736 and packaging and assembly processes 738 are performed to produce a finished integrated circuit 740.

[0135] Specifications for circuits or electronic structures can range from low-level transistor material layouts to high-level description languages. High-level representations can be used to design circuits and systems using hardware description languages ​​(HDLs) such as VHDL, Verilog, SystemVerilog, SystemC, MyHDL, or OpenVera. HDL descriptions can be converted to logic-level register transfer level (RTL) descriptions, gate-level descriptions, layout-level descriptions, or mask-level descriptions. Each lower level of representation (i.e., more detailed descriptions) adds more useful details to the design description, for example, more details for the modules that comprise the description. Lower levels of representation (i.e., more detailed descriptions) can be computer-generated, derived from a design library, or created by another design automation process. An example of a specification language at a lower level of representation language for specifying a more detailed description is SPICE, which is used for detailed descriptions of circuits with many simulation components. The descriptions at each level of representation can be used by the corresponding system for that layer (e.g., a formal verification system). The design process can use Figure 7 The sequence depicted in . The described process is enabled by an EDA product (or EDA system).

[0136] During system design 714, the functionality of the integrated circuit to be manufactured is specified. The design may be optimized for desired characteristics such as power consumption, performance, area (physical and / or lines of code), and reduced cost, etc. The design may be divided into different types of modules or components at this stage.

[0137] During logic design and functional verification 716, modules or components in the circuit are specified with one or more description languages, and the functional accuracy of the specifications is checked. For example, the components of the circuit can be verified to generate outputs that match the specification requirements of the circuit or system being designed. Functional verification can use simulators and other programs, such as test bench generators, static HDL checkers, and formal verifiers. In some embodiments, a special component system called a "simulator" or "prototype system" is used to accelerate functional verification. Functional verification can include any of the above methods 300, 400, 600.

[0138] During synthesis and design for testing 718, the HDL code is converted to a netlist. In some embodiments, the netlist can be a graph structure, where the edges of the graph structure represent components of the circuit, and the nodes of the graph structure represent how the components are interconnected. Both the HDL code and the netlist are layered artifacts that can be used by EDA products to verify that the integrated circuit performs according to the specified design when manufactured. The netlist can be optimized for the target semiconductor manufacturing technology. In addition, the finished integrated circuit can be tested to verify that the integrated circuit meets the requirements of the specification.

[0139] During netlist verification 720, the netlist is checked for compliance with timing constraints and for correspondence with the HDL code. During design planning 722, an overall floor plan for the integrated circuit is constructed and analyzed for timing and top-level routing.

[0140] During layout or physical implementation 724, physical placement (positioning of circuit components such as transistors or capacitors) and wiring (connecting circuit components through multiple conductors) occur, and selection of cells from the library can be performed to enable specific logic functions. As used herein, the term "cell" can specify a group of transistors, other elements, and interconnections that provide Boolean logic functions (e.g., AND, OR, NOT, XOR) or storage functions (such as triggers or latches). As used herein, a circuit "block" can refer to two or more cells. Both cells and circuit blocks can be referred to as modules or components, and can be enabled as physical structures and in simulations. Parameters (such as size) are specified for the selected cell (based on "standard cells"), and it can be accessed in a database for use by EDA products.

[0141] During analysis and extraction 726, circuit functionality is verified at the layout level, which allows refinement of the layout design. During physical verification 728, the layout design is checked to ensure that manufacturing constraints such as DRC constraints, electrical constraints, lithography constraints are correct and that the circuit device functionality matches the HDL design specifications. During resolution enhancement 730, the geometry of the layout is transformed to improve the manufacture of the circuit design.

[0142] During tape-out, data is created for use in producing lithography masks (after applying lithography enhancements if appropriate). During mask data preparation 732, the "tape-out" data is used to produce lithography masks for producing finished integrated circuits.

[0143] Computer systems (such as Figure 8 The storage subsystem of the computer system 800) can be used to store programs and data structures used by some or all of the EDA products described herein, as well as for products used to develop libraries and units of physical and logical design that use the libraries.

[0144] Figure 8 An example machine of a computer system 800 is illustrated in which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate as a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0145] The machine may be a personal computer (PC), a tablet computer, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specifies actions to be taken by the machine. In addition, while a single machine is illustrated, the term "machine" should also be understood to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0146] The example computer system 800 includes a processing device 802, a main memory 804 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM)), a static memory 806 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device 818, which communicate with each other via a bus 830.

[0147] Processing device 802 represents one or more processors, such as a microprocessor, a central processing unit, etc. More specifically, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. Processing device 802 can also be one or more special processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. Processing device 802 can be configured to execute instructions 826 to perform the operations and steps described herein.

[0148] The computer system 800 may also include a network interface device 808 to communicate over a network 820. The computer system 800 may also include a video display unit 810 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 812 (e.g., a keyboard), a cursor control device 814 (e.g., a mouse), a graphics processing unit 822, a signal generating device 816 (e.g., a speaker), a graphics processing unit 822, a video processing unit 828, and an audio processing unit 832.

[0149] The data storage device 818 may include a machine-readable storage medium 824 (also referred to as a non-transitory computer-readable storage medium) on which is stored one or more sets of instructions 826 or software embodying any one or more of the methods or functions described herein. The instructions 826 may also reside, in whole or in part, within the main memory 804 and / or within the processing device 802 during execution by the computer system 800, the main memory 804 and the processing device 802 also constituting machine-readable storage media.

[0150] In some embodiments, the instructions 826 include instructions that implement functionality corresponding to the present disclosure. Although the machine-readable storage medium 824 is shown as a single medium in the example embodiments, the term "machine-readable storage medium" should be understood to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store one or more sets of instructions. The term "machine-readable storage medium" should also be understood to include any medium that can store or encode a set of instructions for execution by a machine and cause the machine and processing device 802 to perform any one or more methods of the present disclosure. The term "machine-readable storage medium" should therefore be understood to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0151] Some parts of the above detailed description have been presented in terms of algorithms and symbolic representations of data bit operations within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing use to most effectively communicate the essence of their work to other skilled in the art. An algorithm can be a series of operations that lead to a desired result. The operations are those operations that require physical manipulation of physical quantities. These quantities can take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Such signals can be referred to as bits, values, elements, symbols, characters, terms, numbers, etc.

[0152] It should be remembered, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless expressly stated otherwise as apparent from this disclosure, it should be understood that throughout the description certain terms refer to actions and processes of computer systems or similar electronic computing devices that manipulate data represented as physical (electronic) quantities within the computer system's registers and memories and convert them into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage devices.

[0153] The present disclosure also relates to a device for performing the operations herein. The device may be specially constructed for the intended purpose, or it may include a computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a non-transitory computer-readable storage medium, such as but not limited to any type of disk, including a floppy disk, an optical disk, a CD-ROM, and a magneto-optical disk, a read-only memory (ROM), a random access memory (RAM), an EPROM, an EEPROM, a magnetic card or an optical card, or any type of medium suitable for storing electronic instructions, each medium being coupled to a computer system bus.

[0154] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various other systems may be used together with the programs taught herein, or it may prove convenient to construct a more specialized device to perform the method. In addition, the present disclosure is not described with reference to any particular programming language. It should be understood that a variety of programming languages ​​may be used to implement the teachings of the present disclosure as described herein.

[0155] The present disclosure may be provided as a computer program product or software, which may include a machine-readable storage medium having instructions stored thereon, which may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable storage medium includes any mechanism for storing information in a machine (e.g., computer) readable form. For example, a machine-readable (e.g., computer-readable) storage medium includes a machine-readable (e.g., computer-readable) storage medium, such as a read-only memory (ROM), a random access memory (RAM), a disk storage medium, an optical storage medium, a flash memory device, etc.

[0156] In the foregoing disclosure, embodiments of the present disclosure have been described with reference to specific example implementations of the present disclosure. It is apparent that various modifications may be made thereto without departing from the broader spirit and scope of embodiments of the present disclosure as set forth in the following claims. Where the present disclosure refers to some elements in the singular, more than one element may be depicted in the accompanying drawings, and the same elements are marked with the same reference numerals. Therefore, the present disclosure and the accompanying drawings should be viewed in an illustrative sense rather than a restrictive sense.< / desmsg> < / desmsg> < / desmsg> < / desmsg> < / dbg> < / desmsg> < / dbg> < / msg>

Claims

1. A method comprising: Obtaining a control binary sequence determined during simulation of a design under test (DUT), wherein simulating the DUT is based on using a constrained random stimulus generator and a coverage biaser for biasing the constrained random stimulus generator, the control binary sequence comprising a first enable bit, the first enable bit corresponding to a corresponding constraint problem solved by the constrained random stimulus generator and biased by the coverage biaser, and triggering a specified message according to the first enable bit during the simulation of the DUT; constructing, by one or more processors, a reduced control binary sequence having a second enable bit that is a subset of the first enable bit; obtaining a simulation result generated by re-simulating the DUT, wherein the re-simulating the DUT comprises: for each of the constraint problems, selectively resuming a solution step of the constrained random stimulus generator for the corresponding constraint problem, the solution step being performed during the simulation of the DUT when a corresponding bit of the simplified control binary sequence is an enable bit in the second enable bit; determining whether the simulation result includes the specified message; and When the simulation result includes the designated message, the simplified control binary sequence is assigned as a trigger control binary sequence for triggering the designated message.

2. The method according to claim 1, wherein constructing the simplified control binary sequence, obtaining the simulation result, determining whether the simulation result includes the specified message, and assigning the simplified control binary sequence when the simulation result includes the specified message are performed iteratively.

3. The method according to claim 2, wherein obtaining the simulation result generated by resimulating the DUT comprises: For the corresponding iteration, when the simulation result corresponding to the same simplified control binary sequence as the simplified control binary sequence is previously stored in a storage device, retrieving the simulation result from the storage device; When the simulation result corresponding to the simplified control binary sequence identical to the simplified control binary sequence has not been previously stored in the storage device: Re-simulating the DUT based on the simplified control binary sequence to obtain the simulation result; and The simulation results corresponding to the simplified control binary sequence are stored in the storage device.

4. The method according to claim 1, further comprising: for each of the constraint problems that the constrained random stimulus generator is to solve during the simulation of the DUT, storing a state of the constrained random stimulus generator at an initial time of the corresponding constraint problem; simulating the DUT using stimulus values ​​generated by the constrained random stimulus generator biased by the overlay biaser, the constrained random stimulus generator generating the stimulus values ​​based on the respective constraint problem and based on a seed value determined by the respective state of the constrained random stimulus generator at the respective initial time of the respective constraint problem; during resimulation of the DUT, restoring the stored corresponding state to the constrained random stimulus generator prior to and for each of the constrained problems to be solved by the constrained random stimulus generator; and The DUT is re-simulated based on the simplified control binary sequence, and the biasing of the constrained random stimulus generator by the overlay biaser is selectively enabled or disabled for the corresponding constraint problem based on the simplified control binary sequence.

5. The method according to claim 1, further comprising: for each of the constraint problems that the constrained random stimulus generator is to solve during the simulation of the DUT, storing a state of the constrained random stimulus generator at an initial time of the corresponding constraint problem; simulating the DUT using stimulus values ​​generated by the constrained random stimulus generator biased by the overlay biaser, the constrained random stimulus generator generating the stimulus values ​​based on the respective constraint problem and based on a seed value determined by the respective state of the constrained random stimulus generator at the respective initial time of the respective constraint problem; Prior to solving a corresponding one of the constraint problems for resimulating the DUT, selectively restoring the stored corresponding state to the constrained random stimulus generator based on the simplified control binary sequence for each of the constraint problems to be solved by the constrained random stimulus generator during the resimulating the DUT; and For each of the constraint problems that the constrained random stimulus generator is to solve during the re-simulating of the DUT, the DUT is re-simulated based on the constrained random stimulus generator being biased by the coverage biaser. The method of claim 1 , further comprising performing a binary search to identify the second enable bit.

7. The method of claim 1 , wherein constructing the simplified control binary sequence comprises: Start an index range with an upper index and a lower index; iterate until (A) an index set is determined such that (i) each of the second enable bits corresponds to a corresponding one of the first enable bits at a corresponding index in the index set, and (ii) the simulation result generated by resimulating the DUT based on the simplified control binary sequence includes the specified message, or (B) a termination condition is reached: Determine the lowest upper index in the index range and the highest lower index in the index range, where: The designated message is triggered by a re-simulation of the DUT based on a first control binary sequence, the first control binary sequence having third enable bits, each of the third enable bits corresponding to a corresponding one of the first enable bits at a corresponding index in the set of indices or at a corresponding index in a range from the highest lower index to the lowest upper index; the designated message is not triggered by a re-simulation of the DUT based on a second control binary sequence, the second control binary sequence having fourth enable bits, each of the fourth enable bits corresponding to a corresponding one of the first enable bits at a corresponding index in the set of indices or at a corresponding index in a range from the highest lower index plus one to the lowest upper index; and the designated message is not triggered by a re-simulation of the DUT based on a third control binary sequence, the third control binary sequence having fifth enable bits, each of the fifth enable bits corresponding to a corresponding one of the first enable bits at a corresponding index in the set of indices or at a corresponding index in a range from the highest lower index to the lowest upper index minus one; and collecting the lowest upper index and the highest lower index in the index set; and The upper index is set to be one less than the lowest upper index, and the lower index is set to be one greater than the highest lower index. The method according to claim 1 , wherein the specified message comprises a fault message or a message defined by a regular expression.

9. The method according to claim 1, further comprising: triggering the designated message based on the control binary sequence to obtain a first trace generated by simulating the DUT; obtaining a second trace resulting from emulating the DUT using a non-triggered control binary sequence based on the triggered control binary sequence and without triggering the specified message, the non-triggered control binary sequence being the control binary sequence except that a disable bit corresponds to an enable bit of the triggered control binary sequence; as well as Stimulus values ​​that differ between the first trace and the second trace for respective simulation cycles are identified.

10. A non-transitory computer readable medium comprising stored instructions which, when executed by one or more processors, cause the one or more processors to: Obtaining a control binary sequence determined during simulation of a design under test (DUT), wherein simulating the DUT is based on using a constrained random stimulus generator and a coverage biaser for biasing the constrained random stimulus generator, the control binary sequence comprising a first enable bit, the first enable bit corresponding to a corresponding constraint problem solved by the constrained random stimulus generator and biased by the coverage biaser, and triggering a specified message according to the first enable bit during the simulation of the DUT; constructing a reduced control binary sequence having a second enable bit that is a subset of the first enable bit; Obtaining a simulation result generated by re-simulating the DUT, the re-simulating the DUT comprising: for each of the constraint problems, selectively resuming a solving step of the constrained random stimulus generator for the corresponding constraint problem, the solving step being performed when a corresponding bit of the simplified control binary sequence is an enable bit of the second enable bits during the simulation of the DUT; determining whether the simulation result includes the specified message; and When the simulation result includes the designated message, the simplified control binary sequence is assigned as a trigger control binary sequence for triggering the designated message.

11. The non-transitory computer readable medium of claim 10, wherein: Constructing the simplified control binary sequence, obtaining the simulation result, determining whether the simulation result includes the specified message, and assigning the simplified control binary sequence when the simulation result includes the specified message are performed iteratively; as well as The instructions that, when executed by the one or more processors, cause the one or more processors to obtain the simulation results generated by re-simulating the DUT include instructions that, when executed by the one or more processors, cause the one or more processors to perform the following operations for corresponding iterations: when the simulation result corresponding to the same simplified control binary sequence as the simplified control binary sequence is previously stored in a storage device, retrieving the simulation result from the storage device; When the simulation result corresponding to the simplified control binary sequence identical to the simplified control binary sequence has not been previously stored in the storage device: re-simulating the DUT based on the simplified control binary sequence to obtain the simulation result; and The simulation results corresponding to the simplified control binary sequence are stored in the storage device.

12. The non-transitory computer readable medium of claim 10, wherein the instructions, when executed by the one or more processors, further cause the one or more processors to: for each of the constraint problems that the constrained random stimulus generator is to solve during the simulation of the DUT, storing a state of the constrained random stimulus generator at an initial time of the corresponding constraint problem; simulating the DUT using stimulus values ​​generated by the constrained random stimulus generator biased by the overlay biaser, the constrained random stimulus generator generating the stimulus values ​​based on the respective constraint problem and based on a seed value determined by the respective state of the constrained random stimulus generator at the respective initial time of the respective constraint problem; during resimulation of the DUT, restoring the stored corresponding state to the constrained random stimulus generator prior to and for each of the constrained problems to be solved by the constrained random stimulus generator; and The DUT is re-simulated based on the simplified control binary sequence, and the biasing of the constrained random stimulus generator by the overlay biaser is selectively enabled or disabled for the corresponding constraint problem based on the simplified control binary sequence.

13. The non-transitory computer readable medium of claim 10, wherein the instructions, when executed by the one or more processors, further cause the one or more processors to: for each of the constraint problems that the constrained random stimulus generator is to solve during the simulation of the DUT, storing a state of the constrained random stimulus generator at an initial time of the corresponding constraint problem; simulating the DUT using stimulus values ​​generated by the constrained random stimulus generator biased by the overlay biaser, the constrained random stimulus generator generating the stimulus values ​​based on the respective constraint problem and based on a seed value determined by the respective state of the constrained random stimulus generator at the respective initial time of the respective constraint problem; Prior to solving a corresponding one of the constraint problems for resimulating the DUT, selectively restoring the stored corresponding state to the constrained random stimulus generator based on the simplified control binary sequence for each of the constraint problems to be solved by the constrained random stimulus generator during the resimulating the DUT; and For each of the constraint problems that the constrained random stimulus generator is to solve during the re-simulating of the DUT, the DUT is re-simulated based on the constrained random stimulus generator being biased by the coverage biaser.

14. The non-transitory computer readable medium of claim 10, wherein the instructions that when executed by the one or more processors cause the one or more processors to construct the reduced control binary sequence include instructions that when executed by the one or more processors cause the one or more processors to: Start an index range with an upper index and a lower index; iterate until (A) an index set is determined such that (i) each of the second enable bits corresponds to a corresponding one of the first enable bits at a corresponding index in the index set, and (ii) the simulation result generated by resimulating the DUT based on the simplified control binary sequence includes the specified message, or (B) a termination condition is reached: Determine the lowest upper index in the index range and the highest lower index in the index range, where: The designated message is triggered by a re-simulation of the DUT based on a first control binary sequence, the first control binary sequence having third enable bits, each of the third enable bits corresponding to a corresponding one of the first enable bits at a corresponding index in the set of indices or at a corresponding index in a range from the highest lower index to the lowest upper index; the designated message is not triggered by a re-simulation of the DUT based on a second control binary sequence, the second control binary sequence having fourth enable bits, each of the fourth enable bits corresponding to a corresponding one of the first enable bits at a corresponding index in the set of indices or at a corresponding index in a range from the highest lower index plus one to the lowest upper index; and the designated message is not triggered by a re-simulation of the DUT based on a third control binary sequence, the third control binary sequence having fifth enable bits, each of the fifth enable bits corresponding to a corresponding one of the first enable bits at a corresponding index in the set of indices or at a corresponding index in a range from the highest lower index to the lowest upper index minus one; as well as collecting the lowest upper index and the highest lower index in the index set; as well as The upper index is set to be one less than the lowest upper index, and the lower index is set to be one greater than the highest lower index.

15. The non-transitory computer readable medium of claim 10, wherein the instructions, when executed by the one or more processors, further cause the one or more processors to: triggering the designated message based on the control binary sequence to obtain a first trace generated by simulating the DUT; obtaining a second trace resulting from emulating the DUT using a non-triggered control binary sequence based on the triggered control binary sequence and without triggering the specified message, the non-triggered control binary sequence being the control binary sequence except that a disable bit corresponds to an enable bit of the triggered control binary sequence; and Stimulus values ​​that differ between the first trace and the second trace for respective simulation cycles are identified.

16. A non-transitory computer readable medium comprising stored instructions which, when executed by one or more processors, cause the one or more processors to: Obtaining an original control binary sequence generated during simulation of a design under test (DUT), wherein simulating the DUT is based on stimulus values ​​generated using a constrained random stimulus generator and a coverage biaser for biasing the constrained random stimulus generator, simulating the DUT to generate the original control binary sequence, the original control binary sequence comprising a first enable bit, the first enable bit corresponding to a corresponding constraint problem solved by the constrained random stimulus generator, and triggering a specified message according to the first enable bit during the simulation of the DUT; starts an index range with an upper index and a lower index; and iterate until (A) a set of indices is determined such that re-simulating the DUT based on a simplified control binary sequence triggers the specified message, the simplified control binary sequence having second enable bits, each of the second enable bits corresponding to a corresponding enable bit of the first enable bits at a corresponding index in the set of indices, or (B) a termination condition is reached: determining a lowest upper index in the index range and a highest lower index in the index range, wherein the designated message is triggered by a re-simulation of the DUT based on a first control binary sequence, the first control binary sequence having third enable bits, each of the third enable bits corresponding to a corresponding one of the first enable bits at a corresponding index in the index set or at a corresponding index in a range from the highest lower index to the lowest upper index; collecting the lowest upper index and the highest lower index in the index set; as well as The upper index is set to be one less than the lowest upper index, and the lower index is set to be one greater than the highest lower index.

17. The non-transitory computer readable medium of claim 16, wherein: the designated message is not triggered by a re-simulation of the DUT based on a second control binary sequence, the second control binary sequence having fourth enable bits, each of the fourth enable bits corresponding to a corresponding one of the first enable bits at a corresponding index in the set of indices or at a corresponding index in a range from the highest lower index plus one to the lowest upper index; and The specified message is not triggered by a re-simulation of the DUT based on a third control binary sequence, the third control binary sequence having fifth enable bits, each of the fifth enable bits corresponding to a corresponding enable bit of the first enable bits at a corresponding index in the index set or at a corresponding index in a range from the highest lower index to the lowest upper index minus one.

18. The non-transitory computer readable medium of claim 16, wherein the instructions that when executed by the one or more processors cause the one or more processors to determine the lowest upper index in the index range and the highest lower index in the index range further cause the one or more processors to: Determining whether the specified message is triggered by a re-simulation of the DUT based on a given control binary sequence, wherein determining whether the specified message is triggered comprises: determining whether a first result of a re-simulation of the DUT based on a control binary sequence identical to the given control binary sequence is stored in a storage device; when the first result is stored in the storage device, reading the first result from the storage device, the first result indicating whether the specified message is triggered by a re-simulation of the DUT based on the given control binary sequence; as well as When the first result is not stored in the storage device: re-simulating the DUT based on the given control binary sequence; and A second result of the re-simulation of the DUT based on the given control binary sequence is stored in the storage device, the second result indicating whether the specified message is triggered by the re-simulation of the DUT based on the given control binary sequence.

19. The non-transitory computer readable medium of claim 16, wherein the instructions, when executed by the one or more processors, further cause the one or more processors to: for each of the constraint problems to be solved by the constrained random stimulus generator during the simulation, storing in a storage device a state of the constrained random stimulus generator at an initial time of the corresponding constraint problem; simulating the DUT using the stimulus values ​​generated by the constrained random stimulus generator biased by the overlay biaser, the constrained random stimulus generator generating the stimulus values ​​based on the respective constraint problem and based on a seed value determined by the respective state of the constrained random stimulus generator at the respective initial time of the respective constraint problem; Prior to resimulating the DUT for each of the constraint problems to be solved by the constrained random stimulus generator during resimulation, restoring the stored corresponding state to the constrained random stimulus generator; and The DUT is re-simulated based on the simplified control binary sequence, and the biasing of the constrained random stimulus generator by the overlay biaser is selectively enabled or disabled for the corresponding constraint problem based on the simplified control binary sequence.

20. The non-transitory computer readable medium of claim 16, wherein the instructions, when executed by the one or more processors, further cause the one or more processors to: triggering the designated message based on the original control binary sequence to obtain a first trace generated by simulating the DUT; obtaining a second trace resulting from emulating the DUT using a non-triggered control binary sequence based on the triggered control binary sequence and without triggering the specified message, the non-triggered control binary sequence being the original control binary sequence except that a disable bit corresponds to an enable bit of the triggered control binary sequence; and Stimulus values ​​that differ between the first trace and the second trace for respective simulation cycles are identified.

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