FinFET process standard unit wiring control method and related equipment

Abstract

The present application discloses a FinFET process standard unit wiring control method and related equipment, which relates to the field of electronic design automation. The method includes: generating two-dimensional and three-dimensional design rule checking rules by preprocessing basic design rule checking data; reading user chip design files to form pre-design data; evaluating three-dimensional design rule prediction values ​​in combination with engine rule data and three-dimensional coordinate values, selecting pin access sequence, and performing basic wiring, through-hole generation and inspection operations. Correcting illegal wiring, and finally generating target wiring data through iterative timing optimization and rule checking.

Description

Technical Field

[0001] The present specification relates to the field of electronic design automation, and more specifically, the present application relates to a FinFET process standard cell wiring control method and related equipment. Background Art

[0002] In the back-end automatic routing process of integrated circuit design, meeting the DRC (Design Rule Check) requirements is an important step to ensure that the routing results meet the manufacturing process requirements. As the integration of transistors per unit area of ​​integrated circuits increases, even reaching 1 trillion scale, the process of integrated circuits continues to evolve. FinFET (Fin Field-Effect Transistor) process, which represents three-dimensional manufacturing process, has become the mainstream process node to replace CMOS (Complementary Metal-Oxide-Semiconductor) process, which replaces two-dimensional planar manufacturing process. At the same time, EDA (Electronic Design Automation) tools that can meet the 1 trillion scale of transistors are also facing problems such as low algorithm efficiency, upgrading of process manufacturing design rules from planar to three-dimensional, an order of magnitude increase in the number and complexity of DRC rules, and inability to identify complex design rules caused by the decomposition of one layer of GDS (Graphic Database System) graphics into multiple layers of GDS graphics due to multiple mask technology. The traditional two-dimensional DRC rule checking engine cannot simulate or predict three-dimensional DRC rule violations across multiple metal layers in FinFET process nodes, resulting in the need for multiple rework and adjustments to the design when problems are found, affecting design efficiency and cost.

[0003] Therefore, it is necessary to propose a FinFET process standard cell wiring method device, which can greatly improve the design efficiency and quality by meeting the DRC rules of the FinFET process node in advance in the automatic wiring process. Summary of the invention

[0004] A series of simplified concepts are introduced in the Summary of the Invention section, which will be further described in detail in the Detailed Description of the Invention section. The Summary of the Invention section of this application does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0005] In a first aspect, the present application proposes a FinFET process standard cell wiring control method, comprising:

[0006] Preprocessing the basic design rule check data to obtain engine rule data, wherein the engine rule data includes two-dimensional design rule check rules and three-dimensional design rule check rules;

[0007] Reading the user chip design file to perform pre-design operations and form pre-design data, wherein the pre-design data includes data such as standard cells and their pins, a network formed by signal paths, connections between standard cells, connections between pins, etc.;

[0008] Performing a design rule check evaluation operation according to the engine rule data and the automatic routing engine requirements to form evaluation tuple data, wherein the evaluation tuple data includes a three-dimensional design rule check prediction value and a three-dimensional coordinate value;

[0009] Determine the corresponding three-dimensional design rule check prediction value based on the three-dimensional coordinate value of each access point of each pin of each standard cell, and perform a pin access sequence selection operation based on the three-dimensional design rule check prediction value to obtain a target access sequence of each standard cell pin of the same type;

[0010] Performing basic wiring and through-hole generation operations based on the network data composed of all the signal paths, the three-dimensional wiring algorithm, and the target access sequence of each standard cell pin of each same type to generate basic wiring data;

[0011] Performing a 3D design rule check operation on the basic wiring data based on the 3D design rule check rules to obtain illegal wiring and through-hole coordinate data;

[0012] Performing routing and through-hole deletion operations based on the illegal routing and through-hole coordinate data, and calling the automatic routing module to perform re-routing and through-hole generation operations based on the illegal routing and through-hole coordinate data to generate secondary routing data;

[0013] Calling the timing network data in the above network data to perform timing analysis and optimization operations on the above secondary wiring data to obtain timing optimized wiring data;

[0014] The above-mentioned design rule check evaluation operation, the above-mentioned pin access sequence selection operation, the basic wiring and via generation operation, the three-dimensional design rule check operation, the wiring and via deletion operation, the re-wiring and via generation operation and the timing analysis and optimization operation are iteratively performed on the above-mentioned timing optimized wiring data until the number of design rule check violations, the total number of timing violations and the worst number of timing violations meet the design parameter requirements to generate the target wiring data.

[0015] In a feasible implementation, the above-mentioned three-dimensional design rule checking rules are obtained by performing an expansion operation based on the current design rule checking rules in the LEF file, and the above-mentioned expansion operation includes a first expansion operation and a second expansion operation. The above-mentioned first expansion operation is performed based on expert knowledge and logical combination and resolution operations, and the above-mentioned second expansion operation is generated based on known prediction values ​​through an optimization algorithm that meets the confidence interval setting. The above-mentioned optimization algorithm includes a linear programming method, a genetic algorithm, a simulated annealing algorithm, and an artificial intelligence-generated content domain-specific model.

[0016] In a feasible implementation manner, the above-mentioned three-dimensional design rule check prediction value is obtained by performing any one or more operations including weighted operation, weighted average operation, mean square error operation and maximum likelihood estimation operation on the Manhattan length of the wiring path, the number of wiring turns, whether the wiring is fixed, whether it is blocked and whether it is re-wired.

[0017] In a feasible implementation manner, the pin access sequence selection operation is performed based on the three-dimensional design rule check prediction value to obtain a target access sequence of each standard cell pin of the same type, including:

[0018] Based on the three-dimensional design rule check prediction value, a pin access sequence selection operation is performed through any one or more algorithms of dynamic programming, genetic algorithm, and simulated annealing algorithm to obtain a target access sequence for each standard cell pin of the same type.

[0019] In a feasible implementation manner, the pin access sequence selection operation is determined based on the three-dimensional design rule check prediction values ​​of all access points on the pins and the structural characteristics of the standard cell.

[0020] In a feasible implementation, the network data formed by all the signal paths, the three-dimensional wiring algorithm and the target access sequence of each standard cell pin of the same type are used to perform basic wiring and through-hole generation operations to generate basic wiring data, including:

[0021] Sorting the three-dimensional design rule check prediction values ​​of each access point of each two interconnected standard cell pins of the same type to obtain a target access point;

[0022] Based on the above-mentioned standard units and their pin data in the above-mentioned pre-design data and the network data constituted by the above-mentioned signal paths, the above-mentioned target access points are physically connected according to the 6-DOF 3D wiring algorithm, through-hole arrangements are performed based on the above-mentioned 3D design rule check rules corresponding to this layer, and the above-mentioned basic wiring data are generated according to the wiring guidance constituted by the above-mentioned 3D design rule check prediction values.

[0023] In a feasible implementation manner, the calling of the timing network data in the network data to perform timing analysis and optimization operations on the secondary wiring data to obtain timing optimized wiring data includes:

[0024] The timing path optimization module calls the timing network data in the above network data to calculate the capacitance data and the total path length data;

[0025] Determine the number of buffer cells between any two standard cells based on the capacitance data and the total path length data;

[0026] Based on the uniform distribution and / or Poisson distribution of the buffer cell density distribution function, the physical position of the corresponding buffer cell and its distribution in the chip design layout are generated, and a corresponding number of buffer cells are inserted to obtain timing optimized wiring data to meet the timing optimization requirements.

[0027] In a second aspect, the present application proposes a FinFET process standard cell wiring control device, comprising:

[0028] A design rule check preprocessing module, used for preprocessing the basic design rule check data to obtain engine rule data, wherein the engine rule data includes two-dimensional design rule check rules and three-dimensional design rule check rules;

[0029] An initialization module, used to read the user chip design file to perform pre-design operations and form pre-design data, wherein the pre-design data includes standard cells and their pin data, network data composed of signal paths, connection data between standard cells, and connection data between pins;

[0030] A design rule check evaluation module, used for performing a design rule check evaluation operation according to the engine rule data and the automatic routing engine requirements to form evaluation tuple data, wherein the evaluation tuple data includes a three-dimensional design rule check prediction value and a three-dimensional coordinate value;

[0031] A standard cell pin selection module, used to determine the corresponding three-dimensional design rule check prediction value based on the three-dimensional coordinate value of each access point of each pin of each standard cell, and perform a pin access sequence selection operation based on the three-dimensional design rule check prediction value to obtain a target access sequence of each standard cell pin of the same type;

[0032] An automatic wiring module, used for performing basic wiring and through-hole generation operations based on the network data composed of all the signal paths, a three-dimensional wiring algorithm and a target access sequence of each standard cell pin of each same type, so as to generate basic wiring data;

[0033] A 3D design rule checking module, used to perform a 3D design rule checking operation on the basic wiring data based on the 3D design rule checking rules to obtain illegal wiring and through-hole coordinate data;

[0034] An incremental rewiring module, used for performing wiring and through-hole deletion operations based on the illegal wiring and through-hole coordinate data, and calling the automatic wiring module to perform rewiring and through-hole generation operations based on the illegal wiring and through-hole coordinate data to generate secondary wiring data;

[0035] A timing path optimization module, used for calling the timing network data in the above network data to perform timing analysis and optimization operations on the above secondary wiring data to obtain timing optimized wiring data;

[0036] The iterative optimization module is used to iteratively perform the above-mentioned design rule check evaluation operation, the above-mentioned pin access sequence selection operation, the basic wiring and through-hole generation operation, the three-dimensional design rule check operation, the wiring and through-hole deletion operation, the re-wiring and through-hole generation operation and the timing analysis and optimization operation on the above-mentioned timing optimized wiring data until the number of design rule check violations, the total number of timing violations and the worst number of timing violations meet the design parameter requirements, so as to generate the target wiring data.

[0037] In a third aspect, an electronic device comprises: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor is used to implement the steps of the FinFET process standard cell wiring control method as described in any one of the above-mentioned first aspects when executing the computer program stored in the memory.

[0038] In a fourth aspect, the present application further proposes a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the FinFET process standard cell wiring control method of any one of the first aspects is implemented.

[0039] In summary, the method proposed in the embodiment of the present application provides an automated process from a one-stop chip design source file to a GDS file. The user only needs to input the corresponding design source file and constraint file, as well as the standard file required for process manufacturing, and the software algorithm automatically generates the GDS layout file, which greatly reduces the inefficiency caused by the original separation design process. The method provides three-dimensional DRC prediction and routing based on the prediction, so that the routing can meet the three-dimensional DRC process requirements brought by the DPT of the FinFET process, so that the product can meet the design rule requirements of the FinFET process. At the same time, 6 degrees of freedom three-dimensional routing is provided, making full use of the routing resources of the 3D space, which can greatly reduce the chip design area. The method can automatically select the optimal access point of the STDCell pin driven by three-dimensional DRC, greatly reducing the number of DRC violations of the initial routing results, thereby reducing the subsequent rewiring iteration cycle. By providing pre-DRC driven routing, the DRC prediction is applied when the routing algorithm is executed, which greatly improves the operating efficiency of the routing tool, reduces a large number of violations after the subsequent DRC check, and greatly improves the operating efficiency of the product, so that the product can support a larger scale design. The incremental routing repair function reduces the complexity of rewiring and re-placing vias after DRC violations and optimizes design performance. At the same time, the parallel computing architecture can reduce the algorithm running time by dozens of times, increasing the chip design scale range covered by the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present specification. Also, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0041] Figure 1 A schematic diagram of a process flow of a FinFET process standard unit wiring control method provided in an embodiment of the present application;

[0042] Figure 2 A schematic diagram of the structure of a FinFET process standard unit wiring control device provided in an embodiment of the present application;

[0043] Figure 3 A schematic diagram of the structure of a FinFET process standard unit wiring control electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0044] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices. The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments.

[0045] See also Figure 1 , which is a schematic flow chart of a FinFET process standard unit wiring control method provided in an embodiment of the present application, which may specifically include:

[0046] S110, performing a preprocessing operation on the basic design rule check data to obtain engine rule data, wherein the engine rule data includes two-dimensional design rule check rules and three-dimensional design rule check rules;

[0047] Exemplarily, the basic design rule check data can be obtained through the standard file formats LEF, Lib and other files provided by the wafer factory, and the file format follows the LEF54\LEF55\LEF58 standards. Then identify the rules of mature processes and FinFET processes, where the mature process realizes the identification and storage of rules through binary tuples. For the rules of FinFET processes, it is also necessary to infer the three-dimensional DRC rules based on the limited DRC rules in the LEF file. For example: for simple prediction values, they are obtained based on expert knowledge combined with logical combination and resolution operations. For potential unknown prediction values, the optimization algorithm set by the known prediction values ​​is used to meet the confidence interval. The above-mentioned optimal algorithm includes linear programming, genetic algorithm, simulated annealing and AIGC field-specific models as support, and is stored through an N-layer binary tree. The DRC rules after preprocessing are stored in the rule engine rule database TechDatabase. The computer storage method includes but is not limited to lists, vectors, tuples, queues, stacks, objects, etc. for use in subsequent processes.

[0048] S120, reading the user chip design file to perform a pre-design operation to form pre-design data, wherein the pre-design data includes standard cells and their pin data, network data composed of signal paths, connection data between standard cells, and connection data between pins;

[0049] Exemplarily, the user chip design file is read, and the user chip design file includes design source files HDL, Verilog, TCL, etc., design constraint files SDC files, and chip design parameters, etc. Chip design parameters include but are not limited to: area, coordinates, voltage, capacitance, parasitic resistance and capacitance (RC), utilization, clock cycle, total timing violation number (TNS), worst timing violation (WNS), number of DRC violations, and specific STDCell (standard cell) that needs to be specified. STDCell includes but is not limited to buffer BUFFERCell, Filler Cell, Tie Hi Cell, Tie Lo Cell, and through-hole files that need to be specified, in addition to some power supply network definition files, etc. After obtaining the design information corresponding to the above chip design files, the pre-design data is formed into a design database DesignDatabase through pre-processes such as layout planning, logic synthesis, STDCell automatic layout and clock tree synthesis, including standard cells and their pins, networks composed of signal paths, connections between standard cells, connections between pins and other data. The construction form is the network data Net class composed of all signal paths. The network data includes all STDCell pins on the network path and all other information related to the design. The network data is stored in ways including but not limited to lists, vectors, tuples, queues, stacks, objects, etc. for use in subsequent processes.

[0050] S130, performing a design rule check evaluation operation according to the engine rule data and the automatic routing engine requirements to form evaluation binary data, wherein the evaluation binary data includes a three-dimensional design rule check prediction value and a three-dimensional coordinate value;

[0051] Exemplarily, the pre-processed engine rule data stored above is used to generate a set of <prediction value, three-dimensional coordinate> tuples corresponding to three-dimensional space coordinates according to the needs of the subsequent automatic routing engine, wherein the prediction value in the tuple is the three-dimensional design rule check prediction value, and the three-dimensional coordinate value includes both the physical relative coordinates of the chip on the actual wafer and the node coordinates of the logical routing track. The prediction value can be stored in the ESTDatabase, and the storage method of the prediction value includes but is not limited to lists, vectors, tuples, queues, stacks, objects, etc., for use in subsequent processes.

[0052] S140, determining a corresponding three-dimensional design rule check prediction value based on the three-dimensional coordinate value of each access point of each pin of each standard cell, and performing a pin access sequence selection operation based on the three-dimensional design rule check prediction value to obtain a target access sequence of each standard cell pin of the same type;

[0053] Exemplarily, each STDCell corresponds to multiple access points. For each access point of each pin of each STDCell, each access point corresponds to a three-dimensional coordinate. The DRC prediction value corresponding to the point is retrieved according to the three-dimensional coordinate. There is a set of corresponding DRC prediction values ​​for each pin. According to the DRC prediction value of each pin and the structural characteristics of the STDCell, the pin access order selection operation is determined to obtain the target access order of each standard unit pin of the same type.

[0054] This step is particularly important in FinFET process nodes. For FinFET process nodes, due to the existence of Fin Track, the width-to-depth ratio of STDCell is often much higher than that of mature process nodes. This mode adaptively adjusts the selection order of pin access points as the width-to-depth ratio of each STDCell changes. Once the sequence mode is determined, the order of the optimal candidate access points of the corresponding pins is also determined. The storage methods of the target access order of each standard cell pin include lists, vectors, tuples, queues, stacks, etc., for use in subsequent processes.

[0055] S150, performing basic wiring and through-hole generation operations based on the network data formed by all the signal paths, the three-dimensional wiring algorithm, and the target access sequence of each standard cell pin of the same type to generate basic wiring data;

[0056] Exemplarily, based on the network data composed of all signal paths, that is, each Net in the DesignDatabase, a three-dimensional space routing algorithm with six degrees of freedom (i.e., east, south, west, north and north in the plane, and up and down in the three-dimensional) driven by a three-dimensional DRC is used to complete the physical connection from the optimal access point of the STDCell pin in each Net. Before each connection, it is necessary to sort according to the three-dimensional DRC prediction value in the ESTDatabase to ensure that the globally optimal direction is always selected for connection when selecting the six-degree-of-freedom direction. After each routing operation is completed, the DRC prediction value is updated, and it is iterated until the routing of all Nets is completed, that is, the process of connecting all STDCell logics in the DesignDatabase to the physical routing is completed.

[0057] For the two degrees of freedom in the Z direction, when selecting the wiring direction, the three-dimensional DRC rules across multiple metal layers in the ESTDatabase are called for prediction until the optimal coordinate is selected, and the VIA through-hole that meets the DRC rules of the level is automatically generated. According to the VIAGEN rules in the LEF file and the basic Width, Space, Direction and other rules of the upper and lower metal layers of the VIA, the wiring and VIA corresponding to the three levels of the upper metal layer, VIA / CUT layer, and lower metal layer are generated to complete the adaptive generation of the through-hole and arrange it in the corresponding position. After the entire wiring operation is completed, the basic wiring data is generated and the DesignDatabase is updated for use in subsequent processes.

[0058] S160, performing a 3D design rule check operation on the basic wiring data based on the 3D design rule check rule to obtain illegal wiring and through-hole coordinate data;

[0059] Exemplarily, after each routing operation is completed, the entire updated routing result DesignDatabase is subjected to a three-dimensional DRC design rule check across multiple metal layers. When a design that violates the DRC rule is found, the physical coordinates corresponding to the illegal routing or through hole are recorded, the coordinates are stored in the marking database DRCDatabase, and the illegal routing or through hole is marked as a DRC violation. Flexible rule settings can be used to allow for different process nodes and design requirements.

[0060] S170, performing routing and through-hole deletion operations based on the illegal routing and through-hole coordinate data, and calling the automatic routing module to perform re-routing and through-hole generation operations based on the illegal routing and through-hole coordinate data to generate secondary routing data;

[0061] Exemplarily, incremental rewiring is performed on DRC illegal wiring and through-holes in the DRCDatabase, the illegal wiring and through-holes are deleted, and the three-dimensional DRC-driven automatic wiring module is executed according to the updated ESTDatabase to rewire only the Nets corresponding to the illegal wiring and through-holes, while other wiring results do not need to be rewired. The incremental rewiring is completed and the predicted value data in the <predicted value, three-dimensional coordinate> tuple is updated at the same time, which greatly improves the algorithm execution efficiency.

[0062] S180, calling the timing network data in the network data to perform timing analysis and optimization operations on the secondary wiring data to obtain timing optimized wiring data;

[0063] For example, the timing network data in the network data, that is, the clock Net in the DesignDatabase, represents the timing path. For this type of Net, timing analysis and timing adjustment need to be performed before routing so that all timing paths meet the requirements of TNS (Total Negative Slack) and WNS (Worst Negative Slack). This module completes the operation before the DRC-driven automatic routing module, and updates the DesignDatabase after completion for use in subsequent processes.

[0064] S190, iteratively perform the above-mentioned design rule check evaluation operation, the above-mentioned pin access sequence selection operation, the basic wiring and via generation operation, the three-dimensional design rule check operation, the wiring and via deletion operation, the re-wiring and via generation operation and the timing analysis and optimization operation on the above-mentioned timing optimized wiring data until the number of design rule check violations, the total number of timing violations and the worst number of timing violations meet the design parameter requirements to generate the target wiring data.

[0065] Exemplarily, the above operations are repeated until three key conditions are met: Design rule check violation number: After routing and via generation, there are no or very few DRC violations. Total timing violation number: TNS is within an acceptable range, that is, the timing problem of the overall design has been optimized to meet the requirements. Worst timing violation number: The worst path timing of WNS has been optimized, and there is no serious timing problem.

[0066] When both the design rule check (DRC) and timing analysis meet the design parameter requirements, the target wiring data is finally generated. This means that all wiring and via layout in the design have been optimized, meet the process rules and timing requirements, and can enter the subsequent manufacturing or simulation stage.

[0067] It should be noted that after completing the above-mentioned target wiring data determination step, the finally updated DesignDatabase in memory can be serialized into a GDS file format according to the standard definition of GDS, including the shape, color and other information of the Device layer, metal layer and through-hole layer.

[0068] It can be understood that the above method can be encapsulated as software. When running the software constructed by the above method, the number of CPU Cores in the software running environment can be obtained, and the entire DesignDatabase can be divided according to the number of CPU Cores. The divided DesignDatabase is allocated to each CPU Core to run the above 8 modules. After the parallel operation is completed, the overall design is merged in the shared area.

[0069] It can also provide users with an easy-to-use parameter configuration page, chip design parameters, including but not limited to: area, coordinates, voltage, capacitance, parasitic resistance and capacitance (RC), utilization, clock cycle, total timing violation number (TNS), worst timing violation (WNS), number of DRC violations, power consumption, and specific STDCell design parameters that need to be specified.

[0070] It can also provide a visual interface for designers to intuitively configure the design, automate routing, generate GDS files, and check whether the timing, area, and DRC results meet the chip design requirements, thereby improving work efficiency.

[0071] In summary, the method proposed in the embodiment of the present application provides an automated process from a one-stop chip design source file to a GDS file. The user only needs to input the corresponding design source file and constraint file, as well as the standard file required for process manufacturing, and the software algorithm automatically generates the GDS layout file, which greatly reduces the inefficiency caused by the original separation design process. The method provides three-dimensional DRC prediction and routing based on the prediction, so that the routing can meet the three-dimensional DRC process requirements brought by the DPT of the FinFET process, so that the product can meet the design rule requirements of the FinFET process. At the same time, 6 degrees of freedom three-dimensional routing is provided, making full use of the routing resources of the 3D space, which can greatly reduce the chip design area. The method can automatically select the optimal access point of the STDCell pin driven by three-dimensional DRC, greatly reducing the number of DRC violations of the initial routing results, thereby reducing the subsequent rewiring iteration cycle. By providing pre-DRC driven routing, the DRC prediction is applied when the routing algorithm is executed, which greatly improves the operating efficiency of the routing tool, reduces a large number of violations after the subsequent DRC check, and greatly improves the operating efficiency of the product, so that the product can support a larger scale design. The incremental routing repair function reduces the complexity of rewiring and re-placing vias after DRC violations and optimizes design performance. At the same time, the parallel computing architecture can reduce the algorithm running time by dozens of times, increasing the chip design scale range covered by the product.

[0072] In some examples, the above-mentioned three-dimensional design rule checking rules are obtained by performing expansion operations based on the current design rule checking rules in the LEF file, and the above-mentioned expansion operations include a first expansion operation and a second expansion operation. The above-mentioned first expansion operation is based on expert knowledge and logical combination and resolution operations, and the above-mentioned second expansion operation is generated based on known prediction values ​​through an optimization algorithm that meets the confidence interval setting. The above-mentioned optimization algorithms include linear programming methods, genetic algorithms, simulated annealing algorithms, and artificial intelligence-generated content domain-specific models.

[0073] Exemplarily, simple prediction values ​​are obtained based on expert knowledge in combination with logical combinations and resolution operations; potential unknown prediction values ​​are obtained based on known prediction values ​​through an optimization algorithm that satisfies confidence interval settings, including linear programming, genetic algorithms, simulated annealing, and AIGC field-specific models as support.

[0074] Specifically, the expansion of 3D design rule checking rules (DRC rules) is performed in two different ways, with the goal of better predicting and processing complex 3D routing rules in the automatic routing process, especially in advanced processes such as FinFET. These expansion operations are based on the design rules provided in the LEF file, combined with expert knowledge and optimization algorithms, including linear programming, genetic algorithms, simulated annealing, and artificial intelligence generation models, to improve the accuracy and efficiency of design rule checking.

[0075] LEF (Library Exchange Format) file is one of the standard file formats in IC design, which is used to describe standard cell layout information and wiring rules. LEF file contains basic design rules for manufacturing process, such as metal layer width, spacing, via size and spacing, etc. These rules provide the initial two-dimensional design rule checking framework, and with the increase of process complexity, especially the introduction of three-dimensional FinFET process, traditional two-dimensional design rules need to be expanded and enhanced to meet the requirements of three-dimensional wiring.

[0076] The first expansion operation is based on expert knowledge and logical combination and resolution operations. In the first expansion operation, the expert's expertise is the core part of the expansion rules. Based on years of experience and specific manufacturing processes, experts propose additional design rules that may not be clearly defined in the LEF file. These rules usually involve interference between cross-layer metal lines, signal integrity requirements, and best practices for via layout. Logical combination refers to the combination through logical reasoning based on the rules defined by experts. For example, if rule A and rule B exist at the same time, a new rule C is generated to handle more complex situations. Logical combination can help deal with the interaction between different metal layers.

[0077] The resolution operation is used to eliminate conflicting or redundant rules. In complex 3D designs, multiple rules may conflict or repeat. The resolution operation can delete or simplify these rules through mathematical or logical operations to ensure that the final DRC rules are consistent and efficient.

[0078] Through the combination of these expert knowledge and logical operations, the first expansion operation can generate a more flexible and practical set of three-dimensional design rules to adapt to the complex FinFET process environment.

[0079] The second expansion operation is based on a domain-specific optimization algorithm, including linear programming, genetic algorithms, simulated annealing, and artificial intelligence models, which are used to predict and generate new design rules. This model is trained with a large amount of historical data, including previous design rule check results, predicted values, and other related wiring information. When designing, some design rules and wiring information are already known, which can be used as input data to provide to the optimization algorithm, including linear programming, genetic algorithms, simulated annealing, and artificial intelligence models to predict more unknown design rules.

[0080] Confidence intervals are used to measure the reliability of predictions from optimization algorithms, including linear programming, genetic algorithms, simulated annealing, and artificial intelligence models. When the model generates new design rules, confidence intervals provide a measure to ensure that these predictions are based on sufficiently reliable data and reasonable speculation. If the confidence interval is too large, it means that the model's predictions may have greater uncertainty, while a smaller confidence interval indicates that the predictions are more accurate.

[0081] Based on known prediction values ​​and confidence intervals, optimization algorithms, including linear programming, genetic algorithms, simulated annealing, and artificial intelligence models can generate new 3D design rules, especially in complex cross-layer wiring or via distribution situations. These rules may be difficult to accurately define with human experience, but through optimization algorithms, including linear programming, genetic algorithms, simulated annealing, and artificial intelligence models, more reasonable expansion results can be obtained. This approach can make up for the limitations of expert knowledge, especially when faced with large amounts of data or extremely complex designs.

[0082] In the actual design process, the first expansion operation and the second expansion operation can complement each other. Expert knowledge and logical operations can ensure the basic rationality of the rules and handle common complex situations in design, while optimization algorithms, including linear programming, genetic algorithms, simulated annealing, and artificial intelligence generation models, further supplement and optimize the rules through big data prediction and analysis.

[0083] The extended rules can better cope with complex 3D design scenarios, especially the 3D rule checking of cross-layer wiring in FinFET process nodes. In the actual design process, the tool will perform design rule checking and evaluation based on these extended rules to ensure that the design meets the requirements of the manufacturing process and avoid rework caused by rule violations.

[0084] The method proposed in the embodiment of the present application enhances the basic design rule checking capability in the LEF file through two extension operations. The first extension operation relies on expert knowledge, logical combination and resolution operations to generate more flexible and applicable design rules; the second extension operation uses optimization algorithms, including linear programming, genetic algorithms, simulated annealing, and artificial intelligence models, to generate more complex three-dimensional design rules using known prediction values ​​and confidence intervals. The combination of the two effectively improves the accuracy and efficiency of design rule checking, especially in three-dimensional process environments such as FinFET, to ensure that the final design meets manufacturing requirements.

[0085] In some examples, the above-mentioned three-dimensional design rule check prediction value is obtained by performing any one or more of weighted operations, weighted average operations, mean square error operations and maximum likelihood estimation operations on the Manhattan length of the routing path, the number of routing turns, whether the routing is fixed, whether it is blocked and whether it is re-routed.

[0086] Exemplarily, the above-mentioned three-dimensional design rule check prediction value EVA = evaluation function EST (Manhattan length of the wiring path, number of wiring turns, whether the wiring is fixed, whether it is blocked, whether it is re-wired), and the calculation formula of the evaluation function EST can be obtained through weighted operation of parameters, weighted average, mean square error, maximum likelihood estimation, etc.

[0087] Specifically, , the formula for the three-dimensional design rule check prediction value EVA can be:

[0088]

[0089] is the Manhattan length of the wiring path, L total is the maximum allowed Manhattan length, is the number of turns, N max is the maximum number of turns allowed, Indicates whether the wiring is fixed, 1 means the wiring is fixed, 0 means the wiring is changeable; Indicates whether there is any obstruction in the routing path, 1 indicates there is obstruction, and 0 indicates there is no obstruction; Indicates whether the wiring needs to be re-planned, 1 means it needs to be re-planned, 0 means it does not; is the mean square error, which is used to measure the fluctuation of the DRC prediction value in wiring. represents the DRC prediction value of the ith position, is the average of these predictions, Used to model the statistical distribution of routing parameters (such as DRC values, path lengths, etc.), , , , , , and are the weight coefficients corresponding to their respective parameters.

[0090] In some examples, the pin access sequence selection operation is performed based on the three-dimensional design rule check prediction value to obtain a target access sequence of each standard cell pin of the same type, including:

[0091] Based on the three-dimensional design rule check prediction value, a pin access sequence selection operation is performed through any one or more algorithms of dynamic programming, genetic algorithm, and simulated annealing algorithm to obtain a target access sequence for each standard cell pin of the same type.

[0092] Exemplarily, the DRC prediction value corresponding to the point is retrieved according to the three-dimensional coordinates, and there is a corresponding pin access point selection order for each pin. The selection order is calculated by dynamic programming, genetic algorithm, and simulated annealing algorithm, and the constraint is that the selection order corresponds to an optimal EVA.

[0093] Specifically, each standard cell pin has multiple available access points in different three-dimensional spaces. These access points are retrieved by their three-dimensional coordinates. Based on the three-dimensional coordinates of each access point, the corresponding design rule check prediction value (EVA) is obtained. These prediction values ​​reflect the compliance of the access point and evaluate its applicability in wiring design.

[0094] Each pin has a set of possible access points. The order of access point selection is determined by its corresponding DRC prediction value and three-dimensional coordinates. The goal is to find the best access order so that the compliance of the entire routing design is optimal. The optimization goal is to find an access order so that the selection of the pin access point of each standard cell corresponds to the optimal EVA, that is, the three-dimensional design rule check prediction value of the access point combination is the smallest and meets all design rules and constraints.

[0095] To find the optimal access sequence, one or a combination of three optimization algorithms can be used: dynamic programming, genetic algorithm, or simulated annealing.

[0096] 1. Dynamic programming solves complex optimization problems by breaking them down into sub-problems. It recursively calculates the optimal access point selection for each pin and builds a global optimal solution based on the local optimal solution.

[0097] Specifically, they may include:

[0098] S101 . Define the DRC prediction value of each pin access point as a state.

[0099] S102, starting from the last pin, recursively calculate forward step by step, and save the currently selected optimal result at each stage.

[0100] S103 finally obtains the globally optimal pin access sequence, so that the EVA of all pins is optimal.

[0101] 2. Genetic algorithm is a search algorithm based on natural selection and genetic mechanisms. It searches for the optimal solution by simulating the process of biological evolution (selection, crossover, mutation, etc.).

[0102] Specifically, they may include:

[0103] S201, initializing the population: generating multiple initial solutions (ie, different pin access sequences) for the selection of each standard cell pin access point.

[0104] S202, fitness evaluation: the fitness is evaluated according to the EVA value of each pin access sequence, and a lower EVA value represents a higher fitness.

[0105] S203, selection operation: select some excellent solutions based on the fitness value as the parents of the next generation.

[0106] S204, crossover and mutation: Perform crossover and mutation operations on the parent generation to generate new solutions and possibly discover a better pin access sequence.

[0107] S205, Iteration: Repeat fitness evaluation, selection, crossover, and mutation until the termination condition is met (for example, the optimal solution is found or the maximum number of iterations is reached).

[0108] 3. The simulated annealing algorithm is an optimization algorithm based on the physical annealing process. It finds the approximate optimal solution to the problem by randomly searching in the solution space and gradually lowering the "temperature".

[0109] Specifically, they may include:

[0110] S301, initialization solution: randomly select an initial pin access sequence and calculate its EVA value.

[0111] S302, neighborhood search: Generate a new solution by changing the current pin access sequence.

[0112] S303, accepting a new solution: If the EVA value of the new solution is better than the current solution, then the new solution is accepted; otherwise, based on a certain probability (related to the current "temperature"), the suboptimal solution is accepted.

[0113] S304, cooling: gradually lower the temperature to reduce the possibility of accepting suboptimal solutions, and eventually converge to the global optimal or approximate optimal solution.

[0114] S305, iteration: repeat the neighborhood search and cooling process until the termination condition is met (such as the temperature reaches a certain threshold or the optimal solution is found).

[0115] It should be noted that no matter which algorithm is used, the final pin access sequence must minimize the total EVA (three-dimensional design rule check prediction value) and meet all design rule constraints. The algorithm's computational resources and time complexity may also be limited by the wiring scale and design rules, so it is very important to choose an appropriate algorithm to balance accuracy and efficiency. Through the above method, the optimal access sequence for each standard cell pin can be determined to ensure that the wiring complies with the three-dimensional design rules and minimize the risk of DRC violations during the wiring process. This not only improves the overall quality of the design, but also reduces subsequent rework and optimization time.

[0116] In some examples, the pin access sequence selection operation is determined based on three-dimensional design rule check prediction values ​​of all access points on the pins and structural characteristics of the standard cell.

[0117] For example, the 3D design rule check prediction value (EVA) reflects whether different access points in the routing process may violate the design rules of the manufacturing process. In integrated circuit design, each pin access point has different 3D coordinates (including X, Y coordinates and plane metal layer Z coordinates), and these access points are represented by corresponding EVA values ​​to indicate their rule compliance.

[0118] The structural characteristics of a standard cell refer to the physical layout and electrical connection characteristics of the cell. It includes the geometry of the cell, the relative positions of inputs and outputs, the preferred paths for signal routing, electrical performance requirements (such as capacitance, delay, signal integrity, etc.), and the relationship between the cell and other surrounding cells.

[0119] When selecting the pin access sequence, the three-dimensional DRC prediction value of each access point and the structural characteristics of the standard cell must be considered comprehensively to achieve the following optimization goals:

[0120] Design rule compliance: When selecting access points, priority must be given to those with lower EVA values ​​and compliance with process rules to avoid DRC violations in routing.

[0121] Electrical performance optimization: Based on the structural characteristics of the standard cell, the access sequence that provides the best electrical performance is selected. For example, access points with lower signal transmission delay may be preferred on the critical path, while slightly more complex routing points may be selected on the non-critical path.

[0122] For example, different weighting coefficients can be set in different areas through weighted operations and weighted average methods, so as to balance the influence of the three-dimensional design rule check prediction value and the structural characteristics of the standard unit, making the pin selection more reasonable.

[0123] In some examples, the network data formed by all the signal paths, the three-dimensional wiring algorithm, and the target access sequence of each standard cell pin of each same type are used to perform basic wiring and via generation operations to generate basic wiring data, including:

[0124] Sorting the three-dimensional design rule check prediction values ​​of each access point of each two interconnected standard cell pins of the same type to obtain a target access point;

[0125] Based on the above-mentioned standard units and their pin data in the above-mentioned pre-design data and the network data constituted by the above-mentioned signal paths, the above-mentioned target access points are physically connected according to the 6-DOF 3D wiring algorithm, through-hole arrangements are performed based on the above-mentioned 3D design rule check rules corresponding to this layer, and the above-mentioned basic wiring data are generated according to the wiring guidance constituted by the above-mentioned 3D design rule check prediction values.

[0126] Exemplarily, each access point of each pin has an EVA value, which reflects the design rule compliance of the access point. The smaller the EVA value, the more the access point meets the requirements. In order to determine the optimal access point, it is first necessary to sort the EVA values ​​of all access points of each pin. The access point that best meets the design rules can be selected through sorting. Select the access point with the best EVA value from the access points of the STDCell pins in each Net to complete the physical connection. Before each connection, it is necessary to sort according to the three-dimensional DRC prediction value in the ESTDatabase to ensure that the global optimal direction is always selected for connection when selecting the direction of the six degrees of freedom. After each wiring operation is completed, the DRC prediction value is updated, and it is iterated until all Net wiring is completed, that is, the process of connecting all STDCell logics in the DesignDatabase to the physical wiring is completed. For the two degrees of freedom in the Z direction, when selecting the wiring direction, the three-dimensional DRC rules across multiple metal layers in the ESTDatabase should be called for prediction until the optimal coordinate is selected.

[0127] Automatically generate VIA through holes that meet the DRC rules of this level, and generate the wiring and VIA corresponding to the three levels of upper metal layer, VIA / CUT layer, and lower metal layer according to the VIAGEN rules in the LEF file and the basic Width, Space, Direction and other rules of the upper and lower metal layers of the VIA, complete the adaptive generation of the through hole, and arrange it in the corresponding position. After the entire wiring operation is completed, the DesignDatabase is updated for use in subsequent processes.

[0128] In some examples, calling the timing network data in the network data to perform timing analysis and optimization operations on the secondary wiring data to obtain timing optimized wiring data includes:

[0129] The timing path optimization module calls the timing network data in the above network data to calculate the capacitance data and the total path length data;

[0130] Determine the number of buffer cells between any two standard cells based on the capacitance data and the total path length data;

[0131] Based on the uniform distribution and / or Poisson distribution of the buffer cell density distribution function, the physical position of the corresponding buffer cell and its distribution in the chip design layout are generated, and a corresponding number of buffer cells are inserted to obtain timing optimized wiring data to meet the timing optimization requirements.

[0132] For example, the clock Net in the DesignDatabase represents the timing path. This type of Net needs to be analyzed during routing. By calculating its capacitance and total path length, the number of buffer cells that need to be inserted between any two STDCell pins in this type of Net is obtained. This type of buffer cell is inserted in the chip design layout so that all timing paths meet the requirements of TNS and WNS. This module completes the operation before the DRC-driven automatic routing module, and updates the DesignDatabase after completion for use in subsequent processes.

[0133] It should be noted that when setting the buffer unit, not only the number of buffer units but also the coordinates of the buffer unit settings need to be considered. The coordinates of the buffer unit settings are determined based on the buffer unit spacing, the buffer unit radius and the minimum number of buffer units in the group.

[0134] The buffer unit coordinates and the number of buffer units can be determined based on the following formula:

[0135] Buffer unit coordinates = density function f (buffer unit spacing, buffer unit radius, minimum number of buffer units in the group);

[0136] The number of buffer units = α (timing path length / timing path negative delay).

[0137] like Figure 2 As shown, the present application proposes a FinFET process standard unit wiring control device, including:

[0138] A design rule check preprocessing module 21 is used to perform preprocessing operations on basic design rule check data to obtain engine rule data, wherein the engine rule data includes two-dimensional design rule check rules and three-dimensional design rule check rules;

[0139] Initialization module 22, used to read user chip design files to perform pre-design operations and form pre-design data, wherein the pre-design data includes standard cells and their pin data, network data composed of signal paths, connection data between standard cells, and connection data between pins;

[0140] A design rule check evaluation module 23, configured to perform a design rule check evaluation operation according to the engine rule data and the automatic routing engine requirements to form evaluation tuple data, wherein the evaluation tuple data includes a three-dimensional design rule check prediction value and a three-dimensional coordinate value;

[0141] The standard cell pin selection module 24 is used to determine the corresponding three-dimensional design rule check prediction value based on the three-dimensional coordinate value of each access point of each pin of each standard cell, and perform a pin access sequence selection operation based on the three-dimensional design rule check prediction value to obtain a target access sequence of each standard cell pin of the same type;

[0142] The automatic wiring module 25 is used to perform basic wiring and through-hole generation operations based on the network data composed of all the signal paths, the three-dimensional wiring algorithm and the target access sequence of each standard cell pin of each same type to generate basic wiring data;

[0143] A 3D design rule checking module 26, configured to perform a 3D design rule checking operation on the basic wiring data based on the 3D design rule checking rules to obtain illegal wiring and through-hole coordinate data;

[0144] The incremental rewiring module 27 is used to perform wiring and through-hole deletion operations based on the illegal wiring and through-hole coordinate data, and call the automatic wiring module to perform rewiring and through-hole generation operations based on the illegal wiring and through-hole coordinate data to generate secondary wiring data;

[0145] A timing path optimization module 28 is used to call the timing network data in the above network data to perform timing analysis and optimization operations on the above secondary wiring data to obtain timing optimized wiring data;

[0146] The iterative optimization module 29 is used to iteratively perform the above-mentioned design rule check evaluation operation, the above-mentioned pin access sequence selection operation, the basic wiring and through-hole generation operation, the three-dimensional design rule check operation, the wiring and through-hole deletion operation, the re-wiring and through-hole generation operation and the timing analysis and optimization operation on the above-mentioned timing optimized wiring data until the number of design rule check violations, the total number of timing violations and the worst number of timing violations meet the design parameter requirements to generate the target wiring data.

[0147] like Figure 3 As shown, an embodiment of the present application also provides an electronic device 300, including a memory 310, a processor 320, and a computer program 311 stored in the memory 310 and executable on the processor, and when the processor 320 executes the computer program 311, the steps of any method of the above-mentioned FinFET process standard unit wiring control are implemented.

[0148] Since the electronic device introduced in this embodiment is a device used to implement a FinFET process standard unit wiring control device in the embodiment of the present application, based on the method introduced in the embodiment of the present application, the technical personnel in this field can understand the specific implementation of the electronic device of this embodiment and its various variations. Therefore, how the electronic device implements the method in the embodiment of the present application is not introduced in detail here. As long as the equipment used by the technical personnel in this field to implement the method in the embodiment of the present application is within the scope of protection of this application.

[0149] In the specific implementation process, when the computer program 311 is executed by the processor, it can achieve Figure 1 Any implementation manner in the corresponding embodiments.

[0150] It should be noted that in the above embodiments, the description of each embodiment has its own emphasis, and for parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0151] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0152] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded computer, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0153] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0154] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0155] An embodiment of the present application further provides a computer program product, which includes computer software instructions. When the computer software instructions are executed on a processing device, the processing device executes the process of FinFET process standard unit wiring control in the corresponding embodiment.

[0156] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from one website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a server or data center that includes one or more available media integrated. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid state disk (SSD)), etc.

[0157] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0158] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0159] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0160] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0161] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program codes.

[0162] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A FinFET process standard cell wiring control method, characterized in that: include: Performing a preprocessing operation on the basic design rule check data to obtain engine rule data, wherein the engine rule data includes two-dimensional design rule check rules and three-dimensional design rule check rules; Reading the user chip design file to perform a pre-design operation and form pre-design data, wherein the pre-design data includes standard cells and their pin data, network data formed by signal paths, connection data between standard cells, and connection data between pins; Performing a design rule check evaluation operation according to the engine rule data and the automatic routing engine requirements to form evaluation tuple data, wherein the evaluation tuple data includes a three-dimensional design rule check prediction value and a three-dimensional coordinate value; Determine the corresponding three-dimensional design rule check prediction value based on the three-dimensional coordinate value of each access point of each pin of each standard cell, and perform a pin access sequence selection operation based on the three-dimensional design rule check prediction value to obtain a target access sequence of each standard cell pin of the same type; Performing basic wiring and through-hole generation operations based on network data formed by all the signal paths, a three-dimensional wiring algorithm, and a target access sequence of each standard cell pin of each same type to generate basic wiring data; Performing a 3D design rule check operation on the basic wiring data based on the 3D design rule check rule to obtain illegal wiring and through-hole coordinate data; Performing routing and through-hole deletion operations based on the illegal routing and through-hole coordinate data, and calling an automatic routing module to perform re-routing and through-hole generation operations based on the illegal routing and through-hole coordinate data to generate secondary routing data; Calling the timing network data in the network data to perform timing analysis and optimization operations on the secondary wiring data to obtain timing optimized wiring data; The design rule check evaluation operation, the pin access sequence selection operation, the basic routing and via generation operation, the three-dimensional design rule check operation, the routing and via deletion operation, the re-routing and via generation operation and the timing analysis and optimization operation are iteratively performed on the timing optimized routing data until the number of design rule check violations, the total number of timing violations and the worst number of timing violations all meet the design parameter requirements to generate target routing data.

2. The FinFET process standard cell wiring control method according to claim 1, characterized in that: The three-dimensional design rule checking rules are obtained by performing an expansion operation based on the current design rule checking rules in the LEF file. The expansion operation includes a first expansion operation and a second expansion operation. The first expansion operation is performed based on expert knowledge and logical combination and resolution operations. The second expansion operation is generated based on known predicted values ​​through an optimization algorithm that satisfies a confidence interval setting. The optimization algorithm includes a linear programming method, a genetic algorithm, a simulated annealing algorithm, and an artificial intelligence-generated content domain-specific model.

3. The FinFET process standard cell wiring control method according to claim 1, characterized in that: The three-dimensional design rule check prediction value is obtained by performing any one or more operations including weighted operation, weighted average operation, mean square error operation and maximum likelihood estimation operation on the Manhattan length of the wiring path, the number of wiring turns, whether the wiring is fixed, whether it is blocked and whether it is re-wired.

4. The FinFET process standard cell wiring control method according to claim 1, characterized in that: The performing a pin access sequence selection operation based on the three-dimensional design rule check prediction value to obtain a target access sequence of each standard cell pin of the same type includes: Based on the three-dimensional design rule check prediction value, a pin access sequence selection operation is performed through any one or more algorithms of a dynamic programming method, a genetic algorithm, and a simulated annealing algorithm to obtain a target access sequence for each standard cell pin of the same type.

5. The FinFET process standard cell wiring control method according to claim 4, characterized in that: The pin access sequence selection operation is determined based on the three-dimensional design rule check prediction values ​​of all access points on the pins and the structural characteristics of the standard cell.

6. The FinFET process standard cell wiring control method according to claim 1, characterized in that: The basic wiring and through-hole generation operations are performed based on the network data formed by all the signal paths, the three-dimensional wiring algorithm and the target access sequence of each standard cell pin of each same type to generate basic wiring data, including: Sorting the three-dimensional design rule check prediction values ​​of each access point of each two interconnected standard cell pins of the same type to obtain a target access point; Based on the network data consisting of the standard cells and their pin data and the signal paths in the pre-design data, the target access points are physically connected according to a 6-DOF 3D wiring algorithm, through-holes are arranged based on the 3D design rule check rules corresponding to this layer, and the basic wiring data is generated according to wiring guidance consisting of the 3D design rule check prediction values.

7. The FinFET process standard cell wiring control method according to claim 1, characterized in that: The calling of the timing network data in the network data to perform timing analysis and optimization operations on the secondary wiring data to obtain timing optimized wiring data includes: The timing path optimization module calls the timing network data in the network data to calculate the capacitance data and the total path length data; determining the number of buffer cells between any two standard cells based on the capacitance data and the total path length data; Based on the uniform distribution and / or Poisson distribution of the buffer cell density distribution function, the physical position of the corresponding buffer cell and its distribution in the chip design layout are generated, and a corresponding number of buffer cells are inserted to obtain timing optimized wiring data to meet the timing optimization requirements.

8. A FinFET process standard unit wiring control device, characterized in that: include: A design rule check preprocessing module, used for preprocessing the basic design rule check data to obtain engine rule data, wherein the engine rule data includes two-dimensional design rule check rules and three-dimensional design rule check rules; An initialization module, used to read the user chip design file to perform a pre-design operation and form pre-design data, wherein the pre-design data includes standard cells and their pin data, network data composed of signal paths, connection data between standard cells, and connection data between pins; A design rule check evaluation module, used for performing a design rule check evaluation operation according to the engine rule data and the automatic routing engine requirements to form evaluation tuple data, wherein the evaluation tuple data includes a three-dimensional design rule check prediction value and a three-dimensional coordinate value; A standard cell pin selection module, configured to determine a corresponding three-dimensional design rule check prediction value based on the three-dimensional coordinate value of each access point of each pin of each standard cell, and perform a pin access sequence selection operation based on the three-dimensional design rule check prediction value to obtain a target access sequence of each standard cell pin of the same type; An automatic wiring module, for performing basic wiring and through-hole generation operations based on network data composed of all signal paths, a three-dimensional wiring algorithm, and a target access sequence of each standard cell pin of each same type to generate basic wiring data; A three-dimensional design rule checking module, used for performing a three-dimensional design rule checking operation on the basic wiring data based on the three-dimensional design rule checking rules to obtain illegal wiring and through-hole coordinate data; An incremental rewiring module, used for performing wiring and through-hole deletion operations based on the illegal wiring and through-hole coordinate data, and calling an automatic wiring module to perform rewiring and through-hole generation operations based on the illegal wiring and through-hole coordinate data to generate secondary wiring data; A timing path optimization module, used for calling the timing network data in the network data to perform timing analysis and optimization operations on the secondary wiring data to obtain timing optimized wiring data; An iterative optimization module is used to iteratively perform the design rule check evaluation operation, the pin access sequence selection operation, the basic wiring and through-hole generation operation, the three-dimensional design rule check operation, the wiring and through-hole deletion operation, the re-wiring and through-hole generation operation and the timing analysis and optimization operation on the timing optimized wiring data until the number of design rule check violations, the total number of timing violations and the worst number of timing violations meet the design parameter requirements, so as to generate target wiring data.

9. An electronic device, comprising: A memory and a processor, wherein the processor is used to implement the steps of the FinFET process standard unit wiring control method as described in any one of claims 1 to 7 when executing the computer program stored in the memory.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the FinFET process standard cell wiring control method according to any one of claims 1 to 7 are implemented.

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