Method and apparatus for performing positive iteration and indexing operations

Abstract

Methods, systems, and apparatus for performing indexing operations using unary iterative quantum circuits are disclosed. In one aspect, a method includes encoding an index value in an index register including an index qubit; encoding the index value in a control register including a plurality of control qubits; and repeatedly calculating and de-calculating the control qubits to perform the operation on one or more target qubits corresponding to the index value according to a state of the control qubits, in which during the encoding, the calculating, and the de-calculating: the plurality of control qubits are sequentially available, and the plurality of control qubits correspond to one-hot encoding of the encoded index value.

Description

[0001] This application is a divisional application of the invention patent application with application date of April 19, 2019, application number 201980020442.3, and invention name “Executing unitary iteration and index operation”. Background Art

[0002] A quantum circuit is a model for quantum computation in which the computation is a series of quantum logic gates - reversible transformations of an n-qubit register. Summary of the invention

[0003] The subject matter of this specification relates to techniques for generating quantum circuits, such as quantum circuits for performing index operations, referred to herein as unitary iteration quantum circuits.

[0004] In general, one innovative aspect of the subject matter described in this specification can be implemented by a method for performing unary iteration to implement an index operation using a unary iterative quantum circuit, the method comprising: encoding an index value in an index register including an index qubit; encoding the index value in a control register including a plurality of control qubits; and repeatedly computing and uncomputing the control qubits to perform an operation on one or more target qubits corresponding to the index value based on states of the control qubits, wherein during encoding, computing, and uncomputing: the plurality of control qubits are sequentially available, and the plurality of control qubits correspond to a one-hot encoding of the encoded index value.

[0005] Other implementations of this aspect include corresponding classical or quantum computer systems, devices, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the method. One or more systems of classical or quantum computers can be configured to perform specific operations or actions by installing software, firmware, hardware, or a combination thereof on the system, which causes the system to perform these actions in operation. One or more computer programs can be configured to perform specific operations or actions by including instructions, which, when executed by a data processing device, cause the device to perform an action.

[0006] The foregoing and other implementations may each optionally include one or more of the following features, alone or in combination. In some implementations, encoding an index value in a control register including a plurality of control qubits includes iteratively computing a plurality of logical AND operations between pairs of corresponding control qubits and index qubits to store a result of a logical AND operation between an inverse of a least significant index qubit and a penultimate control qubit storing a result of a previous logical AND operation in a last control qubit.

[0007] In some implementations, iteratively computing a plurality of logical AND operations between pairs of corresponding control qubits and index qubits to store a result of the logical AND operation between the inverse of the least significant index qubit and the control qubit storing the result of a previous logical AND operation includes: for a first iteration, performing a logical AND operation between a first control qubit and the inverse of a most significant index qubit, and storing the result of the logical AND operation in a second control qubit; and for a subsequent iteration, performing a logical AND operation between a control qubit storing the result of the logical AND operation of the previous iteration and the inverse of the index qubit of the iteration, and storing the result of the logical AND operation in a subsequent control qubit.

[0008] In some implementations, the first control qubit is initially set to an on state.

[0009] In some implementations, repeatedly computing and uncomputing the control qubits includes: for each target qubit, repeatedly in sequence: determining whether a last control qubit is in an on state, and performing an operation on the target qubit in response to determining that the last control qubit is in an on state; determining a number of undo computations of iteratively computed logical AND operations between pairs of corresponding control qubits and index qubits to perform; iteratively performing the determined number of undo computations; performing a controlled NOT (CNOT) operation between the control qubit corresponding to the last undo computed logical AND operation and the next highest control qubit, wherein the next highest control qubit serves as a control for the controlled NOT operation; iteratively computing a plurality of logical AND operations between pairs of corresponding control qubits and index qubits to recompute the last control qubit.

[0010] In some implementations, determining a number of undo computations to perform of iteratively computed logical AND operations between pairs of corresponding control qubits and index qubits includes: determining how many bits are flipped when changing a binary representation of an index value corresponding to a last control qubit to a next one; and determining the number of undo computations as the determined number of bit flips minus one.

[0011] In some implementations, determining a number of undo computations of iteratively computed logical AND operations between pairs of corresponding control qubits and index qubits to perform includes determining a number of times a base 10 index value can be divided by 2 before obtaining a non-integer.

[0012] In some implementations, the method further includes undoing the iteratively computed plurality of logical AND operations between pairs of corresponding control qubits and index qubits to reset the index register to encode the index value.

[0013] In some implementations, the plurality of logical ANDs includes a temporary AND operation defined according to a Toffoli gate and a Clifford+T gate.

[0014] In some implementations, each logical AND operation requires 4 T-gates.

[0015] In some implementations, the total number of AND operations included in the unary iterative circuit is equal to the total number of target qubits N minus 1.

[0016] In some implementations, the T count for performing the index operation is 4(L-1).

[0017] In some implementations, the method further includes:

[0018] The controlled-not operation is incorporated to produce an optimized unary iterative circuit for performing an index operation. In some implementations, the index operation comprises a range index operation, and wherein the unary iterative quantum circuit further comprises an accumulator qubit.

[0019] In some implementations, performing the range index operation includes applying a controlled NOT operation between the accumulator qubit and a last control qubit of each iteration, the last control qubit of the iteration serving as a control bit.

[0020] In some implementations, a unary iterative circuit is constructed by: defining an overall control circuit for implementing an index operation; applying a set of transformations to the overall control circuit to produce a first transformed circuit, including: for each possible index, when applied to the index and 2 b The result of the bitwise OR operator is greater than or equal to L and is applied to L-1 and 2 b The result of the bitwise AND operator is equal to 2 b When removing the expression 2 b controls on the index qubit of , where b represents a binary index; and expanding the remaining controls into a nested AND operation; applying a set of optimizations to the first transformed circuit to produce a unary iterative circuit, including: removing adjacent undo computations and recomputations of the AND operation if the control types match; and replacing adjacent undo computations and recomputations of the AND operation with controlled NOT and NOT operations if the control types do not match.

[0021] In some implementations, the nested AND operations are nested such that the lower controls are inside the higher controls.

[0022] In some implementations, the control qubit associated with an operation is placed directly below its lowest input qubit during expansion of the remaining control.

[0023] In general, another innovative aspect of the subject matter described in this specification can be implemented by a method for operating a quantum read-only memory, the method comprising: encoding an index value in an index register including one or more index qubits; encoding the index value in a control register including a plurality of control qubits; and repeatedly computing and uncomputing the control qubits to load data items corresponding to the index value into a data register of the data qubits according to states of the control qubits, wherein during the encoding, computing, and uncomputing: the plurality of control qubits are sequentially made available, and the plurality of control qubits correspond to a one-hot encoding of the stored index.

[0024] Other implementations of this aspect include corresponding classical or quantum computer systems, devices, and computer programs recorded on one or more computer storage devices, each of which is configured to perform the actions of the method. One or more systems of classical or quantum computers may be configured to perform specific operations or actions by installing software, firmware, hardware, or a combination thereof on the system, which software, firmware, hardware, or a combination thereof causes the system to perform these actions in operation. One or more computer programs may be configured to perform specific operations or actions by including instructions that, when executed by a data processing device, cause the device to perform an action.

[0025] The foregoing and other implementations may each optionally include one or more of the following features, alone or in combination. In some implementations, an index value in a control register including a plurality of control qubits includes iteratively computing a plurality of logical AND operations between pairs of corresponding control qubits and index qubits to store a result of a logical AND operation between an inverse of a least significant index qubit and a penultimate control qubit storing a result of a previous logical AND operation in a last control qubit.

[0026] In some implementations, iteratively computing a plurality of logical AND operations between pairs of corresponding control qubits and index qubits to store a result of the logical AND operation between the inverse of the least significant index qubit and the control qubit storing the result of a previous logical AND operation includes: for a first iteration, performing a logical AND operation between a first control qubit and the inverse of a most significant index qubit, and storing the result of the logical AND operation in a second control qubit; and for a subsequent iteration, performing a logical AND operation between a control qubit storing the result of the logical AND operation of the previous iteration and the inverse of the index qubit of the iteration, and storing the result of the logical AND operation in a subsequent control qubit.

[0027] In some implementations, the first control qubit is initially set to an on state.

[0028] In some implementations, repeatedly computing and uncomputing the control qubits includes: for each repetition: determining whether a last control qubit is in an on state; performing a multi-target controlled NOT operation on the data register qubits in response to determining that the last control qubit is in an on state, wherein the multi-target controlled NOT operation depends on a binary encoding of the data item and is controlled by the last control qubit; determining a number of undo computations of iteratively computed logical AND operations between pairs of corresponding control qubits and index qubits to perform; iteratively performing the determined number of undo computations; performing a controlled NOT operation between the control qubit corresponding to the last undo computed logical AND operation and the next highest control qubit, wherein the next highest control qubit serves as a control for the controlled NOT operation; iteratively computing a plurality of logical AND operations between pairs of corresponding control qubits and index qubits to recompute the last control qubit.

[0029] In some implementations, determining a number of undo computations to perform of iteratively computed logical AND operations between pairs of corresponding control qubits and index qubits includes: determining how many bits are flipped when changing a binary representation of an index value corresponding to a last control qubit to a next one; and determining the number of undo computations as the determined number of bit flips minus one.

[0030] In some implementations, determining a number of undo computations of iteratively computed logical AND operations between pairs of corresponding control qubits and index qubits to perform includes determining a number of times a base 10 index value can be divided by 2 before obtaining a non-integer.

[0031] In some implementations, the method further includes undoing the iteratively computed plurality of logical AND operations between pairs of corresponding control qubits and index qubits to reset the index register to encode the index value.

[0032] In some implementations, the plurality of logical ANDs includes a temporary AND operation defined according to a Toffoli gate and a Clifford+T gate.

[0033] In some implementations, each logical AND operation requires 4 T-gates.

[0034] In some implementations, the total number of AND operations included in the quantum read-only memory circuit is equal to the total number of data register qubits L minus one.

[0035] In some implementations, the T count of a loaded data item is 4(L-1).

[0036] The subject matter described in this specification can be implemented in a specific manner to achieve one or more of the following advantages.

[0037] The presently described disclosure represents a significant and broadly applicable improvement over the state of the art for performing index operations with low T gate counts.

[0038] For example, previously known quantum circuit constructions for performing index operations typically transform an index register that stores indices in the interval [0, L) with a space overhead of L qubits. In contrast, the unary iterative constructions and techniques described herein are exponentially more efficient in space without increasing the T-gate complexity, requiring only log L control qubits. In addition, by utilizing temporary AND constructions to perform logical AND operations, the unary iterative quantum circuits described herein require fewer T-gates than other quantum circuits performing index operations - requiring only 4(L-1) T-gates and can be parallelized when needed without increasing the T count. Since T-gates are notoriously expensive to manufacture, the unary iterative constructions described herein can provide a significant improvement over the prior art.

[0039] The unary iteration constructs described so far can be easily transformed or optimized and can be applied in a variety of settings. For example, the unary iteration constructs can be used to perform certain types of index operations, such as range index operations.

[0040] As another example, the unary iteration construction can form the basis of an improved read-only QRAM (referred to herein as QROM). Since the number of words or data items in a QROM is L, and the size of a word or data item in bits is D, the unary iteration construction described so far can be used to construct a QROM with a T count of 4(L-1) and an auxiliary (control qubit) count of logL. In addition, the QROM construction can be parameterized to achieve an improved T count of O(N / k+kD) and an auxiliary count of O(kD), where k represents an arbitrary number that trades off the control qubit count against the T count.

[0041] Another advantageous property of the QROM described so far is that it does not have to be stored in qubits. In fact, quantum algorithms using QROM can encode the relevant classical data directly into the quantum circuits that execute the algorithms. This makes it possible for near-term error-correcting quantum computers with an order of magnitude of one hundred error-correcting qubits to use QROM.

[0042] The QROM described so far could provide improvements to a variety of applications including quantum simulations, the construction of data lookups for quantum machine learning algorithms, and generally any algorithm that involves loading data into a quantum computer in superposition.

[0043] The details of one or more implementations of the subject matter of this specification are set forth in the accompanying drawings and the following description. Other features, aspects, and advantages of the subject matter will become apparent from the specification, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 An exemplary overall control circuit for performing controlled indexing operations is shown.

[0045] Figure 2 An exemplary circuit for performing a logical AND operation is shown.

[0046] Figure 3 An exemplary transformed overall control circuit is shown.

[0047] Figure 4 is a diagram of how to optimize adjacent AND operations.

[0048] Figure 5 An exemplary univariate iterative quantum circuit is shown.

[0049] Figure 6 An exemplary optimized univariate iterative quantum circuit is shown.

[0050] Figure 7 Another exemplary univariate iterative quantum circuit is shown.

[0051] Fig. 8A An exemplary unary iterative quantum circuit for performing a ranged indexed operation is shown.

[0052] Figure 8B An exemplary unary iterative quantum circuit for performing both range indexing and indexing operations is shown.

[0053] Fig. 9 is a flow chart of an exemplary process for performing an index operation using a unary iterative quantum circuit.

[0054] Fig.10 An exemplary data loading circuit is shown.

[0055] Fig.11 is a flow chart of an exemplary process for loading data using a unary iteration technique.

[0056] Fig.12 An exemplary system is shown. DETAILED DESCRIPTION

[0057] If implemented efficiently, the calculations performed using quantum computing devices will guarantee computational acceleration of specific classes of problems beyond any calculation that can be performed on a classical computer. The efficient implementation of quantum computing depends on the design of the quantum computing device architecture, for example, the design of the underlying quantum circuits of the quantum computer. For example, the quantum circuits included in the quantum computing device should be space efficient. As another example, since T gates are important components for building fault-tolerant quantum circuits, but they are inherently expensive, quantum computing devices should have low T counts. In fact, constructing quantum circuits that perform certain calculations with a reduced or even optimal number of T gates is an important task for the near-term implementation of quantum computing devices.

[0058] This specification describes quantum circuit constructions called unary iterative quantum circuits for performing index operations. Index operations (including range index operations or other complex variants derived from index operations) are important building blocks for performing a wide range of computational tasks (e.g., data loading or encoding electronic structure spectra in quantum circuits).

[0059] Performing an index operation involves performing an operation on one or more target qubits conditioned on the bit value in the index register. The operation performed can be, for example, any single qubit unitary. For example, this specification describes a quantum circuit configuration and method for implementing the index operation given by equation (1) below.

[0060] |l>|ψ>→|l>G l |ψ> (1)

[0061] In equation (1), G represents any single-qubit unitary operator, for example, the Pauli operator, |l> represents an index register of a qubit encoding an index value l, |ψ> represents a target register of a target qubit, and |l>G l |ψ> means applying operator G to the lth target qubit (the qubit at offset l in the target register |ψ>). Operator G does not have to be the same across the target register of qubits. For example, indexing operation G can be defined as one specific type of operation for index register values ​​less than some fixed value, and another specific type of operation for index register values ​​greater than or equal to the same fixed value.

[0062] As described in more detail below, the unary iterative quantum circuits described in this specification are space efficient and T-count efficient. The space and T-gate count efficiency is achieved by a unary iterative technique in which qubits are made available one by one (iteration) and the resulting value corresponds to a unique hot (unary) bit of the value of the index register. Unique hot encoding means that the condition under which the index register is storing a particular value corresponds to a specific qubit that is set or not set at a particular time in the circuit. For an index register that stores an index in the interval [0, L), the space overhead of converting the index register into a unary register using currently known techniques is L qubits. In contrast, the unary iterative quantum circuits and techniques described in this specification are exponentially more space efficient without any increased T complexity, requiring only log L control qubits. In addition, the unary iterative quantum circuits and techniques described in this specification have a T count of at most 4L-4 and can be parallelized without increasing the T count.

[0063] General techniques for implementing index operations

[0064] A method for implementing an index operation (e.g., indexing a NOT gate X l ) include fully controlling X l For all possible binary values ​​that may occur in the index register |l>. For example, to apply X when |l> = |158> 158 , the overall control method involves placing a NOT gate for the qubit at offset 158, but with one control per indexed qubit. The type of control (on or off) will be represented by the binary representation of 158 (158 10 =100111102), so there will be a must-be-OFF control for the low (least significant) bit of the index register (because the low bit of 158 is 0 in binary), a must-be-ON control for the next bit (because the next bit of 158 is 1 in binary), and so on for the remaining index bits (terminating with the most significant bit). To cover all cases, this process is repeated for each integer from 0 to L-1. This will produce L different NOT operations, each for a different qubit in the target register, and each with a number of controls equal to the size of the index register (i.e., logL). Therefore, O(L logL) T gates are required to apply equation (1) using this method. As described below, unary iterations asymptotically increase this T count to 4L-4.

[0065] The unary iterative structures described in this specification can be defined by applying a set of fixed transformations and optimizations of a specific structure to a conventional overall control circuit, as described below with reference to Figures 1 to 5 described.

[0066] Figure 1 An exemplary overall control circuit 100 for performing an index operation is shown. For convenience, the exemplary overall control circuit 100 is described as performing a controlled index NOT operation X. l , where 0≤l≤L=11, but the overall control circuit can be used to perform other index operations, and can be used to perform index operations with fewer or more indices.

[0067] The exemplary overall control circuit 100 includes an index register 102. In this example, the index register 102 includes four qubits l0, l1, l2, and l3, where qubit l3 stores the least significant bit, i.e., 2 0 , and qubit l0 stores the most significant bit, i.e. 2 3 . The exemplary overall control circuit 100 also includes a control register 104. In this example, the control register 204 includes one qubit |c>=(control). The exemplary overall control circuit 100 also includes a system or target register 106. In this example, the target register 106 includes at least 11 target qubits, which for convenience are represented as |ψ>=(ψ0, ψ1, ..., ψ 10 ) T .

[0068] In order to use the overall control circuit 100 to perform a controlled NOT operation on the lth target qubit, the lth target qubit ψ l NOT gate X l is placed in the target register. A control corresponding to the value l is then placed on each index qubit in the index register. In the exemplary overall control circuit 100, a black dot (e.g., dot 108) indicates that a control must be turned on, while an empty circle (e.g., empty circle 110) indicates that a control corresponding to the logical inverse of the input index qubit must be turned off.

[0069] For example, in order to perform an index operation X5 on the target qubit ψ5, the index register qubits are set to l0=0, l1=1, l2=0, l3=1, because the binary representation of 5 in the four-bit register is 0101. Therefore, only the controls for the index operation X5 in the overall control circuit all have a true value corresponding to being turned on, so that only the corresponding target qubit ψ5 is performed.

[0070] A first set of specific transformations applied to the overall control circuit 100 include removing some of the overall control circuit controls using the condition that the index register never encodes an out-of-range value l ≥ L. To illustrate, if Figure 1 X shown 10If the operation is not conditioned on the least significant bit of the index register, then X is also applied at l = 11. 10 This is applied to the target qubit. However, under the condition l < L, this is not a problem, and several controls can be omitted from the circuit under this condition. For each possible l, if the following conditions are true, then the corresponding X is considered l and the control on the b-th index qubit is removed: (i) the b-th bit of L - 1 is not set, and (ii) setting the b-th bit of l would cause l to change to a value greater than L - 1. Visually, as long as a run reaches the right side of the circuit, the "run" where the control must be turned off can be removed.

[0071] After removing the above controls, the remaining controls can be carefully extended into nested AND operations, where the nesting is such that the lower controls are inside the higher controls, and the control qubits associated with the AND operations are exactly below their lowest input qubits. Refer to the following Figure 2 for a description of an exemplary AND operation defined in terms of Toffoli gates and Clifford + T gates. Figure 3 Shows the transformed circuit achieved by removing the above total control circuit controls and extending the remaining controls into nested AND operations. By iteratively optimizing adjacent AND operations using the relationships shown below Figure 4 the circuit shown below Figure 3 is optimized into a unary iterative circuit, as described in the following reference Figure 5 .

[0072] Figure 2 Shows exemplary circuits 200 and 250 for computing and uncomputing AND operations. In Figure 2 the logical AND operation 202 between two control qubits 204 and 206 is represented as a qubit line 208 that emerges vertically from the two controls on control qubits 204 and 206 and then proceeds to the right. The uncomputing logical AND operation is represented as a qubit line 258 that enters from the left and then vertically merges into the two control qubits 204 and 206 that created it.

[0073] To compute logical AND operation 202, an auxiliary qubit 210 is obtained in the T state. A controlled NOT gate (CNOT gate) 212 is applied between control qubit 206 and auxiliary qubit 210. The Hermitian conjugate of T gate 214 is applied to auxiliary qubit 210. A controlled NOT gate 216 is applied between control qubit 204 and auxiliary qubit 210. A T gate 218 is applied to auxiliary qubit 210. A controlled NOT gate 220 is applied between control qubit 206 and auxiliary qubit 210. The Hermitian conjugate of T gate 222, Hadamard gate 224, and optional SWAP gate S226 are applied to auxiliary qubit 210 in sequence. Therefore, the T count for operation 202 is 4 (including the T gate required to prepare the T state of auxiliary qubit 210).

[0074] Undoing the computation logical AND operation 202 includes performing a measurement and correction process. Applying Hadamard gate 260 to auxiliary qubit 210. Measure 262 auxiliary qubit 210. If the measurement result resulting from measurement operation 262 indicates that both control qubits 204, 206 are ON, then applying CZ gate 264 to control qubits 204, 206. Undoing the computation T count is zero.

[0075] Figure 3 shows that by Figure 1 The overall control circuit 100 described above removes specific overall control circuit controls and expands the remaining controls into nested AND operations to implement the exemplary transformation circuit 300 .

[0076] The transformed circuit 300 shows a sawtooth pattern 302, wherein each tooth (eg, tooth 304) is similar to the above reference Figure 1 Describes the index negation operation X l Each tooth includes a corresponding nested AND calculation (e.g., nested AND operation 306) followed by a corresponding undo calculation of the same AND operation (e.g., undo calculation 308), which calculations and undo calculations are described above with reference to Figure 2 Give a description.

[0077] For example, first tooth 304 corresponds to indexing operation X0 and begins by calculating a first logical AND between the first control qubit and the logical inverse of the first index register qubit l0 representing the most significant index register bit. The result of this operation is stored in the second control qubit. A second logical AND is calculated between the second control qubit storing the result of the previous AND operation and the logical inverse of the second index register qubit l1 representing the second most significant index register bit. The result of this calculation is stored in the third control qubit. A third logical AND is calculated between the third control qubit storing the result of the previous AND operation and the logical inverse of the third index register qubit l2 representing the third most significant index register bit. The result of this calculation is stored in the fourth control qubit. A fourth logical AND is calculated between the fourth control qubit storing the result of the previous AND operation and the logical inverse of the fourth index register qubit l3 representing the fourth most significant (or in this example, least significant) index register bit, and the result is stored in the fifth (or in this example, last) control qubit. If the truth value of the fifth control qubit corresponds to on, the corresponding indexing operation X0 controlled by the fifth control qubit is performed on the target qubit ψ0. The control qubits described previously are then uncomputed in the reverse order of the order in which they were computed. Note that during the computation phase 306 and the uncomputation phase 308, the control qubits are made available sequentially.

[0078] Figure 4 400 is a diagram of how adjacent AND operations are optimized for three exemplary cases. There are a total of sixteen possible cases where AND undo computations are adjacent to AND computations, and they can all be optimized to NOT or controlled NOT gates in a similar manner. As shown in sub-diagram 402, for AND operations with adjacent undo computations 402a and recomputation 402b that have controls that must be turned on, these controls can be removed 402c. As shown in sub-diagram 404, AND operations with adjacent undo computations 404a and recomputation 404b (where the second qubit in AND recomputation 404b is a must-turn off control) can be replaced by a controlled NOT operation 404c with the first qubit used as a control on the third qubit. As shown in sub-diagram 406, the adjacent undo computation 406a and recomputation 406b of an AND operation (where both the first qubit and the second qubit in the AND recomputation must turn off the control) can be replaced by a controlled NOT operation 406c on the third qubit with the first qubit used as a control, followed by a controlled NOT operation 406d on the third qubit with the second qubit used as a control, followed by a NOT operation 406e on the third qubit. Each merge 402, 404, and 406 saves 4 T-gates.

[0079] Exemplary univariate iterative quantum circuit

[0080] Figure 5An exemplary unary iterative quantum circuit 500 for performing an index operation on a corresponding target qubit is shown. Figure 1 Consistently, an exemplary unary iterative quantum circuit 500 is shown to perform a controlled index operation X l , where 0≤l≤L=11, but the unary iterative quantum circuit can be used to perform other index operations, and can be used to perform index operations with fewer or more indices, as described below with reference to Figure 7 shown.

[0081] The exemplary unary iterative quantum circuit 500 includes an index register including four index qubits 502a-d. The index register is configured to encode an index value. In some implementations, the index register may be configured to encode only index values ​​within a range (i.e., index values ​​less than L).

[0082] The exemplary unary iterative quantum circuit 500 includes a control register including five control qubits 504a-e. The control qubits are interleaved with the index qubits to form a combined register, wherein the first control qubit 504a is at the top of the combined register, followed by the index qubit 502a representing the most significant bit, followed by the second control qubit 504b, followed by the second index qubit 502b representing the second most significant bit, and so on, until the penultimate control qubit 504d is followed by the index qubit 502d representing the least significant bit, and then the last control qubit 504e.

[0083] The exemplary unary iterative quantum circuit 500 includes a target register 506, which includes a plurality of target qubits. For convenience, the target register 506 is represented by Figure 5 is drawn as a single line.

[0084] The control register encodes the index value encoded in the index register via an iterative cascade 508 of multiple logical AND operations performed between pairs of corresponding control qubits and index qubits, where each control qubit 504a-e is available to the cascade of operations in turn and not in parallel (as described above with reference to Figure 1 At the end of the iterative cascade 508, the result of the logical AND operation 510 between the inverse of the index qubit 502d representing the least significant bit and the penultimate control qubit 504d storing the result of the previous logical AND operation is stored in the last control qubit 504e. Figure 2 Describe the circuits to implement each logical AND operation.

[0085] Exemplary unary iterative quantum circuit 500 repeatedly computes and uncomputes control qubits 504b-e to perform operations on corresponding target qubits in target register 506. The number of repetitions included in the unary iterative quantum circuit depends on the number of different operations that can be applied to the target register and / or the number of index qubits in the index register. For example, exemplary unary iterative quantum circuit 500 includes four index qubits 502a-d and eleven different operations (because the number of controlled X operations for different targets in the register is eleven). Therefore, in this case, the number of compute / undo computation repetitions is equal to 11-1=10 (intuitively, this is because if the numbers 1 to 10 are discerned, the number 11 can be unconditionally executed and then part of the 1 to 10 portion can be undone).

[0086] The repetition of computing and undoing the computation of the control qubit includes: if the last control qubit is in the on state, performing the operation on the target qubit to repeat, iteratively undoing the computation of multiple logical AND operations (as described below with reference to Fig. 9 ), performing a controlled NOT operation between the control qubit corresponding to the last undo logical AND operation and the next highest control qubit, wherein the next highest control qubit serves as a control for the controlled NOT operation, and iteratively calculating a plurality of logical AND operations to recalculate the last control qubit (as described below with reference to Fig. 9 described in more detail).

[0087] For example, in the first iteration, if the last control qubit 504e is in the on state, then operation X is performed on the target qubit corresponding to index value 0. Then no undo computation is performed on the logical AND operation (as described below with reference to Fig. 9 A controlled NOT operation is then performed between the last control qubit 504e and the next highest control qubit 504d. Since no undo computation is performed, no logical AND computation is performed.

[0088] In the second iteration, if the last control qubit 504e is in the on state, operation X is performed on the target qubit corresponding to index value 1. Then an undo calculation is performed on the logical AND operation (as described below with reference to Fig. 9 A controlled NOT operation is then performed between control qubit 504d and the next highest control qubit 504c. A logical AND operation is then calculated.

[0089] The circuit ends by undoing the cascade 508 of iterative computations of the logical AND operation using a second cascade 512 of undo computations. Each control qubit 504a-e is made available to undo the cascade 512 of computations sequentially rather than in parallel.

[0090] The exemplary univariate iterative quantum circuit 500 uses 10 logical AND operations. Since each AND operation requires 4 T gates (see above Figure 3 ), and there are no T gates to undo the computation, and there are no other T-consuming operations in the circuit, so the T count of circuit 500 is 40=4(L-1), in which case L=11.

[0091] Exemplary circuit 500 is a specific example of a univariate iterative quantum circuit, and there are various extensions or variations of circuit 500. For example, a univariate iterative quantum circuit can be constructed for any number of target qubits, two examples of which are described below. Figure 7 Given in.

[0092] As another example, a unary iterative quantum circuit can be used to perform Pauli operations on groups of qubits that are any function of an index register (usually precomputed). As another variant, the target of each individually controlled operation can be easily changed, and thus the qubits to which the operation is applied need not match the value of the index register. The index operation applied to the target register need not be the same across the target registers. For example, the index operation G l When l<10, it can be defined as G l =X l And when l≥10, it can be defined as G l =Y l , X l represents the Pauli X or NOT operation and Y l represents the Pauli Y operation. In addition, as follows Fig. 8A and Figure 8B As described, index operations may include range operations.

[0093] In some cases, as mentioned below Figure 6 As shown, the unary iterative quantum circuit can be optimized to reduce the circuit depth. In some cases, the unary iterative quantum circuit can be mapped, filtered, compressed, aggregated, batched, flattened, or grouped. The unary iterative quantum circuit can be applied to various settings, such as data loading, as described below with reference to Fig.10 and Fig.11 described.

[0094] Figure 6 An exemplary optimized iterative quantum circuit 600 is shown. Figure 5An optimized version of the exemplary unary iterative quantum circuit 500 shown. The exemplary unary iterative quantum circuit 500 is optimized by merging controlled NOT operations, thereby reducing the circuit depth. The merging strategy is as follows. Controlled NOTs can be merged when they are adjacent and have the same controls. In order to create this possible situation, the controlled NOTs must be moved around other controlled NOTs, and especially moved on top of other controlled NOTs. When the order of (i) the controlled NOT from qubit B to qubit C and (ii) the controlled NOT from qubit A to qubit B is interchanged, a third controlled NOT from qubit A to qubit C must be introduced to compensate for the fact that the interchanged operations do not commute. However, if this new operation can be merged with existing controlled NOTs, and interchanging the order of the original operations allows one of them to be merged with another controlled NOT operation, a small amount of depth savings can be achieved because, although one operation is introduced, two merges are performed. In the above Figure 5 In the specific case of , the order of the X1 controlled NOT and the controlled NOT to its left can be swapped. This will introduce an X1 that is controlled by in2h, but it can be merged into the controlled NOT already controlled by in2h. The original controlled X1 can then be merged into the controlled X0. The general strategy is to consider each operation in turn, shift it as far left as possible, and repeat until the circuit reaches a stable state. Then check if there are any operations that can be merged by shifting to the right without causing the introduction of new controlled NOTs and taking advantage of these opportunities.

[0095] exist Figure 7 The figure shows the ratio Figure 5 Another example of a unary iterative quantum circuit with fewer target qubits is shown. Figure 7 A second exemplary unary iterative quantum circuit 700 is shown having four target qubits, two index qubits, and three control qubits.

[0096] FIG8 shows an exemplary unary iterative quantum circuit 800 for performing a range index operation. Although circuit 800 shows the index register and the control register separately (and not as Figure 5 ), but the unary iteration technique performed by circuit 800 is equivalent to Figure 5 The circuit 500 performs a unary iteration technique.

[0097] In a range indexing operation, the operation G is applied to multiple target qubits, rather than just a single target qubit. An exemplary range operation is given in equation (2) below.

[0098]

[0099] In equation (2), G0·G1·…·G l-1 represents the application of operation G to the target qubits ψ0, ψ1, …, ψ l-1Range operation.

[0100] The unary iterative quantum circuits described in this specification can be extended and used to implement such range indexing operations using additional accumulator qubits (e.g., accumulator qubit 802). Each time the last control qubit 804 is calculated, a controlled NOT operation is performed between the additional accumulator qubit 802 and the last control qubit 804, where the last control qubit 804 serves as a control. Thus, accumulator qubit 802 will remain in the on state until l th The last control qubit 804 switches it to off. The accumulator qubit 802 will then remain in the off state. By adjusting the indexing operation to the accumulator qubit 802 instead of the last control qubit 804, the circuit can perform a range indexing operation.

[0101] Various extensions of circuit 800 are possible. For example, in some cases, multiple accumulator qubits can be used to perform multiple operations at different ranges. As another example, in some cases, a unary iterative quantum circuit can perform a range index operation and an index operation, such as Figure 8B As shown in circuit 850. Since the accumulator qubits can be cleared without repeating the unary iteration process, performing range index operations and index operations does not increase the T count.

[0102] Methods for performing indexing operations

[0103] Fig. 9 is a flow chart of an exemplary process 900 for performing an index operation using a unary iterative quantum circuit. For convenience, process 900 is described as being performed by a quantum computing device communicating with one or more classical computing devices located at one or more locations. For example, a properly programmed according to the present specification Fig.12 System 1200 can perform process 900.

[0104] The system encodes the index value in an index register including one or more index qubits (step 902). For example, as described above with reference to Figure 5 As shown, the system may include an index register having N qubits and encoding an index value l, where 0≤l≤2 N -1. In some cases, the index register may not respond to out-of-range values ​​l ≥ 2 N to encode.

[0105] The system encodes the index value in a control register including a plurality of control qubits (step 904). Encoding the index value in the control register can include iteratively computing a plurality of logical AND operations between pairs of corresponding control qubits and index qubits to store a result of a logical AND operation between an inverse of a least significant index qubit and a penultimate control qubit storing a result of a previous logical AND operation in a last control qubit.

[0106] For example, as mentioned above about Figure 5 As shown, the index qubits may be interleaved with the control qubits, with the first control qubit at the top of the combinatorial register followed by the most significant index qubit, followed by the second control qubit, followed by the second most significant index qubit, and so on, until the penultimate control qubit is followed by the least significant index qubit and then the last control qubit. In this case, iteratively computing multiple logical AND operations between pairs of corresponding control qubits and index qubits to store the result of the logical AND operation between the inverse of the least significant index qubit and the control qubit storing the result of the previous logical AND operation may include: for a first iteration, performing a logical AND operation between the first control qubit at the top of the combinatorial register (optionally prepared in an on state) and the inverse of the most significant index qubit. The result of the logical AND operation may then be stored in the second control qubit. In this manner, multiple control qubits are made available sequentially rather than in parallel, and correspond to a one-hot encoding of the stored index values.

[0107] For subsequent iterations, computing multiple logical AND operations between pairs of corresponding control qubits and index qubits to store the result of the logical AND operation between the inverse of the least significant index qubit and the control qubit storing the result of the previous logical AND operation can include: performing a logical AND operation between the control qubit storing the result of the logical AND operation of the previous iteration and the inverse of the index qubit of the iteration, and storing the result of the logical AND operation in the subsequent control qubit. For example, for the second iteration, this can include performing a logical AND operation between the second control qubit and the inverse of the second most significant index qubit. The result of the logical AND operation can then be stored in the third control qubit. For the last iteration, this can include performing a logical AND operation between the second to last control qubit and the inverse of the least significant index qubit. The result of the logical AND operation can then be stored in the last control qubit.

[0108] As mentioned above Figure 5 Described and referenced above Figure 2 As shown, in some implementations, performing a logical AND operation may include performing a temporary AND operation defined according to a Toffoli gate and a Clifford+T gate and requiring four T gates.

[0109] The system repeatedly computes and uncomputes the control qubits to perform an operation on a target qubit corresponding to the index value based on the state of the control qubit (step 906). Computing and uncomputing one or more control qubits may include: for each target qubit in turn, repeatedly

[0110] a) determining whether the last control qubit was in an on state, and performing an operation on a target qubit in response to determining that the last control qubit was in an on state;

[0111] b) determining the number of undo calculations of the iteratively calculated logical AND operation described with reference to step 904 to be performed;

[0112] c) performing the calculation of the cancellation of the determined quantity;

[0113] d) performing a controlled NOT operation between the control qubit corresponding to the last logical AND operation of the undo computation and the next highest control qubit, wherein the next highest control qubit serves as a control for the controlled NOT operation;

[0114] e) Iteratively computing multiple logical AND operations as described above with reference to step 904 to recalculate the final control qubit.

[0115] Determining the number of undo calculations to be performed of the iteratively calculated logical AND operation described with reference to step 904 includes determining how many bits are flipped when changing the binary representation of the index value corresponding to the last control qubit to the next one (or, equivalently, the number of times the base 10 index value can be divided by 2 before the result becomes a non-integer). The number of undo calculations to be performed is then equal to the determined number of required bit flips minus 1. Alternatively, the number of undo calculations to be performed is equal to the number of times the value of the next index value can be divided by 2 before a non-integer result is obtained.

[0116] For example, after each even index value, only one bit flip is needed to change the binary representation of the even index value to the next odd value. Therefore, after each even index value, no undo calculation is performed, and the above method includes only steps a) and d).

[0117] After each odd index value, a different number of bit flips are required to change the binary representation of the odd index value to the next even value. For example, to change the bit representation of the index value 3→011 to 4→100, three bit flips are required. Therefore, the number of undo calculations determined and performed at steps b) and c) above is equal to 2. Alternatively, the value 4 can be divided by 2 a total of 2 times before a non-integer result is obtained.

[0118] In some implementations, such as Figure 5As shown, the above steps a) to e) can be changed for the last target qubit in the circuit. Figure 5 As shown, with the last bit flip left, e.g., in this example, to change index value 9 to 10, steps d) and e) for target qubit 9 and steps a), b) and c) for target qubit 10 can be different. This is because the circuit is truncated at index value 10—there are no target qubits corresponding to index values ​​12 to 15—so the same amount of information does not need to be encoded into the last control qubit for previous index values. In fact, the encoded information in the second least significant bit is sufficient, and performing fewer AND / undo calculations can further reduce the T count.

[0119] The last question is also answered to some extent. Also, you use the second to last one here because it is OK, because there is no X 11 , so there is no need to make an extra distinction. In other words, the value of the second least significant bit is sufficient in this particular case. Then again, you'd want to do this if possible, because it saves one or more AND calculations that require expensive T gates.

[0120] In some implementations, the system may further undo the iteratively computed multiple logical AND operations between pairs of corresponding control qubits and index qubits (as described above with reference to step 902) to reset the index register to encode the index value.

[0121] As mentioned above Figure 5 As described above, the total number of AND operations included in the unary iterative circuit performing the index operation is equal to the total number of different operations on the target qubit 2 N Subtract 1. Therefore, in the implementation of performing AND operations, each AND operation requires 4 T gates, and the T count of the unary iterative circuit is 4 (2 N -1).

[0122] Application of unary iteration in data loading:

[0123] Fig.10 An exemplary data loading quantum circuit 1000 is shown. For convenience, the exemplary data loading quantum circuit 1000 is shown as being configured to load 8 data items, but in some cases the circuit may be expanded (or reduced) and configured to load any number of data items.

[0124] The exemplary data loading quantum circuit 1000 includes an index register 1002 including three index qubits. The uppermost index qubit represents the most significant bit, while the lowermost index qubit represents the least significant bit. Index register 1002 is configured to store an index value. Figure 5 As described, in some implementations, the index register may be configured to encode only in-range index values ​​(ie, index values ​​less than L).

[0125] The exemplary data loading quantum circuit 1000 includes a control register 1004 including four control qubits. Figure 5 The exemplary data loading quantum circuit 1000 also includes a data register 1006, which includes eight data qubits.

[0126] Control register 1004 encodes the index value encoded in index register 1002 via an iterative cascade of multiple logical AND operations performed between pairs of corresponding control qubits and index qubits, where each control qubit can be used by the cascade of operations sequentially rather than in parallel. Figure 5 At the end of the iterative cascade, the result of the logical AND operation between the inverse of the index qubit representing the least significant bit and the penultimate control qubit storing the result of the previous logical AND operation is stored in the last control qubit. Figure 2 Describe the circuits to implement each logical AND operation.

[0127] The exemplary data loading quantum circuit 1000 repeatedly computes and uncomputes a control qubit to load a data item (e.g., one of the data items d0-d7, corresponding to an index value) into a data register of a data qubit. Between each repetition, a controlled NOT operation is performed between the last uncomputed control qubit and the second highest control qubit, where the second highest control qubit is used as a control. For example, between repetition 1 and repetition 2, a controlled NOT gate 1008 is performed between the third control qubit and the second control qubit, where the second control qubit is used as a control. Between repetitions 2 and 3, a controlled NOT gate is performed between the second control qubit and the first control qubit, where the first control qubit is used as a control.

[0128] The number of repetitions included in the data loading quantum circuit depends on the number of different data loading operations and / or the number of index qubits in the index register. For example, the exemplary data loading quantum circuit 1000 includes three index qubits and eight different data loading operations. Therefore, in this case, the number of calculation / undo calculation repetitions is equal to 4.

[0129] The repetition of computing and undoing the computation of the control qubits includes iteratively computing one or more logical AND operations between pairs of control qubits and index qubits to store the computation results in the last control qubit. If the last control qubit is in the on state, a multi-target controlled NOT operation is performed on the data register qubits, wherein the last control qubit serves as a control for the multi-target controlled NOT operation. The multi-target controlled NOT operation depends on the binary encoding of the data item. For example, if the binary representation of the data item is 10000001, the multi-target controlled NOT operation may include a multi-target controlled NOT operation controlled by the last control qubit, the multi-target controlled NOT operation being directed to the qubits at offsets 0 and 7 in the data register, i.e., applying controlled NOT to the first qubit and the last qubit in the data register. As another example, if the binary representation of the data item is 00001111, the multi-target controlled NOT operation may include a multi-target controlled NOT operation controlled by the last control qubit, the multi-target controlled NOT operation being directed to the last four qubits in the data register.

[0130] A controlled NOT operation is then performed between the last control qubit and the penultimate control qubit, wherein the penultimate control qubit serves as a control for the controlled NOT operation. A multi-target controlled NOT operation is then performed on the data register qubits if the last control qubit is in the on state, wherein the multi-target controlled NOT operation is likewise dependent on the binary encoding of the data item. Pairs of control qubits and index qubits are then iteratively uncomputed.

[0131] The number of iterations and undo calculations performed in a repetition depends on which repetition is being executed. Figure 5 Describe the concept.

[0132] Data loading quantum circuit 1000 ends by undoing the cascade of iterative computations of the logical AND operation using a second cascade of undo computations, making each control qubit available to undo the cascade of computations sequentially rather than in parallel.

[0133] The data loading quantum circuit 1000 and its variants described above can be used to construct a "read-only" type of QRAM (referred to herein as QROM). QROM can use the data loading quantum circuit to read the classical data indexed by the quantum register, that is, to perform the transformation given in the following equation (3),

[0134]

[0135] In equation (3), l represents the index to be read, and d l represents the word at offset l in a classical list d containing L words (data items), where each word consists of D bits, and a lis an arbitrary magnitude. The left-hand side of equation (3) describes an arbitrary superposition over the L possible values ​​of the index register when the second register is in state |0>, and QROM d The left multiplication of indicates the application of the QROM circuit. The right hand side of equation (3) describes the state resulting from the application of the QROM circuit, which causes the data bit d in the second register to l Entangled with every possible computational basis state of the first register.

[0136] Since each of the D bits in each of the L words or data items from the QROM determines whether a controlled NOT gate exists, and all QROM bits may be set, the gate complexity of the data loading quantum circuit 1000 (and therefore the QROM construction) is O(LD). However, since controlled NOT is a Clifford operation, it is easy to apply. This is especially true for multi-target controlled NOT operations, which can be combined into a single braided operation in the surface code. The T count of the circuit comes entirely from the unary iterative process (and is independent of the data item size), and its T count is upper bounded by 4L-4.

[0137] Furthermore, since the T count is independent of the data item size, the data item size can be (artificially) increased without having to read d′ l =concat(d 2l ,d 2l+1 ) instead of d l to affect the T count. This changes the T count from 4L to 2L+4D, which is beneficial as long as D is less than L / 2.

[0138] Exemplary method for performing data loading

[0139] Fig.11 is used to use a unary iteration technique (e.g., Figures 5 to 9 1100 for loading data using a quantum computing device in communication with one or more classical computing devices located at one or more locations. For example, a program appropriately programmed according to the present specification Fig.12 The system 1200 can perform the process 1100.

[0140] The system encodes an index value in an index register including one or more index qubits (step 1102), where the index value can be obtained through the process of a larger quantum computation. For example, as described above with reference to Fig.10 As shown, the system may include an index register having N qubits and encoding an index value l, where 0≤l<2 N-1In some cases, the index register may not respond to out-of-range values ​​l ≥ 2 N-1 to encode.

[0141] The system encodes the index value in a control register including a plurality of control qubits (step 1104). Encoding the index value in the control register may include iteratively computing a plurality of logical AND operations between pairs of corresponding control qubits and index qubits to store the result of the logical AND operation between the inverse of the least significant index qubit and the penultimate control qubit storing the result of the previous logical AND operation in the last control qubit, as described above. Fig. 9 Detailed description of step 904.

[0142] The system repeatedly computes and uncomputes the control qubits to load data items corresponding to the index values ​​into data registers of the data qubits according to the states of the control qubits (step 1106). Computing and uncomputing one or more control qubits may include repeatedly:

[0143] a) determining whether the last control qubit is in the on state, and in response to determining that the last control qubit is in the on state, performing a multi-objective controlled-NOT operation on the data register qubits, wherein the multi-objective controlled-NOT operation depends on a binary encoding of the data item and the last control qubit serves as a control for the multi-objective controlled-NOT operation;

[0144] b) determining the number of undo calculations of the iteratively calculated logical AND operation described with reference to step 904 to be performed;

[0145] c) performing the calculation of the cancellation of the determined quantity;

[0146] d) performing a controlled NOT operation between the control qubit corresponding to the last logical AND operation of the undo computation and the next highest control qubit, wherein the next highest control qubit serves as a control for the controlled NOT operation;

[0147] e) Iteratively computing multiple logical AND operations as described above with reference to step 904 to recalculate the final control qubit.

[0148] As mentioned above Fig. 9 As described, determining the number of undo calculations to be performed for the iteratively calculated logical AND operation includes determining how many bits are flipped when changing the binary representation of the index value corresponding to the last control qubit to the next one (or, equivalently, the number of times the base 10 index value can be divided by 2 before the result becomes a non-integer). The number of undo calculations to be performed is then equal to the determined number of required bit flips minus 1. Alternatively, the number of undo calculations to be performed is equal to the number of times the value of the next index value can be divided by 2 before a non-integer result is obtained.

[0149] For example, for the first repetition, if the last control qubit is in the on state, a multi-target controlled NOT operation 1010 is performed on data register qubits 1006, where the multi-target controlled NOT operation 1010 depends on the binary encoding of the data item d0 and the last control qubit serves as a control for the multi-target controlled NOT operation 1010. The undo computation is then not performed. A controlled NOT operation 1012 is then performed between the last control qubit and the penultimate control qubit. The logical AND operation is then not performed.

[0150] As another example, for the sixth repetition, if the last control qubit is in the on state, a multi-target controlled NOT operation 1014 is performed on data register qubits 1006, where the multi-target controlled NOT operation 1014 depends on the binary encoding of data item d5 and the last control qubit serves as a control for the multi-target controlled NOT operation 1014. An undo computation is then performed. A controlled NOT operation 1016 is then performed between the penultimate control qubit and the next highest control qubit. A logical AND operation is then performed.

[0151] In some implementations, the system may further undo the iteratively computed multiple logical AND operations between pairs of corresponding control qubits and index qubits (as described above with reference to step 1102) to reset the index register to encode the index value.

[0152] Example Hardware

[0153] Fig.12 An exemplary system 1200 for implementing a unitary iterative quantum circuit and a data loading quantum circuit is depicted. System 1200 is an example of a system implemented as a quantum or classical computer program on one or more quantum computing devices or classical computers in one or more locations in which the systems, components, and techniques described below can be implemented.

[0154] System 1200 includes a quantum computing device 1202 in data communication with one or more classical processors 1204. For convenience, quantum computing device 1202 and classical processor 1204 are shown as separate entities, but in some implementations, one or more classical processors may be included in quantum computing device 1202.

[0155] The quantum computing device 1202 includes components for performing quantum computing, such as a quantum circuit 1206 , a control device 1208 , and a T-factory 1210 .

[0156] Quantum circuit 1206 includes components for implementing a unitary iterative quantum circuit 1212. For example, a quantum circuit may include a quantum system that includes one or more multi-level quantum subsystems, such as a register 1214 of qubits. The type of multi-level quantum subsystem utilized by system 1200 may vary. For example, in some implementations, the multi-level quantum subsystem may be a superconducting qubit, such as a Gmon or Xmon qubit. In some cases, it may be convenient to include one or more resonators attached to one or more superconducting qubits. In other cases, ion traps, photonic devices, or superconducting cavities (states can be prepared without qubits) may be used. Other examples of implementations of multi-level quantum subsystems include flux qubits, silicon quantum dots, or phosphorus impurity qubits.

[0157] Quantum circuits 1206 may be used to construct quantum circuits including different quantum logic operations, for example, single qubit gates, two qubit gates, and three qubit gates, such as described above with reference to Figure 2 The described logical AND operation. The constructed quantum circuit can be operated / implemented using a control device 1208. The type of control device 1208 included in the quantum system depends on the type of qubit included in the quantum computing device. For example, in some cases, the control device 1208 may include a device for controlling the frequency of the qubit included in the quantum circuit 1206, an excitation pulse generator, and a control circuit that couples the qubit to the excitation pulse generator. The control device can then adjust the frequency of each qubit toward or away from the quantum gate frequency of the excitation pulse on the corresponding control transmission system. The control device 1208 may also include a measurement device, such as a readout resonator. The measurement results obtained via the measurement device can be provided to the classical processor 1204 for processing and analysis.

[0158] The digital and / or quantum subject matter and implementations of digital functional operations and quantum operations described in this specification may be implemented in digital electronic circuits, suitable quantum circuits (or more specifically quantum computing systems), in tangibly embodied digital and / or quantum computer software or firmware, in digital and / or quantum computer hardware, including the structures disclosed in this application and their equivalents, or in a combination of one or more of them. The term "quantum computing system" may include, but is not limited to, a quantum computer, a quantum information processing system, a quantum cryptographic system, or a quantum simulator.

[0159] The implementation of the digital and / or quantum subject matter described in this specification can be implemented as one or more digital and / or quantum computer programs, that is, one or more modules of digital and / or quantum computer program instructions encoded on a tangible non-transitory storage medium to be executed by a data processing device or to control the operation of the data processing device. The digital and / or quantum computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access storage device, one or more qubits, or a combination of one or more of them. Alternatively or additionally, the program instructions can be encoded on an artificially generated propagation signal capable of encoding digital and / or quantum information, such as a machine-generated electrical signal, optical signal, or electromagnetic signal, which is generated to encode digital and / or quantum information for transmission to a suitable receiver device to be executed by the data processing device.

[0160] The terms quantum information and quantum data refer to information or data carried, held or stored by a quantum system, wherein the smallest non-trivial system is a qubit, i.e., a system that defines a unit of quantum information. It should be understood that the term "qubit" encompasses all quantum systems that can be appropriately approximated as a two-level system in the corresponding context. Such quantum systems may include, for example, multi-level systems having two or more levels. For example, such systems may include atoms, electrons, photons, ions, or superconducting qubits. In many implementations, the computational basis state is identified as having a ground state and a first excited state, but it should be understood that other arrangements are possible in which the computational state is identified as having a higher order excited state.

[0161] The term "data processing device" refers to digital and / or quantum data processing hardware, and covers various devices, equipment and machines for processing digital and / or quantum data, including, for example, programmable digital processors, programmable quantum processors, digital computers, quantum computers, multiple digital and quantum processors or computers and combinations thereof. The device may also be or also include a dedicated logic circuit, such as an FPGA (field programmable gate array), an ASIC (application-specific integrated circuit) or a quantum simulator, i.e., a quantum data processing device designed to simulate or generate information about a specific quantum system. In particular, a quantum simulator is a dedicated quantum computer that does not have the ability to perform general-purpose quantum computations. In addition to the hardware, the device may additionally include code that creates an execution environment for a digital and / or quantum computer program, for example, code constituting processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.

[0162] A digital computer program (which may also be referred to or described as a program, software, software application, module, software module, script or code) may be written in any form of programming language, including compiled or interpreted languages ​​or declarative or procedural languages, and it may be deployed in any form, including as a stand-alone program or as a module, component, subroutine or other unit suitable for use in a digital computing environment. A quantum computer program (which may also be referred to or described as a program, software, software application, application, module, software module, script or code) may be written in any form of programming language, including compiled or interpreted languages ​​or declarative or procedural languages, and translated into a suitable quantum programming language, or may be written in a quantum programming language (e.g., QCL or Quipper).

[0163] A digital and / or quantum computer program may, but need not, correspond to a file in a file system. A program may be stored in a portion of a file that stores other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files storing one or more modules, subroutines, or code portions). A digital and / or quantum computer program may be deployed to execute on a digital or quantum computer, or on multiple digital and / or quantum computers located at a site or distributed between multiple sites and interconnected by a digital and / or quantum data communication network. A quantum data communication network is understood to be a network that can use a quantum system (e.g., qubit) to transmit quantum data. Typically, a digital data communication network cannot transmit quantum data, but a quantum data communication network can transmit quantum data and digital data.

[0164] The processes and logic flows described in this specification can be performed by one or more programmable digital and / or quantum computers, operating appropriately with one or more digital and / or quantum processors, executing one or more digital and / or quantum computer programs to perform functions by operating on input digital and quantum data and generating output. The processes and logic flows can also be performed by a dedicated logic circuit (e.g., an FPGA or ASIC or a quantum simulator) and the apparatus can also be implemented as the dedicated logic circuit, or by a combination of a dedicated logic circuit or a quantum simulator and one or more programmed digital and / or quantum computers.

[0165] For a system of one or more digital and / or quantum computers to be "configured" to perform a particular operation or action, this means that the system has installed thereon software, firmware, hardware, or a combination thereof that, when operated, causes the system to perform those operations or actions. For one or more digital and / or quantum computer programs to be configured to perform a particular operation or action, this means that the one or more programs include instructions that, when executed by a digital and / or quantum data processing device, cause the device to perform the operation or action. A quantum computer can receive instructions from a digital computer that, when executed by a quantum computing device, cause the device to perform an operation or action.

[0166] A digital and / or quantum computer suitable for executing a digital and / or quantum computer program may be based on a general or special purpose digital and / or quantum processor or both, or any other kind of central digital and / or quantum processing unit. Typically, the central digital and / or quantum processing unit will receive instructions and digital and / or quantum data from a read-only memory, a random access memory, or a quantum system suitable for transmitting quantum data (e.g., photons), or a combination thereof.

[0167] The basic elements of a digital and / or quantum computer are a central processing unit for running or executing instructions and one or more memory devices for storing instructions and digital and / or quantum data. The central processing unit and the memory can be supplemented by or incorporated into a dedicated logic circuit or a quantum simulator. Typically, a digital and / or quantum computer will also include or be operably coupled to receive digital and / or quantum data from one or more mass storage devices, or to transfer digital and / or quantum data to one or more mass storage devices (e.g., magnetic disks, magneto-optical disks, optical disks, or quantum systems suitable for storing quantum information) in order to store digital and / or quantum data. However, a digital and / or quantum computer does not need to have such a device.

[0168] Digital and / or quantum computer readable media suitable for storing digital and / or quantum computer program instructions and digital and / or quantum data include all forms of non-volatile digital and / or quantum memory, media and memory devices, including, for example, semiconductor memory devices, such as EPROM, EEPROM and flash memory devices; magnetic disks, such as internal hard disks or removable disks; magneto-optical disks; and CD ROM and DVD-ROM disks; and quantum systems, such as trapped atoms or electrons. It will be understood that quantum memory is a device capable of storing quantum data for a long time with high fidelity and efficiency, such as a light-matter interface, where light is used for transmission and matter is used to store and preserve quantum features of quantum data, such as superposition or quantum coherence.

[0169] The control of the various systems or parts thereof described in this specification may be implemented in a digital and / or quantum computer program product, which includes instructions stored on one or more non-transitory machine-readable storage media and can be executed on one or more digital and / or quantum processing devices. The systems or parts thereof described in this specification may each be implemented as an apparatus, method or system, which may include one or more digital and / or quantum processing devices and a memory for storing executable instructions to perform the operations described in this specification.

[0170] Although the present application contains many specific implementation details, these details should not be interpreted as limitations on the scope of the claimed protection, but should be interpreted as descriptions of features that may be specific to a particular implementation. Certain features described in the present application in the context of a separate implementation may also be implemented in combination in a single implementation. In contrast, different features described in the context of a single implementation may also be implemented separately or in any suitable sub-combination in multiple implementations. In addition, although features may be described above as working in certain combinations and even as originally claimed, in some cases, one or more features in the claimed combination may be deleted from the combination, and the claimed combination may point to a sub-combination or a change in the sub-combination.

[0171] Similarly, although operations are depicted in a particular order in the accompanying drawings, this should not be understood as requiring that such operations be performed in the particular order shown or in a sequential order, or that all of the operations shown be performed to achieve the desired results. In some cases, multitasking and parallel processing may be advantageous. In addition, the separation of various system modules and components in the implementations described above should not be understood as requiring such separation in all implementations, but it should be understood that the described program components and systems can generally be integrated together into a single software product or packaged into multiple software products.

[0172] Specific implementations of the subject matter have been described. Other implementations are within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve the desired results. As an example, the processes depicted in the accompanying drawings do not necessarily require the particular order or sequential order shown to achieve the desired results. In some cases, multitasking and parallel processing may be advantageous.

Claims

1. A method performed by a quantum computing device, the method comprising: Applying a unary iterative quantum circuit to the plurality of qubits to perform a single-qubit unitary operation on an l-th target qubit in the register of target qubits, where l represents an integer between zero and a maximum index value L, and performing the single-qubit unitary operation is conditioned on a value encoded in an index register comprising the plurality of index qubits being equal to l, where The plurality of qubits include a plurality of control qubits, a first target qubit, and a plurality of index qubits; The index register is configured to encode a binary representation of a plurality of index values, the plurality of index values ​​comprising integers between zero and a maximum index value L; and The univariate iterative quantum circuit includes: For each index value in the plurality of index values ​​that is less than the largest index value in the plurality of index values, when i) is applied to the index value and 2 b The result of the bitwise OR operator is greater than or equal to the maximum index value and ii) is applied to the maximum index value minus one and 2 b The result of the bitwise AND operator is equal to 2 b When , the realization of single-qubit unitary operation excludes the representation 2 b Controls on the index qubits; One or more implementations of a single qubit unitary operation include corresponding controls on an index qubit, wherein the corresponding controls on the index qubit include nested AND computations and undo computations; one or more groups of controlled NOT and NOT operations, wherein each group of controlled NOT and NOT operations implements adjacent AND calculations and AND recalculations including nested AND calculations and undo calculations with different control types; and One or more controlled NOT operations, wherein each controlled NOT operation implements adjacent AND undo computations and AND recomputations including nested AND computations and undo computations having a pair of different control types.

2. The method of claim 1, wherein: The single-qubit unitary operation is a range operation, the plurality of qubits further include one or more accumulator qubits, and the unary iterative circuit further includes, when computing a final control qubit, a controlled NOT operation between the corresponding accumulator qubit and the last control qubit, wherein the last control qubit serves as a control for the controlled NOT operation.

3. The method of claim 1, wherein: The plurality of qubits includes one or more accumulator qubits, and when computing a final control qubit, a controlled NOT operation is performed between the corresponding accumulator qubit and the final control qubit, wherein the final control qubit serves as a control for the controlled NOT operation.

4. The method of claim 1 , further comprising encoding a plurality of index values ​​in a control qubit of a unary iterative quantum circuit, the encoding comprising, for each index value: A plurality of logical AND operations between corresponding pairs of control qubits and index qubits are iteratively calculated to store a result of a logical AND operation between the inverse of a least significant index qubit and a penultimate control qubit storing a result of a previous logical AND operation in a last control qubit.

5. The method of claim 1, wherein: The single-qubit unitary operation includes a range operation, the unary iterative quantum circuit also includes an accumulator qubit, and the unary iterative circuit includes a controlled NOT operation between the accumulator qubit and a last control qubit of each iteration, the last control qubit of the iteration serving as a control bit.

6. The method of claim 1, wherein: The Undo Calculate and Recalculate controls are nested so that the lower controls are inside the higher controls.

7. The method of claim 1, wherein: and control qubits associated with undoing computation and recomputing are placed directly below its lowest input qubit.

8. The method of claim 1, wherein: The total number of AND undo calculations and recalculations included in the unary iterative circuit is equal to the total number N of target qubits minus 1.

9. The method of claim 1, wherein: Performing a single-qubit unitary operation has a T count of 4(L-1), where L represents the upper limit of the value stored in the index register.

10. An apparatus comprising: Quantum computing hardware includes: A quantum circuit for implementing a univariate iterative quantum circuit, the quantum circuit comprising: an index register comprising a plurality of index qubits, wherein the index register is configured to encode a binary representation of a plurality of index values, the plurality of index values ​​comprising integers between zero and a maximum index value L; a control register, comprising a plurality of control qubits; a system register, including a plurality of target qubits; one or more control devices configured to operate the quantum circuit; a classical processor in data communication with the quantum computing hardware, wherein the classical processor is configured to process and analyze measurements obtained from the control device; Wherein, the apparatus is configured to cause a quantum circuit to perform an operation comprising: Applying a unary iterative quantum circuit to the plurality of qubits to perform a single-qubit unitary operation on an lth target qubit in a register of target qubits, where l represents an integer between zero and a maximum index value L, and performing the single-qubit unitary operation is conditioned on a value encoded in the register including the index being equal to l, where The plurality of qubits includes a plurality of control qubits, a first target qubit, and a plurality of index qubits; and The univariate iterative quantum circuit includes: For each index value in the plurality of index values ​​that is less than the largest index value in the plurality of index values, when i) is applied to the index value and 2 b The result of the bitwise OR operator is greater than or equal to the maximum index value and ii) is applied to the maximum index value minus one and 2 b The result of the bitwise AND operator is equal to 2 b When , the realization of single-qubit unitary operation excludes the representation 2 b Controls on the index qubits; One or more implementations of a single qubit unitary operation include corresponding controls on an index qubit, wherein the corresponding controls on the index qubit include nested AND computations and undo computations; one or more groups of controlled NOT and NOT operations, wherein each group of controlled NOT and NOT operations implements adjacent AND calculations and AND recalculations including nested AND calculations and undo calculations with different control types; and One or more controlled NOT operations, wherein each controlled NOT operation implements adjacent AND undo computations and AND recomputations including nested AND computations and undo computations having a pair of different control types.

11. The device of claim 10, wherein: The single-qubit unitary operation is a range operation, the plurality of qubits further include one or more accumulator qubits, and the unary iterative circuit further includes, when computing a final control qubit, a controlled NOT operation between the corresponding accumulator qubit and the last control qubit, wherein the last control qubit serves as a control for the controlled NOT operation.

12. The device of claim 10, wherein: The plurality of qubits includes one or more accumulator qubits, and when computing a final control qubit, a controlled NOT operation is performed between the corresponding accumulator qubit and the final control qubit, wherein the final control qubit serves as a control for the controlled NOT operation.

13. The device of claim 10, wherein: The operations also include encoding a plurality of index values ​​in a control register of a unary iterative quantum circuit, the control register comprising a plurality of control qubits, the encoding comprising, for each index value: A plurality of logical AND operations between corresponding pairs of control qubits and index qubits are iteratively calculated to store a result of a logical AND operation between the inverse of a least significant index qubit and a penultimate control qubit storing a result of a previous logical AND operation in a last control qubit.

14. The device of claim 10, wherein: The single-qubit unitary operation includes a range operation, the unary iterative quantum circuit also includes an accumulator qubit, and the unary iterative circuit includes a controlled NOT operation between the accumulator qubit and a last control qubit of each iteration, the last control qubit of the iteration serving as a control bit.

15. The device of claim 10, wherein: The Undo Calculate and Recalculate controls are nested so that the lower controls are inside the higher controls.

16. The device of claim 10, wherein: and control qubits associated with undoing computation and recomputing are placed directly below its lowest input qubit.

17. The device of claim 10, wherein: The total number of AND undo calculations and recalculations included in the unary iterative circuit is equal to the total number N of target qubits minus 1.

18. The device of claim 10, wherein: Performing a single-qubit unitary operation has a T count of 4(L-1), where L represents the upper limit of the value stored in the index register.

19. A method for performing unary iteration using a quantum computing device including a unary iterative quantum circuit to implement an index operation, the method comprising: Construct a unary iterative circuit, including: defining an overall control circuit for implementing an index operation, the overall control circuit comprising a control register comprising a plurality of control qubits, one or more target qubits, and an index register comprising a plurality of index qubits, wherein the index register is configured to encode a plurality of index values; Applying a set of transformations to the overall control circuit to generate a first transformed circuit includes, for each index value of a plurality of index values ​​less than a maximum index value: When i) is applied to the index value and 2 b The result of the bitwise OR operator is greater than or equal to the maximum index value and ii) is applied to the maximum index value minus one and 2 b The result of the bitwise AND operator is equal to 2 b When removing the expression 2 b controls for index operations on the index qubits of ; and Extend the remaining controls of the index operation to nested AND operations; and The constructed unary iteration circuit is applied to an index register, a control register, and one or more targets.

20. An apparatus comprising: Quantum computing hardware includes: A quantum circuit for implementing a unary iterative quantum circuit to perform an index operation, the quantum circuit comprising: an index register comprising a plurality of index qubits, wherein the index register is configured to encode a binary representation of a plurality of index values, the plurality of index values ​​comprising integers between zero and a maximum index value L; a control register, comprising a plurality of control qubits; a system register, including a plurality of target qubits; one or more control devices configured to operate the quantum circuit; a classical processor in data communication with the quantum computing hardware, wherein the classical processor is configured to process and analyze measurements obtained from the control device; Wherein, the apparatus is configured to cause a quantum circuit to perform an operation comprising: Construct a unary iterative circuit, including: defining an overall control circuit for implementing an index operation, the overall control circuit comprising a control register comprising a plurality of control qubits, one or more target qubits, and an index register comprising a plurality of index qubits, wherein the index register is configured to encode a plurality of index values; Applying a set of transformations to the overall control circuit to generate a first transformed circuit includes, for each index value of a plurality of index values ​​less than a maximum index value: When i) is applied to the index value and 2 b The result of the bitwise OR operator is greater than or equal to the maximum index value and ii) is applied to the maximum index value minus one and 2 b The result of the bitwise AND operator is equal to 2 b When removing the expression 2 b controls for index operations on the index qubits of ; and Extend the remaining controls of the index operation to nested AND operations; and The constructed unary iteration circuit is applied to an index register, a control register, and one or more targets.

21. The method of claim 19 or the apparatus of claim 20, wherein: The index operation includes an operation of loading a data item corresponding to an index value of an lth target qubit among the one or more target qubits conditionally on the states of the plurality of control qubits, where l represents an integer between zero and a maximum index value L.

22. A method for performing unary iteration to implement an index operation using a quantum computing device including a unary iterative quantum circuit, the method comprising: Construct a unary iterative circuit, including: defining an overall control circuit for implementing the index operation, the overall control circuit comprising a control register comprising a plurality of control qubits, one or more target qubits, and an index register comprising a plurality of index qubits, wherein the index register is configured to encode a plurality of index values; A set of optimizations are applied to the overall control circuit to generate a unary iterative circuit, including, for each adjacent AND undo computation and AND recomputation: When the adjacent and undo calculation and recalculation control types match, removing the adjacent and undo calculation and recalculation; When the control types of adjacent and undo calculations and AND recalculations do not match, replacing the adjacent and undo calculations and AND recalculations with controlled NOT and NOT operations; and When one of the pairs of control types of adjacent and undo calculations and and recalculation matches, adjacent and undo calculations and and recalculation are replaced with a controlled negation operation; and The constructed unary iteration circuit is applied to an index register, a control register, and one or more targets.

23. An apparatus comprising: Quantum computing hardware includes: A quantum circuit for implementing a unary iterative quantum circuit to perform an index operation, the quantum circuit comprising: an index register comprising a plurality of index qubits, wherein the index register is configured to encode a binary representation of a plurality of index values, the plurality of index values ​​comprising integers between zero and a maximum index value L; a control register, comprising a plurality of control qubits; a system register, including a plurality of target qubits; one or more control devices configured to operate the quantum circuit; a classical processor in data communication with the quantum computing hardware, wherein the classical processor is configured to process and analyze measurements obtained from the control device; Wherein, the apparatus is configured to cause a quantum circuit to perform an operation comprising: Construct a unary iterative circuit, including: defining an overall control circuit for implementing the index operation, the overall control circuit comprising a control register comprising a plurality of control qubits, one or more target qubits, and an index register comprising a plurality of index qubits, wherein the index register is configured to encode a plurality of index values; A set of optimizations are applied to the overall control circuit to generate a unary iterative circuit, including, for each adjacent AND undo computation and AND recomputation: When the adjacent and undo calculation and recalculation control types match, removing the adjacent and undo calculation and recalculation; When the control types of adjacent and undo calculations and AND recalculations do not match, replacing the adjacent and undo calculations and AND recalculations with controlled NOT and NOT operations; and When one of the pairs of control types of adjacent and undo calculations and and recalculation matches, adjacent and undo calculations and and recalculation are replaced with a controlled negation operation; and The constructed unary iteration circuit is applied to an index register, a control register, and one or more targets.

24. The method of claim 22 or the apparatus of claim 23, wherein: The index operation includes an operation of loading a data item corresponding to an index value of an lth target qubit among the one or more target qubits conditionally on the states of the plurality of control qubits, where l represents an integer between zero and a maximum index value L.

25. A method for operating a quantum read-only memory, the method comprising: Applying a unary iterative quantum circuit to the plurality of qubits to load a data item corresponding to the index value of the lth data qubit in the data qubit register conditional on the state of the plurality of control qubits by index operation, where l represents an integer between zero and a maximum index value L, wherein The plurality of qubits include a plurality of control qubits, a first data qubit, and a plurality of index qubits; The index register is configured to encode a binary representation of a plurality of index values, the plurality of index values ​​comprising integers between zero and a maximum index value L; and The univariate iterative quantum circuit includes: For each index value in the plurality of index values ​​that is less than the largest index value in the plurality of index values, when i) is applied to the index value and 2 b The result of the bitwise OR operator is greater than or equal to the maximum index value and ii) is applied to the maximum index value minus one and 2 b The result of the bitwise AND operator is equal to 2 b When the index operation is implemented, it excludes the representation 2 b Controls on the index qubits; One or more implementations of an indexing operation include corresponding controls on indexing qubits, where The corresponding controls on the index qubit include nesting and computation and undoing computation; one or more groups of controlled NOT and NOT operations, wherein each group of controlled NOT and NOT operations implements adjacent AND calculations and AND recalculations including nested AND calculations and undo calculations with different control types; and One or more controlled NOT operations, wherein each controlled NOT operation implements adjacent AND undo computations and AND recomputations including nested AND computations and undo computations having a pair of different control types.

26. An apparatus comprising: Quantum computing hardware includes: A quantum circuit for implementing a unary iterative quantum circuit to perform an index operation, the quantum circuit comprising: an index register comprising a plurality of index qubits, wherein the index register is configured to encode a binary representation of a plurality of index values, the plurality of index values ​​comprising integers between zero and a maximum index value L; a control register, comprising a plurality of control qubits; a system register, including a plurality of target qubits; one or more control devices configured to operate the quantum circuit; a classical processor in data communication with the quantum computing hardware, wherein the classical processor is configured to process and analyze measurements obtained from the control device; Wherein, the apparatus is configured to cause a quantum circuit to perform an operation comprising: Applying a unary iterative quantum circuit to the plurality of qubits to load a data item corresponding to the index value of the lth data qubit in the data qubit register conditional on the state of the plurality of control qubits by index operation, where l represents an integer between zero and a maximum index value L, wherein The plurality of qubits includes a plurality of control qubits, a first data qubit, and a plurality of index qubits; and The unary iterative circuit includes: For each index value in the plurality of index values ​​that is less than the largest index value in the plurality of index values, when i) is applied to the index value and 2 b The result of the bitwise OR operator is greater than or equal to the maximum index value and ii) is applied to the maximum index value minus one and 2 b The result of the bitwise AND operator is equal to 2 b When the index operation is implemented, it excludes the representation 2 b Controls on the index qubits; One or more implementations of the index operation include corresponding controls on the index qubit, wherein the corresponding controls on the index qubit include nested AND computations and undo computations; one or more groups of controlled NOT and NOT operations, wherein each group of controlled NOT and NOT operations implements adjacent AND calculations and AND recalculations including nested AND calculations and undo calculations with different control types; and One or more controlled NOT operations, wherein each controlled NOT operation implements adjacent AND undo computations and AND recomputations including nested AND computations and undo computations having a pair of different control types.

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