Display panel

Abstract

The invention discloses a display panel. The display panel comprises a gate drive circuit with N cascaded GOA units, the N GOA units are arranged in the first direction, each GOA unit comprises a first output module, a signal generation module and a second output module which are arranged in the second direction, the first output module is used for outputting a first gate drive signal, and the second output module is used for outputting a second gate drive signal. The first output module is used for outputting a first gate driving signal, the second output module is used for outputting a second gate driving signal, the first gate driving signal and the second gate driving signal are different, and the length of the first output module and the length of the second output module are different; the two output modules which output different gate drive signals and have different lengths are arranged on the two sides of the signal generation module, so that the two output modules have enough width in the first direction, and the performance of transistors in the two output modules is guaranteed; the technical problem that frames are increased due to the fact that the two output modules are stacked on the same side is solved, and the narrow-frame design is achieved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel. Background Art

[0002] OLED (Organic Light-Emitting Diode) display technology is a new type of display technology. It has gradually attracted people's attention with its unique advantages such as low power consumption, high saturation, fast response time and wide viewing angle, and occupies a certain position in the field of panel display technology.

[0003] In the related art, the pixel driving circuit of the OLED display panel is usually an 8T2C circuit. For the pixel driving circuit, a complementary metal oxide semiconductor (CMOS) gate driving circuit (Gate On Array, GOA) is currently proposed to solve the technical problem of high power consumption of the conventional gate driving circuit.

[0004] Since the CMOS GOA circuit needs to generate two gate drive signals, Nout and Pout, the gate drive circuit is provided with two buffer parts corresponding to Nout and Pout respectively. The existing signal generating part is usually arranged close to the frame, and the buffer part is usually arranged close to the display area. The two buffer parts may overlap in the vertical direction. When the longitudinal size of each level of GOA unit is limited, the size of the two buffer parts in the vertical direction will become smaller. In order to ensure the performance of the transistors in Nout and Pout, the size of the buffer part in the horizontal direction needs to be increased. It is necessary to reserve a wider area on the frame of the product to set the gate drive circuit, which is contrary to the narrow frame design of the product. Summary of the invention

[0005] The present application provides a display panel to improve the technical problem of the existing display device having an overly large frame.

[0006] To solve the above-mentioned problems, the technical solutions provided by this application are as follows:

[0007] The present application provides a display panel, which includes a display portion and a gate driving circuit located on one side of the display portion, wherein the gate driving circuit includes N cascaded GOA units, and the N GOA units are arranged along a first direction; wherein each of the GOA units includes a signal generating module, a first output module, and a second output module arranged along a second direction;

[0008] The first output module is disposed on a side of the signal generating module close to the display unit, and the first output module is used to output a first gate driving signal;

[0009] The second output module is arranged at a side of the signal generating module away from the display unit, and the second output module is used to output a second gate driving signal, and the first gate driving signal and the second gate driving signal are different;

[0010] Among them, in the second direction, the lengths of the first output module and the second output module are different, the second direction is parallel to the scan line of the display panel, the angle between the first direction and the second direction is greater than 0° and less than or equal to 90, and N is a positive integer.

[0011] Beneficial effect: The present application arranges two output modules that output different gate drive signals and have different lengths on both sides of the signal generating module, so that the two output modules have sufficient width in the first direction, thereby ensuring the performance of the transistors in the two output modules, avoiding the technical problem of increased borders due to stacking two output modules on the same side, and realizing a narrow border design. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0013] Figure 1 A simplified structural diagram of the display panel of this application;

[0014] Figure 2 This is a simplified structural diagram of the gate driving circuit in the display panel of the present application;

[0015] Figure 3 This is a first equivalent circuit diagram of a gate driving circuit in a display panel of the present application;

[0016] Figure 4 This is a timing control diagram of a gate driving circuit in a display panel of the present application;

[0017] Figure 5 A second equivalent circuit diagram of a gate driving circuit in a display panel of the present application;

[0018] Figure 6 This is a schematic diagram of the film layer in the display panel of this application;

[0019] Figure 7 A film layer diagram of the first gate layer in the display panel of the present application;

[0020] Figure 8 A film layer diagram of the second gate layer in the display panel of the present application;

[0021] Fig. 9 A film layer diagram of a first gate layer and a second gate layer superimposed in a display panel of the present application;

[0022] Fig.10 A film layer diagram of the third gate layer in the display panel of the present application;

[0023] Fig.11 A film layer diagram of the superposition of the second gate layer and the third gate layer in the display panel of the present application;

[0024] Fig.12 A film layer diagram of the first active layer in the display panel of the present application;

[0025] Fig.13 A film layer diagram of a first gate layer, a second gate layer, a third gate layer, a first active layer and a second active layer superimposed in the display panel of the present application;

[0026] Fig.14 A film layer diagram of the second active layer in the display panel of the present application;

[0027] Fig.15 A film layer diagram of the first source and drain electrode layer in the display panel of the present application;

[0028] Fig.16 This is a superimposed film layer diagram of the first active layer, the second active layer and the first source and drain layer of the display panel of the present application;

[0029] Fig.17 This is a superimposed film layer diagram of the first gate layer, the second gate layer and the first source and drain layer of the present application;

[0030] Fig.18 A film layer diagram of the second source and drain electrode layer in the display panel of the present application;

[0031] Fig.19 A film layer diagram of a first source-drain electrode layer and a second source-drain electrode layer in a display panel of the present application;

[0032] Fig. 20 A diagram showing the superimposed film layers of the first active layer, the second active layer and the second source and drain electrode layer in the display panel of the present application;

[0033] Fig.21 This is a diagram of the superimposed film layers of the first gate layer, the first source and drain layer, and the second source and drain layer in the display panel of the present application. DETAILED DESCRIPTION

[0034] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise stated, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the drawings; and "inside" and "outside" refer to the outline of the device.

[0035] In the relevant OLED display panel, a complementary metal oxide semiconductor gate drive circuit is usually used to solve the technical problem of high power consumption of the conventional gate drive circuit. Since the CMOS GOA circuit needs to generate two gate drive signals, Nout and Pout, the gate drive circuit is provided with two buffer parts corresponding to Nout and Pout respectively, and the existing signal generation part is usually set close to the frame, and the buffer part is usually set close to the display area, resulting in a wider area reserved on the frame of the product to set the buffer part, which is contrary to the narrow frame design of the product. Based on the above technical problems, this application proposes the following solution.

[0036] See also Figures 1 to 21 The present application provides a display panel 100, which may include a display portion 200 and a gate driving circuit 300 located on one side of the display portion 200, wherein the gate driving circuit 300 includes N cascaded GOA units 310, and the N GOA units 310 are arranged along a first direction X.

[0037] In this embodiment, each GOA unit 310 includes a signal generating module 10, a first output module 20 and a second output module 30 arranged along the second direction Y; the first output module 20 is arranged on a side of the signal generating module 10 close to the display unit 200, and the first output module 20 is used to output a first gate driving signal; the second output module 30 is arranged on a side of the signal generating module 10 away from the display unit 200, and the second output module 30 is used to output a second gate driving signal, and the first gate driving signal and the second gate driving signal are different.

[0038] In this embodiment, in the second direction Y, the lengths of the first output module 20 and the second output module 30 are different. The second direction Y is parallel to the scan line of the display panel 100 . The first direction X and the second direction Y are perpendicular. N is a positive integer.

[0039] In this embodiment, the angle between the first direction X and the second direction Y is greater than 0° and less than or equal to 90°; see Figure 2 , the second direction Y can be perpendicular to the first direction X.

[0040] The present application arranges two output modules that output different gate drive signals and have different lengths on both sides of the signal generating module 10, so that the two output modules have sufficient width in the first direction X, thereby ensuring the performance of the transistors in the two output modules, avoiding the technical problem of increasing the border due to stacking the two output modules on the same side, and realizing a narrow border design.

[0041] It should be noted that the first gate drive signal is a positive pulse signal, and the second gate drive signal is a negative pulse signal; and, within a frame time interval, the first signal output terminal Nout outputs two positive pulse signals, and the second signal output terminal Pout outputs one negative pulse signal; at the same time, the pulse width of a positive pulse signal is greater than the pulse width of a negative pulse signal.

[0042] Since the CMOS GOA circuit of the present application needs to output a first gate drive signal and a second gate drive signal, and the pulse width of the first gate drive signal is larger than the pulse width of the second gate drive signal, that is, the output load of the first output module 20 is larger than the output load of the second output module 30; therefore, in the present application, the width of the first output module 20 can be larger than the width of the second output module 30, so that the first output module 20 has a larger buffer space and a larger output load capacity.

[0043] It should be noted that since low-temperature polysilicon semiconductors have a larger leakage current and metal oxide transistors have a smaller leakage current, in order to reduce the leakage current of the first output module 20, the present application may set the transistors in the first output module 20 to a combination of low-temperature polysilicon transistors and metal oxide transistors.

[0044] See also Figure 2 The first output module 20 may include a first buffer unit 210 and a second buffer unit 220 arranged along the second direction Y, the first buffer unit 210 is arranged close to the signal generating module 10, and the second buffer unit 220 is arranged away from the signal generating module 10; the first buffer unit 210 includes a first output transistor T10, the first output transistor T10 includes a first active part T10A, the second buffer unit 220 includes a second output transistor T9, the second output transistor T9 includes a second active part T9A, the first active part T10A is a metal oxide semiconductor, and the second active part T9A is a low-temperature polysilicon semiconductor.

[0045] The present application configures the first output module 20 to be a combination of a low-temperature polysilicon transistor and a metal oxide transistor, and utilizes the high mobility of the low-temperature polysilicon transistor and the low leakage current of the metal oxide transistor to improve the device effect of the first output module 20 .

[0046] In the present embodiment, since the display area AA is also provided with a metal oxide semiconductor, that is, the metal oxide semiconductors in the non-display area NA and the display area AA can be formed in the same photomask process, and since the patterning densities of the metal oxide semiconductors in the non-display area NA and the display area AA are different, if the first output transistor T10 is disposed adjacent to the display area AA, the patterning density of the metal oxide semiconductor in the first output transistor T10 may deviate from the design value.

[0047] In the present application, the first output transistor T10 having a metal oxide semiconductor is arranged away from the display area AA, and the second output transistor T9 having a low-temperature polysilicon semiconductor is arranged close to the display area AA, so that the pattern of the metal oxide semiconductor of the first output transistor T10 is arranged away from the pattern of the metal oxide semiconductor in the display area AA, thereby avoiding the deviation of the spacing of the pattern of the metal oxide semiconductor in the non-display area NA from the design value due to the adjacent arrangement of the patterned metal oxide semiconductors in the display area AA and the non-display area NA.

[0048] See also Figure 2 , in the second direction Y, the length of the first output transistor T10 may be greater than the length of the second output transistor T9.

[0049] In this embodiment, the first output transistor T10 is a metal oxide transistor. Although the metal oxide transistor has a smaller leakage current, the mobility of the metal oxide transistor is relatively low. Therefore, in order to improve the driving capability of the first output transistor T10, the present application increases the length of the first output transistor T10 in the second direction Y as much as possible within a limited space to improve the driving capability of the first output transistor T10.

[0050] In the display panel 100 of the present application, the second output module 30 includes a third output transistor T6 and a fourth output transistor T7, the third output transistor T6 includes a third active portion T6A, the fourth output transistor T7 includes a fourth active portion T7A, the third active portion T6A and the fourth active portion T7A are low-temperature polycrystalline silicon semiconductors, and the third output transistor T6 and the fourth output transistor T7 are arranged in parallel along the first direction X.

[0051] In this embodiment, since the third output transistor T6 and the fourth output transistor T7 in the second output module 30 are both low-temperature polycrystalline silicon semiconductors with relatively high mobility, the transistors in the second output module 30 do not need to increase their length in the second direction Y to improve the driving capability of the third output transistor T6 and the fourth output transistor; at the same time, the second gate drive signal output by the second output module 30 is a negative pulse signal, and the pulse width of the negative pulse signal is smaller than the pulse width of the positive pulse signal output by the first output module 20, so the output load of the second output module 30 is lower than the output load of the first output module 20, and therefore the length of the first output module 20 in the second direction Y of the present application is smaller than the length of the second output module 30 in the second direction Y.

[0052] The technical solution of the present application is now described in conjunction with specific embodiments.

[0053] See also Figure 1 The display panel 100 includes a display area AA and a non-display area NA disposed adjacent to the display area AA, and a display unit 200 is disposed in the display area AA. Optionally, the non-display area NA surrounds the display area AA, so that the display area AA is surrounded by the non-display area NA. The display area AA is an area in the display panel 100 for performing a display function, and a plurality of display units for realizing the display function are disposed therein. The non-display area NA may be a frame area of ​​the display panel 100, and a functional component that assists the display unit in the display area AA to perform display may be disposed therein.

[0054] See also Figure 1 The lower side of the display area AA is provided with a binding terminal 400, which can be connected to an external circuit, and transmits the signal input by the external circuit to the data line, thereby driving the display panel 100 to display the picture. For example, the binding terminal 400 can be bound and connected to a chip or a flip chip film, etc., to provide power and driving signals for the display panel 100.

[0055] In this embodiment, a plurality of light emitting devices LED and sub-pixel circuits for driving the light emitting devices LED may be arranged in an array in the display area AA. The sub-pixel circuits may be pixel driving circuits such as 7T1C, 7T2C, and 8T2C, and this application does not impose any specific restrictions.

[0056] In this embodiment, the gate driving circuit 300 is disposed in the non-display area NA, and the gate driving circuit 300 can be disposed on both sides of the display area AA; the gate driving circuit 300 can include N cascaded GOA units 310, and the N GOA units 310 can be arranged along the first direction X. The structure of the GOA unit 310 can be various, for example Figure 3 The circuit structure in Figure 4 for Figure 3Timing control diagram.

[0057] by Figure 3 As an example, each GOA unit 310 may include:

[0058] The stage transmission signal selection module 301 is electrically connected between the start signal line STV and the fourth node O.

[0059] The pull-up control module 302 controls the potential of the first node K according to the potential of the fourth node O and the potential of the second clock signal line XCK.

[0060] The first filter module 303 is electrically connected between the fifth node W and the first node K. The control end of the first filter module 303 is electrically connected to the reset signal line RST.

[0061] The second filter module 304 is electrically connected between the fifth node W and the second node Q. The control end of the second filter module 304 receives the first gate driving signal of the N-2th stage.

[0062] The first inverting module 305 is connected between the first node K and the third node P.

[0063] The feedback module 306 is connected between the first node K and the third node P.

[0064] The first output module 20 is connected between the first node K and the first signal output terminal Nout, and is used for outputting a first gate driving signal.

[0065] The second output module 30 outputs a second gate driving signal according to the potential of the second node Q and the potential of the third node P.

[0066] The first storage capacitor C1, the first plate C1a of the first storage capacitor C1 is connected to the second node Q, and the second plate C1b of the first storage capacitor C1 is connected to the second signal output terminal Pout.

[0067] The voltage regulating module 307 has a first end electrically connected to the first low potential line Nvgl1 , a second end electrically connected to the gate of the first output transistor T10 , and a control end electrically connected to the third node P.

[0068] In this embodiment, in one frame, the gate drive circuit 300 includes stage S100 and stage S200. In stage S100, the pulses of each first gate drive signal and the pulses of each second gate drive signal are output, while in stage S200, the pulses of each first gate drive signal and the pulses of each second gate drive signal are not required.

[0069] In this embodiment, the level transfer signal selection module 301 includes a first-level transfer transistor T13 and a second-level transfer transistor T12, and the first-level transfer transistor T13 is a dual-gate transistor; the two gates of the first-level transfer transistor T13 and the gate of the second-level transfer transistor T12 are connected to the start signal line STV, the source of the first-level transfer transistor T13 is connected to the second low potential line Pvgl, the drain of the first-level transfer transistor T13 and the source of the second-level transfer transistor T12 are connected to the fourth node O, and the drain of the second-level transfer transistor T12 is connected to the third high potential line Pvgh2.

[0070] In this embodiment, the pull-up control module 302 includes a pull-up transistor T2, a gate of the pull-up transistor T2 is connected to the second clock signal line XCK, a source of the pull-up transistor T2 is connected to the fourth node O, and a drain of the pull-up transistor T2 is connected to the first node K.

[0071] In this embodiment, the first filtering module 303 includes a first filtering transistor T11 and a second storage capacitor C2, the gate of the first filtering transistor T11 and the third plate C2a of the second storage capacitor C2 are connected to the reset signal line RST, the source of the first filtering transistor T11 is connected to the first node K, and the drain of the first filtering transistor T11 and the fourth plate C2b of the second storage capacitor C2 are connected to the fifth node W.

[0072] In this embodiment, the second filtering module 304 includes a second filtering transistor T8, the gate of the second filtering transistor T8 is connected to the first signal output terminal Nout of the N-2th level GOA unit 310, the source of the second filtering transistor T8 is connected to the fifth node W, and the drain of the second filtering transistor T8 is connected to the second node Q.

[0073] In this embodiment, the first inversion module 305 includes a first inversion transistor T3 and a second inversion transistor T1, and the second inversion transistor T1 is a dual-gate transistor; the gate of the first inversion transistor T3 and the two gates of the second inversion transistor T1 are connected to the first node K, the source of the first inversion transistor T3 is connected to the third high potential line Pvgh2, the drain of the first inversion transistor T3 and the source of the second inversion transistor T1 are connected to the third node P, and the drain of the second inversion transistor T1 is connected to the second low potential line Pvgl.

[0074] In this embodiment, the feedback module 306 includes a first feedback transistor T4 and a second feedback transistor T5; wherein the gate of the first feedback transistor T4 is connected to the first clock signal line CK, the source of the first feedback transistor T4 is connected to the first node K, the drain of the first feedback transistor T4 is connected to the source of the second feedback transistor T5, the gate of the second feedback transistor T5 is connected to the third node P, and the drain of the second feedback transistor T5 is connected to the second high potential line Pvgh1.

[0075] In this embodiment, the voltage regulating module 307 includes a regulating transistor T14, which is a dual-gate transistor; the two gates of the regulating transistor T14 are connected to the third node P, the source of the regulating transistor T14 is connected to the first node K, and the drain of the regulating transistor T14 is connected to the first low potential line Nvgl1.

[0076] In this embodiment, the first output module 20 includes a first output transistor T10 and a second output transistor T9, and the second output transistor T9 is a dual-gate transistor; the first gate T10G of the first output transistor T10 and the second gate T9G of the second output transistor T9 are connected to the first node K of the signal generating module 10, the first source T10S of the first output transistor T10 is connected to the first high potential line Nvgh, the first drain T10D of the first output transistor T10 and the second source T9S of the second output transistor T9 are connected to the first signal output terminal Nout, and the second drain T9D of the second output transistor T9 is connected to the first low potential line Nvgl1.

[0077] In this embodiment, the second output module 30 includes a third output transistor T6 and a fourth output transistor T7; the third gate T6G of the third output transistor T6 is connected to the second node Q of the signal generating module 10, the third source T6S of the third output transistor T6 is connected to the first clock signal line CK, the third drain T6D of the third output transistor T6 and the fourth source T7S of the fourth output transistor T7 are connected to the second signal output terminal Pout, the fourth gate T7G of the fourth output transistor T7 is connected to the third node P of the signal generating module 10, and the fourth drain T7D of the fourth output transistor T7 is connected to the second high potential line Pvgh1.

[0078] In this embodiment, the first-stage pass transistor T13, the second inverting transistor T1, the first output transistor T10, and the regulating transistor T14 are N-type transistors, and the second-stage pass transistor T12, the pull-up transistor T2, the first filter transistor T11, the second filter transistor T8, the first inverting transistor T3, the second output transistor T9, the third output transistor T6, the fourth output transistor T7, the first feedback transistor T4, and the second feedback transistor T5 are P-type transistors.

[0079] The gate driving circuit 300 provided in this embodiment can stabilize or reduce the gate potential of the first output transistor T10 through the first low potential line Nvgl1 under the control of the third node P, so that the first output transistor T10 is stabilized or better in the cut-off state to reduce the leakage current, and then the potential of the first gate driving signal can be maintained at a high potential or pulse amplitude, thereby improving the potential stability of the gate driving signal.

[0080] In this embodiment, the voltage regulating module 307 is used to stabilize or reduce the low potential of the first node K. Alternatively, in another embodiment, the voltage regulating module 307 is also used to stabilize or reduce the gate potential of the first output transistor T10 during the positive pulse of the first gate driving signal.

[0081] It should be noted that the regulating transistor T14 can stabilize or reduce the gate potential of the first output transistor T10 during the duration of the positive pulse of the first gate drive signal, so that the first output transistor T10 is stable or better in the cut-off state to reduce the leakage current, and then the potential of the first gate drive signal can be maintained at a high potential or pulse amplitude, thereby improving the potential stability of the gate drive signal.

[0082] In this embodiment, the internal node is the third node P, the second low potential line Pvgl and the first low potential line Nvgl1 are low potential lines with the same potential, and the channel type of the regulating transistor T14 is the same as the channel type of the first output transistor T10.

[0083] It should be noted that in this embodiment, the first output transistor T10 and the regulating transistor T14 can share the same low potential line, which can save the number of wiring required for the gate drive circuit 300. The channel type of the regulating transistor T14 is the same as the channel type of the first output transistor T10, and the regulating transistor T14 can be turned on when the first output transistor T10 is in the off state to further reduce the gate potential of the first output transistor T10.

[0084] In one embodiment, see Figure 5 , the internal node can be the third node P, the channel type of the regulating transistor T14 is the same as the channel type of the first output transistor T10, the first low potential line Nvgl1 transmits a first low potential signal, and the third low potential line Nvgl2 transmits a second low potential signal, and the potential of the second low potential signal is lower than the potential of the first low potential signal.

[0085] It should be noted that the channel type of the regulating transistor T14 is the same as the channel type of the first output transistor T10, and when the first output transistor T10 is in the cut-off state, the second low potential signal can be transmitted to the gate of the first output transistor T10 through the regulating transistor T14, so that the gate potential of the first output transistor T10 can be further reduced, thereby reducing the leakage current of the first output transistor T10. In this way, the stability of the low potential of the second node QK and the low potential of the middle node W can be improved.

[0086] In one embodiment, the difference between the potential of the first low potential signal and the potential of the second low potential signal is greater than or equal to 2V.

[0087] It should be noted that this embodiment can not only reduce the leakage current of the first output transistor T10, but also adjust the threshold voltage of the first output transistor T10 to shift toward the positive direction, thereby increasing the range of the threshold voltage of the first output transistor T10.

[0088] The following is for Figure 3 The structure of the display panel 100 of the present application is described.

[0089] See also Figure 6 The display area AA and the non-display area NA of the display panel 100 may be provided with a base substrate 110 and an array driving layer 120 provided on the base substrate 110; in the display area AA, the display panel 100 may also be provided with a pixel definition layer provided on the array driving layer 120, a light emitting device layer provided on the same layer as the pixel definition layer, and a packaging layer provided on the pixel definition layer. The following mainly describes the film layer structure in the non-display area NA.

[0090] In the present embodiment, the base substrate 110 supports various layers disposed on the base substrate 110. When the display panel 100 is a bottom-emitting light-emitting display device or a double-sided light-emitting display device, a transparent base substrate is used. When the display panel 100 is a top-emitting light-emitting display device, a semi-transparent or opaque base substrate as well as a transparent base substrate may be used.

[0091] In the present embodiment, the base substrate 110 is used to support various film layers disposed on the base substrate 110, and the base substrate 110 may be made of an insulating material such as glass, quartz, or a polymer resin. The base substrate 110 may be a rigid substrate or a flexible substrate that can be bent, folded, curled, etc. Examples of flexible materials for the flexible substrate include polyimide (PI), but are not limited to polyimide (PI).

[0092] In this embodiment, the base substrate 110 may include a first flexible substrate 111, a first barrier layer 112, a second flexible substrate 113, and a second barrier layer 114 that are stacked. The first flexible substrate 111 and the second flexible substrate 113 may be formed of the same material such as polyimide, and the first barrier layer 112 and the second barrier layer 114 may be formed of an inorganic material including, for example, at least one of SiOx and SiNx.

[0093] In the present embodiment, the first flexible substrate 111 is formed by coating a polymer material on a support substrate (not shown) and then curing the polymer material, the second flexible substrate 113 is formed by coating the same material as the first flexible substrate 111 and curing the material, and the second flexible substrate 113 is formed by the same method as the method of forming the first flexible substrate 111. Each of the first flexible substrate 111 and the second flexible substrate 113 may be formed to have a thickness of about 8 μm to about 12 μm. In addition, when the base substrate 110 is formed of the first flexible substrate 111 and the second flexible substrate 113, small holes, cracks, etc. formed during the manufacture of the first flexible substrate 111 are covered by the second flexible substrate 113, so that the above-mentioned defects can be removed.

[0094] See also Figure 6 , the array driving layer 120 may include a plurality of thin film transistors, the thin film transistors may be of an etching barrier type, a back channel etching type, or may be divided into a bottom gate thin film transistor, a top gate thin film transistor and the like structure according to the position of the gate and the active layer, or may be divided into an N-type thin film transistor, a P-type thin film transistor according to the performance of the thin film transistor; wherein, Figure 6 The thin film transistor does not represent Figure 2 The structural diagram of any transistor is merely a schematic diagram of each film layer of the display panel 100 of the present application.

[0095] See also Figure 6 The array driving layer 120 may include a light shielding layer 121 disposed on the base substrate 110, a buffer layer 122 disposed on the light shielding layer 121, a first active layer 123 disposed on the buffer layer 122, a first gate insulating layer 124 disposed on the first active layer 123, a first gate layer 125 disposed on the first gate insulating layer 124, a second gate insulating layer 126 disposed on the first gate layer 125, a second gate layer 127 disposed on the second gate insulating layer 126, a third gate insulating layer 128 disposed on the second gate layer 127, A second active layer 129 is arranged on the third gate insulation layer 128, a fourth gate insulation layer 130 is arranged on the second active layer 129, a third gate layer 131 is arranged on the fourth gate insulation layer 130, a first interlayer insulation layer 132 is arranged on the third gate layer 131, a first source-drain layer 133 is arranged on the first interlayer insulation layer 132, a second interlayer insulation layer 134 is arranged on the first source-drain layer 133, a second source-drain layer 135 is arranged on the second interlayer insulation layer 134, and a planarization layer 136 is arranged on the second source-drain layer 135.

[0096] See also Figure 6The light shielding layer 121 is disposed on the second barrier layer 114. The light shielding layer 121 is used to block external light from entering the thin film transistor from the bottom. The material of the light shielding layer 121 can be composed of a black light shielding material, such as a black light shielding metal or a black organic material.

[0097] See also Figure 6 The buffer layer 122 is disposed on the light-shielding layer 121. The buffer layer 122 is used to isolate the light-shielding layer 121 from the upper metal material. The material of the buffer layer 122 may include a compound composed of nitrogen, silicon and oxygen, such as a single-layer silicon oxide film layer, or a silicon oxide-silicon nitride stacked structure.

[0098] See also Figure 6 The first active layer 123 is disposed on the buffer layer 122, and the second active layer 129 can be disposed on the third gate insulating layer 128. The materials of the first active layer 123 and the second active layer 129 can be indium gallium zinc oxide semiconductor, amorphous silicon or low-temperature polycrystalline silicon. For example, in the present application, the material of the first active layer 123 can be low-temperature polycrystalline silicon, and the material of the second active layer 129 can be indium gallium zinc oxide semiconductor.

[0099] See also Figure 6 The first gate insulating layer 124, the second gate insulating layer 126, the third gate insulating layer 128, the fourth gate insulating layer 130, the first interlayer insulating layer 132, and the second interlayer insulating layer 134 are respectively arranged on the corresponding metal layers or semiconductor layers, and are separated by different layers of metal layers or semiconductor layers; the materials of the first gate insulating layer 124, the second gate insulating layer 126, the first interlayer insulating layer 132, the third gate insulating layer 128, the fourth gate insulating layer 130, and the second interlayer insulating layer 134 can be composed of inorganic substances composed of nitride oxide silicon or organic materials with flatness.

[0100] See also Figure 6 The first gate layer 125, the second gate layer 127 and the third gate layer 131 are respectively disposed on corresponding insulating layers, and the materials of the first gate layer 125, the second gate layer 127 and the third gate layer 131 can be copper, molybdenum or molybdenum-titanium alloy.

[0101] See also Figure 6 The first source-drain electrode layer 133 is disposed on the first interlayer insulating layer 132 , and the second source-drain electrode layer 135 is disposed on the second interlayer insulating layer 134 . The materials of the first source-drain electrode layer 133 and the second source-drain electrode layer 135 may be copper or molybdenum-titanium alloy, copper or titanium, etc.

[0102] See also Figure 6 The planarization layer 136 is laid as a whole layer to ensure the flatness of the film layer of the array driving layer 120. The material of the planarization layer 136 can be an inorganic material composed of nitride oxide silicon or an organic material with flatness.

[0103] See also Figure 7 , Figure 7 FIG. 1 is a film layer diagram of the first gate layer 125 in the display panel 100 of the present application.

[0104] In this embodiment, the first gate layer 125 may include a second gate T9G and a third gate T6G; in the second direction Y, the length of the second gate T9G is greater than the length of the third gate T6G, and the area of ​​the second gate T9G is greater than the area of ​​the third gate T6G.

[0105] In this embodiment, since the second output transistor T9 is used to output the first gate drive signal and the third output transistor T6 is used to output the second gate drive signal, and since the load of the first gate drive signal is greater than the load of the second gate drive signal, in order to increase the output load of the first output module 20, the present application makes the area of ​​the second gate T9G greater than the area of ​​the third gate T6G.

[0106] See also Figure 7 The second gate T9G may include a second trunk gate T9Ga and a plurality of second branch gates T9Gb arranged at intervals, the second trunk gate T9Ga extends along the first direction X, the second branch gates T9Gb extend along the second direction Y, and the plurality of second branch gates T9Gb are electrically connected to the second trunk gate T9Ga at one end facing the signal generating module 10; for example, the second gate T9G may include one second trunk gate T9Ga and four second branch gates T9Gb.

[0107] See also Figure 7 The third gate T6G may include a third trunk gate T6Ga and a plurality of third branch gates T6Gb arranged at intervals, the third trunk gate T6Ga extends along the first direction X, the third branch gates T6Gb extend along the second direction Y, and the plurality of third branch gates T6Gb are electrically connected to the third trunk gate T6Ga at one end facing the signal generating module 10; for example, the third gate T6G includes one third trunk gate T6Ga and three third branch gates T6Gb.

[0108] In this embodiment, the length and number of the strip branch gates in the second direction Y are positively correlated with the output load of the output transistor. Therefore, in order to improve the driving capability of the second gate T9G and the third gate T6G, the present application sets the second gate T9G and the third gate T6G into a plurality of separately arranged strip branch gates, each strip branch gate bears the load of the corresponding transistor, the strip branch electrode corresponds to the channel of the active part in the corresponding transistor, and the space between two adjacent strip branch gates corresponds to the source and drain of the upper layer. The composite electric field formed by the plurality of separately arranged strip branch gates can improve the driving capability of the transistor.

[0109] In this embodiment, in the first direction X, a distance between two adjacent second branch gates T9Gb and a distance between two adjacent third branch gates T6Gb may be equal.

[0110] See also Figure 7 The first gate layer 125 further includes a fourth gate T7G, which extends along the second direction Y. The fourth gate T7G and a plurality of third branch gates T6Gb in the third gate T6G are arranged in parallel and at intervals.

[0111] In this embodiment, since the third output transistor T6 is connected to the first clock signal line CK, the load it needs to bear is relatively large. Therefore, the present application sets the third gate T6G with three strip-shaped branch gates, while the fourth gate T7G is not connected to the corresponding clock signal line. The load that the fourth output transistor T7 needs to bear is relatively small, so the fourth gate T7G is only set with one strip-shaped branch gate.

[0112] In this embodiment, in the first direction X, the spacing between the fourth gate T7G and the adjacent third branch gate T6Gb may be equal to the spacing between two adjacent third branch gates T6Gb; that is, the spacing between two adjacent second branch gates T9Gb, the spacing between two adjacent third branch gates T6Gb, and the spacing between the fourth gate T7G and the adjacent third branch gate T6Gb are all equal, that is, the spacing between the strip-shaped branch electrodes is equal, which reduces the difficulty of patterning.

[0113] See also Figure 7 The first gate layer 125 further includes a first electrode plate C1a, and one end of the plurality of third branch gates T6Gb away from the signal generating module 10 is connected to the first electrode plate C1a. For example, the first electrode plate C1a is connected to three third branch gates T6Gb, and the three third branch gates T6Gb transmit voltage signals to different positions of the first electrode plate C1a, so that any area of ​​the first electrode plate C1a can simultaneously receive the voltage signals transmitted by the three third branch gates T6Gb.

[0114] See also Figure 7 , in the second direction Y, the width of the first electrode plate C1a is greater than the width of the third main grid T6Ga. Since the capacitance of the storage capacitor is positively correlated with the facing panel of the electrode plate in the storage capacitor, the present application can make the width of the first electrode plate C1a greater than the width of the third main grid T6Ga in a limited space, thereby increasing the area of ​​the first electrode plate C1a, thereby increasing the facing area between the two electrodes, and increasing the capacitance of the first storage capacitor C1.

[0115] See also Figure 7The first gate layer 125 also includes a gate T2G of the pull-up transistor T2, a gate T3G of the first inverting transistor T3, a gate T4G of the first feedback transistor T4, a gate T5G of the second feedback transistor T5, a gate T8G of the second filter transistor T8, a gate T11G of the first filter transistor T11, a gate T12G of the second stage pass transistor T12, and a third plate C2a of the second storage capacitor C2.

[0116] In the present embodiment, the gate T2G of the pull-up transistor T2, the gate T3G of the first inverting transistor T3, the gate T11G of the first filtering transistor T11, the gate T12G of the second-stage pass transistor T12, and the third electrode plate C2a of the second storage capacitor C2 extend along the second direction Y, the gate T12G of the second-stage pass transistor T12 is arranged close to the first output module 20, the gate T3G of the first inverting transistor T3, the gate T2G of the pull-up transistor T2, and the gate T11G of the first filtering transistor T11 are arranged in sequence along the first direction X in the middle area of ​​the signal generating module 10, the gate T12G of the second-stage pass transistor T12 is on the same straight line as the third electrode plate C2a of the second storage capacitor C2, and the gate T11G of the first filtering transistor T11 is directly connected to the third electrode plate C2a of the second storage capacitor C2.

[0117] In this embodiment, the gate T4G of the first feedback transistor T4, the gate T5G of the second feedback transistor T5, and the gate T8G of the second filtering transistor T8 extend along the first direction X, and the three are arranged close to the second output module 30, the gate T4G of the first feedback transistor T4 and the gate T5G of the second feedback transistor T5 are arranged in parallel along the second direction Y, and the gate T4G of the first feedback transistor T4 is arranged away from the fourth gate T7G, the gate T5G of the second feedback transistor T5 is arranged close to the fourth gate T7G, the gate T5G of the second feedback transistor T5 and the gate T8G of the second filtering transistor T8 are arranged along the first direction X, and the gate T5G of the second feedback transistor T5 and the fourth gate T7G of the fourth output transistor T7 are directly connected in the extension section in the second direction Y.

[0118] See also Figure 8 , Figure 8 FIG. 1 is a film layer diagram of the second gate layer 127 in the display panel 100 of the present application.

[0119] The second gate layer 127 may include a first gate T10G, the first gate T10G includes two first trunk gates T10Ga and a plurality of first branch gates T10Gb disposed between the two first trunk gates T10Ga, the two first trunk gates T10Ga are disposed oppositely and in parallel, the two first trunk gates T10Ga extend along a first direction X, the plurality of first branch gates T10Gb extend along a second direction Y, and both ends of the plurality of first branch gates T10Gb are respectively connected to the two first trunk gates T10Ga. For example, the first gate T10G includes two first trunk gates T10Ga and four first branch gates T10Gb, and both ends of the four first branch gates T10Gb are respectively connected to the two first trunk gates T10Ga.

[0120] In this embodiment, the length of the first branch gate T10Gb is greater than the length of the second branch gate T9Gb in the second direction Y. Since the first output transistor T10 is a metal oxide semiconductor transistor, and its mobility is relatively low, in order to improve the driving capability of the first output transistor T10, the present application increases the length of the first branch gate T10Gb, which is equivalent to increasing the width of the channel in the first active portion T10A, thereby improving the electron mobility in the first output transistor T10 and ensuring the driving capability of the first output transistor T10.

[0121] See also Figure 8 , the second gate layer 127 also includes the second plate C1b of the first storage capacitor C1, the first plate C1a and the second plate C1b are arranged oppositely and in parallel, and the orthographic projection of the first plate C1a on the second plate C1b is located inside the second plate C1b. Since the capacitance of the storage capacitor is positively correlated with the facing panel of the plate in the storage capacitor, the present application can make the orthographic projection of the first plate C1a on the second plate C1b located inside the second plate C1b in a limited space, that is, the area of ​​the first plate C1a is less than or equal to the area of ​​the second plate C1b. In this embodiment, the area of ​​the first plate C1a is less than the area of ​​the second plate C1b, that is, the area of ​​the second plate C1b is increased as much as possible to increase the facing area between the two plates, increase the capacitance of the first storage capacitor C1, and improve the output stability of the first signal output terminal Nout.

[0122] In this embodiment, the second gate layer 127 also includes a first gate T1G of the second inverting transistor T1, a first gate T131G of the first-stage pass transistor T13, a first gate T14G of the regulating transistor T14, and a fourth plate C2b of the second storage capacitor C2; the first gate T1G of the second inverting transistor T1, the first gate T13G of the first-stage pass transistor T13, and the fourth plate C2b of the second storage capacitor C2 extend along the second direction Y, and the first gate T14G of the regulating transistor T14 extends along the first direction X.

[0123] See also Fig. 9 , Fig. 9 It is a film layer diagram of the first gate layer 125 and the second gate layer 127 superimposed in the display panel 100 of the present application.

[0124] In this embodiment, the orthographic projection of the third electrode plate C2a on the fourth electrode plate C2b is located inside the fourth electrode plate C2b, that is, the area of ​​the third electrode plate C2a is less than or equal to the area of ​​the fourth electrode plate C2b. In this embodiment, the area of ​​the third electrode plate C2a is smaller than the area of ​​the fourth electrode plate C2b, that is, the area of ​​the fourth electrode plate C2b is increased as much as possible to increase the facing area between the two electrodes, increase the capacitance of the second storage capacitor C2, and improve the stability of the voltage in the fifth node W.

[0125] In this embodiment, the capacitance of the second storage capacitor C2 needs to be greater than 50F.

[0126] In this embodiment, the area of ​​the first electrode plate C1a is greater than the area of ​​the third electrode plate C2a, and the area of ​​the third electrode plate is greater than the area of ​​the fourth electrode plate C2b, and the ratio of the capacitance of the first storage capacitor C1 to the capacitance of the second storage capacitor C2 is greater than 2; since the first electrode plate C1a in the first storage capacitor C1 is connected to the third gate T6G of the third output transistor T6, the second electrode plate C1b in the first storage capacitor C1 is connected to the third drain T6D of the third output transistor T6, and the third source T6S of the third output transistor T6 is connected to the first clock signal line CK, the output signal of the clock signal line at different times will flip, which will affect the stability of the output signal of the second signal output terminal Pout connected to the third drain T6D of the third output transistor T6, so the present application ensures the output stability of the first signal output terminal Nout by increasing the capacitance of the first storage capacitor C1.

[0127] exist Fig. 9In the structure, the gate T1G of the second inverting transistor T1 and the gate T3G of the first inverting transistor T3 are arranged adjacent to each other, and the gate T12G of the second-stage pass transistor T12 is arranged between the gate T13G of the first-stage pass transistor T13 and the first gate T10G, the gate T13G of the first-stage pass transistor T13 and the gate T12G of the second-stage pass transistor T12 are arranged adjacent to each other, the gate T14G of the regulating transistor T14 is arranged between the gate T2G of the pull-up transistor T2 and the first gate T10G, and the gate T13G of the first-stage pass transistor T13 is arranged on the side of the gate T12G of the second-stage pass transistor T12 away from the first gate T10G.

[0128] See also Fig.10 , Fig.10 FIG. 1 is a film layer diagram of the third gate layer 131 in the display panel 100 of the present application.

[0129] The array driving layer 120 further includes a third gate layer 131 disposed on a side of the second gate layer 127 away from the base substrate 110, and the third gate layer 131 includes a fifth gate T10H; the fifth gate T10H includes two fifth trunk gates T10Ha and a plurality of fifth branch gates T10Hb disposed between the two fifth trunk gates T10Ha, the two fifth trunk gates T10Ha are disposed oppositely and in parallel, the two fifth trunk gates T10Ha extend along the first direction X, the plurality of fifth branch gates T10Hb extend along the second direction Y, and the two ends of the plurality of fifth branch gates T10Hb are respectively connected to the two first trunk gates T10Ga. For example, the fifth gate T10H may include two fifth trunk gates T10Ha and four fifth branch gates T10Hb, and the two ends of the four fifth branch gates T10Hb are connected to the two fifth trunk gates T10Ha.

[0130] In this embodiment, the first output transistor T10 is a dual-gate transistor, and the first gate T10G and the fifth gate T10H of the first output transistor T10 are arranged on the upper and lower sides of the first active part T10A, and the first gate T10G and the fifth gate T10H are electrically connected to simultaneously drive the migration of carriers in the first active part T10A, thereby improving the conduction rate of the first output transistor T10.

[0131] In this embodiment, in the second direction Y, the length of the first branch gate T10Gb is equal to the length of the fifth branch gate T10Hb, and both the first branch gate T10Gb and the fifth branch gate T10Hb bear the output load of the first output transistor T10; at the same time, since the fifth branch gate T10Hb is required as a shielding layer to ion-dope the first active portion T10A, the length of the channel in the first active portion T10A in the first direction X is equal to the length of the fifth branch gate T10Hb in the fifth gate T10H in the first direction X, and In order to ensure that external light enters the first active portion T10A, the present application makes the orthographic projection of the fifth branch gate T10Hb on the corresponding first branch gate T10Gb located within the corresponding first branch gate T10Gb, that is, the area of ​​the first branch gate T10Gb is greater than or equal to the area of ​​the fifth branch gate T10Hb. In this embodiment, the area of ​​the first branch gate T10Gb can be greater than the area of ​​the fifth branch gate T10Hb, or the distance between two adjacent first branch gates T10Gb can be less than the distance between two adjacent fifth branch gates T10Hb.

[0132] In this embodiment, the distance between two adjacent first branch gates T10Gb may be smaller than the distance between two adjacent second branch gates T9Gb in the second output transistor T9, and the distance between two adjacent second branch gates T9Gb may be smaller than the distance between two adjacent fifth branch gates T10Hb.

[0133] See also Fig.11 , Fig.11 It is a diagram showing the superimposed film layers of the second gate layer 127 and the third gate layer 131 in the display panel 100 of the present application.

[0134] Since the second inverting transistor T1, the first stage pass transistor T13 and the regulating transistor T14 are all metal oxide semiconductor transistors, in order to improve the driving capabilities of the second inverting transistor T1, the first stage pass transistor T13 and the regulating transistor T14, the second inverting transistor T1, the first stage pass transistor T13 and the regulating transistor T14 can all be double-gate transistors. That is, the third gate layer 131 can also include the second gate T1H of the second inverting transistor T1, the second gate T13H of the first stage pass transistor T13 and the second gate T14H of the regulating transistor T14, the second gate T1H of the second inverting transistor T1 and the second gate T13H of the first stage pass transistor T13 extend along the second direction Y, and the second gate T14H of the regulating transistor T14 extends along the first direction X.

[0135] In this embodiment, in order to prevent external light from entering the active parts of the second inverter transistor T1, the first-stage pass transistor T13 and the adjustment transistor T14, the second gate T1H of the second inverter transistor T1 is projected on the corresponding first gate T1G and inside the corresponding first gate T1G, the second gate T13H of the first-stage pass transistor T13 is projected on the corresponding first gate T13G and inside the corresponding first gate T13G, and the second gate T14H of the adjustment transistor T14 is projected on the corresponding first gate T14G and inside the corresponding first gate T14G; the area of ​​the second gate T1H of the second inverter transistor T1 is smaller than the area of ​​the corresponding first gate T1G, the area of ​​the second gate T13H of the first-stage pass transistor T13 is smaller than the area of ​​the corresponding first gate T13G, and the area of ​​the second gate T14H of the adjustment transistor T14 is smaller than the area of ​​the corresponding first gate T14G.

[0136] See also Fig.12 and Fig.13 , Fig.12 is a film layer diagram of the first active layer 123 in the display panel 100 of the present application, Fig.13 It is a film layer diagram of the first gate layer 125 , the second gate layer 127 , the third gate layer 131 , the first active layer 123 and the second active layer 129 in the display panel 100 of the present application.

[0137] The array driving layer 120 also includes a first active layer 123 arranged between the first gate layer 125 and the base substrate 110, and the first active layer 123 includes a low-temperature polycrystalline silicon semiconductor; the first active layer 123 includes a second active portion T9A and a third active portion T6A, the second active portion T9A and a plurality of second branch gates T9Gb overlap, and the third active portion T6A and a plurality of third branch gates T6Gb overlap.

[0138] In this embodiment, the second output transistor T9 and the third output transistor T6 are top-gate transistors, the second gate T9G can be used as a shielding layer of the second active portion T9A to perform ion doping on the second active portion T9A, and the third gate T6G can be used as a shielding layer of the third active portion T6A to perform ion doping on the third active portion T6A; therefore, the portion of the active portion that overlaps with the corresponding branch gate is the channel portion, and the non-overlapping portion of the active portion is the source connection portion and the drain connection portion on both sides of the channel portion; for example Fig.14 In the structure, the second active portion T9A overlaps with four second branch gates T9Gb, the third active portion T6A overlaps with three third branch gates T6Gb, the second active portion T9A has four channel portions, and the third active portion T6A has three channel portions.

[0139] In this embodiment, since the lengths of the second branch gate T9Gb and the third branch gate T6Gb in the second direction Y are long enough, in order to increase the width of the channel in the active portion, the size of the second active portion T9A and the third active portion T6A in the second direction Y is increased as much as possible. However, when the size of the low-temperature polycrystalline silicon semiconductor in the second direction Y is too large, static electricity will be concentrated in the active portion, which may cause the active portion to be damaged by static electricity. Therefore, the second active portion T9A and the third active portion T6A can be arranged as two sub-active portions that are separately arranged.

[0140] See also Fig.12 and Fig.13 The second active portion T9A may include two second sub-active portions T9Aa disposed at intervals, the third active portion T6A includes two third sub-active portions T6Aa disposed at intervals, and the second sub-active portion T9Aa and the third sub-active portion T6Aa extend along the first direction X. The two second sub-active portions T9Aa disposed separately and the two third sub-active portions T6Aa disposed separately reduce the sizes of the second active portion T9A and the third active portion T6A in the third direction, and avoid the technical problem of static electricity concentration in the active portion.

[0141] In this embodiment, the width of the second sub-active portion T9Aa is greater than the width of the third sub-active portion T6Aa in the second direction Y. Since the output load of the second output transistor T9 is greater than the output load of the third output transistor T6, the present application increases the width of the second sub-active portion T9Aa to increase the second output load.

[0142] It should be noted that the width of the second sub-active portion T9Aa and the width of the third sub-active portion T6Aa are width dimensions of the corresponding sub-active portions in the second direction Y.

[0143] See also Fig.12 and Fig.13 The first active layer 123 also includes a fourth active portion T7A, the fourth active portion T7A includes two fourth sub-active portions T7Aa arranged at intervals, the two fourth sub-active portions T7Aa overlap with the fourth gate T7G, and the fourth sub-active portion T7Aa is connected to the corresponding third sub-active portion T6Aa; for example, one fourth active portion T7A overlaps with one fourth gate T7G, and the fourth active portion T7A has one channel.

[0144] In the present embodiment, in the second direction Y, the width of the fourth sub-active portion T7Aa may be equal to the width of the third sub-active portion T6Aa.

[0145] In this embodiment, in order to simplify the process, the pattern of the third active part T6A can be connected to the pattern of the fourth active part T7A, which increases the pattern area of ​​the active part in the second output module 30, reduces the film forming accuracy of the active part in this area, and simplifies the film forming process.

[0146] exist Fig.13 In the structure, the first active layer 123 also includes an active portion T2A of the pull-up transistor T2, an active portion T3A of the first inverting transistor T3, an active portion T4A of the first feedback transistor T4, an active portion T5A of the second feedback transistor T5, an active portion T8A of the second filter transistor T8, an active portion T11A of the first filter transistor T11, and an active portion T12A of the second stage pass transistor T12. The active portions of the pull-up transistor T2, the first inverting transistor T3, the first feedback transistor T4, the second feedback transistor T5, the second filter transistor T8, the first filter transistor T11, and the second stage pass transistor T12 are vertically arranged with the gate of the corresponding transistor and have an overlapping portion with the gate of the corresponding transistor, and the overlapping portion is the channel portion of the corresponding active portion.

[0147] See also Fig.14 , Fig.14 FIG. 1 is a film layer diagram of the second active layer 129 in the display panel 100 of the present application.

[0148] In this embodiment, the array driving layer 120 also includes a second active layer 129 arranged between the third gate layer 131 and the second gate layer 127, and the second active layer 129 includes a metal oxide semiconductor; the second active layer 129 includes a first active portion T10A, and the first active portion T10A includes two first sub-active portions T10Aa arranged at intervals, and the first sub-active portion T10Aa extends along the first direction X, and the two first sub-active portions T10Aa and multiple first branch gates T10Gb overlap.

[0149] In this embodiment, since the first output transistor T10 is a dual-gate transistor, the first gate T10G and the fifth gate T10H of the first output transistor T10 can both serve as switches of the first output transistor T10; at the same time, the fifth gate T10H can serve as a shielding layer of the first active portion T10A to perform ion doping on the first active portion T10A; therefore, the portion of the first active portion T10A that overlaps with the plurality of first branch gates T10Gb is the channel portion of the first active portion T10A, and the portion of the first active portion T10A that does not overlap with the plurality of first branch gates T10Gb is the source connection portion and the drain connection portion on both sides of the channel portion; for example Fig.13 and Fig.14 In the structure, the first active portion T10A and the four first branch gates T10Gb overlap, and the first active portion T10A has four channel portions.

[0150] In this embodiment, since the first output transistor T10 is a metal oxide semiconductor transistor, this type of transistor has the advantage of low leakage current, but its mobility is relatively small. Therefore, in order to improve the mobility of the first output transistor T10, it is necessary to increase the width of the channel portion in the first active portion T10A, which is equivalent to the width of the first sub-active portion T10Aa in the second direction Y. Therefore, in the second direction Y, the width of the first sub-active portion T10Aa is greater than the width of the second sub-active portion T9Aa.

[0151] In addition, when the width of the first active portion T10A in the second direction Y is too large, static electricity will be concentrated on the first active portion T10A, which may cause the first active portion T10A to be damaged by static electricity. Therefore, the present application can set the first active portion T10A into two first sub-active portions T10Aa that are separately set.

[0152] See also Fig.13 and Fig.14 The second active layer 129 also includes an active portion T1A of the second inverting transistor T1, an active portion T13A of the first-stage pass transistor T13, and an active portion T14A of the regulating transistor T14. The active portions of the second inverting transistor T1, the first-stage pass transistor T13, and the regulating transistor T14 are vertically arranged with the gate of the corresponding transistor, and have an overlapping portion with the gate of the corresponding transistor, and the overlapping portion is the channel portion of the corresponding active portion; at the same time, in order to improve the mobility of the metal oxide semiconductor transistor, in the signal generating module 10, the channel widths of the active portions in the second inverting transistor T1, the first-stage pass transistor T13, and the regulating transistor T14 are all greater than the channel widths of the active portions in the pull-up transistor T2, the first inverting transistor T3, the first feedback transistor T4, the second feedback transistor T5, the second filter transistor T8, the first filter transistor T11, and the second-stage pass transistor T12.

[0153] exist Fig.13 and Fig.14 In the structure, since the first output transistor T10 is a metal oxide semiconductor transistor, the second output transistor T9 and the third output transistor T6 are low-temperature polysilicon semiconductor transistors, and since the mobility of the metal oxide semiconductor transistor is low, in order to improve the mobility of the first output transistor T10, the first gate T10G and the fifth gate T10H of the first output transistor T10 are provided with two trunk gates to connect the two ends of the plurality of branch gates together, so that the electric field formed by the newly added trunk gates further drives the migration of electrons in the active portion.

[0154] In this embodiment, the spacing between the first trunk gate T10Ga and the fifth trunk gate T10Ha and the first active portion T10A in the second direction Y is a first spacing, the spacing between the end of the second branch gate T9Gb away from the second trunk gate T9Ga and the second active portion T9A in the second direction Y is a second spacing, and the spacing between the end of the third branch gate T6Gb away from the third trunk gate T6Ga and the third active portion T6A in the second direction Y is a third spacing, the first spacing is greater than the second spacing, and the second spacing is greater than or equal to the third spacing.

[0155] In this embodiment, the first spacing may be greater than 5 micrometers, the second spacing may be greater than 2.5 micrometers, and the third spacing may be greater than 2.5 micrometers.

[0156] See also Fig.15 , Fig.15 FIG. 1 is a film layer diagram of the first source-drain electrode layer 133 in the display panel 100 of the present application.

[0157] In this embodiment, the array driving layer 120 further includes a first source-drain layer 133 disposed on a side of the third gate layer 131 away from the second gate layer 127 . The first source-drain layer 133 includes a first source T10S, a first drain T10D, a second source T9S, and a second drain T9D.

[0158] In this embodiment, the first source T10S includes a first main source T10Sa and a plurality of first branch sources T10Sb that are spaced apart and arranged in parallel, the first drain T10D includes a plurality of first branch drains T10Db, the first main source T10Sa extends along a first direction X, the first branch source T10Sb extends along a second direction Y, the plurality of first branch sources T10Sb are connected to the first main source T10Sa at a side away from the signal generating module 10, the plurality of first branch drains T10Db extend along the second direction Y, and the plurality of first branch drains T10Db are arranged between the plurality of first branch sources T10Sb.

[0159] In this embodiment, in the top view direction of the display panel 100, two first branch source electrodes T10Sb on both sides of the plurality of first branch source electrodes T10Sb are disposed on both sides of the first gate electrode T10G, and at least one first branch source electrode T10Sb on the inner side of the plurality of first branch source electrodes T10Sb and the plurality of first branch drain electrodes T10Db are disposed between the plurality of first branch gate electrodes T10Gb; for example Fig.15In the structure, the first source T10S includes one first main source T10Sa and three first branch sources T10Sb, the first drain T10D includes two first branch drains T10Db, the three first branch sources T10Sb and the two first branch drains T10Db are arranged at intervals in the first direction X, that is, the two first branch drains T10Db can be arranged between two adjacent first branch sources T10Sb; at the same time, the outermost two first branch sources T10Sb of the three first branch sources T10Sb are arranged on both sides of the first gate T10G, and one first branch source T10Sb and the two first branch drains T10Db are arranged between multiple first branch gates T10Gb.

[0160] In this embodiment, the second drain T9D includes a second main drain T9Da and a plurality of second branch drains T9Db that are spaced apart and arranged in parallel, the second source T9S includes a plurality of second branch sources T9Sb, the second main drain T9Da extends along the first direction X, the second branch drain T9Db extends along the second direction Y, the plurality of second branch drains T9Db are connected to the second main drain T9Da near the side of the signal generating module 10, the plurality of second branch sources T9Sb extend along the second direction Y, and the plurality of second branch sources T9Sb are arranged between the plurality of second branch drains T9Db, and the first main source T10Sa is connected to the second main drain T9Da.

[0161] In this embodiment, in the top view direction of the display panel 100, two second branch drains T9Db on both sides of the plurality of second branch drains T9Db are arranged on both sides of the second gate T9G, and at least one second branch drain T9Db on the inner side of the plurality of second branch drains T9Db and the plurality of second branch sources T9Sb are arranged between the plurality of second branch gates T9Gb; for example Fig.15 In the structure, the second source T9S includes two second branch sources T9Sb, the second drain T9D includes one second main drain T9Da and three second branch drains T9Db, the two second branch sources T9Sb and the three second branch drains T9Db are arranged at intervals in the first direction X, that is, the two second branch sources T9Sb can be arranged between two adjacent second branch drains T9Db; at the same time, the outermost two second branch drains T9Db of the three second branch drains T9Db are arranged on both sides of the second gate T9G, and one second branch drain T9Db and two second branch sources T9Sb are arranged between multiple second branch gates T9Gb.

[0162] In this embodiment, the first trunk source T10Sa and the second trunk drain T9Da both overlap with the first trunk gate T10Ga at a side away from the signal generating module 10 , that is, the first trunk source T10Sa and the second trunk drain T9Da can share a trunk electrode.

[0163] In this embodiment, since the mobility of the first output transistor T10 is relatively low, in order to improve the driving capability of the first output transistor T10, the present application increases the width of the channel in the first active portion T10A to improve the electron mobility in the first output transistor T10; and in order to enable the data signal to be transmitted from the source in the transistor to the drain of the transistor as quickly as possible, the present application provides spaced first branch source electrodes T10Sb and first branch drain electrodes T10Db on both sides of a plurality of first branch gate electrodes T10Gb, and at the same time, the first branch source electrodes T10Sb and the source connection portion in the first sub-active portion T10Aa are electrically connected through a plurality of source contact holes, and the first branch drain electrodes T10Db and the drain connection portion in the first sub-active portion T10Aa are electrically connected through a plurality of drain contact holes; therefore, in the second direction Y, the length of the first branch source electrodes T10Sb is greater than the length of the second branch drain electrodes T9Db.

[0164] See also Fig.16 , Fig.16 It is a superimposed film layer diagram of the first active layer 123 , the second active layer 129 and the first source and drain layer 133 of the display panel 100 of the present application.

[0165] In this embodiment, each first branch source T10Sb is electrically connected to the source connecting portion in the first sub-active portion T10Aa through four first source T10S contact holes, and each first branch drain T10Db is electrically connected to the drain connecting portion in the first sub-active portion T10Aa through four first drain T10D contact holes; each second branch drain T9Db is electrically connected to the drain connecting portion in the first sub-active portion T10Aa through three second drain T9D contact holes, and each first branch source T10Sb is electrically connected to the source connecting portion in the first sub-active portion T10Aa through three second source T9S contact holes.

[0166] In this embodiment, the first source T10S contact hole and the first drain T10D contact hole penetrate the first interinsulating layer 132 and the fourth gate insulating layer 130, and the second source T9S contact hole and the second drain T9D contact hole penetrate the first interinsulating layer 132, the fourth gate insulating layer 130, the third gate insulating layer 128, the second gate insulating layer 126, and the first gate insulating layer 124.

[0167] Since the first gate T10G in the first output transistor T10 is electrically connected to the second gate T9G of the second output transistor T9, but the first gate T10G is in the first gate layer 125 and the second gate T9G is in the second gate layer 127, in order to electrically connect the first gate T10G and the second gate T9G, a certain distance needs to be left between the end of the second branch source T9Sb close to the signal generating module 10 and the second trunk drain T9Da to set a first connecting segment 151 connecting the first gate T10G and the second gate T9G.

[0168] See also Fig.15 The distance between the end of the first branch drain T10Db away from the signal generating module 10 and the first main source T10Sa is smaller than the distance between the end of the second branch source T9Sb close to the signal generating module 10 and the second main drain T9Da.

[0169] In this example, see Fig.15 The first source-drain electrode layer 133 further includes a first connecting segment 151, which is disposed between an end of the second branch source electrode T9Sb close to the signal generating module 10 and the second main drain electrode T9Da; Fig.10 The third gate layer 131 further includes a first protrusion 141 disposed on the fifth trunk gate T10Ha at a side away from the signal generating module 10 , the first protrusion 141 is connected to the fifth trunk gate T10Ha, and the first protrusion 141 extends toward a side away from the signal generating module 10 .

[0170] In this embodiment, the first end of the first connection segment 151 overlaps with the first protrusion 141 and the second trunk gate T9Ga, the second end of the first connection segment 151 overlaps with the second trunk gate T9Ga, and the first end of the first connection segment 151 is electrically connected to the first protrusion 141 through the first via hole HL1, and the second end of the first connection segment 151 is electrically connected to the second trunk gate T9Ga through the second via hole HL2; that is, the first end of the first connection segment 151 is electrically connected to the fifth gate T10H, the second end of the first connection segment 151 is electrically connected to the second gate T9G, and since the first gate T10G is electrically connected to the fifth gate T10H, the second gate T9G is electrically connected to the first gate T10G through the fifth gate T10H.

[0171] exist Fig.10 and Fig.15 In the structure, the third gate layer 131 includes two first protrusions 141, and the first source and drain layer 133 may include two first connection segments 151. In order to avoid disconnection of the second gate T9G and the fifth gate T10H, the two first protrusions 141 are electrically connected to the corresponding first connection segments 151.

[0172] In this embodiment, the first via hole HL1 penetrates the first inter-insulating layer 132 , and the second via hole HL2 penetrates the first inter-insulating layer 132 , the fourth gate insulating layer 130 , the third gate insulating layer 128 , and the second gate insulating layer 126 .

[0173] Since the first gate T10G and the fifth gate T10H in the first output transistor T10 are electrically connected, but the first gate T10G is in the first gate layer 125 and the fifth gate T10H is in the third gate layer 131, in order to electrically connect the first gate T10G and the fifth gate T10H, the present application may set a connecting segment connecting the first gate T10G and the fifth gate T10H on the side of the first branch drain T10Db close to the signal generating module 10.

[0174] See also Fig.15 The first source-drain electrode layer 133 further includes a second connecting segment 152, and the second connecting segment 152 is disposed on a side of the first branch drain T10Db close to the signal generating module 10; see Figure 8 and Fig. 9 The second gate layer 127 further includes a second protrusion 142 disposed on a side close to the signal generating module 10, the second protrusion 142 is connected to the first trunk gate T10Ga, and the second protrusion 142 extends toward a side close to the signal generating module 10; see Fig.10 The third gate layer 131 may further include a third protrusion 143 disposed on a side close to the signal generating module 10 , the third protrusion 143 is connected to the fifth trunk gate T10Ha, and the third protrusion 143 extends toward a side close to the signal generating module 10 .

[0175] In this embodiment, the first end of the second connecting segment 152 overlaps with the second protrusion 142, the second end of the second connecting segment 152 overlaps with the third protrusion 143, and the first end of the second connecting segment 152 is electrically connected to the third protrusion 143 through the third via hole HL3, and the second end of the second connecting segment 152 is electrically connected to the second protrusion 142 through the fourth via hole HL4; that is, the first end of the second connecting segment 152 is electrically connected to the fifth gate T10H, and the second end of the second connecting segment 152 is electrically connected to the first gate T10G. The arrangement of the first connecting segment 151 and the second connecting segment 152 electrically connects the first gate T10G, the second gate T9G and the fifth gate T10H together.

[0176] In the display panel 100 of the present application, multiple first branch sources T10Sb include a first bottom electrode T10Sc close to the next-level GOA unit 310, and multiple second branch drains T9Db include a second bottom electrode T9Dc close to the next-level GOA unit 310. The first bottom electrode T10Sc and the second bottom electrode T9Dc are both electrically connected to the first signal output terminal Nout.

[0177] See also Fig.15 The first source T10S includes three first branch sources T10Sb, and the first branch source T10Sb among the three first branch sources T10Sb close to the next-level GOA unit 310 is the first bottom electrode T10Sc. The second drain T9D includes three second branch drains T9Db, and the second branch drain T9Db among the three second branch drains T9Db close to the next-level GOA unit 310 is the second bottom electrode T9Dc. The first bottom electrode T10Sc is electrically connected to the second bottom electrode T9Dc; secondly, an end of the second bottom electrode T9Dc away from the signal generating module 10 is electrically connected to the first signal output terminal Nout to transmit the first gate driving signal to the display unit 200.

[0178] See also Fig.15 The first source-drain layer 133 may further include a third source electrode T6S, a third drain electrode T6D, a fourth source electrode T7S, and a fourth drain electrode T7D.

[0179] In this embodiment, the third source T6S may include a third main source T6Sa and two third branch sources T6Sb arranged in parallel and at intervals, the two third branch sources T6Sb are connected to the third main source T6Sa at one end close to the signal generating module 10, the third drain T6D includes a third main drain T6Da and two third branch drains T6Db arranged in parallel and at intervals, the two third branch drains T6Db are connected to the third main drain T6Da at one end close to the signal generating module 10, and the two third branch sources T6Sb and the two third branch drains T6Db are alternately arranged in the first direction X.

[0180] In this embodiment, the fourth source T7S and the fourth drain T7D extend along the second direction Y, the fourth drain T7D is arranged adjacent to the third branch drain T6Db, the fourth source T7S is arranged on a side of the fourth drain T7D away from the third branch drain T6Db, and the first end of the fourth source T7S is connected to the third main drain T6Da.

[0181] See also Fig.15 The fourth source electrode T7S further includes a second extension segment 162 extending along the second direction Y, part of the second extension segment 162 is located in the GOA unit 310 of the current level, and part of the second extension segment 162 is located in the GOA unit 310 of the next level; at the same time, refer to Figure 7The first gate layer 125 further includes an output wire 170 extending along the second direction Y, the output wire 170 is arranged on a side of the first bottom electrode T10Sc in the first source T10S away from the first branch drain T10Db, the second end of the fourth source T7S is electrically connected to the first end of the second extension segment 162, the second end of the second extension segment 162 is connected to the first end of the output wire 170 through the tenth via HL10, and the second end of the output wire 170 is connected to the second signal output terminal Pout.

[0182] In this embodiment, the tenth via hole HL10 penetrates the first inter-insulating layer 132 , the fourth gate insulating layer 130 , the third gate insulating layer 128 , and the second gate insulating layer 126 , and the second signal output terminal Pout is used to output a second gate driving signal.

[0183] See also Fig.17 , Fig.17 It is a superimposed film layer diagram of the first gate layer 125, the second gate layer 127 and the first source and drain layer 133 of the present application.

[0184] See also Figure 8 and Fig.17 The second plate C1b of the first storage capacitor C1 and the third main drain T6Da have an overlapping portion, and the second plate C1b is electrically connected to the third main drain T6Da through the third via HL3. The third via HL3 penetrates the first inter-insulating layer 132, the fourth gate insulating layer 130, and the third gate insulating layer 128.

[0185] See also Fig.15 and Fig.16 The first source-drain layer 133 also includes a source T2S and a drain T2D of the pull-up transistor T2, a source T3S and a drain T3D of the first inverting transistor T3, a source T4S and a drain of the first feedback transistor T4, a source and a drain T5D of the second feedback transistor T5, a source T8S and a drain T8D of the second filter transistor T8, a source T11S and a drain T11D of the first filter transistor T11, a source T12S and a drain T12D of the second stage pass transistor T12, a source T1S and a drain T1D of the second inverting transistor T1, a source T13S and a drain T13D of the first stage pass transistor T13, and a source T14S and a drain T14D of the regulating transistor T14, and the sources and drains of the above transistors are arranged on both sides of the corresponding active portion.

[0186] In this embodiment, the drain T3D of the first inverting transistor T3 and the source T1S of the second inverting transistor T1 extend along the second direction Y and are connected, and the drain T2D of the pull-up transistor T2, the source T11S of the first filtering transistor T11, the source T4S of the first feedback transistor T4 and the second connecting section 152 are connected to each other.

[0187] In this example, see Fig.15 The first source-drain layer 133 also includes a start signal line STV, a first end of the start signal line STV is connected to the first bottom electrode T10Sc in the previous level GOA unit 310, and a second end of the start signal line STV is electrically connected to the gate of the first level pass transistor T13 and the gate of the second level pass transistor T12 in this level.

[0188] See also Fig.18 , Fig.18 FIG. 1 is a film layer diagram of the second source-drain electrode layer 135 in the display panel 100 of the present application.

[0189] In this embodiment, the array driving layer 120 also includes a second source-drain layer 135 arranged on the side of the first source-drain layer 133 away from the base substrate 110, and the second source-drain layer 135 includes a first high potential line Nvgh, and the first high potential line Nvgh extends along the first direction X; the first high potential line Nvgh overlaps with multiple second branch source electrodes T9Sb and multiple second branch drain electrodes T9Db in each GOA unit 310, and the first high potential line Nvgh is electrically connected to the multiple second branch source electrodes T9Sb in each GOA unit 310 through the fifth via HL5.

[0190] See also Fig.19 , Fig.19 The first high potential line Nvgh is electrically connected to two second branch source electrodes T9Sb in each level of GOA unit 310, and the first high potential line Nvgh is electrically connected to one second branch source electrode T9Sb through two fifth via holes HL5, and the fifth via hole HL5 penetrates the second inter-insulating layer 134.

[0191] See also Fig.18 and Fig.19 The second source-drain layer 135 also includes a first low potential line Nvgl1, the first low potential line Nvgl1 and the first high potential line Nvgh are arranged opposite and in parallel, the first low potential line Nvgl1 overlaps with multiple first branch source electrodes T10Sb and multiple first branch drain electrodes T10Db in each GOA unit 310, and the first low potential line Nvgl1 is electrically connected to multiple first branch drain electrodes T10Db in each GOA unit 310 through the sixth via hole HL6; for example, the first low potential line Nvgl1 is electrically connected to two first branch drain electrodes T10Db in each level of GOA unit 310, and the first low potential line Nvgl1 is electrically connected to one first branch drain electrode T10Db through two sixth via holes HL6, and the sixth via hole HL6 passes through the second inter-insulating layer 134.

[0192] See also Fig. 20, Fig. 20 FIG. 1 is a diagram of superimposed film layers of the first active layer 123 , the second active layer 129 and the second source-drain electrode layer 135 in the display panel 100 of the present application.

[0193] In this embodiment, in order to avoid the interference of the voltage of the first high potential line Nvgh on the voltage of the signal line in the display unit 200, the present application can overlap the first high potential line Nvgh with the second sub-active portion T9Aa on the side close to the signal generating module 10; at the same time, in order to leave enough space for arranging the reset signal line RST, the first low potential line Nvgl1 can overlap with the first sub-active portion T10Aa on the side away from the signal generating module 10.

[0194] See also Figures 18 to 20 The second source-drain layer 135 also includes a second high potential line Pvgh1, which is arranged opposite and parallel to the first high potential line Nvgh, and overlaps with the third sub-active portion T6Aa and the fourth sub-active portion T7Aa on the side close to the signal generating module 10, and the second high potential line Pvgh1 is electrically connected to the fourth drain T7D through the seventh via HL7, and the first via HL1 passes through the second inter-insulating layer 134.

[0195] exist Figures 18 to 20 In the second direction Y, the width of the first high potential line Nvgh is equal to the width of the first low potential line Nvgl1, and the width of the first high potential line Nvgh is greater than the width of the second high potential line Pvgh1. Since the first high potential line Nvgh and the first low potential line Nvgl1 are mainly used to provide high-level signals and low-level signals to the first output module 20, respectively, and the first output module 20 needs to output a level transfer signal to the next-level GOA unit 310 in addition to outputting a gate drive signal to the display unit 200, the output load of the first output module 20 is higher than the output load of the second output module 30, and the output loads of the first high potential line Nvgh and the first low potential line Nvgl1 are both greater than the output loads of the second high potential line Pvgh1 and the second low potential line Pvgl, and therefore the widths of the first high potential line Nvgh and the first low potential line Nvgl1 of the present application are both greater than the widths of the second high potential line Pvgh1 and the second low potential line Pvgl.

[0196] See also Figures 18 to 20The second source-drain layer 135 may further include a second low potential line Pvgl and a third high potential line Pvgh2 overlapping the signal generating module 10; the second low potential line Pvgl, the third high potential line Pvgh2, and the second high potential line Pvgh1 are parallel and spaced apart; the second low potential line Pvgl is disposed between the second high potential line Pvgh1 and the third high potential line Pvgh2; the widths of the third high potential line Pvgh2, the second high potential line Pvgh1, and the second low potential line Pvgl are all equal.

[0197] See also Figures 18 to 20 The second source-drain layer 135 also includes a first clock signal line CK and a second clock signal line XCK overlapping with the signal generating module 10. The first clock signal line CK and the second clock signal line XCK are parallel to and spaced apart from the second high potential line Pvgh1. The first clock signal line CK and the second clock signal line XCK are arranged between the second high potential line Pvgh1 and the second low potential line Pvgl.

[0198] In this embodiment, in the display panel 100 of the present application, the gate driving circuit 300 includes a plurality of repeating units, each of which includes at least four GOA units 310. Four GOA units 310 are taken as one repeating unit as an example below, and the plurality of repeating units are arranged in the first direction X.

[0199] See also Fig.21 , Fig.21 It is a diagram of the superimposed film layers of the first gate layer 125 , the first source-drain electrode layer 133 , and the second source-drain electrode layer 135 in the display panel 100 of the present application.

[0200] In this embodiment, the repeating unit may include a first GOA unit 311, a second GOA unit 312, a third GOA unit 313 and a fourth GOA unit 314 arranged in sequence along the first direction X, and the display panel 100 may include a first clock signal line PCK1, a second clock signal line PCK2, a third clock signal line PCK3, and a fourth clock signal line PCK4 arranged along the second direction Y, and every two clock signal lines are connected to one GOA unit 310.

[0201] In this embodiment, the first clock signal line PCK1, the second clock signal line PCK2 and the first GOA unit 311 are connected, the first clock signal line PCK1 is the first clock signal line CK of the first GOA unit 311, and the second clock signal line PCK2 is the second clock signal line XCK of the first GOA unit 311, that is, the first clock signal line PCK1 is connected to the gate of the third output transistor T6 in the first GOA unit 311, and the second clock signal line PCK2 is connected to the gate of the pull-up transistor T2 in the first GOA unit 311.

[0202] In this embodiment, the second clock signal line PCK2, the third clock signal line PCK3 are connected to the second GOA unit 312, the second clock signal line PCK2 is the first clock signal line CK of the first GOA unit 311, and the third clock signal line PCK3 is the second clock signal line XCK of the first GOA unit 311, that is, the second clock signal line PCK2 is connected to the gate of the third output transistor T6 in the first GOA unit 311, and the third clock signal line PCK3 is connected to the gate of the pull-up transistor T2 in the first GOA unit 311.

[0203] In this embodiment, the third clock signal line PCK3, the fourth clock signal line PCK4 and the third GOA unit 313 are connected, the third clock signal line PCK3 is the first clock signal line CK of the first GOA unit 311, and the fourth clock signal line PCK4 is the second clock signal line XCK of the first GOA unit 311, that is, the third clock signal line PCK3 is connected to the gate of the third output transistor T6 in the first GOA unit 311, and the fourth clock signal line PCK4 is connected to the gate of the pull-up transistor T2 in the first GOA unit 311.

[0204] In this embodiment, the fourth clock signal line PCK4, the first clock signal line PCK1 and the fourth GOA unit 314 are connected, the fourth clock signal line PCK4 is the first clock signal line CK of the first GOA unit 311, and the first clock signal line PCK1 is the second clock signal line XCK of the first GOA unit 311, that is, the fourth clock signal line PCK4 is connected to the gate of the third output transistor T6 in the first GOA unit 311, and the fourth clock signal line PCK4 is connected to the gate of the pull-up transistor T2 in the first GOA unit 311.

[0205] See also Fig.15 and Fig.21 The first source-drain layer 133 in each level of the GOA unit 310 also includes a first extension segment 161 connected to the third source T6S, the first extension segment 161 extends along the second direction Y, and the first extension segment 161 is located in the area where the signal generating module 10 is located, and the first clock signal line CK in each level of the GOA unit 310 is electrically connected to the first extension segment 161 through the fourth via HL4; wherein the fourth via HL4 passes through the second inter-insulating layer 134.

[0206] In this embodiment, since the third output transistor T6 in the first GOA unit 311, the second GOA unit 312, the third GOA unit 313 and the fourth GOA unit 314 is connected to different clock signal lines, in the repeating unit, the lengths of the first extension segments 161 in some GOA units 310 in the first direction X are different, that is, the lengths of the first extension segments 161 in the first GOA unit 311, the second GOA unit 312, the third GOA unit 313 and the fourth GOA unit 314 are different; for example, the lengths of the first extension segments 161 in the first GOA unit 311 and the second GOA unit 312 are equal, and the lengths of the first extension segments 161 in the second GOA unit 312, the third GOA unit 313 and the fourth GOA unit 314 gradually increase.

[0207] In this embodiment, in the second GOA unit 312, since the gate of the first feedback transistor T4 and the third output transistor T6 are both connected to the second clock signal line PCK2, and the connection positions of the two are close, in order to avoid interference between the two, the first source and drain layer 133 in the second GOA unit 312 also includes a third extension segment 163, and the third extension segment 163 extends along the first direction X, and the second clock signal line PCK2 is electrically connected to the first extension segment 161 through the third extension segment 163.

[0208] In this example, see Figure 7 The first gate layer 125 in each level of the GOA unit 310 further includes a fourth extension segment 164 connected to the gate of the pull-up transistor T2, and the fourth extension segment 164 extends along the second direction Y, that is, the fourth extension segment 164 mainly extends to a side away from the first output module 20; at the same time, refer to Fig.15 and Fig.21 The first source-drain layer 133 in each level of the GOA unit 310 further includes a fifth extension segment 165, which extends along the second direction Y. The first end of the fifth extension segment 165 is connected to the second clock signal line XCK in the corresponding GOA unit 310, and the second end of the fifth extension segment 165 is electrically connected to the fourth extension segment 164.

[0209] exist Figure 7 , Fig.15 and Fig.21In the embodiment, the length of the fifth extension segment 165 in the first GOA unit 311, the second GOA unit 312 and the third GOA unit 313 gradually decreases, and the length of the fifth extension segment 165 in the fourth GOA unit 314 increases compared with the length of the fifth extension segment 165 in the third GOA unit 313; at the same time, the lengths of the fourth extension segment 164 in the first GOA unit 311, the second GOA unit 312 and the third GOA unit 313 are equal, and the length of the fourth extension segment 164 in the fourth GOA unit 314 is longer than the length of the fourth extension segment 164 in the third GOA unit 313.

[0210] exist Figure 7 , Fig.15 and Fig.21 In the embodiment, since the pull-up transistors T2 in the first GOA unit 311, the second GOA unit 312, the third GOA unit 313 and the fourth GOA unit 314 are connected to different clock signal lines, in one repeating unit, the sum of the lengths of the fourth extension segment 164 and the fifth extension segment 165 in different GOA units 310 is different; for example, the sum of the lengths of the fourth extension segment 164 and the fifth extension segment 165 in the first GOA unit 311, the second GOA unit 312 and the third GOA unit gradually decreases, and the sum of the lengths of the fourth extension segment 164 and the fifth extension segment 165 in the fourth GOA unit 314 is greater than the sum of the lengths of the fourth extension segment 164 and the fifth extension segment 165 in the first GOA unit.

[0211] See also Figure 7 and Fig.15 The first gate layer 125 also includes a sixth extension segment 166 and a seventh extension segment 167, which extend along the second direction Y. The first end of the sixth extension segment 166 is connected to the fourth gate T7G, the second end of the sixth extension segment 166 is connected to the source T1S of the second inverting transistor T1 through a via, the first end of the seventh extension segment 167 is connected to the drain T3D of the first inverting transistor T3 through a via, and the second end of the seventh extension segment 167 is connected to the gate T14G of the regulating transistor T14.

[0212] See also Fig.18 and Fig.19 The second source-drain layer 135 includes a plurality of reset signal lines RST arranged at intervals, the plurality of reset signal lines RST overlap with the first buffer unit 210, and the plurality of reset signal lines RST are arranged between the first low potential line Nvgl1 and the third high potential line Pvgh2, the first end of the reset signal line RST is connected to the second branch source T9Sb in the N-10th level GOA unit 310 through the eighth via HL8, and the second end of the reset signal line RST is connected to the gate of the first filter transistor T11 through the ninth via HL9.

[0213] In this embodiment, the eighth transistor penetrates the second inter-insulating layer 134 , and the ninth transistor penetrates the third via hole HL3 that penetrates the second inter-insulating layer 134 , the first inter-insulating layer 132 , the fourth gate insulating layer 130 , the third gate insulating layer 128 , and the second gate insulating layer 126 .

[0214] See also Fig.10 , the third gate layer 131 includes a third connection segment 153, and the third connection segment 153 extends from the Nth stage GOA unit 310 to the N-1th stage GOA unit 310; see Fig.15 The first source-drain layer 133 also includes a fourth connection segment 154, a first end of the fourth connection segment 154 is connected to the gate of the second filter transistor T8, a second end of the fourth connection segment 154 is connected to the first end of the third connection segment 153, and a second end of the third connection segment 153 is electrically connected to the start signal line STV in the N-1th level GOA unit 310. Since the signal of the start signal line STV in the N-1th level GOA unit 310 comes from the first signal transmission segment of the N-2th level GOA unit 310, the signal of the gate of the second filter transistor T8 of the present application comes from the first signal output terminal Nout of the N-2th level.

[0215] It should be noted that the source and drain in the above transistor of the present application are only different in naming, as long as one of them is the input terminal and the other is the output terminal.

[0216] It should be noted that the film structure diagram provided in this application is not only applicable to Figure 3 and Figure 5 The circuit structure in, as long as it has the same module structure as the present application, that is, a module structure having two gate drive signals, Nout and Pout, is applicable to the present application.

[0217] The present application also provides a display terminal, which includes the above-mentioned display panel. The display terminal can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.

[0218] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0219] The above is a detailed introduction to a display panel provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solution and core idea of ​​the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solution to deviate from the scope of the technical solution of the embodiments of the present application.

Claims

1. A display panel, characterized in that: It includes a display unit and a gate driving circuit located on one side of the display unit, wherein the gate driving circuit includes N cascaded GOA units, and the N GOA units are arranged along a first direction; wherein each of the GOA units includes a signal generating module, a first output module, and a second output module arranged along a second direction; The first output module is disposed on a side of the signal generating module close to the display unit, and the first output module is used to output a first gate driving signal; The second output module is arranged at a side of the signal generating module away from the display unit, and the second output module is used to output a second gate driving signal, and the first gate driving signal and the second gate driving signal are different; Among them, in the second direction, the lengths of the first output module and the second output module are different, the second direction is parallel to the scan line of the display panel, the angle between the first direction and the second direction is greater than 0° and less than or equal to 90, and N is a positive integer.

2. The display panel according to claim 1, characterized in that: The first output module comprises a first buffer unit and a second buffer unit arranged along the second direction, the first buffer unit is arranged close to the signal generating module, and the second buffer unit is arranged far away from the signal generating module; The first buffer unit includes a first active portion, the second buffer unit includes a second active portion, the first active portion is a metal oxide semiconductor, and the second active portion is a low temperature polysilicon semiconductor.

3. The display panel according to claim 2, characterized in that: The first buffer unit includes a first output transistor having the first active portion, and the second buffer unit includes a second output transistor having the second active portion; Wherein, in the second direction, the length of the first output transistor is greater than the length of the second output transistor.

4. The display panel according to claim 3, characterized in that: The second output module includes a third output transistor and a fourth output transistor, the third output transistor includes a third active portion, the fourth output transistor includes a fourth active portion, the third active portion and the fourth active portion are low temperature polysilicon semiconductors, and the third output transistor and the fourth output transistor are arranged in parallel along the first direction Wherein, the first gate of the first output transistor and the second gate of the second output transistor are connected to the first node of the signal generating module, the first source of the first output transistor is connected to the first high potential line, the first drain of the first output transistor and the second source of the second output transistor are connected to the first signal output terminal, and the second drain of the second output transistor is connected to the first low potential line; In addition, the third gate of the third output transistor is connected to the second node of the signal generating module, the third source of the third output transistor is connected to the first clock signal line, the third drain of the third output transistor and the fourth source of the fourth output transistor are connected to the second signal output terminal, the fourth gate of the fourth output transistor is connected to the third node of the signal generating module, and the fourth drain of the fourth output transistor is connected to the second high potential line.

5. The display panel according to claim 4, characterized in that: The first output transistor further includes a fifth gate disposed opposite to the first gate, and the fifth gate is connected to the first node.

6. The display panel according to claim 5, characterized in that: The display panel includes a base substrate and an array driving layer arranged on the base substrate, and the array driving layer includes: A first gate layer, comprising the second gate, the third gate and the fourth gate; In the second direction, the length of the second gate is greater than the length of the third gate, and the area of ​​the second gate is greater than the area of ​​the third gate.

7. The display panel according to claim 6, characterized in that: The second gate includes a second main gate and a plurality of second branch gates arranged at intervals, the third gate includes a third main gate and a plurality of third branch gates arranged at intervals, the second main gate and the third main gate extend along the first direction, the second branch gate and the third branch gate extend along the second direction, the fourth gate extends along the second direction, and the fourth gate and a plurality of the third branch gates in the third gate are parallel and arranged at intervals; Among them, one end of the plurality of second branch gates facing the signal generating module is electrically connected to the second trunk gate, and one end of the plurality of third branch gates facing the signal generating module is electrically connected to the third trunk gate.

8. The display panel according to claim 7, characterized in that: The display panel further comprises a first storage capacitor, a first plate of the first storage capacitor is connected to the second node, and a second plate of the storage capacitor is connected to the second signal output terminal; The first gate layer further includes the first electrode plate, and one end of the plurality of third branch gates away from the signal generating module is connected to the first electrode plate. In the second direction, the width of the first electrode plate is greater than the width of the third main gate.

9. The display panel according to claim 7, characterized in that: The array driving layer further comprises a second gate layer arranged on a side of the first gate layer away from the base substrate, and the second gate layer comprises the first gate; Among them, the first gate includes two first main gates and multiple first branch gates arranged between the two first main gates, the two first main gates are arranged opposite to each other and in parallel, the two first main gates extend along the first direction, the multiple first branch gates extend along the second direction, and the two ends of the multiple first branch gates are respectively connected to the two first main gates.

10. The display panel according to claim 9, characterized in that: The array driving layer further comprises a third gate layer arranged on a side of the second gate layer away from the base substrate, and the third gate layer comprises the fifth gate; Among them, the fifth gate includes two fifth main gates and multiple fifth branch gates arranged between the two fifth main gates, the two fifth main gates are arranged oppositely and in parallel, the two fifth main gates extend along the first direction, and the multiple fifth branch gates extend along the second direction, and the two ends of the multiple fifth branch gates are respectively connected to the two first main gates.

11. The display panel according to claim 10, characterized in that: The array driving layer further comprises a first active layer disposed between the first gate layer and the base substrate, wherein the first active layer comprises a low temperature polysilicon semiconductor; The first active layer includes the second active portion, the third active portion and the fourth active portion, the second active portion overlaps with a plurality of the second branch gates, and the third active portion overlaps with a plurality of the third branch gates; the second active portion includes two second sub-active portions arranged at intervals, the third active portion includes two third sub-active portions arranged at intervals, the second sub-active portion and the third sub-active portion extend along the first direction, the fourth active portion includes two fourth sub-active portions arranged at intervals, and the two fourth sub-active portions overlap with the fourth gate; Among them, in the second direction, the width of the second sub-active portion is greater than the width of the third sub-active portion, the width of the fourth sub-active portion is equal to the width of the third sub-active portion, and the fourth sub-active portion is connected to the corresponding third sub-active portion.

12. The display panel according to claim 11, characterized in that: The array driving layer further comprises a second active layer disposed between the third gate layer and the second gate layer, wherein the second active layer comprises a metal oxide semiconductor; The second active layer includes the first active portion, the first active portion includes two first sub-active portions that are spaced apart, the first sub-active portions extend along the first direction, and the two first sub-active portions and a plurality of the first branch gates overlap.

13. The display panel according to claim 12, characterized in that: The array driving layer further comprises a first source-drain electrode layer disposed on a side of the third gate layer away from the second gate layer, wherein the first source-drain electrode layer comprises the first source electrode, the first drain electrode, the second source electrode and the second drain electrode; Wherein, the first source includes a first main source and a plurality of first branch sources arranged in parallel and at intervals, the first drain includes a plurality of first branch drains, the first main source extends along the first direction, the first branch source extends along the second direction, a side of the plurality of first branch sources away from the signal generating module is connected to the first main source, the plurality of first branch drains extends along the second direction, and the plurality of first branch drains are arranged between the plurality of first branch sources; Furthermore, the second drain includes a second main drain and a plurality of second branch drains that are spaced apart and arranged in parallel, the second source includes a plurality of second branch sources, the second main drain extends along the first direction, the second branch drain extends along the second direction, a plurality of second branch drains are connected to the second main drain near the signal generating module, a plurality of second branch sources extend along the second direction, and a plurality of second branch sources are arranged between a plurality of second branch drains, and the first main source and the second main drain are connected.

14. The display panel according to claim 13, characterized in that: The first source-drain electrode layer further includes a first connecting segment, and the first connecting segment is arranged between an end of the second branch source electrode close to the signal generating module and the second trunk drain electrode; The third gate layer further includes a first protrusion disposed on the fifth trunk gate at a side away from the signal generating module, the first protrusion is connected to the fifth trunk gate, and the first protrusion extends toward a side away from the signal generating module; The first end of the first connecting segment overlaps with the first protrusion and the second main gate, the second end of the first connecting segment overlaps with the second main gate, and the first connecting segment is electrically connected to the first protrusion, and the second end of the first connecting segment is electrically connected to the second main gate.

15. The display panel according to claim 14, characterized in that: The first source-drain electrode layer further includes a second connecting segment, and the second connecting segment is arranged on a side of the first branch drain electrode close to the signal generating module; Wherein, the second gate layer further includes a second protrusion disposed on a side close to the signal generating module, the second protrusion is connected to the first trunk gate, and the second protrusion extends toward a side close to the signal generating module; The third gate layer further includes a third protrusion disposed on a side close to the signal generating module, the third protrusion is connected to the fifth trunk gate, and the third protrusion extends toward a side close to the signal generating module; The first end of the second connecting segment overlaps with the second protrusion, the second end of the second connecting segment overlaps with the third protrusion, and the first end of the second connecting segment is electrically connected to the third protrusion, and the second end of the second connecting segment is electrically connected to the fourth protrusion.

16. The display panel according to claim 14, characterized in that: The first source-drain electrode layer further includes a third source electrode, a third drain electrode, a fourth source electrode and a fourth drain electrode; Wherein, the third source includes a third main source and two third branch sources arranged in parallel and at intervals, one end of the two third branch sources close to the signal generating module is connected to the third main source, the third drain includes a third main drain and two third branch drains arranged in parallel and at intervals, one end of the two third branch drains close to the signal generating module is connected to the third main drain, and the two third branch sources and the two third branch drains are alternately arranged in the first direction; The fourth source and the fourth drain extend along the second direction, the fourth drain is arranged adjacent to the third branch drain, the fourth source is arranged on a side of the fourth drain away from the third branch drain, and the first end of the fourth source is connected to the third main drain.

17. The display panel according to claim 16, characterized in that: The first source-drain electrode layer further includes a first extension segment connected to the third source electrode, the first extension segment extends along the second direction, and the first extension segment is located in the area where the signal generating module is located; The gate driving circuit includes a plurality of repeating units, each of the repeating units includes at least four GOA units, and in the repeating units, the first extension segments in some of the GOA units have different lengths in the first direction.

18. The display panel according to claim 16, characterized in that: The array driving layer further comprises a second source-drain layer arranged on a side of the first source-drain layer away from the base substrate, the second source-drain layer comprises the first high potential line, the first low potential line and the second high potential line, the first high potential line, the first low potential line and the second high potential line are arranged in parallel and extend along the first direction; Wherein, the first high potential line overlaps with a plurality of the second branch sources and a plurality of the second branch drains in each of the GOA units, and the first high potential line is electrically connected to a plurality of the second branch sources in each of the GOA units; The first low potential line overlaps with a plurality of the first branch sources and a plurality of the first branch drains in each of the GOA units, and the first low potential line is electrically connected to a plurality of the first branch drains in each of the GOA units; The second high potential line overlaps with the third sub-active portion and the fourth sub-active portion close to the signal generating module. In the second direction, the width of the first high potential line is equal to the width of the first low potential line, and the width of the first high potential line is greater than the width of the second high potential line.

19. The display panel according to claim 4, characterized in that: The signal generating module comprises: A level transmission signal selection module is electrically connected between the start signal line and the fourth node; A pull-up control module, controlling the potential of the first node K according to the potential of the fourth node and the potential of the second clock signal line; A first filtering module is electrically connected between the fifth node and the first node, and a control end of the first filtering module is electrically connected to a reset signal line; A second filtering module, electrically connected between the fifth node and the second node, wherein a control end of the second filtering module receives the first gate driving signal of the N-2th stage; A first inverting module, connected between the first node and the third node; a feedback module connected between the first node and the third node; and A voltage regulating module, wherein a first end of the voltage regulating module is electrically connected to the first low potential line, a second end of the voltage regulating module is connected to the gate of the first output transistor, and a control end of the voltage regulating module is electrically connected to the third node.

20. The display panel according to any one of claims 1 to 19, characterized in that: The first gate driving signal is a positive pulse signal, and the second gate driving signal is a negative pulse signal; Wherein, within a time interval of one frame, the first signal output terminal outputs two positive pulse signals, and the second signal output terminal outputs one negative pulse signal.

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