Driving method of display panel and display device

Abstract

The embodiment of the invention provides a driving method of a display panel and a display device. According to the driving method of the display panel, a first driving signal is output to a gate driving circuit in a first time period, so that a scanning line outputs an effective level, a first data voltage is output to a data line, and a first common voltage is output to a common signal line, so that a cholesteric liquid crystal layer is configured to be in a transparent state; outputting a second data voltage to the data line in a second time period, outputting a second common voltage to the common signal line to enable the cholesteric liquid crystal layer to be configured in a reflection state, and outputting a second driving signal to the gate driving circuit to enable the scanning line to output a scanning signal and outputting a data signal to the data line in a third time period, the cholesteric liquid crystal layer is configured to be in a fog state, so that normal display of the cholesteric liquid crystal display panel is realized through the driving framework of the liquid crystal display panel, the cost is reduced, and the applicability of the driving framework is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel driving method and a display device. Background Art

[0002] Cholesteric liquid crystal (CLC) display devices are widely used due to their low power consumption, eye protection, high contrast and rich colors. The specific display process of cholesteric liquid crystal display devices is to achieve different display effects by converting cholesteric liquid crystal between transparent state, foggy state and reflective state. Liquid crystal display devices refer to controlling the display brightness of pixels by controlling the deflection angle of liquid crystal, thereby realizing display. Since the liquid crystal in the liquid crystal display device only has two states, namely, transparent state and non-transparent state, and the cholesteric liquid crystal in the cholesteric liquid crystal display device has transparent state, foggy state and reflective state, and the transition voltage of each state of cholesteric liquid crystal is different from the deflection voltage of the liquid crystal in the liquid crystal display device, for example, the transition voltage of the transparent state of cholesteric liquid crystal reaches more than 40 volts, resulting in the driving architecture of the liquid crystal display device being unable to be suitable for the cholesteric liquid crystal display device, and the driving architecture needs to be redesigned for the cholesteric liquid crystal display device, which leads to higher costs and reduced applicability of the driving architecture.

[0003] Therefore, the existing cholesteric liquid crystal display device cannot use the driving architecture of the liquid crystal display device, resulting in a technical problem of high cost. Summary of the invention

[0004] The embodiments of the present application provide a display panel driving method and a display device, which are used to solve the technical problem that the existing cholesteric liquid crystal display device cannot use the driving architecture of the liquid crystal display device, resulting in high cost.

[0005] In a first aspect, this embodiment provides a method for driving a display panel, including:

[0006] receiving a display request of a display panel, wherein the display panel includes a cholesteric liquid crystal layer;

[0007] According to a display request of the display panel, within a first time period, a first driving signal is output to a gate driving circuit so that a scan line outputs an effective level, a first data voltage is output to a data line, and a first common voltage is output to a common signal line, so that the cholesteric liquid crystal layer is configured to be in a transparent state; a difference between the first data voltage and the first common voltage is greater than a transition voltage of the display panel;

[0008] In a second time period, a second data voltage is output to the data line and a second common voltage is output to the common signal line, so that the cholesteric liquid crystal layer is configured to be in a reflective state; the second data voltage is equal to the second common voltage;

[0009] In a third time period, a second driving signal is output to the gate driving circuit to make the scanning line output a scanning signal, and a data signal is output to the data line, so that the cholesteric liquid crystal layer is configured to be in a fog state.

[0010] In some embodiments, the gate driving circuit includes a plurality of transistors, and the transistors are in an on state during the first time period and the second time period.

[0011] In some embodiments, the gate drive circuit includes a clock signal line, a low potential signal line and a low frequency clock signal terminal. In the first time period and the second time period, the clock signal line, the low potential signal line and the low frequency clock signal terminal output a high potential signal.

[0012] In some embodiments, the gate driving circuit includes a plurality of clock signal lines. In the third time period, each of the clock signal lines outputs a valid level in a time-sharing manner, and there is no overlap in the time when each of the clock signal lines outputs a valid level.

[0013] In some embodiments, in the third time period, the pulse width of the effective level of the scanning signal is smaller than the pulse width of the effective level of the data signal, and the writing time of the effective level of the data signal is earlier than the writing time of the corresponding effective level of the scanning line, and the ending time of the effective level of the data signal is later than the ending time of the effective level of the corresponding scanning line.

[0014] In some embodiments, the gate driving circuit further includes a start signal line, and the start signal line outputs a valid level in the first time period, the second time period, and the third time period, respectively.

[0015] In some embodiments, the third time period includes at least two frames, and in any frame, the signal output to the data line is the same.

[0016] In some embodiments, the first data voltage and the second data voltage have the same polarity; or the second data voltage is 0.

[0017] In some embodiments, after a third time period, a shutdown signal is output to the gate driving circuit and the data line to keep the display panel in a foggy state.

[0018] In a second aspect, the present embodiment further provides a display device, the display device comprising a display panel and a timing control board, the display panel being connected to the timing control board, the timing control board comprising:

[0019] A receiving module, configured to receive a display request from a display panel, wherein the display panel includes a cholesteric liquid crystal layer;

[0020] A driving module, for outputting a first driving signal to a gate driving circuit in a first time period according to a display request of the display panel so that the scan line outputs a high potential signal, outputs a first data voltage to the data line, and outputs a first common voltage to the common signal line, so that the cholesteric liquid crystal layer is configured as a transparent state; a difference between the first data voltage and the first common voltage is greater than a transition voltage of the cholesteric liquid crystal; in a second time period, outputting a second data voltage to the data line and a second common voltage to the common signal line, so that the cholesteric liquid crystal layer is configured as a reflective state; the second data voltage is equal to the second common voltage; in a third time period, outputting a second driving signal to the gate driving circuit so that the scan line outputs a scan signal, and outputting a data signal to the data line, so that the cholesteric liquid crystal layer is configured as a foggy state.

[0021] Beneficial effects:

[0022] The embodiment of the present application provides a driving method and a display device for a display panel; after receiving a display request of the display panel, the driving method of the display panel outputs a first driving signal to a gate driving circuit in a first time period so that a scan line outputs a valid level, thereby turning on pixel units of all rows, and outputs a first data voltage to a data line and a first common voltage to a common signal line, so that a cholesteric liquid crystal layer is configured to a transparent state, and the display panel is reset; then, in a second time period, a second data voltage is output to the data line and a second common voltage is output to the common signal line, so that the cholesteric liquid crystal layer is configured to a reflective state, and the display panel is initialized; then, in a third time period, a second driving signal is output to a gate driving circuit so that the scan line outputs a scan signal and a data signal is output to the data line, so that the cholesteric liquid crystal layer is configured to a fog state, and can be maintained in the fog state for display, thereby realizing normal display of the cholesteric liquid crystal display panel through the driving architecture of the liquid crystal display panel, reducing costs, and improving the applicability of the driving architecture.

[0023] Other features and advantages of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0025] Figure 1 It is a flow chart of a method for driving a display panel provided in an embodiment of the present application.

[0026] Figure 2 A schematic diagram of three states of a display panel provided in an embodiment of the present application.

[0027] Figure 3 A circuit diagram of a gate driving circuit of a display panel provided in an embodiment of the present application.

[0028] Figure 4 This is a first timing diagram of a display panel provided in an embodiment of the present application.

[0029] Figure 5 A timing diagram of a gate driving circuit of a display panel provided in an embodiment of the present application.

[0030] Figure 6 This is a second timing diagram of the display panel provided in an embodiment of the present application.

[0031] Figure 7 A structural diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0032] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0033] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, which are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0034] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0035] The use of "suitable for" or "configured to" in this application is meant to be open and inclusive language, which does not exclude devices that are suitable for or configured to perform additional tasks or steps. In addition, the use of "based on" is meant to be open and inclusive, because the process, step, calculation or other action "based on" one or more stated conditions or values ​​can be based on additional conditions or values ​​beyond the stated values ​​in practice.

[0036] In this application, the word "exemplary" is used to mean "used as an example, illustration, or description." Any embodiment described in this application as "exemplary" is not necessarily to be construed as being preferred or advantageous over other embodiments. The following description is given to enable any technician in the field to implement and use the present application. In the following description, details are listed for the purpose of explanation. It should be understood that a person of ordinary skill in the art can recognize that the present application can be implemented without using these specific details. In other instances, well-known structures and processes will not be elaborated in detail to avoid obscuring the description of the present application with unnecessary details. Therefore, the present application is not intended to be limited to the embodiments shown, but is consistent with the widest scope consistent with the principles and features disclosed in the present application.

[0037] The embodiments of the present application aim to solve the technical problem that the existing cholesteric liquid crystal display device cannot use the driving architecture of the liquid crystal display device, resulting in high cost, and provide a display panel driving method and driving device, and a display device to solve the above technical problem.

[0038] The present application provides a method for driving a display panel. Figure 1 As shown, the driving method of the display panel includes:

[0039] S1, receiving a display request of a display panel, where the display panel includes a cholesteric liquid crystal layer.

[0040] Specifically, when the display panel needs to display, a display request of the display panel can be received to drive the display panel. The display request may include the setting position or relative position of each sub-pixel unit of the display panel, and may include the grayscale that each sub-pixel unit needs to display within a display time period of the display panel, so that the display panel can be driven according to the display request.

[0041] Specifically, a display time period may include multiple frames, specifically including a first time period, a second time period and a third time period.

[0042] Specifically, the display panel in the embodiment of the present application includes an array substrate, a color film substrate, and a cholesteric liquid crystal layer disposed between the array substrate and the color film substrate, and the material of the cholesteric liquid crystal layer is cholesteric liquid crystal. The embodiment of the present application sets a cholesteric liquid crystal layer in the array substrate and the color film substrate, and adopts the architecture of the liquid crystal display panel. It is only necessary to replace the liquid crystal in the liquid crystal layer with cholesteric liquid crystal and modify the driving timing, so that the cholesteric liquid crystal display panel can use the driving architecture of the liquid crystal display panel, improve the applicability of the driving architecture of the liquid crystal display panel, and when forming the cholesteric liquid crystal display panel, there is no need to redesign the corresponding film layer structure and driving architecture for the cholesteric liquid crystal display panel, thereby reducing the cost and design difficulty.

[0043] Specifically, the specific design of the array substrate and the color film substrate in the embodiment of the present application can refer to the design of the array substrate and the color film substrate of the common liquid crystal display panel. For example, the array substrate includes a substrate, a thin film transistor array layer and a pixel electrode layer, the pixel electrode layer includes a plurality of spaced pixel electrodes, and the color film substrate includes a common electrode layer, a color resist layer and a black matrix layer arranged on the entire surface. It can be seen that the common electrode layer in the display panel in the embodiment of the present application is arranged as a whole layer, while the common electrode layer in the current cholesteric liquid crystal display panel is a plurality of common electrode blocks.

[0044] Specifically, the array substrate can also be a COA (Color On Array, a color film layer is arranged on the array side) substrate. It can be understood that the embodiments of the present application are not limited to this. The two substrates of the display panel in the embodiments of the present application can be two substrates in a conventional liquid crystal display panel. There is no need to separately set up different substrates and corresponding driving architectures for the cholesteric liquid crystal display panel, thereby reducing design costs and preparation costs, reducing design difficulty and improving production efficiency.

[0045] Specifically, Figure 2 As shown, taking a display panel provided in an embodiment of the present application as an example, the display panel 1 includes an array substrate 11, a color film substrate 12 and a cholesteric liquid crystal layer 13. The cholesteric liquid crystal layer 13 includes three states, and the three states can be switched. Specifically, when the cholesteric liquid crystal layer 13 is in a reflective state, it will reflect the light 14. When the cholesteric liquid crystal layer 13 is in a foggy state, it will reflect part of the light and transmit part of the light. When the cholesteric liquid crystal layer 13 is in a transparent state, it will transmit the light.

[0046] Specifically, Figure 2As shown, when the cholesteric liquid crystal layer 13 is in a reflective state, an external electric field can be applied, and when the voltage of the external electric field is less than the transition voltage of the display panel, the cholesteric liquid crystal layer 13 can be changed from the reflective state to the foggy state, and when the voltage of the external electric field is greater than the transition voltage of the display panel, the cholesteric liquid crystal layer 13 can be changed from the reflective state to the transparent state; when the cholesteric liquid crystal layer 13 is in a foggy state, an external electric field can be applied, and when the voltage of the external electric field is greater than the transition voltage of the display panel, the cholesteric liquid crystal layer 13 can be changed from the foggy state to the transparent state; when the cholesteric liquid crystal layer 13 is in a transparent state, the electric field can be quickly removed to change the cholesteric liquid crystal layer 13 from the transparent state to the reflective state, or the electric field can be slowly removed to change the cholesteric liquid crystal layer 13 from the transparent state to the foggy state.

[0047] S2, according to the display request of the display panel, within the first time period, outputs a first drive signal to the gate drive circuit so that the scan line outputs a valid level, outputs a first data voltage to the data line, and outputs a first common voltage to the common signal line, so that the cholesteric liquid crystal layer is configured to be in a transparent state; the difference between the first data voltage and the first common voltage is greater than the transition voltage of the display panel.

[0048] Specifically, it can be understood that the gate driving circuit includes a plurality of signal lines. When the first driving signal is input to the gate driving circuit, the driving signal can be input to each signal line of the gate driving circuit so that the scanning line outputs a valid level.

[0049] Specifically, the display panel includes a plurality of scan lines, and each scan line can output a valid level.

[0050] Specifically, the effective level refers to an electrical signal that can turn on the transistor. For example, when the transistor is turned on when the gate input is high, the high potential is the effective level and the low potential is the invalid level. When the transistor is turned off when the gate input is high, and turned on when the gate input is low, the low potential is the effective level and the high potential is the invalid level. The embodiment of the present application is described by taking the case where the transistor is turned on when the gate input is high as an example, but the embodiment of the present application does not limit the effective level of the transistor to be a high potential.

[0051] Specifically, after receiving a display request from the display panel, considering that the cholesteric liquid crystal may remain in a foggy state and still display the content of the previous display screen, it is necessary to reset the display panel first to make the cholesteric liquid crystal layer in a transparent state, and then display the image to be displayed to avoid poor display.

[0052] Specifically, the display panel may include a gate driving circuit, which outputs a first driving signal to the gate driving circuit to make the scanning line output a valid level, thereby turning on all sub-pixel units, and outputs a first data voltage and a first common voltage to the data line and the common signal line respectively, so that the display panel is configured in a transparent state, so that normal display can be achieved.

[0053] Specifically, Figure 3 , Figure 4 As shown, the display panel includes a plurality of cascaded gate drive circuits 21, the gate drive circuit 21 includes a pull-up control transistor T11, a pull-up transistor T21, a pull-down transistor T31, a pull-down maintenance transistor T33, a first inversion transistor T41 and a second inversion transistor T42, the gate of the pull-up control transistor T11 in the first-stage gate drive circuit is connected to the start signal line STV, and the gates of the pull-up control transistors T11 in the other-stage gate drive circuits are connected to the signal output ends of the other-stage gate drive circuits ( Figure 3 In the example, the gate of the pull-up control transistor T11 of the gate drive circuit of this stage is connected to the signal output terminal G(N-1) of the gate drive circuit of the previous stage, but the embodiments of the present application are not limited to this. The gate of the pull-up control transistor of the gate drive circuit of this stage can be connected to the signal output terminal of the gate drive circuit of other stages), the first electrode of the pull-up control transistor T11 is connected to the output terminal G(N-1) of the gate drive circuit of the previous stage, the second electrode of the pull-up control transistor T11 and the gate of the pull-up transistor T21 are connected to the internal node Q(N) of this stage, the first electrode of the pull-up transistor T21 is connected to the clock signal line CK, the second electrode of the pull-up transistor T21 is connected to the signal output terminal G(N), the gate of the pull-down transistor T31 is connected to the gate of the pull-down maintenance transistor T33, and the gate of the pull-down transistor T31 is connected to the gate of the pull-down maintenance transistor T33. The first electrode is connected to the low potential signal line VSS, the second electrode of the pull-down transistor T31 is connected to the signal output terminal G(N), the first electrode of the pull-down maintenance transistor T33 is connected to the low potential signal line VSS, the second electrode of the pull-down maintenance transistor T33 is connected to the internal node Q(N) of this stage, the gate of the first inversion transistor T41 is connected to the internal node Q(N) of this stage, the first electrode of the first inversion transistor T41 is connected to the low potential signal line VSS, the second electrode of the first inversion transistor T41 is connected to the second electrode of the second inversion transistor T42, the gate of the second inversion transistor T42 and the first electrode of the second inversion transistor T42 are connected to the low frequency clock signal terminal LC, one end of the storage capacitor C is connected to the internal node Q(N) of this stage, and the other end of the storage capacitor C is connected to the signal output terminal G(N).

[0054] Specifically, it can be understood that the signal output end of each level of gate driving circuit will be connected to the scan line. Therefore, when the influence of impedance is not considered, the output signal of the signal output end G(N) of each level of gate driving circuit is the input signal of each scan line.

[0055] Specifically, it is understandable that Figure 3 A circuit diagram of a gate driving circuit is shown in FIG. 1 , but the embodiments of the present application are not limited to this, and the specific circuit of the gate driving circuit can be of other designs.

[0056] Specifically, Figure 4 As shown, in the first time period t1, the start signal line STV outputs a valid level, so that the gate drive circuit works normally. Figure 5 As shown, the clock signal line CK, the low potential signal line VSS and the low frequency clock signal terminal LC all output high potential signals, so that each level of gate driving circuit outputs a high potential, so that in the first time period, the transistors in the gate driving circuit are all turned on, so that in the first time period, the gate driving circuits of each level output a high potential, Figure 4 Taking the signal output terminal G(N) of the Nth level gate driving circuit and the signal output terminal G(N+1) of the N+1th level gate driving circuit outputting high potential as an example, the signal output terminals of the other levels of gate driving circuits can all output high potential in the first time period t1, so that each row or column of sub-pixels (depending on the different pixel architectures, the scanning line is set in different ways, and the embodiments of the present application are not limited to this) can be turned on, and then the data line Data inputs the first data voltage Data-H, the common signal line VCOM inputs the first common voltage VCOM-L, and the difference between the first data voltage Data-H and the first common voltage VCOM-L is greater than the transition voltage of the display panel, then the display panel will change from a reflective state or a foggy state to a transparent state.

[0057] Specifically, it can be understood that the display panel includes multiple data lines, each of which can input the first data voltage Data-H in the first time period. Since the common electrode layer is set as a whole layer, when the voltage drop is not considered or other methods are used to reduce the voltage drop, the entire surface of the common electrode layer can be regarded as the first common voltage VCOM-L, so that the cholesteric liquid crystals in the areas corresponding to each sub-pixel unit of the display panel are all transformed into a transparent state.

[0058] Specifically, it can be understood that after the data line outputs a signal, it will be transmitted to the pixel electrode, the common signal line is connected to the common electrode layer, and after the common signal line inputs a signal, it will be transmitted to the common electrode layer, so that the cholesteric liquid crystal changes its form under the electric field formed by the pixel electrode and the common electrode layer. Since when the external electric field is greater than the transition voltage of the display panel, the display panel can be transformed into a transparent state regardless of whether it is in a reflective state or a foggy state, and when the display panel is in a transparent state, it will not display, so the display panel can be reset.

[0059] S3, in a second time period, outputting a second data voltage to the data line and a second common voltage to the common signal line, so that the cholesteric liquid crystal layer is configured to be in a reflective state; the second data voltage is equal to the second common voltage.

[0060] Specifically, after the display panel is reset in the first time period, the display panel needs to be initialized. At this time, the electric field can be quickly removed to change the cholesteric liquid crystal layer from a transparent state to a reflective state.

[0061] Specifically, Figure 4 As shown, it can be seen that in the second time period t2, the first drive signal is continuously output to the gate drive circuits of each level, so that each transistor is in the on state in the second time period, and the gate drive circuit outputs a high potential signal to make the scan line output a valid level. Each scan line is kept at a high potential, so that all sub-pixel units are turned on. At the same time, the second data voltage Data-L is output to the data line Data, and the second common voltage VCOM-H is output to the common signal line VCOM, so that the second data voltage Data-L is equal to the second common voltage VCOM-H, then there can be no voltage difference between the pixel electrode and the common electrode layer, which is equivalent to quickly removing the electric field, so that the cholesteric liquid crystal will change from a transparent state to a reflective state, and the display panel is initialized.

[0062] Specifically, it can be seen that in the embodiment of the present application, the common signal line has two different potentials, and the common signal line in the existing liquid crystal display panel is a constant voltage. Therefore, the signal output to the common signal line can be modified to make it editable in timing, so that the change of different forms of cholesteric liquid crystal can be achieved through the change of the signals of the common signal line and the data line.

[0063] In some embodiments, Figures 3 to 5As shown, the gate driving circuit 21 includes a clock signal line CK, a low potential signal line VSS and a low frequency clock signal terminal LC. In the first time period t1 and the second time period t2, the clock signal line CK, the low potential signal line VSS and the low frequency clock signal terminal LC output high potential signals. By making the clock signal line, the low potential signal line and the low frequency clock signal terminal in the gate driving circuit all output high potential signals, no matter which transistor is turned on, the signal output terminal of each level of gate driving unit outputs a high potential signal, so that each sub-pixel unit can be turned on, so that in the first time period and the second time period, the sub-pixel units in the display panel are all turned on, and the display panel is reset and initialized in sequence through the difference in signals between the data line and the common signal line.

[0064] Specifically, in the existing liquid crystal display panel, the low-potential signal line VSS continuously outputs a low-potential signal. In the embodiment of the present application, in order to adopt the architecture of the liquid crystal display panel to realize the driving of cholesteric liquid crystal, the low-potential signal line VSS is modified to an editable timing, and the timing of the clock signal line and the low-frequency clock signal end is also modified.

[0065] S4, in a third time period, outputting a second driving signal to the gate driving circuit so that the scanning line outputs a scanning signal, and outputting a data signal to the data line, so that the cholesteric liquid crystal layer is configured to be in a fog state.

[0066] Specifically, it can be understood that after the display panel is initialized, the display panel needs to display the picture. At this time, the second drive signal can be output to the gate drive circuit, so that the scan line outputs a scan signal to turn on the corresponding pixel, and the data line outputs a data signal, so that each sub-pixel unit of the display panel inputs a corresponding voltage and is charged to different degrees of fog, thereby displaying different gray levels and realizing normal display of the display picture.

[0067] Specifically, it can be understood that compared with the different frames in the current liquid crystal display panel, when the cholesteric liquid crystal display panel is charged in the embodiment of the present application, the length of the third time period will be multiple frames, and the picture of each frame is the same. Through the electric field accumulation effect, each sub-pixel unit can be continuously charged to a foggy state, thereby displaying normally.

[0068] Specifically, it can be understood that the first time period, the second time period and the third time period in the embodiment of the present application can all include multiple frames, and the lengths of the first time period, the second time period and the third time period can be different. Compared with the current liquid crystal display panel in which one display screen is one frame, a display time period in the embodiment of the present application includes multiple frames.

[0069] Specifically, when the second driving signal is output to the gate driving circuit, each gate driving circuit can be controlled to output different signals according to the different display images of the display panel. Accordingly, each row of scanning lines can output the same or different signals, for example, each row of scanning lines inputs a high potential signal, or some scanning lines input a high potential signal and some scanning lines input a low potential signal, or all scanning lines input a low potential signal; at the same time, according to the different grayscales of each sub-pixel unit, each data line outputs a different signal, thereby realizing normal display of the display image.

[0070] In some embodiments, Figures 4 to 6 As shown, the gate driving circuit 21 includes a plurality of clock signal lines CK. In the third time period t3, each of the clock signal lines CK outputs a valid level in a time-sharing manner, and the time when each of the clock signal lines CK outputs a valid level does not overlap.

[0071] Specifically, Figures 4 to 6 As shown, the clock signal line CK includes a first clock signal line CK1, a second clock signal line CK2, a third clock signal line CK3, a fourth clock signal line CK4, a fifth clock signal line CK5 and a sixth clock signal line CK6. The first clock signal line CK1 to the sixth clock signal line CK6 output valid levels in sequence, and the time when each clock signal line outputs a valid level does not overlap. Compared with the liquid crystal display panel that needs to adopt a pre-charging design, the valid levels of each clock signal line will overlap, and in the embodiment of the present application, it is necessary to output non-overlapping valid levels.

[0072] Specifically, Figure 6 As shown, it can be seen that when each clock signal line outputs a valid level, each scan line will output a corresponding scan signal. Figure 6 1 shows the timings of the first scan line Gate1 , the second scan line Gate2 , the seventh scan line Gate7 and the eighth scan line Gate8 . For the timings of other scan lines, corresponding outputs can be performed according to different requirements.

[0073] Specifically, Figure 6 As shown, Figure 6 The timing of the internal node Q(1) in the first-level gate drive circuit and the internal node Q(4) in the fourth-level gate drive circuit are shown in the figure. The timing of the internal nodes in other levels of gate drive circuits can refer to the timing of the above-mentioned internal nodes, and corresponding outputs can be made as required.

[0074] In some embodiments, Figures 4 to 6As shown, in the third time period t3, the pulse width of the effective level of the scanning signal is smaller than the pulse width of the effective level of the data signal, and the writing time of the effective level of the data signal is earlier than the writing time of the effective level of the corresponding scanning line, and the ending time of the effective level of the data signal is later than the ending time of the effective level of the corresponding scanning line. By making the timing of the data signal completely wrap the timing of the corresponding scanning signal, and staggering the output time of the effective level of each clock signal line, the problem of mischarging can be avoided.

[0075] like Figure 4 As shown, in the third time period t3, the data line Data can output the data signal Data0, and the potential of the data signal Data0 can be a voltage between the first data voltage Data-H and the second data voltage Data-L.

[0076] In some embodiments, Figures 3 to 6 As shown, the gate driving circuit 21 further includes a start signal line STV, and the start signal line STV outputs a valid level in the first time period t1, the second time period t2, and the third time period t3. By making the start signal line output a valid level in the first time period, the second time period, and the third time period, the gate driving circuit is turned on and works in the three time periods.

[0077] In some embodiments, the third time period t3 includes at least two frames, and in any frame, the signal output to the data line Data is the same. By making the third time period include multiple frames, the signal input to the data line in each frame is the same, and the pixel is continuously charged to the fog state through the electric field accumulation effect.

[0078] In some embodiments, the first data voltage and the second data voltage have the same polarity; or the second data voltage is 0.

[0079] Specifically, there is no need to use polarity inversion in the embodiments of the present application. Compared with the current liquid crystal display panel, the data voltage will have positive and negative polarities. For example, the high potential of the data line is positive one volt, and the low potential of the data line is negative one volt. In the embodiments of the present application, the first data voltage of the data line can be made positive two volts, and the second data voltage of the data line can be 0. It can be understood that the specific numerical values ​​here are only examples, and the embodiments of the present application are not limited to this.

[0080] In some embodiments, after the third time period, a shutdown signal is output to the gate drive circuit and the data line to keep the display panel in a foggy state. By turning off the gate drive circuit and the data line in the third time period, the display panel can be kept in a foggy state. Since the foggy state of the cholesteric liquid crystal is relatively stable, the display can be maintained without outputting a potential, thereby reducing power consumption.

[0081] Specifically, the source driver chip and the gate driver circuit can be adjusted to a dormant state without outputting a signal until the next picture needs to be displayed, and then the next picture can be refreshed and written again.

[0082] The embodiment of the present application provides a method for driving a display panel. The method for driving a display panel utilizes the driving architecture of a liquid crystal display panel to drive cholesteric liquid crystals, and modifies the timing of each component and signal line in the liquid crystal display panel, so as to realize the normal display of the cholesteric liquid crystal display panel, and it is not necessary to set a corresponding structure and driving architecture for the cholesteric liquid crystal display panel separately, thereby reducing the design cost and the production cost, shortening the design cycle and the production cycle, and improving the applicability of the driving architecture. It can be seen from the above embodiment that the timing of each signal line in the embodiment of the present application is different from the timing of the current cholesteric liquid crystal display device, and is different from the timing of the current liquid crystal display panel, so that the cholesteric liquid crystal is driven by the structure of the liquid crystal display panel, reducing the cost and improving the applicability of the driving architecture.

[0083] At the same time, the embodiment of the present application provides a display device, such as Figure 7 As shown, the display device 31 includes a display panel 1 and a timing control board 30, the display panel 1 is connected to the timing control board 30, and the timing control board 30 includes:

[0084] A receiving module 301, configured to receive a display request from a display panel, wherein the display panel includes a cholesteric liquid crystal layer;

[0085] The driving module 302 is used to output a first driving signal to the gate driving circuit in a first time period according to the display request of the display panel, so that the scan line outputs a high potential signal, outputs a first data voltage to the data line, and outputs a first common voltage to the common signal line, so that the cholesteric liquid crystal layer is configured to be in a transparent state; the difference between the first data voltage and the first common voltage is greater than the transition voltage of the cholesteric liquid crystal; in a second time period, output a second data voltage to the data line and output a second common voltage to the common signal line, so that the cholesteric liquid crystal layer is configured to be in a reflective state; the second data voltage is equal to the second common voltage; in a third time period, output a second driving signal to the gate driving circuit so that the scan line outputs a scan signal, and outputs a data signal to the data line, so that the cholesteric liquid crystal layer is configured to be in a fog state. Specifically, the display device includes a memory and a processor, the memory stores a computer program, and when the computer program is executed by the processor, the display panel driving method described in any of the above embodiments is implemented.

[0086] An embodiment of the present application further provides a computer-readable storage medium on which a computer program is stored. The computer program is loaded by a processor to execute the steps in the method for driving a display panel in any one of the above embodiments.

[0087] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0088] The above is a detailed introduction to a display panel driving method and a display device provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A method for driving a display panel, characterized in that: include: receiving a display request of a display panel, wherein the display panel includes a cholesteric liquid crystal layer; According to a display request of the display panel, within a first time period, a first driving signal is output to a gate driving circuit so that a scan line outputs an effective level, a first data voltage is output to a data line, and a first common voltage is output to a common signal line, so that the cholesteric liquid crystal layer is configured to be in a transparent state; a difference between the first data voltage and the first common voltage is greater than a transition voltage of the display panel; In a second time period, a second data voltage is output to the data line and a second common voltage is output to the common signal line, so that the cholesteric liquid crystal layer is configured to be in a reflective state; the second data voltage is equal to the second common voltage; In a third time period, a second driving signal is output to the gate driving circuit to make the scanning line output a scanning signal, and a data signal is output to the data line, so that the cholesteric liquid crystal layer is configured to be in a fog state.

2. The method for driving a display panel according to claim 1, wherein: The gate driving circuit includes a plurality of transistors, and the transistors are in an on state during the first time period and the second time period.

3. The method for driving a display panel according to claim 2, wherein: The gate driving circuit includes a clock signal line, a low potential signal line and a low frequency clock signal terminal. In the first time period and the second time period, the clock signal line, the low potential signal line and the low frequency clock signal terminal output a high potential signal.

4. The method for driving a display panel according to claim 3, wherein: The gate driving circuit includes a plurality of clock signal lines. In the third time period, each of the clock signal lines outputs a valid level in a time-sharing manner, and the time when each of the clock signal lines outputs a valid level does not overlap.

5. The method for driving a display panel according to claim 3, wherein: In the third time period, the pulse width of the effective level of the scanning signal is smaller than the pulse width of the effective level of the data signal, and the writing time of the effective level of the data signal is earlier than the writing time of the effective level of the corresponding scanning line, and the ending time of the effective level of the data signal is later than the ending time of the effective level of the corresponding scanning line.

6. The method for driving a display panel according to claim 3, wherein: The gate driving circuit further includes a start signal line, and the start signal line outputs a valid level in the first time period, the second time period, and the third time period respectively.

7. The method for driving a display panel according to claim 1, wherein: The third time period includes at least two frames, and in any frame, the signals output to the data lines are the same.

8. The method for driving a display panel according to claim 1, wherein: The first data voltage and the second data voltage have the same polarity; or the second data voltage is 0.

9. The method for driving a display panel according to claim 1, wherein: After a third time period, a shutdown signal is output to the gate driving circuit and the data line to keep the display panel in a foggy state.

10. A display device, characterized in that: It includes a display panel and a timing control board, wherein the display panel is connected to the timing control board, and the timing control board includes: A receiving module, configured to receive a display request from a display panel, wherein the display panel includes a cholesteric liquid crystal layer; A driving module, for outputting a first driving signal to a gate driving circuit in a first time period according to a display request of the display panel so that the scan line outputs a high potential signal, outputs a first data voltage to the data line, and outputs a first common voltage to the common signal line, so that the cholesteric liquid crystal layer is configured as a transparent state; a difference between the first data voltage and the first common voltage is greater than a transition voltage of the cholesteric liquid crystal; in a second time period, outputting a second data voltage to the data line and a second common voltage to the common signal line, so that the cholesteric liquid crystal layer is configured as a reflective state; the second data voltage is equal to the second common voltage; in a third time period, outputting a second driving signal to the gate driving circuit so that the scan line outputs a scan signal, and outputting a data signal to the data line, so that the cholesteric liquid crystal layer is configured as a foggy state.

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