Dual mode hardware reset

Abstract

The invention relates to a dual mode hardware reset. Systems and methods are disclosed that include providing, to a memory system, one of a first reset or a second reset for transitioning a low power mode to an operating power mode in response to a hardware reset signal and a value of a control bit on the memory system.

Description

[0001] Information about divisional applications

[0002] This application is a divisional application of the Chinese invention patent application with the application date of May 29, 2020, application number "202010472573.X", and invention name "Dual Mode Hardware Reset". Technical Field

[0003] The present disclosure relates to a host system, and in particular to a dual-mode hardware reset of the host system. Background Art

[0004] A memory device is a semiconductor circuit that provides electronic storage of data for a host system (e.g., a computer or other electronic device). A memory device can be volatile or non-volatile. Volatile memory requires power to maintain data and includes random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), or synchronous dynamic random access memory (SDRAM), etc. Non-volatile memory can retain stored data when power is off, and includes devices such as flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), resistance variable memory (such as phase change random access memory (PCRAM)), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM).

[0005] A host system (e.g., a host) typically includes a host processor, a first amount of host memory (e.g., main memory, typically volatile memory such as DRAM) to support the host processor, and one or more storage systems (e.g., typically non-volatile memory such as flash memory) that provide additional storage to retain data in addition to or separate from the main memory.

[0006] A storage system (e.g., a solid-state drive (SSD), a universal flash storage (UFS) device, etc.) may include a memory controller and one or more memory devices, the one or more memory devices including a number of (e.g., multiple) dies or logical units (LUNs). In some instances, each die may include multiple memory arrays and peripheral circuitry thereon, such as die logic or a die processor. The memory controller may include an interface circuitry configured to communicate with a host device (e.g., a host processor or interface circuitry) via a communication interface (e.g., a bidirectional parallel or serial communication interface). The memory controller may receive commands or operations associated with memory operations or instructions from the host system, such as read operations or write operations for transferring data (e.g., user data and associated integrity data, such as error data or address data, etc.) between the memory device and the host device, erase operations for erasing data from the memory device and performing drive management operations (e.g., data migration, garbage collection, block retirement), etc.

[0007] Software (e.g., programs), instructions, operating systems (OS), and other data are typically stored on a storage system and accessed by the main memory for use by the host processor. The main memory (e.g., RAM) is typically faster, more expensive, and a different type of memory device (e.g., volatile memory device) than most memory devices of the storage system (e.g., non-volatile memory devices, such as SSDs, etc.). In addition to the main memory, the host system may also include different forms of volatile memory that are typically faster than the main memory, such as a set of static memory (e.g., cache, typically SRAM), which in some instances is configured to operate at speeds approaching or exceeding the speed of the host processor, but with lower density and higher cost. Summary of the invention

[0008] One aspect of the present application relates to a host system, the host system comprising: a host device, the host device comprising a host processor; a storage system, the storage system comprising at least one non-volatile memory device, a control circuit system coupled to the non-volatile memory device, and a storage register for storing at least one control bit; and a communication interface, the communication interface being located between the host device and the storage system; and a reset interface, the reset interface being located between the host device and the storage system, wherein the host device is configured to control a power mode of the storage system, the power mode comprising an operating power mode and a low power mode disabling the communication interface, and wherein in the low power mode, the control circuit system is configured to provide the storage system with one of a first reset or a second reset for transitioning from the low power mode to the operating power mode in response to a reset signal from the host device on the reset interface and the value of the at least one control bit.

[0009] Another aspect of the present application relates to a system, comprising: a storage system, the storage system comprising a group of non-volatile memory cells, a control circuit system coupled to the group of non-volatile memory cells, and a control bit, wherein in an operating power mode of the storage system, the control circuit system is configured to communicate with a host device through a bidirectional communication interface; and wherein in a low power mode of the storage system, the control circuit system is configured to provide the storage system with one of a first reset or a second reset for transitioning from the low power mode to the operating power mode in response to a hardware reset signal and the value of the control bit.

[0010] Another aspect of the present application relates to a method implemented by a control circuit system of a storage system, the method comprising: receiving a hardware reset signal from a host device in a low power mode of the storage system; and providing one of a first reset or a second reset to the storage system for transitioning from the low power mode to an operating power mode in response to the received hardware reset signal and the value of a control bit on the storage system.

[0011] Yet another aspect of the present application relates to a machine-readable medium storing instructions which, when executed by a storage system, cause the storage system to perform operations including: receiving a hardware reset signal from a host device in a low power mode of the storage system; and providing the storage system with one of a first reset or a second reset for transitioning from the low power mode to an operating power mode in response to the received hardware reset signal and the value of a control bit on the storage system. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In the drawings, which are not necessarily drawn to scale, the same numerals may describe similar components in different views. The same numerals with different letter suffixes may represent different instances of similar components. The drawings generally illustrate various embodiments discussed in this document by way of example and not by way of limitation.

[0013] Figure 1 An example host system including a host device and a storage system is shown.

[0014] Figure 2 Example tables are shown that illustrate different parameters for different storage system configurations and the resulting wakeup latency and power savings.

[0015] Figure 3 An example method of a host system transitioning between different modes is generally presented.

[0016] Figure 4 An example schematic diagram of a 3D non-architecture semiconductor memory array is shown.

[0017] Figure 5 shows an example block diagram of a memory module.

[0018] Figure 6 A simplified block diagram of an information processing system is shown. DETAILED DESCRIPTION

[0019] Modern host systems including a host device, a storage system, and a communication interface have different power modes, including, for example, a normal (e.g., active) mode, one or more levels of power saving modes, such as a sleep mode, and a disconnected mode. In various sleep modes, certain system resources are powered off to save power, but the communication interface may remain active or in a reduced power state (higher than power down). Further, many host systems share power rails throughout the system, thereby preventing power from being removed from the storage system alone, thereby limiting power savings. Therefore, the host system may additionally include other power modes, such as a deep sleep mode, which is configured to allow the host system to power off most or all of the communication interface between the storage system and the host device to further reduce the power consumption of the host system as compared to the sleep mode.

[0020] For example, in a UFS system, a deep sleep mode may stop communication between a host device and a storage system on upstream and downstream channels of a communication interface (e.g., DIN_t, DIN_c and DOUT_t, DOUT_c, respectively), but keep a unidirectional hardware (HW) reset signal interface from the host device to the storage system separate from the upstream and downstream channels.

[0021] When in deep sleep mode, a power cycle or hardware reset signal may be required to return the storage system or communication interface to normal mode. Traditionally, the host device controls the deep sleep mode. Because the host cannot monitor the storage system while the communication interface is powered off, when returning to normal mode, the host device can reinitialize the storage system to a known state to continue normal operation. Such traditional reinitialization requires a certain amount of time.

[0022] The inventors of the present invention have recognized that, among other things, control bits at the storage system (e.g., tags, attributes, registers, descriptors, or other data structures of a memory device or storage system, etc.) may be added, or existing bits may be adapted and used to allow the hardware reset function to provide multiple (e.g., dual) behaviors at the storage system, such as a first full reset (e.g., traditional full reinitialization, etc.) and a second modified reset (e.g., modified initialization, etc.) that is faster than the first full reset.

[0023] A control bit (e.g., a hardware reset bit) may be stored in the storage system and controlled by the host device during normal operation (e.g., before entering a deep sleep mode). The control bit may be controlled by the storage system upon receiving a command from the host device at the storage system to enter a deep sleep mode (e.g., disabling a communication interface). When the host device provides instructions to the communication interface to resume normal mode, such as using a hardware reset signal, the storage system may control reinitialization, thereby waking up faster than conventional power cycling or hardware reset and reinitialization.

[0024] If the control bit is not set (e.g., if the bit value is "0"), then the storage system operation may be normal, including performing a conventional hardware reset when resuming to normal mode. A conventional hardware reset may trigger reinitialization of the storage system, loading (or reloading) all firmware, resetting the memory controller, performing a full initialization of one or more memory devices, etc. Powering down as many non-essential aspects of the storage system as possible achieves the greatest power savings, but also results in longer reinitialization times or wait times when waking up or resuming to normal mode.

[0025] In contrast, if the control bit is set (e.g., if the bit value is "1"), the memory system operation may enter a modified operation recovery mode that is configured to reduce the initialization wait time of a conventional (or "normal") hardware reset mode for recovery after a deep sleep power mode. If power is not removed from the system (e.g., if one or more power signals are maintained above a threshold), one or more components of the memory system may not require a full reinitialization to resume operation. When recovering from a deep sleep mode that retains some power (e.g., retains, removes, or a combination thereof, one or more of VCC, VCCQ, or VCCQ2, or if one or more voltage regulators or charge pumps are disabled, etc.), the one or more memory devices or memory controllers may not require a full reinitialization, but in certain instances (e.g., supply voltage below a threshold, etc.), the static memory (e.g., SRAM) of the memory system may need to be reloaded. In other instances, some power domains (e.g., voltage levels, regulators, charge pumps, etc.) that were disabled during the deep sleep mode may need to be powered back on. There is a trade-off between power savings and latency; the more power retained / used during deep sleep mode, the faster the wake-up time to resume normal mode.

[0026] If power is lost, or if the power level drops below a threshold operating level, the control bit may be reset (e.g., to a bit value of "0", etc.) so that a conventional hardware reset function will be triggered upon return to normal mode. If the storage system is not fully cycled and reinitialized, but a full storage system reset is required by the host device, the host device may reassert the hardware reset signal after the storage system wakes up from deep sleep mode to initiate a full reset.

[0027] Although described herein with respect to UFS and NAND systems, other types of storage systems or memories having faster wake-up times than NAND (e.g., 3D NAND), such as 3DXPoint memory, ferroelectric memory (FeRAM, or in some embodiments referred to as hybrid RAM, HRAM) may benefit even more than the UFS system described herein, resulting in a more significant time savings as a percentage of total wake-up time.

[0028] Figure 1An example system (e.g., host system) 100 is shown that includes a host device 105 (e.g., UFS host) and a storage system 110 (e.g., UFS device), which are configured to communicate through a communication interface (I / F) 115 (e.g., a bidirectional parallel or serial communication interface, such as a UFS interface). In one example, the communication interface 115 can be referred to as a host interface. The host device 105 can include a host processor 106 (e.g., a host central processing unit (CPU) or other processor or processing circuit system, such as a memory management unit (MMU), interface circuit system, etc.). In some examples, the host device 105 can include a main memory (MAIN MEM) 108 (e.g., DRAM, etc.) and optionally a static memory (STATIC MEM) 109 to support the operation of the host processor (HOST PROC) 106.

[0029] The storage system 110 may include a universal flash memory (UFS) device, an embedded MMC (eMMC TM ) device or one or more other memory devices. For example, if the storage system 110 includes a UFS device, the communication interface 115 may include a serial bidirectional interface as defined in one or more Joint Electron Device Engineering Council (JEDEC) standards (e.g., JEDEC Standard D223D (JESD223D), commonly referred to as JEDEC UFS Host Controller Interface (UFSHCI) 3.0, etc.), including, for example, an upstream channel and a downstream channel (e.g., DIN_t, DIN_c and DOUT_t, DOUT_c, respectively). The UFS device may further include a unidirectional reset signal interface (RST) 116 from the host device 105 to the storage system 110, such as a hardware reset signal interface.

[0030] In another example, if the storage system 110 includes an eMMC device, the communication interface 115 may include a plurality of parallel bidirectional data lines (e.g., DAT[7:0]) and one or more command lines as defined in one or more JEDEC standards (e.g., JEDEC Standard D84-B51 (JESD84-A51), commonly referred to as JEDEC eMMC Standard 5.1, etc.). In other examples, depending on the host device 105 and the storage system 110, the storage system 110 may include one or more other memory devices, or the communication interface 115 may include one or more other interfaces.

[0031] The storage system 110 may include a memory controller (MEM CTRL) 111 and a non-volatile memory device 112. The memory controller 111 may optionally include a limited amount of static memory 119 to support the operation of the memory controller 111. In one example, the non-volatile memory device 112 may include multiple non-volatile memory devices (e.g., dies or LUNs), such as (e.g., as shown by the stacked dashed lines below the non-volatile memory device 112) one or more stacked flash memory devices, etc., each of which includes a non-volatile memory (NVM) 113 (e.g., one or more groups of non-volatile memory cells) and a device controller (CTRL) 114 or other peripheral circuitry thereon (e.g., device logic, etc.) and is controlled by the memory controller 111 through an internal storage system communication interface (e.g., an Open Non-Flash Interface (ONFI) bus, etc.) separate from the communication interface 115. As used herein, control circuitry may refer to one or more of memory controller 111 , device controller 114 , or other peripheral circuitry in storage system 110 , NVM device 112 , and the like.

[0032] Flash memory devices typically include one or more groups of single-transistor memory cells, floating gate (FG) memory cells, or replacement gate (RG) memory cells. Two common types of flash memory array architectures include NAND architectures and NOR architectures. The memory cells of a memory array are typically arranged in a matrix. The gate of each memory cell in a row of the array is coupled to an access line (e.g., a word line). In a NOR architecture, the drain of each memory cell in a column of the array is coupled to a data line (e.g., a bit line). In a NAND architecture, the drain of each memory cell in a column of the array is coupled in series from source to drain between a source line and a bit line.

[0033] Each memory cell in a semiconductor memory array of NOR, NAND, 3D crosspoint, FeRAM, MRAM, or one or more other architectures can be independently or uniformly programmed to one or more programming states. A single-level cell (SLC) can represent one data bit (e.g., 1 or 0) per cell in one of two programming states. A multi-level cell (MLC) can represent two or more data bits (e.g., 2 n , where n is the number of data bits). In some instances, MLC may refer to a memory cell that can store two data bits in one of four programming states. Triple-layer cell (TLC) may represent three data bits per cell in one of eight programming states. Quad-layer cell (QLC) may represent four data bits per cell in one of 16 programming states. In other instances, MLC may refer to any memory cell that can store more than one data bit per cell, including TLC and QLC, etc.

[0034] The storage system 110 may include a multimedia card (MMC) solid-state storage device (e.g., a micro secure digital (SD) card, etc.). The MMC device includes multiple parallel interfaces (e.g., an 8-bit parallel interface) with the host device 105 and is typically removable and detachable from the host device. In contrast, an embedded MMC (eMMC) device is attached to a circuit board and is considered a host device component with a read speed comparable to a Serial ATA (SATA)-based SSD device. As the demand for mobile device performance, such as fully enabling virtual reality devices or augmented reality devices, taking advantage of increasing network speeds, etc., continues to increase, storage systems have transitioned from a parallel communication interface between the storage system and the host device to a serial communication interface between the storage system and the host device. The UFS device, which includes a controller and firmware, communicates with the host device using a low voltage differential signaling (LVDS) serial interface with a dedicated read / write path, thereby further increasing the read / write speed between the host device and the storage system.

[0035] In three-dimensional (3D) architecture semiconductor memory device technology, vertical floating gate (FG) memory structures or replacement gate (RG) (or charge trapping) memory structures can be stacked to increase the number of layers, physical pages, and therefore increase the density of memory cells in the memory device. Data is usually stored arbitrarily on the storage system as small units. Even when accessed as a single unit, data can be received in the form of small random 4-16k single file reads (for example, 60%-80% of operations are less than 16k). It is difficult for users and even kernel applications to indicate that data should be stored as a continuous cohesive unit. File systems are usually designed to optimize space usage rather than optimizing sequential retrieval space.

[0036] The memory controller 111 may receive instructions from the host device 105 and may communicate with the non-volatile memory device 112, such as transferring (e.g., writing or erasing) data to or transferring (e.g., reading) data from one or more memory cells of the non-volatile memory device 112. The memory controller 111 may include, among other things, circuitry or firmware, etc., such as a plurality of components or integrated circuits. For example, the memory controller 111 may include one or more memory control units, circuits, or components configured to control access across the memory array and provide a translation layer between the host device 105 and the storage system 100, such as a memory manager, one or more memory management tables, etc.

[0037] The memory manager may include, among other things, circuitry or firmware, such as a plurality of components or integrated circuits associated with various memory management functions, including, among other functions, wear leveling (e.g., garbage collection or reclamation), error detection or correction, block retirement, or one or more other memory management functions. The memory manager 125 may parse or format host commands (e.g., commands received from the host device 105) into device commands (e.g., commands associated with operation of a memory array, etc.), or generate device commands for the device controller 114 or one or more other components of the storage system 110 (e.g., to perform various memory management functions).

[0038] The memory manager may include a set of management tables configured to maintain various information associated with one or more components of the storage system 110 (e.g., various information associated with a memory array or one or more memory cells coupled to the memory controller 111). For example, the management table may include information about a block age, a block erase count, an error history, or one or more error counts (e.g., a write operation error count, a read bit error count, a read operation error count, an erase error count, etc.) of one or more blocks of memory cells coupled to the memory controller 111. In some instances, if the number of detected errors of one or more of the error counts is above a threshold, the bit error may be referred to as an uncorrectable bit error. Among other things, the management table may maintain counts of correctable or uncorrectable bit errors. In one instance, the management table may include a translation table or an L2P map.

[0039] The memory manager may implement and use data structures to reduce latency of the storage system 110 in operations (such as garbage collection) involving searching for valid pages in the L2P table. To this end, the memory manager is arranged to maintain a data structure of physical blocks (e.g., a table region data structure, a tracking data structure, etc.). The data structure contains an indication of an L2P mapping table region of the L2P table. In some instances, the data structure is a bitmap (e.g., a binary array). In one example, the bitmap contains a bit for each of a plurality of mutually exclusive regions across the L2P table.

[0040] The non-volatile memory device 112 or non-volatile memory 113 (e.g., one or more 3D AND-N architecture semiconductor memory arrays) may include a plurality of memory cells arranged, for example, in a plurality of devices, planes, blocks, physical pages, super blocks, or super pages. As an example, a TLC memory device may include 18,592 bytes (B) of data per page, 1536 pages per block, 548 blocks per plane, and 4 planes per device. As another example, an MLC memory device may include 18,592 bytes (B) of data per page, 1024 pages per block, 548 blocks per plane, and 4 planes per device, but with half the required write time and twice the program / erase (P / E) cycles compared to a corresponding TLC memory device. Other examples may include other quantities or arrangements. A SuperBlock may contain a combination of multiple blocks, such as from different planes, and a Window may refer to a stripe of a SuperBlock that typically matches the portion covered by a Physical to Logical (P2L) table chunk, etc., and a SuperPage may contain a combination of multiple Pages.

[0041] The term "super" may refer to a combination or multiple of one or more things. For example, a superblock may include a combination of blocks. If a memory device includes 4 planes, a superblock may refer to the same block on each plane, or a pattern of blocks across planes (e.g., a combination of block 0 on plane 0, block 1 on plane 1, block 2 on plane 2, and block 3 on plane 3, etc.). In one example, if a storage system includes multiple memory devices, the combination or pattern of blocks may extend across the multiple memory devices. The term "stripe" may refer to a combination or pattern of one or more things. For example, a stripe of a superblock may refer to a combination or pattern of pages from each block in a superblock.

[0042] In operation, data is typically written to or read from the storage system 110 in pages and erased in blocks. However, one or more memory operations (e.g., read, write, erase, etc.) may be performed on larger or smaller groups of memory cells as needed. For example, partial updates of tag data from unloaded units may be collected during data migration or garbage collection to ensure that they are efficiently rewritten. The data transfer size of a memory device is typically referred to as a page, while the data transfer size of a host device is typically referred to as a sector. Although a page of data may contain multiple bytes of user data (e.g., a data payload containing multiple data sectors) and its corresponding metadata, the size of a page typically refers only to the number of bytes used to store user data. As an example, a data page with a page size of 4kB may contain 4kB of user data (e.g., assuming 8 sectors with a sector size of 512B) and multiple bytes (e.g., 32B, 54B, 224B, etc.) of auxiliary data or metadata corresponding to the user data, such as integrity data (e.g., code data for error detection or error correction), address data (e.g., logical address data, etc.), or other metadata associated with the user data.

[0043] Different types of memory cells or memory arrays may provide different page sizes or may require different amounts of metadata associated therewith. For example, different memory device types may have different bit error rates, which may result in different amounts of metadata required to ensure the integrity of a data page (e.g., a memory device with a higher bit error rate may require more bytes of error correction code (ECC) data than a memory device with a lower bit error rate). As an example, MLC and non-flash memory devices may have higher bit error rates than corresponding SLC and non-flash memory devices. As such, an MLC device may require more metadata bytes for erroneous data than a corresponding SLC device.

[0044] In one example, data in a chunk or data unit can be handled in an optimized manner throughout its lifetime on the storage system. For example, during data migration (e.g., garbage collection, etc.), the data is managed as a unit so that efficient read / write properties are preserved when the data is moved to its new physical location on the storage system. In some examples, the only limit on the data that can be configured for storage, labeling, etc. in a chunk, data unit, or block is the capacity of the system.

[0045] One or more of the host device 105 or the storage system 110 may include an interface circuit system, such as a host interface circuit system (I / F CKT) 107 or a storage interface circuit system (I / F CKT) 117, which is configured to enable communication between components of the host system 100. Each interface circuit system may include one or more UFS interconnect (UIC) layers. In some examples, the host I / F CKT 107 may include a controller (e.g., a UFS controller), a driver circuit (e.g., a UFS driver), etc.

[0046] The components of the host system 100 may be configured to receive or operate using one or more host voltages, including, for example, VCC, VCCQ, and optionally VCCQ2. VCC may be a first supply voltage (e.g., 2.7V-3.3V, 1.7V-1.95V, etc.). In one example, one or more of the static memory 119 or the non-volatile memory device 112 may require VCC for operation. VCCQ may be a second supply voltage lower than VCC (e.g., 1.1V-1.3V, etc.). In one example, one or more of the memory controller 111, the communication interface 115, or the memory input / output (I / O) or other low voltage blocks may optionally require VCCQ for operation. VCCQ2 may be a third supply voltage between VCC and VCCQ (e.g., 1.7V-1.95V, etc.). In one example, one or more of the memory controllers or other low voltage blocks in the memory controller 111 of the communication interface may optionally require VCCQ2. In some examples, in deep sleep mode, VCC (and optionally VCCQ2) may be removed, leaving VCCQ enabled.

[0047] Figure 2 An example table 200 is shown showing different parameters for different storage system configurations 200 and the resulting wake-up latency and power savings. Although described above as a single bit, in some instances, the control bit may include multiple control bits to indicate one or more different deep sleep configurations, wake-up configurations, recovery configurations, or reinitialization configurations, such as to select between different deep sleep modes with varying combinations of power savings and wake-up latency in response to a hardware reset signal. The multiple control bits may include multiple flags or multiple bits of one or more registers, descriptors, etc. In one example, 1 bit may represent two configurations, 2 bits may represent up to 4 configurations, 3 bits may represent up to 8 configurations, etc.

[0048] In one example, the storage system can include multiple deep sleep modes, including first to fourth deep sleep modes (e.g., DEEP SLEEP_0-DEEP SLEEP_3). Table 200 shows example deep sleep modes compared to sleep modes and power-off modes. In one example, the host device can be configured to provide a desired configuration using one or more operations, such as through a communication interface, before entering the deep sleep mode. After entering the deep sleep mode, when the communication interface is disabled, the storage system can control the power mode according to one or more conditions of the deep sleep mode.

[0049] The parameters of table 200 include different power levels, the state of the communication interface (I / F), and the desired amount of static memory (SRAM) retained. The storage system can be configured to maintain or shut down different power levels during different power modes. VCC can be removed, disabled, or placed in a "disconnected" state in all sleep modes, deep sleep modes, and power-off modes. In contrast, VCCQ and VCCQ2 can be retained in all modes except power-off mode, and the communication interface can be disabled in all modes except sleep mode. In some instances, VCCQ2 is completely omitted from the storage system, and only VCC and VCCQ are used. In other instances, other combinations of VCC, VCCQ, or VCCQ2 can be used (e.g., VCC and VCCQ2, instead of VCCQ; etc.).

[0050] The amount of static memory retained during sleep mode or deep sleep mode changes from 50% in sleep mode and the first deep sleep mode to 10% in the fourth deep sleep mode and 0% during power-off. In other instances, although such parameters show expected parameters, the storage system can be configured to monitor one or more parameters during such deep sleep mode, and if one or more of the expected expected parameters are not maintained, the mode is changed. Further, such values ​​shown above and in Table 200 are illustrative and non-restrictive, and other values ​​may be included in other instances consistent therewith. Further, other circuits or systems may be powered down according to a desired power mode (e.g., a charge pump circuit, a voltage regulator, a power supply to a specific circuit or circuit group, such as a regulator or power supply configured to power a storage system I / O circuit, etc.). In other instances, one or more other circuits or circuit groups that provide one or more functions during full or normal operation may be isolated and disconnected according to a desired power mode.

[0051] Wake-up latency and power savings are generally relative to each other. The greater the desired power savings, the longer the wake-up latency, because more static memory, data structures, etc. must be rebuilt or reloaded. In this example, 1P is the highest power savings, where 1P>1Z+K>1Z+J>1Z+I>1Z+H>1Z. In contrast, 1Y is the maximum wake-up latency (e.g., the slowest wake-up time), where 1Y>1X+D>1X+C>1X+B>1X+A>1X.

[0052] In other examples, other configurations or other numbers of configurations may be used between, in addition to, or in combination with one or more of the configurations described herein. The configurations described herein and one or more control bits in combination with a hardware reset signal may reduce system cost (compared to more complex solutions requiring further communication with or monitoring of one or more components of the host system), speed up wake-up time from deep sleep mode (reduced latency), power savings (e.g., compared to conventional power modes), or a combination thereof. Further, in some instances, the normal mode may include an idle mode.

[0053] Figure 3 An example method 300 of a host system is generally presented for transitioning from a normal mode to a deep sleep (DS) mode and then resuming normal mode after a full reset or modified reset in response to a hardware (HW) reset signal and the state of control bits in a memory system (as described above).

[0054] At 301, a host system is in normal mode, ready to perform operations, etc. At 302, while in normal mode, the host device may control control bits on a storage system, such as through a bidirectional communication interface, etc. The state of the control bits may extend the functionality of a hardware reset function of the storage system, such as enabling more than one reset mode when resuming from a deep sleep mode, etc. The host device may be configured to control the values ​​written to the control bits on the storage system when the communication interface is enabled, or when the host system is in normal mode, or not in a deep sleep mode, etc. To change the values, the host device may be configured to provide a write command to the storage system (e.g., to a memory controller), and the memory controller may be configured to write the received values ​​to a storage system register, a flag, a descriptor, or one or more other data units on one or more of a non-volatile memory device, a static memory, etc.

[0055] At 303, the host device may determine to enter a deep sleep mode. If a determination to enter a deep sleep mode is not made or received, the process may return to 302 and the host device may control a control bit on the storage system. If a determination to enter a deep sleep mode is made or received at 303, the communication interface may be disabled at 304. When disabling the communication interface between the host device and the storage system, the storage system may control the control bit at 305.

[0056] In one example, the storage system may retain values ​​written by the host device. In other examples, the storage system, such as the control circuit system, etc., may monitor one or more conditions of the storage system in the second mode, such as power loss, a drop in power supply voltage below one or more thresholds, etc. If such conditions are detected, or one or more other conditions indicating that data stored on the storage system may not be retained, the storage system (e.g., the control circuit system, etc.) may erase, write, or rewrite the value written by the host device (or not written in the case of an empty state, etc.) when the communication interface is active. In one example, the storage system may include one or more other voltage circuits, comparators, sample and hold circuits, etc., which are configured to monitor the voltage (e.g., the lowest voltage) on one or more power supplies of the storage system, such as when the communication interface is disabled or powered off.

[0057] At 306, the host device may determine to resume normal mode or exit deep sleep mode. If a determination to resume normal mode or exit deep sleep mode is not made or received, the process may return to 305 and the storage system may control the control bit. If a determination to resume normal mode or exit deep sleep mode is made or received at 306, a hardware reset signal may be provided to the storage system at 307 and the communication interface may be enabled.

[0058] At 308, the storage system may determine whether the control bit is set. If the control bit is not set by the host device or subsequently by the storage system (e.g., if the bit value is "0"), a full reset may be performed by the storage system at 309 before the process returns to the normal mode at 301. If the control bit is set by the host device or subsequently by the storage system (e.g., if the bit value is "1"), a modified reset may be performed by the storage system at 310 before the process returns to the normal mode at 301, as described above. Figure 2 One or more modified reset configurations described or otherwise described.

[0059] Figure 4An example flow chart of a 3D AND-NON architecture semiconductor memory array 400 is shown, wherein the semiconductor memory array includes blocks (e.g., block A 401A, block B 401B, etc.) and sub-blocks (e.g., sub-block A0 401A0, sub-block A1 401A1, sub-block A2 401A2, etc.) of memory cells. n 401A n , sub-block B0 401B0, sub-block B n 401B n etc.) (e.g., first-third A0 memory strings 405A0-407A0, first-third A0 memory strings 405A0-407A0, n Memory string 405A n -407A n , first-third B0 memory string 405B0-407B0, first-third B n Memory string 405B n -407B n Memory array 400 represents a portion of a larger number of similar structures that are typically found in a block, device, or other unit of a memory device.

[0060] Each string of memory cells includes a source line (SRC) 435 or a source side select gate (SGS) (eg, first-third A0 SGS 431A0-433A0, first-third A n SGS 431A n -433A n 、First-third B0 SGS 431B0-433B0、First-third B n SGS 431B n -433B n etc.) and drain side select gate (SGD) (e.g., first-third A0 SGD426A0-428A0, first-third A n SGD 426A n -428A n 、1st-3rd B0 SGD 426B0-428B0、1st-3rd B n SGD 426B n -428B n Multiple layers of memory transistors (e.g., floating gate, replacement gate, charge trapping structure, etc.) stacked from source to drain along the Z direction between the memory cells of the 3D memory array. Each string of memory cells in the 3D memory array can be arranged as a data line (e.g., bit lines (BL) BL0-BL3 420-422) along the X direction and arranged as a physical page along the Y direction.

[0061] Within a physical page, each layer represents a row of memory cells, and each string of memory cells represents a column. A sub-block may include one or more physical pages. A block may include multiple sub-blocks (or physical pages) (e.g., 128, 256, 384, etc.). Although shown herein as having two blocks, each block having two sub-blocks, each sub-block having a single physical page, each physical page having three memory cell strings, and each string having 8 memory cell layers, in other instances, the memory array 400 may include more or fewer blocks, sub-blocks, physical pages, memory cell strings, memory cells, or layers. For example, each memory cell string may include more or fewer layers (e.g., 16, 32, 64, 128, etc.), and one or more additional layers of semiconductor material located above or below the storage transistor (e.g., select gates, data lines, etc.), as desired. As an example, a 48GB TLC NAND memory device may contain 18,592 bytes (B) of data per page (16,384 + 2208 bytes), 1536 pages per block, 548 blocks per plane, and 4 or more planes per device.

[0062] Each memory cell in the memory array 400 includes a control gate (CG) coupled to (e.g., electrically connected to or otherwise operably connected to) an access line (e.g., word lines (WL) WL00-WL70 410A-417A, WL01-WL71 410B-417B, etc.) that couples the control gate (CG) in common across a particular layer or portion of a layer. A particular layer in the 3D memory array, and thus a particular memory cell in a string, may be accessed or controlled using a corresponding access line. Various select lines may be used to access select gate groups. For example, the first-third A0 SGD 426A0-428A0 may be accessed using A0 SGD line SGDA0 425A0, the A0 SGD 427A0-428A0 may be accessed using A0 SGD line SGDA0 428A0, the A0 SGD 428A0-429A0 may be accessed using A0 SGD line SGDA0 429A0, the A0 SGD 429 ... n SGD Line SGDA n 425A n Access 1st-3rd A n SGD426A n -428A n , the first to third B0 SGDs 426B0-428B0 can be accessed using B0 SGD line SGDB0 425B0, and the B n SGD Line SGDB n 425B n Access 1st-3rd B n SGD426B n -428B nThe first-third A0 SGS 431A0-433A0 and the first-third A0 SGS 431A0-433A0 can be accessed using the gate select line SGS0 430A. n SGS 431A n -433A n , and the first-third B0 SGS 431B0-433B0 and the first-third B0 SGS 431B0-433B0 can be accessed using the gate select line SGS1 430B n SGS431B n -433B n .

[0063] In one example, the memory array 400 may include multiple levels of semiconductor material (e.g., polysilicon, etc.) configured to couple the control gate (CG) of each memory cell or select gate (or CG or a portion of a select gate) of a corresponding layer of the array. A specific string of memory cells in the array may be accessed, selected, or controlled using a combination of a bit line (BL) and a select gate, etc., and a specific memory cell at one or more layers in a specific string may be accessed, selected, or controlled using one or more access lines (e.g., word lines).

[0064] In a non-AND architecture semiconductor memory array, the state of a selected memory cell can be accessed by sensing a current or voltage change associated with a specific data line containing the selected memory cell. The memory array 400 can be accessed using one or more drivers (e.g., by a control circuit, one or more processors, digital logic, etc.). In one example, the one or more drivers can activate a specific memory cell or group of memory cells by driving a specific potential of one or more data lines (e.g., bit lines BL0-BL2), access lines (e.g., word lines WL0-WL7), or select gates according to the type of operation desired to be performed on the specific memory cell or group of memory cells.

[0065] To program or write data to a memory cell, a programming voltage (Vpgm) (e.g., one or more programming pulses, etc.) may be applied to a selected word line (e.g., WL40), and thus to the control gate of each memory cell coupled to the selected word line. The programming pulse may start, for example, at or near 15V, and in some instances may increase in magnitude during each programming pulse application. When the programming voltage is applied to the selected word line, a potential, such as a ground potential (e.g., Vss), may be applied to the data line (e.g., bit line) and substrate (and thus the channel between the source and drain) of the memory cell targeted for programming, thereby causing charge transfer (e.g., direct injection or Fowler-Nordheim (FN) tunneling, etc.) from the channel to the floating gate of the target memory cell.

[0066] In contrast, a pass voltage (Vpass) may be applied to one or more word lines with memory cells not targeted for programming, or an inhibit voltage (e.g., Vcc) may be applied to data lines (e.g., bit lines) with memory cells not targeted for programming, for example, to inhibit charge transfer from the channel to the floating gates of such non-target memory cells. For example, the pass voltage may be variable depending on the proximity of the pass voltage applied to the word lines targeted for programming. The inhibit voltage may include a supply voltage (Vcc) relative to a ground potential (e.g., Vss), such as a voltage from an external power source or supply (e.g., a battery, an AC to DC converter, etc.).

[0067] As an example, if a programming voltage (e.g., 15V or higher) is applied to a particular word line, such as WL40, a pass voltage of 10V may be applied to one or more other word lines, such as WL30, WL50, etc., to inhibit programming of non-target memory cells, or to preserve values ​​stored on such memory cells that are not targeted for programming. As the distance between the applied programming voltage and the non-target memory cells increases, the pass voltage required to inhibit programming of the non-target memory cells may decrease. For example, where a programming voltage of 15V is applied to WL40, a pass voltage of 10V may be applied to WL30 and WL50, a pass voltage of 8V may be applied to WL20 and WL60, a pass voltage of 7V may be applied to WL10 and WL70, etc. In other examples, the pass voltage or number of word lines, etc. may be higher or lower, or more or less.

[0068] The sense amplifier can be coupled to one or more of the data lines (e.g., the first bit line, the second bit line, or the third bit line (BL0-BL2) 420-422) and can detect the state of each memory cell in the corresponding data by sensing the voltage or current on a specific data line.

[0069] Between applying one or more programming pulses (e.g., Vpgm), a verification operation may be performed to determine whether the selected memory cell has reached its intended programming state. If the selected memory cell has reached its intended programming state, the selected memory cell may be inhibited from further programming. If the selected memory cell has not yet reached its intended programming state, additional programming pulses may be applied. If the selected memory cell has not reached its intended programming state after a certain number (e.g., a maximum number) of programming pulses, the selected memory cell or a string, block, or page associated with such selected memory cell may be marked as defective.

[0070] In order to erase a memory cell or a group of memory cells (e.g., erasure is typically performed in blocks or sub-blocks), an erase voltage (Vers) (e.g., typically Vpgm) can be applied to the substrate (and therefore the channel between the source and drain) of the memory cell targeted for erasure (e.g., using one or more bit lines, select gates, etc.) while maintaining the word line of the target memory at a certain potential, such as ground potential (e.g., Vss), thereby causing charge transfer from the floating gate of the target memory cell to the channel (e.g., direct injection or Fowler-Nordheim (FN) tunneling, etc.).

[0071] Figure 5 An example block diagram of a memory device 500 is shown, the memory device including a memory array 502 having a plurality of memory cells 504, and one or more circuits or components for communicating with the memory array 502 or performing one or more memory operations on the memory array. Although shown with a single memory array 502, in other examples, one or more additional memory arrays, dies, or LUNs may be included herein. In some examples, in a storage system with multiple dies or LUNs, the memory device 500 may represent a block diagram of the circuits and components of each die or LUN. The memory device 500 may include a row decoder 512, a column decoder 514, a sense amplifier 520, a page buffer 522, a selector 524, an input / output (I / O) circuit 526, and a memory control unit 530.

[0072] The memory cells 504 of the memory array 502 may be arranged into blocks, such as a first block 502A and a second block 502B. Each block may include sub-blocks. For example, the first block 502A may include a first sub-block 502A0 and a second sub-block 502A1. n , and the second block 502B may include a first sub-block 502B0 and a second sub-block 502B n Each sub-block may include multiple physical pages, each page including multiple memory cells 504. Although shown herein as having two blocks, each block having two sub-blocks, and each sub-block having multiple memory cells 504, in other examples, the memory array 502 may include more or fewer blocks, sub-blocks, memory cells, etc. In other examples, the memory cells 504 may be arranged into multiple rows, columns, pages, sub-blocks, blocks, etc., and accessed using, for example, an access line 506, a first data line 510, or one or more select gates, source lines, etc.

[0073] The memory control unit 530 may control the memory operation of the memory device 500 according to one or more signals or instructions received on the control line 532 (including, for example, one or more clock signals or control signals indicating the desired operation (e.g., write, read, erase, etc.) or address signals (A0-AX) received on the one or more address lines 516). One or more devices external to the memory device 500 may control the value of the control signal on the control line 532 or the value of the address signal on the address line 516. Examples of devices external to the memory device 500 may include, but are not limited to, a host, a memory controller, a processor, or Figure 5 One or more circuits or components not shown.

[0074] The memory device 500 can use the access lines 506 and the first data lines 510 to transfer (e.g., write or erase) data to or transfer (e.g., read) data from one or more of the memory cells 504. As described above, the row decoder 512 and the column decoder 514 can receive and decode address signals (A0-AX) from the address lines 516, can determine which memory cells of the memory cells 504 are to be accessed, and can provide signals to one or more of the access lines 506 (e.g., one or more word lines of the plurality of word lines (WL0-WLm)) or the first data lines 510 (e.g., one or more bit lines of the plurality of bit lines (BL0-BLn)).

[0075] The memory device 500 may include sensing circuitry, such as sense amplifiers 520, configured to determine (e.g., read) a value of data on a memory cell 504 or to determine a value of data to be written to the memory cell using the first data line 510. For example, in a selected string of memory cells 504, one or more of the sense amplifiers 520 may read a logic level in the selected memory cell 504 in response to a read current flowing through the selected string in the memory array 502 to the data line 510.

[0076] One or more devices external to the memory device 500 may communicate with the memory device 500 using the I / O lines (DQ0-DQN) 508, the address lines 516 (A0-AX), or the control lines 532. The input / output (I / O) circuits 526 may use the I / O lines 508 to transfer values ​​of data within or outside the memory device 500, such as within or outside the page buffer 522 or the memory array 502, based on, for example, the control lines 532 and the address lines 516. The page buffer 522 may store data received from one or more devices external to the memory device 500 before programming the data into the associated portion of the memory array 502, or may store data read from the memory array 502 before transferring the data to the one or more devices external to the memory device 500.

[0077] The column decoder 514 may receive the address signals (A0-AX) and decode them into one or more column select signals (CSEL1-CSELn). The selector 524 (e.g., a selection circuit) may receive the column select signals (CSEL1-CSELn) and select data representing the value of the data to be read from or programmed to the memory cell 504 in the page buffer 522. The selected data may be transmitted between the page buffer 522 and the I / O circuit 526 using the second data line 518.

[0078] The memory control unit 530 may receive positive and negative supply signals, such as a supply voltage (Vcc) 534 and a negative supply voltage (Vss) 536 (e.g., ground potential) from an external power source or supply (e.g., an internal or external battery, an AC to DC converter, etc.). In some examples, the memory control unit 530 may include a regulator 528 for internally providing the positive and negative supply signals.

[0079] Figure 6 A block diagram of an example machine (eg, a host system) 600 is shown on which any one or more of the techniques (eg, methods) discussed herein may be performed, for example, Figure 1Those technologies described, etc. In alternative embodiments, machine 600 can be operated as a stand-alone device or can be connected (e.g., networked) to other machines. In a networked deployment, machine 600 can operate with the capabilities of a server machine, a client machine, or both in a server-client network environment. In one example, machine 600 can act as a peer-to-peer (P2P) (or other distributed) network environment. Machine 600 can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile phone, a web device, an IoT device, an automotive system, or any machine capable of (in succession or otherwise) executing instructions for the actions to be taken by the machine. Further, although only a single machine is shown, the term "machine" should also be considered to include any machine collection that executes an instruction set (or multiple sets) individually or jointly to perform any one or more methods in the method discussed herein (such as cloud computing, software as a service (SaaS), other computer cluster configurations).

[0080] As described herein, an instance may include logic, components, devices, packages, or mechanisms, or may be operated by them. A circuit system is a collection (e.g., set) of circuits implemented in a tangible entity that includes hardware (e.g., simple circuits, gates, logic, etc.). As time passes and the variability of the underlying hardware, the members of the circuit system may become flexible. The circuit system includes components that can perform specific tasks individually or in combination when operating. In one example, the hardware of the circuit system can be designed to perform specific operations (e.g., hard wiring) in an unchangeable manner. In one example, the hardware of the circuit system may include variably connected physical components (e.g., execution units, transistors, simple circuits, etc.), including computer-readable media that are physically modified (e.g., magneto-electrically movable placement of invariant massed particles, etc.) to encode instructions for specific operations. When the physical components are connected, the underlying electrical properties of the hardware components change, for example, from an insulator to a conductor, or vice versa. The instructions enable the participating hardware (e.g., execution units or loading mechanisms) to create components of the circuit system in hardware through variable connections to perform parts of specific tasks when operating. Thus, when the device is operating, the computer-readable medium may be communicatively coupled to other components of the circuit system. In one example, any of the physical components may be used in more than one component of more than one circuit system. For example, in operation, an execution unit may be used in a first circuit of a first circuit system at one point in time and may be reused by a second circuit in the first circuit system, or by a third circuit in the second circuit system at a different time.

[0081] The machine (e.g., a computer system, a host system, etc.) 600 may include a processing device 602 (e.g., a hardware processor, a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination thereof, etc.), a main memory 604 (e.g., a read-only memory (ROM), a dynamic random access memory (DRAM), such as synchronous dynamic DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 606 (e.g., a static random access memory (SRAM), etc.), and a storage system 618, some or all of which may communicate with each other via a communication interface (e.g., a bus) 630.

[0082] The processing device 602 may represent one or more general-purpose processing devices, such as a microprocessor, a central processing unit, etc. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets or a processor that implements a combination of instruction sets. The processing device 602 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. The processing device 602 may be configured to execute instructions 626 for performing the operations and steps discussed herein. The computer system 600 may further include a network interface device 608 for communicating via a network 620.

[0083] The storage system 618 may include a machine-readable storage medium (also referred to as a computer-readable medium) having stored thereon one or more sets of instructions 626 or software embodying any one or more of the methods or functions described herein. The instructions 626 may also reside, completely or at least partially, within the main memory 604 or within the processing device 602 during execution of the instructions by the computer system 600, the main memory 604 and the processing device 602 also constituting readable storage media.

[0084] The term "machine-readable storage medium" should be deemed to include a single medium or multiple media storing the one or more instruction sets, or any medium capable of storing or encoding an instruction set that is executed by a machine and causes the machine to perform any one or more of the methods of the present disclosure. Therefore, the term "machine-readable storage medium" should be deemed to include, but not limited to, solid-state memory, optical media, and magnetic media. In one example, a massed machine-readable medium includes a machine-readable medium having a plurality of particles, the plurality of particles having a constant (e.g., stationary) mass. Therefore, a massed machine-readable medium is a non-transitory propagating signal. Specific examples of massed machine-readable media can include: non-volatile memory, such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)) and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM disks and DVD-ROM disks.

[0085] The machine 600 may further include a display unit, an alphanumeric input device (e.g., a keyboard), and a user interface (UI) navigation device (e.g., a mouse). In one example, one or more of the display unit, the input device, or the UI navigation device may be a touch screen display. The machine may include a signal generating device (e.g., a speaker), or one or more sensors, such as a global positioning system (GPS) sensor, a compass, an accelerometer, or one or more other sensors. The machine 600 may include an output controller, such as a serial (e.g., universal serial bus (USB), parallel or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection to communicate with or control one or more peripheral devices (e.g., printers, card readers, etc.).

[0086] Instructions 626 (e.g., software, programs, operating systems (OS), etc.) or other data stored on storage system 618 can be accessed by main memory 604 for use by processing device 602. Main memory 604 (e.g., DRAM) is typically fast, but volatile, and is therefore a different type of storage than storage system 618 (e.g., SSD), which is suitable for long-term storage when included in the "off" state. Instructions 626 or data used by the user or machine 600 are typically loaded into main memory 604 for use by processing device 602. When main memory 604 is full, virtual space from storage system 618 can be allocated to supplement main memory 604; however, because storage system 618 devices are typically slower than main memory 604, and write speeds are typically at least twice as slow as read speeds, the use of virtual memory may significantly reduce the user experience due to storage system latency (compared to main memory 604, e.g., DRAM). Further, using storage system 618 for virtual memory may significantly reduce the useful life of storage system 618.

[0087] The instructions 626 may further be transmitted or received over the network 620 using a transmission medium via the network interface 608 using any of a number of transmission protocols (e.g., frame relay, Internet Protocol (IP), transmission control protocol (TCP), user datagram protocol (UDP), hypertext transfer protocol (HTTP), etc.). Example communication networks may include a local area network (LAN), a wide area network (WAN), a packet data network (e.g., the Internet), a mobile telephone network (e.g., a cellular network), a plain old telephone (POTS) network, and a wireless data network (e.g., a wireless network called The Institute of Electrical and Electronics Engineers (IEEE) 802.11 series of standards, known as ), IEEE 802.16 family of standards, IEEE 802.15.4 family of standards, peer-to-peer (P2P) networks, etc. In one example, the network interface device 608 may include one or more physical jacks (e.g., Ethernet, coaxial cable, or telephone jacks) or one or more antennas for connecting to the network 620. In one example, the network interface device 608 may include multiple antennas to wirelessly communicate using at least one of single-input multiple-output (SIMO) technology, multiple-input multiple-output (MIMO) technology, or multiple-input single-output (MISO) technology. The term "transmission media" should be deemed to include any intangible media that can store, encode, or carry instructions for execution by the machine 600, and includes digital or analog communication signals or other intangible media for facilitating the communication of such software.

[0088] The above detailed description includes reference to the accompanying drawings, which form a part of the detailed description. The accompanying drawings show specific embodiments in which the present invention can be practiced by way of illustration. These embodiments are also referred to as "examples" in this article. Such examples may include elements other than those elements shown or described. However, the inventors of the present invention also contemplate that only examples of those elements shown or described are provided. In addition, the inventors of the present invention also contemplate using any combination or permutation of those elements (or one or more aspects thereof) shown or described with respect to a specific example (or one or more aspects thereof), or with respect to other examples (or one or more aspects thereof) shown or described herein.

[0089] All publications, patents, and patent documents mentioned in this document are incorporated herein by reference in their entirety, as if individually incorporated by reference. In the event of an inconsistency in usage between this document and those documents so incorporated by reference, the usage in one or more of the incorporated references should be considered supplementary to that of this document; for irreconcilable inconsistencies, the usage in this document controls.

[0090] In this document, as is common in patent documents, the terms "a / an" are used to include one or more than one, independent of any other instances or uses of "at least one" or "one or more." In this document, unless otherwise indicated, the term "or" is used to refer to a non-exclusive or, such that "A or B" includes "A but not B," "B but not A," and "A and B." In the appended claims, the terms "including" and "in which" are used as the plain English equivalents of the corresponding terms "comprising" and "wherein." Moreover, in the appended claims, the terms "including" and "comprising" are open-ended, that is, systems, devices, articles, or processes that include elements other than those listed after such terms in the claims are still deemed to fall within the scope of the appended claims. In addition, in the appended claims, the terms "first," "second," and "third," etc. are used merely as labels and are not intended to impose numerical requirements on their objects.

[0091] In various instances, the components, controllers, processors, units, engines, or tables described herein may include, among other things, physical circuitry or firmware stored on a physical device. As used herein, "processor" means any type of computing circuit, such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor (DSP), or any other type of processor or processing circuit, including a group of processors or a multi-core device.

[0092] The term "horizontal" as used in this document is defined as a plane parallel to a conventional plane or surface of a substrate, such as a plane parallel to the plane beneath a wafer or die, regardless of the actual orientation of the substrate at any point in time. The term "vertical" refers to a direction perpendicular to the horizontal as defined above. Prepositions such as "on", "above", and "below" are defined relative to a conventional plane or surface located on the top or exposed surface of a substrate, regardless of the orientation of the substrate; and (in the absence of a statement to the contrary) when "on" is intended to imply direct contact of one structure relative to another structure located thereon; the terms "above" and "below" are explicitly intended to identify the relative placement of structures (or layers, features, etc.), which explicitly includes - but is not limited to - direct contact between the identified structures unless explicitly so identified. Similarly, the terms "above" and "below" are not limited to a horizontal orientation, because if a structure is the outermost part of the structure in question at a certain point in time, then the structure may be "above" a reference structure even if such structure extends vertically relative to the reference structure, rather than extending in a horizontal orientation.

[0093] The terms "wafer" and "substrate" are used herein to refer generally to any structure on which an integrated circuit is formed, and also to such structures during the various stages of integrated circuit fabrication. The following detailed description should therefore not be taken in a limiting sense, and the scope of the various embodiments is defined solely by the appended claims, along with the full scope of equivalents to which such claims are entitled.

[0094] Various embodiments according to the present disclosure and described herein include memories utilizing vertical structures of memory cells (e.g., NAND strings of memory cells). As used herein, directional adjectives will be considered relative to the surface of the substrate on which the memory cell is formed (i.e., a vertical structure will be considered to extend away from the substrate surface, a bottom end of the vertical structure will be considered to be the end closest to the substrate surface, and a top end of the vertical structure will be considered to be the end farthest from the substrate surface).

[0095] As used herein, unless otherwise specified, directional adjectives such as horizontal, vertical, normal, parallel, perpendicular, etc. may refer to relative orientations and are not intended to require strict adherence to specific geometric properties. For example, as used herein, a vertical structure need not be strictly perpendicular to the surface of a substrate, but may instead be generally perpendicular to the surface of the substrate and may form an acute angle with the surface of the substrate (e.g., between 60 and 120 degrees, etc.).

[0096] In some embodiments described herein, different doping configurations may be applied to a select gate source (SGS), a control gate (CG), and a select gate drain (SGD), in which instance each of the select gate source, the control gate, and the select gate drain may be formed of or at least include polysilicon, with the result that these layers (e.g., polysilicon, etc.) may have different etching rates when exposed to an etching solution. For example, during the formation of an integral pillar in a 3D semiconductor device, the SGS and CG may form a recess, while the SGD may remain less recessed or even not recessed. These doping configurations may therefore enable selective etching into different layers (e.g., SGS, CG, and SGD) in a 3D semiconductor device using an etching solution (e.g., tetramethylammonium hydroxide (TMCH)).

[0097] As used herein, operating a memory cell includes reading from the memory cell, writing to the memory cell, or erasing the memory cell. The operation of placing a memory cell in an intended state is referred to herein as "programming" and may include both writing to the memory cell or erasing from the memory cell (i.e., the memory cell may be programmed to an erased state).

[0098] According to one or more embodiments of the present disclosure, a memory controller (e.g., a processor, a controller, firmware, etc.) located inside or outside a memory device is capable of determining (e.g., selecting, setting, adjusting, calculating, changing, clearing, transferring, adapting, obtaining, defining, utilizing, modifying, applying, etc.) the number of wear cycles or a wear state (e.g., recording wear cycles, counting operations of the memory device as they occur, tracking operations of the memory device initiated by the memory device, evaluating characteristics of the memory device corresponding to the wear state, etc.).

[0099] According to one or more embodiments of the present disclosure, a memory access device may be configured to provide wear cycle information to a memory device through each memory operation. A memory device control circuit system (e.g., control logic) may be programmed to compensate for memory device performance changes corresponding to the wear cycle information. The memory device may receive the wear cycle information and determine one or more operating parameters (e.g., values, characteristics) in response to the wear cycle information.

[0100] It should be understood that when an element is referred to as being "on another element," "connected to another element," or "coupled to another element," the element may be directly on, connected to, or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to another element," there are no intervening elements or layers. If two elements are shown in a drawing as being connected by a line, the two elements may be coupled or directly coupled unless otherwise specified.

[0101] The method examples described herein may be at least partially machine or computer implemented. Some examples may include a computer readable medium or machine readable medium encoded with instructions, which can be operated to configure an electronic device to perform the method described in the above examples. The implementation of such methods may include code, such as microcode, assembly language code, high-level language code, etc. Such code may include computer readable instructions for performing various methods. The code may form part of a computer program product. Further, the code may be tangibly stored on one or more volatile or non-volatile tangible computer readable media, such as during execution or during other times. Examples of these tangible computer readable media may include, but are not limited to, hard disks, removable disks, removable optical disks (e.g., compact disks and digital video disks), cassettes, memory cards or memory sticks, random access memories (RAM), read-only memories (ROM), etc.

[0102] Example 1 is a host system, which includes: a host device, the host device including a host processor; a storage system, the storage system including at least one non-volatile memory device, a control circuit system coupled to the non-volatile memory device, and a storage register for storing at least one control bit; and a communication interface, the communication interface is located between the host device and the storage system; and a reset interface, the reset interface is located between the host device and the storage system, wherein the host device is configured to control a power mode of the storage system, the power mode including an operating power mode and a low power mode that disables the communication interface, and wherein in the low power mode, the control circuit system is configured to provide the storage system with one of a first reset or a second reset for transitioning from the low power mode to the operating power mode in response to a reset signal from the host device on the reset interface and the value of the at least one control bit.

[0103] In Example 2, the subject matter of Example 1 optionally includes wherein the first reset has a first wait time and a first power requirement, wherein the second reset has a second wait time and a second power requirement, and wherein the second wait time is less than the first wait time and the first power requirement is less than the second power requirement.

[0104] In Example 3, the subject matter of any one or more of Examples 1-2 optionally includes a bidirectional communication interface, wherein the host processor is configured to disable the bidirectional communication interface in the low power mode.

[0105] In Example 4, the subject matter of Example 3 optionally includes wherein the host processor is configured to enable the bidirectional communication interface in the operating power mode.

[0106] In Example 5, the subject matter of any one or more of Examples 1-4 optionally includes wherein in the operating power mode, the host processor is configured to control the value of the control bit, and wherein in the low power mode, the control circuit system is configured to control the value of the control bit.

[0107] In Example 6, the subject matter of any one or more of Examples 1-5 optionally includes wherein the operating power mode is a normal power mode and the low power mode is a deep sleep mode, wherein the first reset is a normal reset, the normal reset includes reinitializing the control circuit system, the set of non-volatile memory cells, and wherein the second reset is a modified reset, the modified reset includes limiting reinitialization of the storage system to reduce the time to transition from the low power mode to the operating power mode.

[0108] In Example 7, the subject matter of any one or more of Examples 1-6 optionally includes wherein the host device includes a UFS host, wherein the storage system includes a UFS device, wherein the control bits include multiple control bits indicating multiple different resets, and wherein in the low power mode, the control circuit system is configured to provide one of the multiple resets in response to a hardware reset signal and the values ​​of the multiple control bits.

[0109] Example 8 is a system, comprising: a storage system, the storage system comprising a group of non-volatile memory cells, a control circuit system coupled to the group of non-volatile memory cells, and a control bit, wherein in an operating power mode of the storage system, the control circuit system is configured to communicate with a host device through a bidirectional communication interface; and wherein in a low power mode of the storage system, the control circuit system is configured to provide the storage system with one of a first reset or a second reset for transitioning from the low power mode to the operating power mode in response to a hardware reset signal and the value of the control bit.

[0110] In Example 9, the subject matter of Example 8 optionally includes wherein in the operating power mode of the storage system, the control bit is controlled by the host device through the bidirectional communication interface, wherein the storage system is configured to store a value on the control bit in response to a command from the host device, wherein in the low power mode of the storage system, the bidirectional communication interface is disabled and the control bit is controlled by the storage system, and wherein the low power mode is a lower power mode than the operating power mode.

[0111] In Example 10, the subject matter of any one or more of Examples 8-9 optionally includes wherein the first reset has a first wait time and a first power requirement, wherein the second reset has a second wait time and a second power requirement, and wherein the second wait time is less than the first wait time and the first power requirement is less than the second power requirement.

[0112] In Example 11, the subject matter of any one or more of Examples 1-10 optionally includes wherein the operating power mode is a normal power mode and the low power mode is a deep sleep mode, wherein the first reset is a normal reset, the normal reset includes reinitializing the control circuit system, the set of non-volatile memory cells, and wherein the second reset is a modified reset, the modified reset includes limiting reinitialization of the storage system to reduce the time to transition from the low power mode to the operating power mode.

[0113] In Example 12, the subject matter of any one or more of Examples 1-11 optionally includes wherein the storage system includes a UFS device, wherein the control bits include multiple control bits indicating multiple different resets, and wherein in the low power mode, the control circuit system is configured to provide one of the multiple resets in response to a hardware reset signal and the values ​​of the multiple control bits.

[0114] Example 13 is a method implemented by a control circuit system of a storage system, the method comprising: receiving a hardware reset signal from a host device in a low power mode of the storage system; and providing one of a first reset or a second reset to the storage system for transitioning from the low power mode to an operating power mode in response to the received hardware reset signal and the value of a control bit on the storage system.

[0115] In Example 14, the subject matter of Example 13 optionally includes wherein the low power mode is a lower power mode than the operating power mode.

[0116] In Example 15, the subject matter of any one or more of Examples 13-14 optionally includes wherein the first reset has a first wait time and a first power requirement, wherein the second reset has a second wait time and a second power requirement, and wherein the second wait time is less than the first wait time and the first power requirement is less than the second power requirement.

[0117] In Example 16, the subject matter of any one or more of Examples 13-15 optionally includes wherein the operating power mode is a normal power mode and the low power mode is a deep sleep mode, and wherein the first reset is a normal reset, the normal reset includes reinitializing the control circuit system, the set of non-volatile memory cells, and wherein the second reset is a modified reset, the modified reset includes limiting reinitialization of the storage system to reduce the time to transition from the low power mode to the operating power mode.

[0118] In Example 17, the subject matter of any one or more of Examples 13-16 optionally includes wherein the storage system includes a UFS device, wherein the control bits include multiple control bits indicating multiple different resets, and wherein in the low power mode, the control circuit system is configured to provide one of the multiple resets in response to a hardware reset signal and the values ​​of the multiple control bits.

[0119] Example 18 is a machine-readable medium storing instructions that, when executed by a storage system, cause the storage system to perform operations including: receiving a hardware reset signal from a host device in a low power mode of the storage system; and providing one of a first reset or a second reset to the storage system for transitioning from the low power mode to an operating power mode in response to the received hardware reset signal and the value of a control bit on the storage system.

[0120] In Example 19, the subject matter of Example 18 optionally includes wherein the low power mode is a lower power mode than the operating power mode.

[0121] In Example 20, the subject matter of any one or more of Examples 18-19 optionally includes wherein the first reset has a first wait time and a first power requirement, wherein the second reset has a second wait time and a second power requirement, and wherein the second wait time is less than the first wait time and the first power requirement is less than the second power requirement.

[0122] In Example 21, the subject matter of any one or more of Examples 18-20 optionally includes wherein the operating power mode is a normal power mode and the low power mode is a deep sleep mode, and wherein the first reset is a normal reset, the normal reset includes reinitializing the control circuit system, the set of non-volatile memory cells, and wherein the second reset is a modified reset, the modified reset includes limiting reinitialization of the storage system to reduce the time to transition from the low power mode to the operating power mode.

[0123] In Example 22, the subject matter of any one or more of Examples 18-21 optionally includes wherein the storage system includes a UFS device, wherein the control bits include multiple control bits indicating multiple different resets, and wherein the operation further includes: in the low power mode, providing one of the multiple resets in response to the hardware reset signal and the values ​​of the multiple control bits.

[0124] In Example 23, the subject matter (e.g., a system or device) may optionally combine any portion of any one or more of Examples 1-21 or a combination of any portions thereof to include a "device" for performing any portion of any one or more of the functions or methods in Examples 1-21, or at least one "non-transitory machine-readable medium" containing instructions that, when executed by a machine, cause the machine to perform any portion of any one or more of the functions or methods in Examples 1-21.

[0125] The above description is intended to be illustrative and not restrictive. For example, the above examples (or one or more aspects thereof) can be used in combination with each other. Other embodiments can be used as by those of ordinary skill in the art after reviewing the above description. An abstract is provided to comply with 37C.FR§1.72(b) to allow readers to quickly determine the nature of the present technology disclosure. It should be understood that the content of the present invention should not be used to interpret or limit the scope or meaning of the claims. Moreover, in the above specific embodiments, various features can be brought together to make the present disclosure fluent. This should not be interpreted as the disclosure features that are not intended to be necessary for any claim. On the contrary, the subject matter of the present invention may be less than all the features of a specific disclosed embodiment. Therefore, the attached claims are thus incorporated into the specific embodiments, wherein each claim exists independently as a separate embodiment, and it is envisioned that such embodiments can be combined with each other in various combinations or permutations. The scope of the present invention should be determined with reference to the attached claims together with the full range of equivalents to which such claims are entitled.

Claims

1. A system comprising: A memory system comprising a group of non-volatile memory cells, a control circuit coupled to the group of non-volatile memory cells, and at least one control bit to control the memory system to transition from a low power mode to an operational power mode, The storage system is configured to selectively receive a first power source VCC. When the first power source VCC remains on the memory system, the control circuit is configured to provide a first value on the at least one control bit. wherein when the first power supply VCC is not retained on the memory system, the control circuit is configured to provide a second value at the at least one control bit, and Wherein the control circuit is configured to provide one of a first reset or a second reset in response to a hardware reset signal and a value of the at least one control bit to transition the memory system to the operating power mode.

2. The system according to claim 1, wherein the memory system is configured to selectively receive the first power supply VCC and the second power supply VCCQ, in, The control circuit is configured to provide the second value at the at least one control bit when the first power supply VCC is not reserved and the second power supply VCCQ is reserved on the memory system.

3. The system according to claim 2, wherein: When the first power supply VCC is not reserved and the second power supply VCCQ is not reserved on the memory system, the control circuit is configured to provide a third value at the at least one control bit.

4. The system according to claim 1, wherein: The control circuit is configured to provide one of the first reset or the second reset in response to the hardware reset signal from a host device on a reset interface and the value of the at least one control bit to transition the storage system from the low power mode to the operational power mode.

5. The system according to claim 1, wherein: The control circuit is configured to: providing the first reset in response to the reset signal from the host device on the reset interface and the at least one control bit having a first value to transition the memory system from the low power mode to the operational power mode; as well as The second reset is provided in response to the reset signal from the host device on the reset interface and the at least one control bit having a second value to transition the memory system from the low power mode to the operational power mode.

6. The system according to claim 1, comprising: a host device comprising a host processor; a communication interface located between the host device and the storage system; as well as a reset interface located between the host device and the storage system, The host device is configured to control a power mode of the storage system, the power mode comprising an operation mode and the low power mode, wherein the communication interface is disabled in the low power mode.

7. The system according to claim 6, in, In the operating power mode, the host processor is configured to control the value of the at least one control bit, and Wherein, in the low power mode, the control circuit is configured to control the value of the at least one control bit.

8. The system of claim 1, wherein the first reset has a first delay and a first power requirement, wherein the second reset has a second delay and a second power requirement, and The second delay is less than the first delay, and the first power requirement is lower than the second power requirement.

9. The system of claim 1 , wherein the operating power mode is a normal power mode and the low power mode is a deep sleep mode, in, The first reset is a normal reset, the normal reset includes reinitializing the control circuit and the set of non-volatile memory cells, and Wherein, relative to the first reset, the second reset is a modified reset, and the modified reset includes limiting reinitialization of the storage system to reduce the time of transitioning from the low power mode to the operating power mode.

10. A method implemented by a control circuit system of a memory system for controlling the memory system to transition from a low power mode to an operating mode using at least one control bit, the method comprising: Selectively receiving a first power supply VCC on the storage system; providing a first value at the at least one control bit when the first power supply VCC remains on the memory system; providing a second value at the at least one control bit when the first power supply VCC is not retained on the memory system; and One of a first reset or a second reset is provided in response to a hardware reset signal and the value of the at least one control bit to transition the memory system to the operational power mode.

11. The method according to claim 10, comprising: selectively receiving a second power supply VCCQ on the storage system; Wherein, providing the second value at the at least one control bit includes when the first power supply VCC is not reserved and the second power supply VCCQ is reserved on the memory system.

12. The method according to claim 11, comprising: When the first power source VCC is not reserved and the second power source VCCQ is not reserved on the memory system, a third value is provided on the at least one control bit.

13. The method of claim 10, wherein the control circuit is configured to provide one of the first reset or the second reset in response to the hardware reset signal from a host device on a reset interface and the value of the at least one control bit to transition the storage system from the low power mode to the operational power mode.

14. The method according to claim 10, comprising: providing the first reset in response to the reset signal from the host device on the reset interface and the at least one control bit having a first value to transition the memory system from the low power mode to the operational power mode; as well as The second reset is provided in response to the reset signal from the host device on the reset interface and the at least one control bit having a second value to transition the memory system from the low power mode to the operational power mode.

15. The method according to claim 10, comprising: A power mode of the storage system is controlled using a host device, the power mode including the operation mode and the low power mode, wherein in the low power mode, a communication interface between the host device and the storage system is disabled.

16. The method according to claim 15, comprising: controlling the value of the at least one control bit using the host device in the operating power mode; as well as The value of the at least one control bit is controlled using the control circuit in the low power mode.

17. The method of claim 10, wherein the first reset has a first delay and a first power requirement, wherein the second reset has a second delay and a second power requirement, and The second delay is less than the first delay, and the first power requirement is less than the second power requirement.

18. A non-transitory machine-readable medium storing instructions that, when executed by a storage system, cause the storage system to perform operations comprising: providing a first value at at least one control bit when a first power supply VCC remains on the memory system; providing a second value at the at least one control bit when the first power supply VCC is not retained on the memory system; and One of a first reset or a second reset is provided in response to a hardware reset signal and the value of the at least one control bit to transition the memory system to the operational power mode.

19. The method according to claim 18, in, Providing the second value at the at least one control bit includes, when the first power supply VCC is not retained and the second power supply VCCQ is retained on the memory system, The second power source VCCQ has a voltage lower than the first power source VCC, and Wherein, the low power mode has a lower power requirement than the operating power mode.

20. The method according to claim 18, wherein the first reset has a first delay and a first power requirement, wherein the second reset has a second delay and a second power requirement, and The second delay is less than the first delay, and the first power requirement is lower than the second power requirement.

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