Circuit structure and method for matching asymmetric reading and writing current of STT-MRAM (Spin Transfer Torque Magnetic Random Access Memory)

Abstract

The invention belongs to the technical field of memories, and discloses a circuit structure and method for matching asymmetric reading and writing current of an STT-MRAM, and the circuit structure comprises a current matching circuit which is connected in series between a transition line TL and a source line SL of the STT-MRAM, and comprises N connected transistors, N > = 2; three control signals are connected to the grid electrodes of one or more transistors, namely, a write-in '1' operation activation signal WR1, a write-in '0' operation activation signal WR0 and a read operation activation signal RD. After the N transistors are connected in parallel or connected in series and in parallel, the matching circuit meets the following conditions: when WR1 is activated, the equivalent resistance of the current matching circuit is R1; when the WR0 is activated, the equivalent resistance of the current matching circuit is R2; when the RD is activated, the current is matched with an equivalent resistor R3 of the circuit; r3 > R2 > R1. According to the invention, the area overhead of the matching structure can be reduced while the current of different operations is matched.

Description

Technical Field

[0001] The present invention belongs to the field of memory technology, and more specifically, relates to a circuit structure and method for matching asymmetric read and write currents of STT-MRAM. Background Art

[0002] Spin-transfer torque magnetoresistive random access memory (STT-MRAM) has attracted much attention due to its non-volatility, high endurance, high speed, high density and long retention time. Its theoretical high density and simple structure have also attracted a lot of attention due to its low process cost. However, the magnetic tunnel junction (MTJ), the core device of STT-MRAM, is affected by its magnetization reversal mechanism, energy barrier, and MTJ design and material properties, resulting in inconsistent currents required to write "1" and "0". In addition, in order to prevent the MTJ from flipping in the reading process, the read current is usually set lower than the minimum write current and a certain safety margin must be maintained, which makes the actual required read current much smaller than the write current.

[0003] In the prior art, the current inconsistency problem is mainly solved by introducing additional transistors into the bit cell structure design composed of a magnetic tunnel junction (MTJ) and a transistor. For example, the 2T1MTJ structure can match the different currents required to write "1" and "0", and the 3T2MTJ structure can match different write currents and read currents. However, these designs, on the one hand, cannot completely match the different currents required to write "1" and "0" at the same time, as well as the different write currents and read currents; on the other hand, more importantly, the existing designs are all designed to match the operation from the perspective of the bit cell design, that is, it is necessary to integrate additional transistors in each bit cell; since the size of the transistor is significantly larger than the size of the magnetic tunnel junction (MTJ), this integration method will lead to a significant reduction in storage density when multiple cells are integrated, which is not conducive to small-area integration. Therefore, it is very necessary to study a method that reduces the area overhead while matching the current size of different operations. Summary of the invention

[0004] In view of the above defects or improvement needs of the prior art, the present invention provides a circuit structure and method for matching the asymmetric read and write currents of STT-MRAM, which aims to match the current sizes of different operations while reducing the area overhead of the matching structure.

[0005] To achieve the above object, according to a first aspect of the present invention, a circuit structure for matching asymmetric read and write currents of an STT-MRAM is provided, comprising a current matching circuit connected in series between a transition line TL and a source line SL of the STT-MRAM, the STT-MRAM comprising a bit cell array reference layer, each bit cell in the bit cell array being connected in parallel between a bit line BL of the STT-MRAM and the transition line TL, and the STT-MRAM being powered by a single power supply;

[0006] The current matching circuit comprises: N connected transistors, N≥2; wherein a write "1" operation activation signal WR1 is connected to the gate of one or more of the transistors, a write "0" operation activation signal WR0 is connected to the gate of one or more of the transistors, and a read operation activation signal RD is connected to the gate of one or more of the transistors;

[0007] When N transistors are connected in parallel or in series, the matching circuit satisfies:

[0008] When the WR1 is activated, the equivalent resistance of the current matching circuit is R1;

[0009] When the WR0 is activated, the equivalent resistance of the current matching circuit is R2;

[0010] When the RD is activated, the equivalent resistance of the current matching circuit is R3; and R3>R2>R1.

[0011] Further, when N transistors are connected in parallel, or there is only one transistor in the branch after the series-parallel connection, the transition line TL is connected to the source or drain of the branch transistor, and the source line SL is correspondingly connected to the drain or source of the branch transistor;

[0012] When N transistors are connected in parallel, or there are multiple transistors connected in series in a branch after series-parallel connection, the transition line TL connects the source or drain of the transistor in the branch close to the transition line TL side, and the source line SL connects the source or drain of the transistor in the branch close to the source line SL side.

[0013] Further, when N=3, the current matching circuit includes: three transistors T1-T3 with different width-to-length ratios connected in parallel; wherein the width-to-length ratios of the transistors T1-T3 decrease in sequence;

[0014] The WR1 is connected to the gate of the transistor T1, the WR0 is connected to the gate of the transistor T2, and the RD is connected to the gate of the transistor T3;

[0015] The transition line TL is connected to the source or drain of the transistors T1 - T3 , and the source line SL is correspondingly connected to the drain or source of the transistors T1 - T3 .

[0016] Furthermore, when N=3, the current matching circuit includes: transistors T1-T3; wherein transistors T1 and T2 are connected in series and then connected in parallel with transistor T3;

[0017] The WR1 is connected to the gates of transistors T1-T3, the WR0 is connected to the gate of transistor T3, and the RD is connected to the gates of transistors T1 and T2;

[0018] The transition line TL is connected to the source or drain of the transistor T3, and the source line SL is correspondingly connected to the drain or source of the transistor T3; the transition line TL is also connected to the source or drain of the transistor T1 close to the transition line TL side, and the source line SL is also connected to the source or drain of the transistor T2 close to the source line SL side.

[0019] Further, when N=2, the current matching circuit includes: two parallel-connected transistors T1 and T2 with different width-to-length ratios, wherein the width-to-length ratio of the transistor T1 is greater than the width-to-length ratio of the transistor T2;

[0020] The WR1 is connected to the gates of the transistors T1 and T2 at the same time, the WR0 is connected to the gate of the transistor T1, and the RD is connected to the gate of the transistor T2;

[0021] The transition line TL is connected to the source or drain of the transistors T1 and T2 , and the source line SL is connected to the drain or source of the transistors T1 and T2 .

[0022] Furthermore, the bit unit is a bit unit of a 1T1R structure, and the free layer of the magnetic tunnel junction of each of the bit units is connected to the bit line BL, and the transistor end of each of the bit units is connected to the transition line TL.

[0023] Furthermore, the transistor is NMOS or PMOS.

[0024] According to a second aspect of the present invention, there is provided a method for performing asymmetric read and write current matching of STT-MRAM using the circuit structure described in any one of the first aspects, comprising:

[0025] When "1" is written to a specific bit unit, the WR1 is activated;

[0026] When writing "0" to a specific bit unit, the WR0 is activated;

[0027] When data stored in a specific cell is read, the RD is activated.

[0028] According to a third aspect of the present invention, there is provided an STT-MRAM, comprising a plurality of bit cell arrays and corresponding current matching circuits;

[0029] Wherein, the current matching circuit is the current matching circuit in the circuit structure described in any one of the first aspects.

[0030] Furthermore, each bit unit in the bit unit array is a bit unit of a 1T1R structure.

[0031] In general, the above technical solutions conceived by the present invention can achieve the following beneficial effects:

[0032] (1) The current matching circuit of the present invention adds a transition line TL between the bit line BL and the source line SL of the STT-MRAM, and sets a matching circuit structure between the transition line TL and the source line SL for matching the different current sizes required for different operations of the STT-MRAM. Since the current required for the write "1" operation, the write "0" operation, and the read operation of the STT-MRAM decreases in sequence, when the STT-MRAM is powered by a single power supply, the voltage difference between the bit line BL and the source line SL is the same. Therefore, when the equivalent resistance of the matching circuit is small, the current passing through the MTJ in the bit unit is large. Based on this, when the write "1" operation activation signal WR1, the write "0" operation activation signal WR0, and the read operation activation signal RD connected to the gate of one or more transistors are activated accordingly, the equivalent resistance of the corresponding matching circuit is set to satisfy R3>R2>R1 (R1, R2 and R3 are the equivalent resistances of the current matching circuit when activating WR1, WR0 and RD respectively), so that the current passing through the MTJ in the bit unit can be reduced in turn, so as to match the current required for the write "1" operation, write "0" operation, and read operation of the STT-MRAM. At the same time, the bit unit array shares a matching circuit, and there is no need to introduce additional transistors on each bit unit, which saves space and greatly reduces area overhead. Especially when large-scale integration is performed, the advantages of the current matching circuit structure of the present invention are more prominent.

[0033] (2) Preferably, when N=3, the structure of the corresponding current matching circuit uses only three transistors to achieve asymmetric current matching for the STT-MRAM composed of a bit cell array, which greatly reduces the area overhead required for matching asymmetric current.

[0034] (3) Preferably, when N=2, the structure of the corresponding current matching circuit uses a minimum number of transistors to achieve asymmetric current matching for the STT-MRAM composed of a bit cell array, thereby minimizing the area overhead required for matching the asymmetric current. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 Schematic diagram of a current matching circuit structure when N=3 in an embodiment of the present invention.

[0036] Figure 2 FIG. 4 is a schematic diagram of another current matching circuit structure when N=3 in an embodiment of the present invention.

[0037] Figure 3 Schematic diagram of a current matching circuit structure when N=2 in an embodiment of the present invention. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0039] Example 1

[0040] like Figure 1 As shown, in an embodiment of the present invention, a circuit structure for matching the asymmetric read and write currents of STT-MRAM is provided, wherein the STT-MRAM includes a bit cell array, and in an embodiment of the present invention, the bit cell array is an m*n array composed of bit cells of a 1T1R structure. The 1T1R structure is a bit cell composed of a transistor and a magnetic tunnel junction (MTJ). Each bit cell of the 1T1R structure is connected in parallel between the bit line (BL) and the transition line (TL) of the STT-MRAM to store binary data. Specifically, the reference layer of each MTJ of the 1T1R structure is connected to the bit line BL, and the transistor end of each 1T1R structure is connected to the transition line TL; and the STT-MRAM is powered by a single power supply.

[0041] In the embodiment of the present invention, the current matching circuit is connected in series between the transition line TL and the source line (SL) of the STT-MRAM to match the different current sizes required for different operations (writing and reading operations on the STT-MRAM). The source line and the bit line of the STT-MRAM are used to provide a high level or a reference ground during the writing and reading operations to provide a current through the magnetic tunnel junction (MTJ). The transition line is used to transitionally connect the bit cell array and the current matching circuit.

[0042] The current matching circuit structure mainly includes: N connected transistors, N≥2; wherein, the gate of one or more transistors is connected to a write "1" operation activation signal WR1, the gate of one or more transistors is connected to a write "0" operation activation signal WR0, and the gate of one or more transistors is connected to a read operation activation signal RD.

[0043] When N transistors are connected in parallel, or in series and parallel, the matching circuit satisfies:

[0044] When WR1 is activated, the equivalent resistance of the current matching circuit is R1;

[0045] When WR0 is activated, the equivalent resistance of the current matching circuit is R2;

[0046] When RD is activated, the equivalent resistance R3 of the current matching circuit is satisfied; and R3>R2>R1.

[0047] In the embodiment of the present invention, the transistor of the current matching circuit can be NMOS or PMOS. When it is NMOS, the corresponding signal is activated when the transistor inputs a high level; when it is PMOS, the corresponding signal is activated when the transistor inputs a low level.

[0048] It should be noted that, since the parameters of the MTJ selected by STT-MRAM vary greatly, in practical applications, accurate equivalent resistances R1-R3 can be designed according to the parameters of the MTJ to match the different current sizes required for different operations.

[0049] Specifically, when N transistors are connected in parallel, or there is only one transistor in the branch after N transistors are connected in series and parallel, the transition line TL connects the source or drain of the branch transistor, and the source line SL connects the drain or source of the branch transistor accordingly, that is, when the transition line TL connects the source of the branch transistor, the source line SL connects the drain of the branch transistor accordingly, and when the transition line TL connects the drain of the branch transistor, the source line SL connects the source of the branch transistor accordingly. When N transistors are connected in parallel, or there are multiple transistors connected in series in the branch after N transistors are connected in series and parallel, the transition line TL connects the source or drain of the transistor of the branch close to the transition line TL side, and the source line SL connects the source or drain of the transistor of the branch close to the source line SL side.

[0050] As a preferred implementation, when N=3, Figure 1The current matching circuit structure shown in the dotted box includes three transistors T1-T3 with different width-to-length ratios connected in parallel; wherein the width-to-length ratios of transistors T1-T3 decrease in sequence; the write "1" operation activation signal WR1 is connected to the gate of transistor T1, the write "0" operation activation signal WR0 is connected to the gate of transistor T2, and the read operation activation signal RD is connected to the gate of transistor T3; the three transistors are connected in parallel to form three branches, each branch has only one transistor, the transition line TL is connected to the source or drain of T1-T3, and the source line SL is connected to the drain or source of T1-T3 accordingly. Since the width-to-length ratios of T1-T3 decrease in sequence, when transistors T1-T3 are connected in parallel, when WR1, WR0, and RD are correspondingly activated, the equivalent resistance of the current matching circuit satisfies R3>R2>R1.

[0051] As a preferred implementation, when N=3, Figure 2 As shown, the current matching circuit is composed of three transistors T1-T3 connected in series and in parallel. Specifically, after transistors T1 and T2 are connected in series, they are connected in parallel with transistor T3; the write "1" operation activation signal WR1 is connected to the gates of T1-T3 at the same time, the write "0" operation activation signal WR0 is connected to the gate of transistor T3, and the read operation activation signal RD is connected to the gates of transistors T1 and T2 at the same time; for the branch containing only transistor T3, the transition line TL is connected to the source or drain of transistor T3, and the source line SL is connected to the drain or source of transistor T3 correspondingly; for the branch containing transistors T1 and T2 in series at the same time, the transition line TL is connected to the source or drain of transistor T1 close to the transition line TL side, and the source line SL is connected to the source or drain of transistor T2 close to the source line SL side. Since the equivalent resistance of the transistors after being connected in parallel is less than the resistance of the transistors in parallel, through the above connection method, when WR1, WR0, and RD are activated correspondingly, the equivalent resistance of the current matching circuit satisfies R3>R2>R1.

[0052] In the above two specific implementations, only three transistors are used to achieve asymmetric current matching for the STT-MRAM composed of m*n bit cells, which greatly reduces the area overhead required for matching the asymmetric current.

[0053] As a preferred implementation, when N=2, Figure 3As shown, the current matching circuit includes two parallel transistors T1 and T2 with different width-to-length ratios, wherein the width-to-length ratio of transistor T1 is greater than that of transistor T2; the write "1" operation activation signal WR1 is connected to the gates of transistors T1 and T2 at the same time, the write "0" operation activation signal WR0 is connected to the gate of transistor T1, and the read operation activation signal RD is connected to the gate of transistor T2; the two transistors are connected in parallel to form two branches, each branch has only one transistor, the transition line TL connects the source or drain of transistors T1 and T2, and the source line SL connects the drain or source of transistors T1 and T2 accordingly. Through the above connection method, when WR1, WR0, and RD are correspondingly activated, the equivalent resistance of the current matching circuit satisfies R3>R2>R1, and the minimum number of transistors is used to realize the asymmetric current matching for the STT-MRAM composed of m*n bit units, which minimizes the area overhead required for matching the asymmetric current.

[0054] The current matching circuit of the present invention adds a transition line TL between the bit line BL and the source line SL of the STT-MRAM, and sets a matching circuit structure for matching different current sizes required for different operations of the STT-MRAM between the transition line TL and the source line SL. Since the current required for the write "1" operation, the write "0" operation, and the read operation of the STT-MRAM decreases in sequence, when the STT-MRAM is powered by a single power supply, the voltage difference between the bit line BL and the source line SL is the same. Therefore, when the equivalent resistance of the matching circuit is small, the current passing through the MTJ in the bit unit is large. Based on this, when the write "1" operation activation signal WR1, the write "0" operation activation signal WR0, and the read operation activation signal RD connected to the gate of one or more transistors are correspondingly activated, the equivalent resistance of the corresponding matching circuit is set to satisfy R3>R2>R1, so that the current passing through the MTJ in the bit unit can be correspondingly reduced in sequence, so as to match the current required for the write "1" operation, the write "0" operation, and the read operation of the STT-MRAM. At the same time, since m*n bit units share one matching circuit, there is no need to introduce additional transistors on each bit unit, which saves space and greatly reduces area overhead. Especially when large-scale integration is performed, the matching circuit structure of the present invention has more prominent advantages.

[0055] Example 2

[0056] The embodiment of the present invention provides a method for performing asymmetric read and write current matching of STT-MRAM using the current matching circuit in the above embodiment 1, comprising:

[0057] When writing "1" to a specific bit cell, the word line corresponding to the specific bit cell in the bit cell array is activated, such as Figure 1The word line WLx is activated, that is, the bit unit corresponding to the word line WLx is activated. At this time, the write "1" operation activation signal WR1 is activated, and all transistors whose gates are connected to WR1 in the current matching circuit are activated. The current matching circuit generates a current that is consistent with the current required for the corresponding write "1" operation, which allows a larger write current to pass through a specific bit unit.

[0058] When writing "0" to a specific bit cell, the word line corresponding to the specific bit cell in the bit cell array is activated. At this time, the write "0" operation activation signal WR0 is activated, and all transistors whose gates are connected to WR0 in the current matching circuit are activated. The current matching circuit generates a current that is consistent with the current required for the corresponding write "0" operation, which allows a smaller write current to pass through the specific bit cell.

[0059] When reading data stored in a specific cell, the word line corresponding to the specific bit cell in the bit cell array is activated. At this time, the read operation activation signal RD is activated, and all transistors whose gates are connected to RD in the current matching circuit are activated. The current matching circuit generates a current that is consistent with the current required for the corresponding read operation, so that the minimum read current can pass through the specific bit cell.

[0060] Example 3

[0061] An embodiment of the present invention provides an STT-MRAM, comprising a plurality of bit cell arrays and the current matching circuit in the above-mentioned embodiment 1, wherein one current matching circuit corresponds to one bit cell array to match different current sizes required for writing and reading operations.

[0062] For the related technical solutions, please refer to the corresponding description in Example 1, which will not be repeated here.

[0063] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A circuit structure for matching asymmetric read and write currents of STT-MRAM, characterized in that: A current matching circuit is connected in series between a transition line TL and a source line SL of an STT-MRAM, wherein the STT-MRAM includes a bit cell array, each bit cell in the bit cell array is connected in parallel between a bit line BL of the STT-MRAM and the transition line TL, and the STT-MRAM is powered by a single power supply; The current matching circuit comprises: N connected transistors, N≥2; wherein a write "1" operation activation signal WR1 is connected to the gate of one or more of the transistors, a write "0" operation activation signal WR0 is connected to the gate of one or more of the transistors, and a read operation activation signal RD is connected to the gate of one or more of the transistors; When N transistors are connected in parallel or in series, the matching circuit satisfies: When the WR1 is activated, the equivalent resistance of the current matching circuit is R1; When the WR0 is activated, the equivalent resistance of the current matching circuit is R2; When the RD is activated, the equivalent resistance of the current matching circuit is R3; and R3>R2>R1.

2. The circuit structure according to claim 1, characterized in that: When N transistors are connected in parallel, or there is only one transistor in the branch after the series-parallel connection, the transition line TL is connected to the source or drain of the branch transistor, and the source line SL is correspondingly connected to the drain or source of the branch transistor; When N transistors are connected in parallel, or there are multiple transistors connected in series in a branch after series-parallel connection, the transition line TL connects the source or drain of the transistor in the branch close to the transition line TL side, and the source line SL connects the source or drain of the transistor in the branch close to the source line SL side.

3. The circuit structure according to claim 1 or 2, characterized in that: When N=3, the current matching circuit includes: three transistors T1-T3 with different width-to-length ratios connected in parallel; wherein the width-to-length ratios of the transistors T1-T3 decrease in sequence; The WR1 is connected to the gate of the transistor T1, the WR0 is connected to the gate of the transistor T2, and the RD is connected to the gate of the transistor T3; The transition line TL is connected to the source or drain of the transistors T1 - T3 , and the source line SL is correspondingly connected to the drain or source of the transistors T1 - T3 .

4. The circuit structure according to claim 1 or 2, characterized in that: When N=3, the current matching circuit includes: transistors T1-T3; wherein transistors T1 and T2 are connected in series and then connected in parallel with transistor T3; The WR1 is connected to the gates of transistors T1-T3, the WR0 is connected to the gate of transistor T3, and the RD is connected to the gates of transistors T1 and T2; The transition line TL is connected to the source or drain of the transistor T3, and the source line SL is correspondingly connected to the drain or source of the transistor T3; the transition line TL is also connected to the source or drain of the transistor T1 close to the transition line TL side, and the source line SL is also connected to the source or drain of the transistor T2 close to the source line SL side.

5. The circuit structure according to claim 1 or 2, characterized in that: When N=2, the current matching circuit includes: two parallel-connected transistors T1 and T2 with different width-to-length ratios, wherein the width-to-length ratio of the transistor T1 is greater than the width-to-length ratio of the transistor T2; The WR1 is connected to the gates of the transistors T1 and T2 at the same time, the WR0 is connected to the gate of the transistor T1, and the RD is connected to the gate of the transistor T2; The transition line TL is connected to the source or drain of the transistors T1 and T2 , and the source line SL is connected to the drain or source of the transistors T1 and T2 .

6. The circuit structure according to claim 1, characterized in that: The bit cells are bit cells of a 1T1R structure, and the free layer of the magnetic tunnel junction of each of the bit cells is connected to the bit line BL, and the transistor end of each of the bit cells is connected to the transition line TL.

7. The circuit structure according to claim 1, characterized in that: The transistor is NMOS or PMOS.

8. A method for performing STT-MRAM asymmetric read and write current matching using the circuit structure of any one of claims 1 to 7, characterized in that: include: When "1" is written to a specific bit unit, the WR1 is activated; When "0" is written to a specific bit unit, the WR0 is activated; When data stored in a specific cell is read, the RD is activated.

9. A STT-MRAM, characterized in that: comprising a plurality of bit cell arrays and corresponding current matching circuits; Wherein, the current matching circuit is the current matching circuit in the circuit structure described in any one of claims 1-7.

10. The STT-MRAM according to claim 9, characterized in that: Each bit unit in the bit unit array is a bit unit of a 1T1R structure.

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