A 130nm SOI process SRAM storage cell circuit and layout structure resistant to multi-node flipping

Abstract

The invention discloses a 130nm SOI process SRAM storage unit circuit and a layout structure thereof which are resistant to multi-node flipping. The storage unit circuit structure at least comprises: a pull-up circuit structure and a pull-down circuit structure are connected to form two inversely linked storage structures for keeping multiple nodes stable; a stacked transistor circuit structure, wherein a storage node is formed by stacking PMOS transistors, so that the unit circuit can resist multi-node flipping, and the logic state on the storage node is restored to normal in the case of interference; an access tube is used to connect the word line and the bit line of the unit circuit; a tail transistor is used to reduce static power consumption and improve the write-read rate; two nodes generated by stacking P-type transistors can effectively cope with multi-node flipping, and the logic state on the storage bit is restored to normal in the case of interference, thereby improving the anti-flipping capability of the SRAM memory in an irradiated environment.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuit design, and in particular relates to a 130nm SOI process SRAM storage unit circuit resistant to multi-node flipping and a layout structure thereof. Background Art

[0002] Under harsh conditions such as nuclear radiation and aerospace radiation, the radiation situation is very complicated. There will be a large number of protons, neutrons, heavy ions, etc. filling the space environment, which will cause hidden dangers to electronic systems, especially integrated circuits; under complex radiation conditions, radiation effects will occur, among which single particle effects will cause serious reliability problems. Single particle effects refer to the unpredictable interference or failure of semiconductor devices caused by the interaction between high-energy charged particles in space and electrons in semiconductor devices. Single particle flip is a type of single particle effect, which means that in a radiation environment, when high-energy particles (such as neutrons, protons or heavy ions) pass through semiconductor materials, the charge generated may temporarily change the state of the storage unit. Specifically, the bit stored in the register, memory or other digital circuit may flip from "0" to "1" or from "1" to "0". This usually does not cause permanent damage, but it will cause data errors or malfunctions of the control logic.

[0003] The transient dose rate effect is one of the important ways in which nuclear radiation environment induces anomalies in electronic systems, mainly causing device anomalies through radiation-induced transient photocurrent in semiconductor devices.

[0004] Static random access memory (SRAM) is a common memory. SRAM has the advantages of fast speed, low power consumption and stable performance, and is widely used in existing integrated circuits. However, since SRAM occupies a significant area, it is also greatly affected by single-particle upsets.

[0005] Therefore, it is necessary to reduce the impact of single-particle upsets on SRAM and solve the problem of single-node or even multi-node upsets caused by single particles, so as to reduce soft errors and reduce the impact of electronic systems in high radiation environments. Summary of the invention

[0006] In view of the problems existing in the prior art, the present invention provides a 130nm SOI process SRAM memory cell circuit structure resistant to multi-node flipping, wherein the memory cell circuit structure at least comprises: a pull-up circuit structure, a pull-down circuit structure, a stacked transistor circuit structure, an access transistor and a tail transistor;

[0007] The pull-up circuit structure is connected with the pull-down circuit structure to form two inversely interlocked structures, which are used to keep multiple nodes stable;

[0008] A stacked transistor circuit structure, wherein a storage node is formed by stacking PMOS transistors, so that the unit circuit can resist multi-node flipping and restore the logic state on the storage node to normal in the event of interference, wherein the stacked transistor circuit structure comprises a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, and an eighth PMOS transistor; wherein the stacked transistor circuit structure comprises a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, and an eighth PMOS transistor; the seventh PMOS transistor and the eighth PMOS transistor respectively form a stacked structure of a first storage node and a second storage node; the fifth PMOS transistor and the sixth PMOS transistor respectively form a stacked structure of a third storage node and a fourth storage node;

[0009] The access tube is used to connect the word line and the bit line of the unit circuit, and the access tube includes a first NMOS transistor and a second NMOS transistor;

[0010] The tail transistor adopts a seventh NMOS transistor, which is used to reduce static power consumption and improve write and read speed.

[0011] As a further illustration of the present invention, the pull-up circuit structure includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor; the pull-down circuit structure includes a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor;

[0012] The first PMOS transistor and the second PMOS transistor are pull-up structures of the first storage node and the second storage node, respectively, and the fifth NMOS transistor and the sixth NMOS transistor are pull-down structures of the first storage node and the second storage node, respectively; the third PMOS transistor and the fourth PMOS transistor are pull-up structures of the third storage node and the fourth storage node, respectively, and the third NMOS transistor and the fourth NMOS transistor are pull-down structures of the third storage node and the fourth storage node, respectively.

[0013] As a further explanation of the present invention, the sources of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, and the fourth PMOS transistor are all connected to the power supply VDD, the drain of the first PMOS transistor is connected to the gate of the second PMOS transistor, the gate of the fifth NMOS transistor, and the source of the seventh PMOS transistor to form a first storage node, the drain of the second PMOS transistor is connected to the gate of the first PMOS transistor, the gate of the sixth NMOS transistor, and the source of the eighth PMOS transistor to form a second storage node, the drain of the fourth PMOS transistor is connected to the source of the sixth PMOS transistor, the drain of the third PMOS transistor is connected to the source of the fifth PMOS transistor, the drain of the sixth PMOS transistor is connected to the gate of the third PMOS transistor, the source of the second NMOS transistor, the gate of the third NMOS transistor, the drain of the fourth NMOS transistor, and the gate of the sixth NMOS transistor to form a third storage node, and the drain of the fifth PMOS transistor is connected to the gate of the third PMOS transistor, the source of the second NMOS transistor, the gate of the third NMOS transistor, the drain of the fourth NMOS transistor, and the gate of the sixth NMOS transistor to form a third storage node. The gate of the fourth PMOS transistor, the source of the first NMOS transistor, the gate of the fourth NMOS transistor, the drain of the third NMOS transistor and the gate of the fifth NMOS transistor are connected to form a fourth storage node, the drain of the eighth PMOS transistor is connected to the drain of the sixth NMOS transistor, the drain of the seventh PMOS transistor is connected to the drain of the fifth NMOS transistor, the source of the fourth NMOS transistor and the source of the third NMOS transistor are both connected to the drain of the seventh NMOS transistor, the source of the sixth NMOS transistor, the source of the fifth NMOS transistor and the source of the seventh NMOS transistor are all connected to GND; the gate of the second NMOS transistor and the gate of the first NMOS transistor are both connected to the word line WL, the drain of the second NMOS transistor is connected to the bit line BL, the drain of the first NMOS transistor is connected to the bit line BLB, the gate of the eighth PMOS transistor is connected to the word bit line WBLB, the gate of the seventh PMOS transistor is connected to the word bit line WBL, and the gate of the seventh NMOS transistor is connected to the write word line WWL.

[0014] The present invention also provides a layout structure of a 130nmSOI process SRAM storage unit circuit structure that is resistant to multi-node flipping. The layout structure of the SRAM storage unit adopts a symmetrical structure, wherein the center is an NMOS transistor source region and the two ends are PMOS transistor source regions; a word bit line WBLB is located at the upper left corner of the SRAM storage unit, a word bit line WBL is located at the upper right corner of the SRAM storage unit, a bit line BLB is located at the lower left corner of the SRAM storage unit, a bit line BL is located at the lower right corner of the SRAM storage unit, a write word line WWL is located above the SRAM storage unit, a word line WL is located below the SRAM storage unit, a power supply VDD is located at the left and right ends of the SRAM storage unit, and a GND is located at the center of the SRAM storage unit.

[0015] As a further explanation of the present invention, the source widths of the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, the sixth NMOS transistor and the seventh NMOS transistor are all 2.4 μm, the source widths of the first NMOS transistor and the second NMOS transistor are all 0.8 μm, and the source widths of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, the sixth PMOS transistor, the seventh PMOS transistor and the eighth PMOS transistor are all 0.4 μm.

[0016] As a further explanation of the present invention, in the layout structure of the SRAM storage unit, the SOI device adopts an H-gate type device, and the two ends of the H gate are of unequal length. The H gate has two body regions, one of which is connected to the long end of the H gate, and the short end of the H gate is connected to the other body region; the body region of the PMOS transistor is connected to VDD through the short end of the H gate, and the body region of the NMOS transistor is connected to GND through the short end of the H gate.

[0017] As a further explanation of the present invention, in the layout structure of the SRAM storage unit, the first storage node is isolated from the second storage node, the third storage node is isolated from the fourth storage node, the first storage node is connected to the third storage node, and the second storage node is connected to the fourth storage node.

[0018] Compared with the prior art, the present invention has the following beneficial technical effects:

[0019] 1. The 130nm SOI process SRAM memory cell circuit structure with resistance to multi-node flipping provided by the present invention adopts a stack of P-type transistors to form a storage node so that the SRAM memory cell circuit has the performance of resisting single particle flipping, i.e., multi-node flipping; in the event of interference, the logical state on the storage bit is restored to normal, thereby improving the anti-flipping capability of the SRAM memory in an irradiated environment.

[0020] 2. The layout structure of the 130nm SOI process SRAM storage unit circuit resistant to multi-node flipping provided by the present invention adopts "H" gate devices on the basis of SOI process to reduce the influence of single particle effect and transient dose rate effect on the circuit. At the same time, the layout structure adopts the active area sharing method to reduce the layout area. When laying out the layout, the sensitive nodes, the first storage node and the second storage node, are isolated, the third storage node and the fourth storage node are isolated, and the first storage node and the third storage node are connected, and the second storage node and the fourth storage node are connected, so as to enhance the ability to resist single particle effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 The present invention provides a schematic diagram of a circuit structure of a 130nm SOI process SRAM storage unit that is resistant to multi-node flipping.

[0022] Figure 2 The present invention provides a schematic diagram of the layout structure of a 130nm SOI process SRAM storage unit circuit structure that is resistant to multi-node flipping.

[0023] Figure 3 It is a double exponential current source simulation diagram of a single-node second storage node Q2 in a 130nm SOI process SRAM storage unit resistant to multi-node flipping provided by the present invention, wherein T1 and T2 represent error simulations at two different times respectively.

[0024] Figure 4 It is a double exponential current source simulation diagram of a single-node first storage node Q1 in a 130nm SOI process SRAM storage unit resistant to multi-node flipping provided by the present invention, wherein T1 and T2 represent error simulations at two different times respectively.

[0025] Figure 5 It is a double exponential current source simulation diagram of a single-node third storage node Q3 in a 130nm SOI process SRAM storage unit resistant to multi-node flipping provided by the present invention, wherein T1 and T2 represent error simulations at two different times respectively.

[0026] Figure 6It is a double exponential current source simulation diagram of a single-node fourth storage node Q4 in a 130nm SOI process SRAM storage unit resistant to multi-node flipping provided by the present invention, wherein T1 and T2 represent error simulations at two different times respectively.

[0027] Figure 7 This is a double exponential current source simulation diagram of the second storage node Q2 and the fourth storage node Q4 of the double-node same-potential well in a 130nm SOI process SRAM storage unit that is resistant to multi-node flipping provided by the present invention, wherein T1 and T2 respectively represent error simulations at two different times on the second storage node Q2, and T3 and T4 respectively represent error simulations at two different times on the fourth storage node Q4.

[0028] Figure 8 It is a double exponential current source simulation diagram of a node between a second storage node Q2 with double nodes and different potential wells and a seventh PMOS transistor P7 and a fifth NMOS transistor N5 in a 130nm SOI process SRAM storage unit resistant to multi-node flipping provided by the present invention, wherein T1 and T2 respectively represent error simulations at two different times on the second storage node Q2, and T3 and T4 respectively represent error simulations at two different times on the node between the seventh PMOS transistor P7 and the fifth NMOS transistor N5. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments.

[0030] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0031] In the description of the present invention, it should be noted that the terms, "upper", "lower", "left", "right", "inner", "outer", etc. indicate the orientation or position relationship based on the orientation or position relationship shown in the drawings, or the orientation or position relationship in which the product of the invention is usually placed when in use, which is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0032] In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0033] In the description of the present invention, it is also necessary to explain that the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interfaces, devices or units, which may be electrical, mechanical or other forms.

[0034] It should be noted that, in the absence of conflict, the features in the embodiments of the present invention may be combined with each other.

[0035] like Figure 1 As shown, the present invention provides a 130nm SOI process SRAM storage unit circuit structure that is resistant to multi-node flipping, which uses P-type transistor stacking to form storage nodes so that the SRAM storage unit circuit has the performance of resisting single particle flipping, i.e., multi-node flipping;

[0036] Specifically, the sources of the first PMOS transistor P1, the second PMOS transistor P2, the third PMOS transistor P3, and the fourth PMOS transistor P4 are all connected to the power supply VDD, the drain of the first PMOS transistor P1 is connected to the gate of the second PMOS transistor P2, the gate of the fifth NMOS transistor P5, and the source of the seventh PMOS transistor P7 to form a first storage node Q1, the drain of the second PMOS transistor P2 is connected to the gate of the first PMOS transistor P1, the gate of the sixth NMOS transistor P6, and the source of the eighth PMOS transistor P8 to form a second storage node Q2, the drain of the fourth PMOS transistor P4 is connected to the source of the sixth PMOS transistor P6, the drain of the third PMOS transistor P3 is connected to the source of the fifth PMOS transistor P5, the drain of the sixth PMOS transistor P6 is connected to the gate of the third PMOS transistor P3, the source of the second NMOS transistor N2, the gate of the third NMOS transistor N3, the drain of the fourth NMOS transistor N4, and the gate of the sixth NMOS transistor N6 to form a third storage node Q3, and the drain of the fifth PMOS transistor N5 is connected to the gate of the fourth PMOS transistor P1. The gate of the PMOS transistor P4, the source of the first NMOS transistor N1, the gate of the fourth NMOS transistor N4, the drain of the third NMOS transistor N3 and the gate of the fifth NMOS transistor N5 constitute a fourth storage node Q4, the drain of the eighth PMOS transistor P8 is connected to the drain of the sixth NMOS transistor N6, the drain of the seventh PMOS transistor P7 is connected to the drain of the fifth NMOS transistor N5, the source of the fourth NMOS transistor N4 and the source of the third NMOS transistor N3 are both connected to the drain of the seventh NMOS transistor N7, and the sixth NMOS The source of the OS transistor N6, the source of the fifth NMOS transistor N5 and the source of the seventh NMOS transistor N7 are all connected to GND; the gate of the second NMOS transistor N2 and the gate of the first NMOS transistor N1 are all connected to the word line WL, the drain of the second NMOS transistor N2 is connected to the bit line BL, the drain of the first NMOS transistor N1 is connected to the bit line BLB, the gate of the eighth PMOS transistor P8 is connected to the word bit line WBLB, the gate of the seventh PMOS transistor P7 is connected to the word bit line WBL, and the gate of the seventh NMOS transistor P7 is connected to the write word line WWL.

[0037] In one embodiment of the present invention, the pull-up circuit structure and the pull-down circuit structure are connected to form two inversely linked storage structures, the storage nodes are isolated from each other and controlled by each other, and the voltage division can effectively avoid multi-node flipping, so that the nodes remain stable, wherein the first PMOS transistor P1 and the second PMOS transistor P2 are respectively the pull-up structures of the first storage node Q1 and the second storage node Q2 of the SRAM storage unit, the fifth NMOS transistor N5 and the sixth NMOS transistor N6 are respectively the pull-down structures of the first storage node Q1 and the second storage node Q2 of the SRAM storage unit, and the seventh PMOS transistor P7 and the eighth PMOS transistor P8 are respectively the pull-down structures of the first storage node Q1 and the second storage node Q2 of the SRAM storage unit. MOS transistor P8 is a voltage-dividing structure of the first storage node Q1 and the second storage node Q2 of the SRAM storage cell; the third PMOS transistor P3 and the fourth PMOS transistor P4 are pull-up structures of the third storage node Q3 and the fourth storage node Q4 of the SRAM storage cell, respectively; the third NMOS transistor N3 and the fourth NMOS transistor N4 are pull-down structures of the third storage node Q3 and the fourth storage node Q4 of the SRAM storage cell, respectively; the fifth NMOS transistor P5 and the sixth PMOS transistor P6 are voltage-dividing structures of the third storage node Q3 and the fourth storage node Q4 of the SRAM storage cell, respectively.

[0038] like Figure 2 As shown, the layout structure of a 130nmSOI process SRAM memory cell circuit structure resistant to multi-node flipping provided by the present invention adopts a symmetrical structure, which is conducive to the arrangement and interconnection of "H" gate devices and the connection between SRAM memory cells; in addition, the conductivity of the P-type stacked tube is weaker than that of the N-type stacked tube. When the stacking voltage is designed, the width-to-length ratio of the P-type stacked tube is smaller than that of the N-type stacked tube, which can reduce the area of ​​the memory cell;

[0039] Specifically, the center of the layout structure is the NMOS source region, and the two ends are the PMOS source regions; the word bit line WBLB is located at the upper left corner of the SRAM storage cell, the word bit line WBL is located at the upper right corner of the SRAM storage cell, the bit line BLB is located at the lower left corner of the SRAM storage cell, the bit line BL is located at the lower right corner of the SRAM storage cell, the write word line WWL is located above the SRAM storage cell, the word line WL is located below the SRAM storage cell, the power supply VDD is located at the left and right ends of the SRAM storage cell, and GND is located at the center of the SRAM storage cell; the third NMOS transistor N3 and the fourth NM The source widths of the OS transistor N4, the fifth NMOS transistor N5, the sixth NMOS transistor N6 and the seventh NMOS transistor N7 are all 2.4 μm, the source widths of the first NMOS transistor N1 and the second NMOS transistor N2 are all 0.8 μm, and the source widths of the first PMOS transistor P1, the second PMOS transistor P2, the third PMOS transistor P3, the fourth PMOS transistor P4, the fifth PMOS transistor P5, the sixth PMOS transistor P6, the seventh PMOS transistor P7 and the eighth PMOS transistor P8 are all 0.4 μm;

[0040] In one embodiment of the present invention, the purpose of setting the source region width is to ensure that when reading data, the charging and discharging rate of the third storage node Q3 and the fourth storage node Q4 through the first NMOS transistor N1 and the second NMOS transistor N2 is lower than the discharge rate of the SRAM transistor pull-down structure, so that the data of the storage node remains stable; when writing data, the charging and discharging rate when writing the third storage node Q3 and the fourth storage node Q4 through the first NMOS transistor N1 and the second NMOS transistor N2 is greater than the charging rate of the pull-up structure to ensure that the data can be written normally.

[0041] In the layout structure of the SRAM storage unit, the SOI device uses an "H" gate type device, and the two ends of the "H" gate are of unequal length. The "H" gate has two body regions, one of which is represented by a box and a cross symbol ( Figure 2 ), and connected to the "H" gate long end, the "H" gate short end is connected to another body region; the PMOS transistor body region is connected to VDD through the "H" gate short end, and the NMOS transistor body region is connected to GND through the "H" gate short end;

[0042] In one embodiment of the present invention, the SOI structure eliminates the body effect in traditional bulk silicon devices by inserting an insulating layer (usually silicon dioxide) between the active layer and the silicon substrate. The body effect will increase the charge collection caused by the single particle effect, so reducing the body effect helps to improve the radiation resistance. Due to the presence of the insulating layer, the charge sharing effect is greatly weakened, that is, the charge caused by a particle impact is difficult to propagate in adjacent devices, reducing the impact of the single particle effect on the overall performance of the circuit. The parasitic capacitance between the source and drain of the SOI device is small, which makes it difficult for the charge to accumulate after the impact of high-energy particles, thereby reducing the possibility of single-particle flipping. The lower parasitic capacitance also makes the circuit respond faster, which is conducive to maintaining stable performance in a high-radiation environment. The use of an "H" gate can better control the potential distribution in the channel, so that the threshold voltage of the device changes less when it is impacted by high-energy particles, which helps to maintain the normal working state of the circuit and reduce the probability of data errors.

[0043] like Figure 2 As shown, by optimizing the circuit structure, the impact of the effect can be effectively reduced, so that the flipping of the circuit node will not cause a major failure in the system, so as to improve the reliability of the system. During the layout, the first storage node Q1 and the second storage node Q2 are isolated, the third storage node Q3 and the fourth storage node Q4 are isolated, and the first storage node Q1 and the third storage node Q3 are connected, and the second storage node Q2 and the fourth storage node Q4 are connected, so as to enhance the ability to resist single particle effects.

[0044] Example 1

[0045] When the SRAM storage cell is in the latching stage, the word bit line WBL and the word bit line WBLB are kept at a low level, the word line WL is at a low level, and the state of the SRAM storage cell remains unchanged through feedback, and the write word line WWL is at a low level, which can reduce the static power consumption of the third storage node Q3 and the fourth storage node Q4 caused by leakage;

[0046] In the data reading stage of the SRAM storage cell, the bit line BL and the bit line BLB are precharged to a high level, the word line WL is a high level, the word bit line WBL and the word bit line WBLB remain at a low level, the state of the SRAM storage cell remains unchanged, the first NMOS transistor N1 and the second NMOS transistor N2 are turned on, the write word line WWL rises to VDD, and discharges according to the data stored in the third storage node Q3 and the fourth storage node Q4, so that a voltage difference is generated between the bit line BL and the bit line BLB. If the stored data is "0", the bit line BL is discharged through the pull-down circuit of the third storage node Q3, so that the level of the bit line BL is lower than that of the bit line BLB. If the stored data is "1", the bit line BLB is discharged through the pull-down circuit of the fourth storage node Q4, so that the level of the bit line BLB is lower than that of the bit line BL. The bit lines BL and BLB of the SRAM storage cell are read out through the sense amplifier of the readout circuit to read out the corresponding data;

[0047] In the data writing stage of the SRAM storage unit, the word line WL is at a high level, the write word line WWL is at a high level, and the third storage node Q3 and the fourth storage node Q4 store inverted data according to the voltage difference between the bit line BL and the bit line BLB, and the writing of the storage node is completed. Taking the writing data as "1" as an example, when writing, the bit line BL is at a high level and the bit line BLB is at a low level, then "1" is written to the third storage node Q3 through the fourth PMOS transistor P4, the sixth PMOS transistor P6 and the second NMOS transistor N2, and "1" is written to the first storage node Q1 through the first PMOS transistor P1, and "0" is written to the fourth storage node Q4 through the third NMOS transistor N3 and the first NMOS transistor N1, and "0" is written to the second storage node Q2 through the sixth NMOS transistor N6 and the eighth PMOS transistor P8. When writing, the word bit line WBLB maintains a low level to ensure that "0" is smoothly written into the second storage node Q2, and the word bit line WBL maintains a high level to turn off the pull-down path of the first storage node Q1.

[0048] The mutual control relationship of the point signals inside the latch structure is that, in the storage stage, taking the storage data as "1" as an example, the data stored in the third storage node Q3 is "1", so that the third PMOS transistor P3 is turned off, the third NMOS transistor N3 and the sixth NMOS transistor N6 are turned on, thereby controlling the second storage node Q2 and the fourth storage node Q4, so that the pull-down tube sixth NMOS transistor N6 pulls down the second storage node Q2, so that the second storage node Q2 maintains the latched data "0", and the pull-down tube third NMOS transistor N3 pulls down the fourth storage node Q4, so that the fourth storage node Q4 maintains the latched data "0", and the pull-up tube third NMOS transistor N6 of the fourth storage node Q4 is turned off. The OS transistor P3 is turned on so that the fourth storage node Q4 maintains the latched data "0"; the data stored in the fourth storage node Q4 is "0", so that the fourth PMOS transistor P4 is turned on, the fourth NMOS transistor N4 and the fifth NMOS transistor N5 are turned off, so as to control the first storage node Q1 and the third storage node Q3, so that the fifth NMOS transistor N5 is turned off, so that the first storage node Q1 maintains the latched data "1"; the fourth PMOS transistor P4 pulls up the third storage node Q3, so that the third storage node Q3 maintains the latched data "1", and turns off the fourth NMOS transistor N4 of the third storage node Q3 so that the third storage node Q3 maintains the latched data "1";

[0049] The data stored in the first storage node Q1 is "1", so that the second PMOS transistor P2 is turned off, thereby controlling the second storage node Q2, turning off the second PMOS transistor P2 of the pull-up tube of the second storage node Q2 so that the second storage node Q2 keeps latching data "0"; the data stored in the second storage node Q2 is "0", so that the first PMOS transistor P1 is turned on, thereby controlling the first storage node Q1, turning on the first PMOS transistor P1 of the pull-up tube of the first storage node Q1 so that the first storage node Q1 keeps latching data "0".

[0050] Example 2

[0051] For single-node flipping, take the first storage node Q1 and the third storage node Q3 as "1", and the second storage node Q2 and the fourth storage node Q4 as "0" as an example. If it is "1" to "0", only the first storage node Q1, the third storage node Q3 and the nodes between the third PMOS transistor P3 and the fifth PMOS transistor P5 connected thereto and the nodes between the seventh PMOS transistor P7 and the fifth NMOS transistor N5 need to be considered. At this time, for the flipping of the first storage node Q1, the fifth PMOS transistor P5 is turned on, but the third PMOS transistor P3 is still turned off, and the fourth storage node Q4 will not be affected. The second PMOS transistor P2 is turned on, and the sixth NMOS transistor N6 is turned on. At this time, the pull-down tube is stronger than the pull-up tube, and the second storage node Q2 remains "0", so that it is fed back to the first storage node Q1 and gradually recovers to "1";

[0052] When the third storage node Q3 is flipped, the third PMOS transistor P3 is turned on. However, since the first storage node Q1 remains at "1", the fifth PMOS transistor P5 is turned off, and the pull-up will not affect the fourth storage node Q4. The sixth NMOS transistor N6 is turned off. Since the first storage node Q1 has not changed, the pull-up transistor, the second PMOS transistor P2, is still turned off, so that the second storage node Q2 remains at "0", and finally they are fed back to the third storage node Q3, so that the third storage node Q3 is restored to "1".

[0053] If it is from "0" to "1", at this time, only the second storage node Q2, the fourth storage node Q4 and the nodes connected thereto, the third PMOS transistor P3, the fifth PMOS transistor P5 and the node between the eighth PMOS transistor P8 and the sixth NMOS transistor N6 need to be considered. At this time, the second storage node Q2 is flipped, the first PMOS transistor P1 and the sixth PMOS transistor P6 are turned off, but the fourth NMOS transistor N4 of the pull-down tube of the fourth storage node Q4 is still turned on, the fourth storage node Q4 remains at "0", the fifth NMOS transistor N5 of the pull-down tube of the first storage node Q1 remains turned off, and the first storage node Q1 remains at "1", thereby gradually feeding back to the second storage node Q2 to restore it to "0".

[0054] When the fourth storage node Q4 flips, since the fifth PMOS transistor P5 is controlled by the first storage node Q1 and remains in the off state, the pull-up transistor third PMOS transistor P3 cannot charge the fourth storage node Q4, and the fourth storage node Q4 cannot be maintained at a high level all the time, and eventually returns to "0".

[0055] Example 3

[0056] For multi-node flipping, the second storage node Q2 and the node between the seventh PMOS transistor P7 and the fifth NMOS transistor N5 are in different potential wells. After the second storage node Q2 is flipped, the first PMOS transistor P1 is turned off, the sixth PMOS transistor P6 is turned off, and the node between the seventh PMOS transistor P7 and the fifth NMOS transistor N5 is maintained at a low level due to the voltage divider node of the seventh PMOS transistor P7, and the first storage node Q1 is maintained at a high level, thereby feeding back to the second storage node Q2 to restore it, and finally feeding back to the node between the seventh PMOS transistor P7 and the fifth NMOS transistor N5 to restore it.

[0057] For the first storage node Q1 and the third storage node Q3, the two are in the same potential well, but do not directly control each other; since the fourth storage node Q4 and the second storage node Q2 are not flipped, the first storage node Q1 is at "1" due to the charging of the first PMOS transistor P1, and the flipping of the third storage node Q3 is restored due to the flipping of the first storage node Q1, which is the same as the analysis of single node flipping, so these two nodes will eventually be restored.

[0058] Based on the above SRAM storage unit circuit, simulations are performed for the flipping conditions of different nodes, wherein single-node and double-node transient error injections are performed on the first storage node Q1, the second storage node Q2, the third storage node Q3, and the fourth storage node Q4, respectively. The error source is a double exponential current source. The single-node error simulation results are shown in FIG. Figure 3 Single-node second storage node Q2 error injection simulation, Figure 4 Single-node first storage node Q1 error injection simulation, Figure 5 Single-node third storage node Q3 error injection simulation, Figure 6 The single-node fourth storage node Q4 error injection simulation is shown in which the error occurring in a single node does not affect other nodes, and the stored data is not flipped; the dual-node transient error simulation results are shown in Figure 7 Error injection simulation of the second storage node Q2 and the fourth storage node Q4 of the double node same potential well, Figure 8 As shown in the simulation results of node error injection between the second storage node Q2 of different potential wells of the double nodes and the seventh PMOS transistor P7 and the fifth NMOS transistor N5, the transient error occurring at the double nodes did not cause data flipping on the nodes, and the transient error did not further affect other nodes, and the system has the ability to resist single and double transient error flipping.

[0059] The above embodiments are preferred examples for implementing the present invention, and the present invention is not limited to the above embodiments. Any non-essential additions and substitutions made by those skilled in the art based on the technical features of the technical solution of the present invention shall fall within the protection scope of the present invention.

Claims

1. A 130nm SOI process SRAM storage unit circuit structure resistant to multi-node flipping, characterized in that: The memory cell circuit structure at least includes: a pull-up circuit structure, a pull-down circuit structure, a stacked transistor circuit structure, an access transistor and a tail transistor; The pull-up circuit structure is connected with the pull-down circuit structure to form two inversely interlocked structures, which are used to keep multiple nodes stable; The stacked transistor circuit structure adopts a stack of PMOS transistors to form a storage node, so that the unit circuit can resist multi-node flipping and restore the logic state on the storage node to normal when interference occurs, wherein the stacked transistor circuit structure includes a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, and an eighth PMOS transistor; the seventh PMOS transistor and the eighth PMOS transistor respectively form a stacked structure of a first storage node and a second storage node; the fifth PMOS transistor and the sixth PMOS transistor respectively form a stacked structure of a third storage node and a fourth storage node; The access tube is used to connect the word line and the bit line of the unit circuit, and the access tube includes a first NMOS transistor and a second NMOS transistor; The tail transistor adopts a seventh NMOS transistor, which is used to reduce static power consumption and improve write and read rates; The pull-up circuit structure includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor; the pull-down circuit structure includes a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor; The first PMOS transistor and the second PMOS transistor are pull-up structures of the first storage node and the second storage node, respectively, and the fifth NMOS transistor and the sixth NMOS transistor are pull-down structures of the first storage node and the second storage node, respectively; the third PMOS transistor and the fourth PMOS transistor are pull-up structures of the third storage node and the fourth storage node, respectively, and the third NMOS transistor and the fourth NMOS transistor are pull-down structures of the third storage node and the fourth storage node, respectively; The sources of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, and the fourth PMOS transistor are all connected to the power supply VDD, the drain of the first PMOS transistor is connected to the gate of the second PMOS transistor, the gate of the fifth PMOS transistor, and the source of the seventh PMOS transistor to form a first storage node, the drain of the second PMOS transistor is connected to the gate of the first PMOS transistor, the gate of the sixth PMOS transistor, and the source of the eighth PMOS transistor to form a second storage node, the drain of the fourth PMOS transistor is connected to the source of the sixth PMOS transistor, the drain of the third PMOS transistor is connected to the source of the fifth PMOS transistor, the drain of the sixth PMOS transistor is connected to the gate of the third PMOS transistor, the source of the second NMOS transistor, the gate of the third NMOS transistor, the drain of the fourth NMOS transistor, and the gate of the sixth NMOS transistor to form a third storage node, the drain of the fifth PMOS transistor is connected to the gate of the fourth PMOS transistor, and the drain of the fifth PMOS transistor is connected to the gate of the sixth NMOS transistor. The gate of the MOS transistor, the source of the first NMOS transistor, the gate of the fourth NMOS transistor, the drain of the third NMOS transistor and the gate of the fifth NMOS transistor constitute a fourth storage node, the drain of the eighth PMOS transistor is connected to the drain of the sixth NMOS transistor, the drain of the seventh PMOS transistor is connected to the drain of the fifth NMOS transistor, the source of the fourth NMOS transistor and the source of the third NMOS transistor are both connected to the drain of the seventh NMOS transistor, the source of the sixth NMOS transistor, the source of the fifth NMOS transistor and the source of the seventh NMOS transistor are all connected to GND; the gate of the second NMOS transistor and the gate of the first NMOS transistor are both connected to the word line WL, the drain of the second NMOS transistor is connected to the bit line BL, the drain of the first NMOS transistor is connected to the bit line BLB, the gate of the eighth PMOS transistor is connected to the word bit line WBLB, the gate of the seventh PMOS transistor is connected to the word bit line WBL, and the gate of the seventh NMOS transistor is connected to the write word line WWL.

2. The layout structure of a 130nm SOI process SRAM memory cell circuit structure resistant to multi-node flipping according to claim 1, characterized in that: The layout structure of the SRAM storage cell adopts a symmetrical structure, wherein the center is the NMOS transistor source region and the two ends are the PMOS transistor source regions; the word bit line WBLB is located at the upper left corner of the SRAM storage cell, the word bit line WBL is located at the upper right corner of the SRAM storage cell, the bit line BLB is located at the lower left corner of the SRAM storage cell, the bit line BL is located at the lower right corner of the SRAM storage cell, the write word line WWL is located above the SRAM storage cell, the word line WL is located below the SRAM storage cell, the power supply VDD is located at the left and right ends of the SRAM storage cell, and GND is located at the center of the SRAM storage cell.

3. The layout structure of a 130nm SOI process SRAM memory cell circuit structure resistant to multi-node flipping according to claim 2, characterized in that: The source widths of the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, the sixth NMOS transistor and the seventh NMOS transistor are all 2.4 μm, the source widths of the first NMOS transistor and the second NMOS transistor are all 0.8 μm, and the source widths of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, the sixth PMOS transistor, the seventh PMOS transistor and the eighth PMOS transistor are all 0.4 μm.

4. The layout structure of a 130nm SOI process SRAM memory cell circuit structure resistant to multi-node flipping according to claim 2, characterized in that: In the layout structure of the SRAM storage unit, the SOI device adopts an H-gate type device, and the two ends of the H gate are of unequal length. The H gate has two body regions, one of which is connected to the long end of the H gate, and the short end of the H gate is connected to the other body region; the body region of the PMOS transistor is connected to VDD through the short end of the H gate, and the body region of the NMOS transistor is connected to GND through the short end of the H gate.

5. The layout structure of a 130nm SOI process SRAM memory cell circuit structure resistant to multi-node flipping according to claim 2, characterized in that: In the layout structure of the SRAM storage unit, the first storage node is isolated from the second storage node, the third storage node is isolated from the fourth storage node, the first storage node is connected to the third storage node, and the second storage node is connected to the fourth storage node.

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