Parallel test method and system for shift memory

Abstract

The invention relates to a parallel test method and system for a shift memory. The method comprises the following steps: receiving first test data from a test machine, generating first output data, and when the potential of the first output data is consistent with that of the first test data, determining that the storage function is normal; receiving second test data from the test machine, generating second output data, and determining that the shift function is normal when the second output data is consistent with a preset output potential; receiving a first test signal from the test machine, obtaining an output port driving voltage of the shift memory, and when the output port driving voltage is within a preset voltage range, determining that the output end driving voltage function is normal; and receiving a second test signal from the test machine, obtaining an output port current of the shift memory, and when the output port current is within a predetermined current range, determining that the high-impedance state current function of the output end is normal. According to the invention, the accuracy and reliability of the test result are ensured, and the test cost is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of production testing of shift memory, and in particular to a parallel testing method and system for shift memory. Background Art

[0002] Shift registers are widely used in digital systems, usually in serial input and parallel output scenarios. The performance and reliability of shift registers directly affect the stability of the system, so the testing process in the production process is particularly important. Taking the 74HC595 shift register as an example, the device integrates two functional modules, the shift register and the storage register, which can realize the input of serial data and store these data at the same time. Existing production test technology mainly focuses on the functional verification of the shift register and the storage register to confirm whether the memory can work accurately and stably.

[0003] However, the current testing methods have the following major problems: Traditional testing methods usually use chip-by-chip testing, which takes a long time, especially in large-scale production, increasing the production efficiency and cost of the testing process; due to the performance limitations of existing testing equipment, test results are often affected by equipment errors, making it difficult to ensure the complete accuracy of the test, which may cause unqualified chips to be mistakenly judged as qualified, or qualified chips to be mistakenly judged as unqualified. Summary of the invention

[0004] To this end, the present invention provides a shift memory parallel testing method and system for testing wafers or packaged finished products of shift memories, which can quickly eliminate chips with poor shift and storage functions, improve test efficiency, ensure the accuracy and reliability of test results, and reduce test costs.

[0005] In order to solve the above technical problems, the present invention provides a shift memory parallel testing method, which is applied to a shift memory, at least one of the shift memories is connected to a tester, and the method comprises: Receive a control signal from the tester, wherein the control signal is used to adjust the internal timing of the shift memory so that the shift memory enters a verification mode of a storage function, a shift function, an output end driving voltage function, and an output end high impedance current function correspondingly; In the verification mode of the storage function, the shift memory receives the first test data from the tester and generates the first output data, and when the potential of the first output data is consistent with the potential of the first test data, it is determined that the storage function is normal; In the verification mode of the shift function, the shift memory receives second test data from the test machine and generates second output data, and when the second output data is consistent with a preset output potential, it is determined that the shift function is normal; In the verification mode of the output end driving voltage function, the shift memory receives the first test signal from the tester and obtains the output port driving voltage of the shift memory, and when the output port driving voltage is within a predetermined voltage range, it is determined that the output end driving voltage function is normal; In the verification mode of the output high-impedance current function, the shift memory receives a second test signal from the tester and obtains the output port current of the shift memory. When the output port current is within a predetermined current range, it is determined that the output high-impedance current function is normal.

[0006] In one embodiment of the present invention, the tester adopts a TR6836 tester, and the shift memory adopts a 74HC595 chip, including a serial data input pin, a serial data output pin, a shift register clock pin, a storage register clock pin, an output enable control pin, a data control pin and a parallel output pin. The timing of the shift memory is set through the Pattern Format mode of the TR6836 tester, so that the port of the shift memory enters a predetermined high level, a low level, an arbitrary state or a high impedance state.

[0007] In one embodiment of the present invention, when a plurality of the shift memories are connected to one tester, all the shift memories share a Pattern Format mode.

[0008] In one embodiment of the present invention, setting the timing of the shift memory by using the Pattern Format of the TR6836 tester includes: Inputting data into the shift register via the serial data input pin; Controlling the shifting of data via the shift register clock pin; Controlling the storage of data through the storage register clock pin; By means of the output enable control pin, a low power enable output is controlled; The data control pin is used to clear the existing data in the shift register when the level is low.

[0009] In one embodiment of the present invention, in the verification mode of the storage function, the storage function is verified by inputting the first test data into the serial data input pin and reading the corresponding first output data through the parallel output pin.

[0010] In one embodiment of the present invention, in the verification mode of the shift function, the shift function is verified by inputting the second test data into the serial data input pin and reading the corresponding second output data through the serial data output pin.

[0011] In one embodiment of the present invention, in the verification mode of the output end driving voltage function, by continuously inputting 00 or FF to the serial data input pin and keeping the power supply to the shift memory continuous, the driving voltage of each parallel output pin is tested through the power module of the digital channel of the test machine.

[0012] In one embodiment of the present invention, it also includes: A 5 mA current is provided to the parallel output pin through the power supply module of the test machine, and the driving voltage is measured after a delay of 10 milliseconds.

[0013] In one embodiment of the present invention, in the verification mode of the output high-impedance current function, the output enable control pin is set to a high level.

[0014] The present invention also provides a shift memory parallel testing system, comprising: A timing adjustment module, used for receiving a control signal from the tester, wherein the control signal is used for adjusting the internal timing of the shift memory so that the shift memory enters a verification mode of a storage function, a shift function, an output end driving voltage function, and an output end high impedance current function correspondingly; A storage function verification module, used for, in a verification mode of the storage function, the shift memory receives first test data from the test machine and generates first output data, and when the potential of the first output data is consistent with the potential of the first test data, determining that the storage function is normal; A shift function verification module, used for, in a verification mode of the shift function, the shift memory receives second test data from the test machine and generates second output data, and when the second output data is consistent with a preset output potential, determining that the shift function is normal; An output end driving voltage function verification module, used for, in a verification mode of the output end driving voltage function, the shift memory receives a first test signal from the test machine and obtains an output port driving voltage of the shift memory, and when the output port driving voltage is within a predetermined voltage range, determines that the output end driving voltage function is normal; The output end high-impedance current function verification module is used to, in the verification mode of the output end high-impedance current function, enable the shift memory to receive a second test signal from a test machine and obtain the output port current of the shift memory. When the output port current is within a predetermined current range, it is determined that the output end high-impedance current function is normal.

[0015] The above technical solution of the present invention has the following advantages compared with the prior art: The present invention discloses a shift memory parallel testing method and system. The parallel testing not only improves the efficiency, but also reduces the occupancy time of the testing equipment, thereby reducing the overall testing cost. By testing multiple shift memories in parallel, the testing time is significantly shortened, and the system is suitable for large-scale production applications.

[0016] The present invention ensures the comprehensiveness of the test and reduces the possibility of misjudgment during the test by verifying the storage function, the shift function, the output drive voltage and the high-resistance current.

[0017] The present invention utilizes the Pattern Format function of the TR6836 test machine to automatically configure the status of each pin of the chip, reduces manual intervention and setting errors, and improves test accuracy and repeatability. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to make the contents of the present invention more clearly understood, the present invention is further described in detail below based on specific embodiments of the present invention in conjunction with the accompanying drawings.

[0019] Figure 1 It is a schematic diagram of the connection between the shift memory and the test machine of the present invention.

[0020] Figure 2 It is a flow chart of verification of storage function of the present invention.

[0021] Figure 3 It is a verification flow chart of the shift function of the present invention.

[0022] Figure 4 It is a flow chart of verifying the output end driving voltage function of the present invention.

[0023] Figure 5 It is a flow chart of verifying the high-resistance current function of the output terminal according to the present invention. DETAILED DESCRIPTION

[0024] The present invention is further described below in conjunction with the accompanying drawings and specific embodiments so that those skilled in the art can better understand the present invention and implement it, but the embodiments are not intended to limit the present invention.

[0025] In the present invention, "several" means one or more, "multiple" means more than two, "greater than", "less than", "exceed" and the like are understood to exclude the number itself; "above", "below", "within" and the like are understood to include the number itself. In the description of the present invention, if there is a description of "first" or "second", it is only used for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0026] In the present invention, unless otherwise clearly defined, the words "set", "install", "connect" and the like should be understood in a broad sense, for example, they can be directly connected or indirectly connected through an intermediate medium; they can be fixedly connected or detachably connected or integrally formed; they can be mechanically connected or electrically connected or able to communicate with each other; they can be the internal connection of two elements or the interaction relationship between two elements. Those skilled in the art can reasonably determine the specific meanings of the above words in the present invention in combination with the specific content of the technical solution.

[0027] Example 1 Reference Figure 1 As shown, a parallel testing method for a shift memory of the present invention is applied to a shift memory, at least one of the shift memories is connected to a tester, and the method comprises: Receive a control signal from the tester, wherein the control signal is used to adjust the internal timing of the shift memory so that the shift memory enters a verification mode of a storage function, a shift function, an output end driving voltage function, and an output end high impedance current function correspondingly; In the verification mode of the storage function, the shift memory receives the first test data from the tester and generates the first output data, and when the potential of the first output data is consistent with the potential of the first test data, it is determined that the storage function is normal; In the verification mode of the shift function, the shift memory receives second test data from the test machine and generates second output data, and when the second output data is consistent with a preset output potential, it is determined that the shift function is normal; In the verification mode of the output end driving voltage function, the shift memory receives the first test signal from the tester and obtains the output port driving voltage of the shift memory, and when the output port driving voltage is within a predetermined voltage range, it is determined that the output end driving voltage function is normal; In the verification mode of the output high-impedance current function, the shift memory receives a second test signal from the tester and obtains the output port current of the shift memory. When the output port current is within a predetermined current range, it is determined that the output high-impedance current function is normal.

[0028] In this embodiment, refer to Figure 1 As shown, the test machine adopts a TR6836 test machine, and the shift memory adopts a 74HC595 chip. The TR6836 test machine is connected to the shift memory (74HC595 chip) to be tested through a test board and a cable. The 64 digital source channels of the test board (PEB board) are configured on the test machine to achieve parallel testing of multiple groups of 74HC595 chips at the same time. Each test board can test 4 groups of chips in parallel, which greatly improves the test efficiency. And when multiple shift memories are connected to one test machine, all the shift memories share a Pattern Format mode.

[0029] Set the power supply voltage of the TR6836 tester to 5V, connect it to the VCC port of the 74HC595 chip, and the chip starts to power on. At this time, since the internal timing of the chip may be unstable, use the PatternFormat (vector mode) of the TR6836 tester to set the various pin signals of the chip to ensure that the timing of the chip is synchronized with the test equipment to meet the test requirements.

[0030] It should be noted that, since the 74HC595 chip has certain requirements for timing, if the port state of the channel connecting the tester and the chip cannot be kept consistent with the chip's internal clock, the chip will not be able to output the required results. The chip's port is set to the desired mode through the TR6836 tester Pattern Format, 1 represents high level, 0 represents low level, X represents any state, Z represents high impedance state, H represents the port is read as a high level state, and L represents the port is read as a low level state. The TR6836 tester will generate a control signal according to the predetermined timing and send it to the chip through the signal channel. After receiving the control signal from the tester, the shift memory adjusts its internal timing according to the input clock signal and data input signal, so that it can enter different verification modes.

[0031] Specifically, the 74HC595 chip includes a serial data input pin DS, a serial data output pin Q7S, a shift register clock pin SH_CP, a storage register clock pin ST_CP, an output enable control pin OE, a data control pin (reset pin) MR, and parallel output pins Q1-Q7; Among them, the shift register clock pin SH_CP: rising edge trigger, controls the shift of data in the shift register; Storage register clock pin ST_CP: rising edge triggered, transfers the data in the shift register to the storage register.

[0032] Serial data input pin DS: inputs data into the shift register through the SH_CP clock, cascade serial data output pin Q7S; Output enable control pin OE: Low level is valid, controls whether the data in the storage register is output to the parallel output pins Q0 to Q7.

[0033] Data control pin MR: When the level is low, the shift register is reset and its contents are cleared.

[0034] Parallel output pins Q0-Q7: Display the data in the shift or storage register, the status is controlled by SH_CP and ST_CP.

[0035] The timing of the shift memory is set by the Pattern Format mode of the TR6836 test machine, so that the port of the shift memory enters a predetermined high level, low level, any state or high impedance state.

[0036] Specifically, the timing of the shift memory is set by the Pattern Format of the TR6836 test machine, including: Inputting data into the shift register via the serial data input pin; Controlling the shifting of data via the shift register clock pin; Controlling the storage of data through the storage register clock pin; By means of the output enable control pin, a low power enable output is controlled; The data control pin is used to clear the existing data in the shift register when the level is low.

[0037] It is understandable that when performing a shift operation, when the rising edge of the SH_CP clock arrives, data will be input from DS to the shift register. It is necessary to ensure that the clock cycle of SH_CP is synchronized with the DS input signal to prevent data errors during the shift process.

[0038] When performing a storage operation, the data in the shift register will be transferred to the storage register when the ST_CP clock rises. ST_CP must be triggered after the shift operation is completed to ensure that the correct data is stored.

[0039] Specifically, in the verification mode of the storage function, the storage function is verified by inputting the first test data into the serial data input pin and reading the corresponding first output data through the parallel output pin.

[0040] Reference Figure 2 As shown, in this embodiment, when performing a storage function test, the 74HC595 chip needs to be powered on first to provide a stable operating voltage (such as 5V) for the chip; Ensure that the pins of the 74HC595 chip are correctly configured according to the timing requirements, including the serial data input pin DS, the shift register clock pin SH_CP, the storage register clock pin ST_CP and other timing control signals; the storage function is triggered on the rising edge of the storage register clock (ST_CP) to transfer the complete data in the shift register to the storage register.

[0041] Use Pattern Format to input the hexadecimal data 55AA to the chip through the DS pin in sequence, which corresponds to the binary 0101010110101010.

[0042] Read the status of the chip's parallel output pins Q0-Q7. The expected output is LHLHLHLHLHLHLHL (corresponding to the binary of 55AA). If the output is consistent with the expected output, it means that the storage function is normal.

[0043] Specifically, in the verification mode of the shift function, the shift function is verified by inputting the second test data into the serial data input pin and reading the corresponding second output data through the serial data output pin.

[0044] Reference Figure 3 As shown, in this embodiment, when performing the shift test, the chip is first powered on to ensure normal operating voltage.

[0045] Ensure that the timing control of the chip pins is correct; the shift function depends on the rising edge of the shift register clock (SH_CP), and the data enters the shift register bit by bit and is shifted out through the serial output.

[0046] Use Pattern Format to input the hexadecimal data 55AA through the serial data input pin DS in sequence, which corresponds to the binary number 0101010110101010.

[0047] Read the serial output pin Q7S of the chip, and the expected output is LHLHLHLH (corresponding to the binary of 55). If the output is consistent with the expected output, it means that the shift function is normal.

[0048] Specifically, in the verification mode of the output end driving voltage function, by continuously inputting 00 or FF to the serial data input pin and keeping the power supply to the shift memory continuous, the driving voltage of each parallel output pin is tested through the power module of the digital channel of the tester.

[0049] In addition, a 5 mA current is provided to the parallel output pin through the power module of the test machine, and the driving voltage is measured after a delay of 10 milliseconds.

[0050] Reference Figure 4 As shown, in this embodiment, when the output end driving voltage is tested, the chip is powered on first to ensure stable power supply.

[0051] Ensure that the timing control of the chip pins is correct; Use Pattern Format to continuously input 00 or FF through the serial data input pin DS pin in sequence, that is, low level or high level is output to the parallel pin of the chip.

[0052] Use the tester's power module and digital channels to measure the drive voltage of the parallel output pins Q0-Q7 respectively to ensure that each output pin can maintain the expected voltage level when current is applied.

[0053] During the test, a fixed current (such as 5mA) is supplied to each pin, and the voltage is measured to see if it meets the design requirements.

[0054] If the driving voltage is as expected, it means that the output driving voltage function is normal.

[0055] Reference Figure 5 As shown, in this embodiment, during the high impedance test at the output end, it is ensured that the chip has been powered on to ensure the normal operation of the chip.

[0056] Set the output enable control pin OE to a high level to put the chip output pin into a high-impedance state.

[0057] Use the power module of the test machine to measure the current of the chip's output ports Q0-Q7 by testing the digital channel to ensure that the current of the output pin is close to zero in the high-impedance state.

[0058] If the current is within the expected range, the high-impedance output is functioning properly.

[0059] For example, according to the characteristics and timing requirements of the chip, the state of each pin is set through the Pattern Format mode to ensure that the chip can work normally, and the state of the output port is read to verify whether it is consistent with the input data, so as to determine whether the chip functions normally.

[0060] Pattern writing steps: Step 1: Define pin names First, use HEAD (system reserved word) in Pattern Format to define the pin name of the chip. The pin name must be consistent with the pin map (Pin Map) in Pin_Channel_Map in the test program to ensure that the test equipment can correctly identify and control each pin. For example: HEAD DS,SH_CP,ST_CP,OE,MR,Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8; Step 2: Set Pattern (timing control) The second line starts: pattern is placed in brackets and ends with a semicolon. That is, each line defines the state of the chip pins in a clock cycle. The value in the brackets represents the level state of each pin, 0 represents low level, 1 represents high level, X represents any state, Z represents high impedance state, H represents reading high level, and L represents reading low level.

[0061] For example, the following setup shows the process of the chip starting to shift and store data: START: ( 0 0 0 0 0 XXXXXXXXX ); / / Initial state, MR reset ( 0 0 0 0 1 XXXXXXXXX ); / / MR=1, start shift register ( 0 1 0 0 1 XXXXXXXXX ); / / SH_CP shift rising edge ( 1 0 0 0 1 XXXXXXXXX ); / / DS=1, continue shifting ( 1 1 0 0 1 XXXXXXXXX ); / / Write data into the shift register.

[0062] Step 3: Read and verify output data After completing the data shifting and storage, read the status of the parallel output ports Q0-Q7. For example, after inputting the data 01010101 (hexadecimal 55), the chip output status should be 10101010. The output can be verified by the following pattern setting: ( X 0 0 0 0 HLHLHLHLX ); / / Read Q0-Q7 and verify shift and store functionality.

[0063] In a similar way, the chip can be made to output hexadecimal AA (10101010) or 55AA (0101010110101010) to verify whether the chip's shift and storage functions are normal by alternating high and low levels of the output pin.

[0064] To test the chip's output drive capability, use Pattern to set the chip to output all high level (FF) or all low level (00). Keep the chip powered on, and the reset pin MR cannot be set to 0. Then, apply a fixed current to the chip's output pin through the tester's digital channel and measure the drive voltage to ensure that its output capability is normal. The example code is: peb.ppmu.FI("Q0",5*1e-3,peb.ppmu.I_RNG_32MA,2,-2); / / Apply 5mA current to Q0 pin util.dlyms(10); / / Delay 10 milliseconds peb.ppmu.MV("Q0",1); / / Measure the voltage of Q0 pin Correspondingly, measure the voltage of each parallel output pin to check whether the driving voltage is consistent with the current state of each port. If not, it means that the chip is defective.

[0065] For example, let the chip output the pattern of 01010101 (55) as follows; HEAD DS,SH_CP,ST_CP,OE,MR,Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8; START: ( 0 0 0 0 0 XXXXXXXXX ); ( 0 0 0 0 0 XXXXXXXXX ); ( 0 0 0 0 1 XXXXXXXXX ); ( 0 0 0 0 1 XXXXXXXXX ); ( 0 1 0 0 1 XXXXXXXXX ); / / 0 MR=1 OE=0 DS continuously inputs 0, and puts it into Q0 when SH_CP changes from 0 to 1; ( 0 1 0 0 1 XXXXXXXXX ); ( 1 0 0 0 1 XXXXXXXXX ); ( 1 0 0 0 1 XXXXXXXXX ); ( 1 1 0 0 1 XXXXXXXXX ); / / 1 ( 1 1 0 0 1 XXXXXXXXX ); ( 0 0 0 0 1 X X X X X X X X X ); ( 0 0 0 0 1 X X X X X X X X X ); ( 0 1 0 0 1 X X X X X X X X X ); / / 0 ( 0 1 0 0 1 X X X X X X X X X ); ( 1 0 0 0 1 X X X X X X X X X ); ( 1 0 0 0 1 X X X X X X X X X ); ( 1 1 0 0 1 X X X X X X X X X ); / / 1 ( 1 1 0 0 1 X X X X X X X X X ); ( 0 0 0 0 1 X X X X X X X X X ); ( 0 0 0 0 1 X X X X X X X X X ); ( 0 1 0 0 1 X X X X X X X X X ); / / 0 ( 0 1 0 0 1 X X X X X X X X X ); ( 1 0 0 0 1 X X X X X X X X X ); ( 1 0 0 0 1 X X X X X X X X X ); ( 1 1 0 0 1 X X X X X X X X X ); / / 1 ( 1 1 0 0 1 X X X X X X X X X ); ( 0 0 0 0 1 X X X X X X X X X ); ( 0 0 0 0 1 X X X X X X X X X ); ( 0 1 0 0 1 X X X X X X X X X ); / / 0 ( 0 1 0 0 1 X X X X X X X X X ); ( 1 0 0 0 1 X X X X X X X X X ); ( 1 0 0 0 1 X X X X X X X X X ); ( 1 1 0 0 1 XXXXXXXXX ); / / 1 ( 1 1 0 0 1 XXXXXXXXX ); ( X 1 0 0 1 XXXXXXXXX ); / / Input data 55, Q0-Q7: 10101010 ( X 0 1 0 1 XXXXXXXXX ); ( X 0 1 0 1 XXXXXXXXX ); ( X 0 1 0 1 XXXXXXXXX ); ( X 0 1 0 1 XXXXXXXXX ); ( X 0 1 0 1 XXXXXXXXX ); ( X 0 1 0 1 XXXXXXXXX ); T1: ( X 0 0 0 0 XXXXXXXXX ); ( X 1 0 0 0 XXXXXXXXX ); ( X 0 0 0 0 HLHLHLHLX ); ( X 1 0 0 0 HLHLHLHLX ); / / Read output port STOP: (X 0 0 0 0 HLHLHLHLX).

[0066] Example 2 Based on the same inventive concept, this embodiment provides a shift memory parallel test system, the principle of solving the problem is similar to that of the shift memory parallel test method, and the repeated parts are not repeated here.

[0067] This embodiment provides a shift memory parallel testing system, including: A timing adjustment module, used for receiving a control signal from the tester, wherein the control signal is used for adjusting the internal timing of the shift memory so that the shift memory enters a verification mode of a storage function, a shift function, an output end driving voltage function, and an output end high impedance current function correspondingly; A storage function verification module, used for, in a verification mode of the storage function, the shift memory receives first test data from the test machine and generates first output data, and when the potential of the first output data is consistent with the potential of the first test data, determining that the storage function is normal; A shift function verification module, used for, in a verification mode of the shift function, the shift memory receives second test data from the test machine and generates second output data, and when the second output data is consistent with a preset output potential, determining that the shift function is normal; An output end driving voltage function verification module, used for, in a verification mode of the output end driving voltage function, the shift memory receives a first test signal from the test machine and obtains an output port driving voltage of the shift memory, and when the output port driving voltage is within a predetermined voltage range, determines that the output end driving voltage function is normal; The output end high-impedance current function verification module is used to, in the verification mode of the output end high-impedance current function, enable the shift memory to receive a second test signal from a test machine and obtain the output port current of the shift memory. When the output port current is within a predetermined current range, it is determined that the output end high-impedance current function is normal.

[0068] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0069] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0070] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0071] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0072] Finally, it should be noted that the above specific implementation methods are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to examples, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the spirit and scope of the technical solution of the present invention, which should be included in the scope of the claims of the present invention.

Claims

1. A parallel testing method for a shift memory, applied to a shift memory, wherein at least one of the shift memories is connected to a testing machine, characterized in that: The method comprises: Receive a control signal from the tester, wherein the control signal is used to adjust the internal timing of the shift memory so that the shift memory enters a verification mode of a storage function, a shift function, an output end driving voltage function, and an output end high impedance current function correspondingly; In the verification mode of the storage function, the shift memory receives the first test data from the tester and generates the first output data, and when the potential of the first output data is consistent with the potential of the first test data, it is determined that the storage function is normal; In the verification mode of the shift function, the shift memory receives second test data from the test machine and generates second output data, and when the second output data is consistent with a preset output potential, it is determined that the shift function is normal; In the verification mode of the output end driving voltage function, the shift memory receives the first test signal from the tester and obtains the output port driving voltage of the shift memory, and when the output port driving voltage is within a predetermined voltage range, it is determined that the output end driving voltage function is normal; In the verification mode of the output high-impedance current function, the shift memory receives a second test signal from the tester and obtains the output port current of the shift memory. When the output port current is within a predetermined current range, it is determined that the output high-impedance current function is normal.

2. A shift memory parallel testing method and system according to claim 1, characterized in that: The test machine adopts a TR6836 test machine, and the shift memory adopts a 74HC595 chip, including a serial data input pin, a serial data output pin, a shift register clock pin, a storage register clock pin, an output enable control pin, a data control pin and a parallel output pin. The timing of the shift memory is set through the Pattern Format mode of the TR6836 test machine, so that the port of the shift memory enters a predetermined high level, a low level, an arbitrary state or a high impedance state.

3. A shift memory parallel testing method and system according to claim 2, characterized in that: When a plurality of the shift memories are connected to one tester, all the shift memories share a Pattern Format mode.

4. A shift memory parallel testing method and system according to claim 2, characterized in that: The timing of the shift memory is set by the Pattern Format of the TR6836 test machine, including: Inputting data into the shift register via the serial data input pin; Controlling the shifting of data via the shift register clock pin; Controlling the storage of data through the storage register clock pin; By means of the output enable control pin, a low power enable output is controlled; The data control pin is used to clear the existing data in the shift register when the level is low.

5. A shift memory parallel testing method and system according to claim 2, characterized in that: In the verification mode of the storage function, the storage function is verified by inputting the first test data into the serial data input pin and reading the corresponding first output data through the parallel output pin.

6. A shift memory parallel testing method and system according to claim 2, characterized in that: In the verification mode of the shift function, the shift function is verified by inputting the second test data into the serial data input pin and reading the corresponding second output data through the serial data output pin.

7. A shift memory parallel testing method and system according to claim 2, characterized in that: In the verification mode of the output drive voltage function, by continuously inputting 00 or FF to the serial data input pin and keeping the power supply to the shift memory continuous, the drive voltage of each parallel output pin is tested through the power module of the digital channel of the tester.

8. A shift memory parallel testing method and system according to claim 7, characterized in that: Also includes: A 5 mA current is provided to the parallel output pin through the power supply module of the test machine, and the driving voltage is measured after a delay of 10 milliseconds.

9. A shift memory parallel testing method and system according to claim 2, characterized in that: In the verification mode of the output high-impedance current function, the output enable control pin is set to a high level.

10. A shift memory parallel test system, characterized in that: include: A timing adjustment module, used for receiving a control signal from the tester, wherein the control signal is used for adjusting the internal timing of the shift memory so that the shift memory enters a verification mode of a storage function, a shift function, an output end driving voltage function, and an output end high impedance current function correspondingly; A storage function verification module, used for, in a verification mode of the storage function, the shift memory receives first test data from the test machine and generates first output data, and when the potential of the first output data is consistent with the potential of the first test data, determining that the storage function is normal; A shift function verification module, used for, in a verification mode of the shift function, the shift memory receives second test data from the test machine and generates second output data, and when the second output data is consistent with a preset output potential, determining that the shift function is normal; An output end driving voltage function verification module, used for, in a verification mode of the output end driving voltage function, the shift memory receives a first test signal from the test machine and obtains an output port driving voltage of the shift memory, and when the output port driving voltage is within a predetermined voltage range, determines that the output end driving voltage function is normal; The output end high-impedance current function verification module is used to, in the verification mode of the output end high-impedance current function, enable the shift memory to receive a second test signal from a test machine and obtain the output port current of the shift memory. When the output port current is within a predetermined current range, it is determined that the output end high-impedance current function is normal.

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