Semiconductor structure and method for forming the same

Abstract

The present disclosure provides a semiconductor structure and a method for forming the same, relating to the field of semiconductor technology. The formation method comprises: providing a substrate, the substrate comprising an array region and a mark region; forming a stacked structure on the surface of the substrate, the stacked structure comprising a first barrier layer and a first semiconductor layer in a direction away from the substrate; forming a second barrier layer on the surface of the stacked structure, the second barrier layer comprising nitrogen and silicon elements; etching the stacked structure to simultaneously form a contact hole in the array region and an alignment mark in the mark region, wherein the contact hole passes through the second barrier layer and the stacked structure and extends into the interior of the substrate to expose the active area in the substrate. The present disclosure forms a second barrier layer in the alignment mark, and the second barrier layer comprises nitrogen and silicon elements. Through the anti-corrosion effect of the second barrier layer, when the structure is wet-etched, the film layer in the alignment mark is prevented from being damaged, thereby affecting the alignment accuracy of the alignment mark.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] In semiconductor manufacturing, overlay error (OVL) refers to the misalignment or misregistration between different layers during the multi-layer semiconductor manufacturing process. Measuring and controlling OVL is crucial to ensuring the accuracy and reliability of multi-layer semiconductor manufacturing.

[0003] Currently, in semiconductor manufacturing processes, to reduce misalignment between different layers, alignment marks are formed in the marking area simultaneously with device formation in the active area. By comparing the alignment marks, alignment between the different layers is achieved. However, due to process limitations, during the formation of different film layers, the film layer within the alignment marks formed in the marking area can be lost, reducing the alignment accuracy of the alignment marks and, in turn, the device yield.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0005] In view of this, a semiconductor structure and a method for forming the same are provided. The method for forming the semiconductor structure forms an alignment mark having a second barrier layer in the mark area. The second barrier layer has high corrosion resistance and can ensure the integrity of the film layer of the alignment mark, thereby ensuring the alignment of the alignment mark.

[0006] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by practice of the present disclosure.

[0007] According to one aspect of the present disclosure, a method for forming a semiconductor structure is provided, the method comprising:

[0008] Providing a substrate, the substrate comprising an array region and a marking region;

[0009] forming a stacked structure on a surface of the substrate, wherein the stacked structure includes a first barrier layer and a first semiconductor layer in a direction away from the substrate;

[0010] forming a second barrier layer on the surface of the stacked structure, wherein the second barrier layer includes nitrogen and silicon;

[0011] The stacked structure is etched to simultaneously form a contact hole in the array region and an alignment mark in the mark region, wherein the contact hole penetrates the second barrier layer and the stacked structure and extends into the interior of the substrate to expose the active area in the substrate.

[0012] In some embodiments of the present disclosure, based on the aforementioned solution, the bottoms of the contact hole and the alignment mark have a damaged layer, and the damaged layer is removed. The method includes:

[0013] Conformally forming a protective layer on the surface of the second barrier layer, in the contact hole, and in the alignment mark;

[0014] removing a portion of the protective layer to expose the surfaces of the damaged layer and the second barrier layer;

[0015] The damaged layer is removed by wet etching.

[0016] In some embodiments of the present disclosure, based on the above solution, the method further includes:

[0017] A second semiconductor layer is filled in the contact hole and the alignment mark.

[0018] In some embodiments of the present disclosure, based on the above solution, the method further includes:

[0019] removing the remaining portion of the protective layer;

[0020] A second semiconductor layer is filled in the contact hole and the alignment mark.

[0021] In some embodiments of the present disclosure, based on the above solution, the active region is formed in the substrate, and the method includes:

[0022] A plurality of isolation structures distributed at intervals are formed on the substrate, wherein the orthographic projections of the plurality of isolation structures on the substrate are located in the array region to form the active region.

[0023] According to another aspect of the present disclosure, a semiconductor structure is provided, comprising:

[0024] a substrate comprising an array region and a marking region;

[0025] a stacked structure formed on the substrate, the stacked structure comprising a first barrier layer and a first semiconductor layer in a direction away from the substrate;

[0026] a second barrier layer formed on the surface of the stacked structure, wherein the second barrier layer comprises nitrogen and silicon;

[0027] A contact hole and an alignment mark, wherein the contact hole penetrates the second barrier layer and the stacked structure and extends into the interior of the substrate to expose the active area in the substrate, wherein the orthographic projection of the contact hole on the substrate is located in the array area, and the orthographic projection of the alignment mark on the substrate is located in the mark area.

[0028] In some embodiments of the present disclosure, based on the aforementioned solution, the weight content of the nitrogen element in the second barrier layer is greater than or equal to 30%.

[0029] In some embodiments of the present disclosure, based on the aforementioned solution, the second barrier layer includes silicon oxynitride or silicon nitride.

[0030] In some embodiments of the present disclosure, based on the aforementioned solution, the semiconductor structure further includes a second semiconductor layer, and the second semiconductor layer is filled in the contact hole and the alignment mark.

[0031] In some embodiments of the present disclosure, based on the aforementioned solution, the semiconductor structure further includes a plurality of isolation structures, and the plurality of isolation structures are spaced apart and distributed on the substrate to form an active region in the substrate.

[0032] The present disclosure provides a method for forming a semiconductor structure, which forms a stacked structure on a substrate, forms a second barrier layer on the stacked structure, and etches the stacked structure to simultaneously form contact holes in the array area of ​​the substrate and alignment marks in the mark area, wherein the second barrier layer includes nitrogen and silicon elements. By improving the corrosion resistance of the second barrier layer, the integrity of the alignment mark can be ensured during a wet etching process, avoiding the problem of decreased alignment accuracy caused by damage to the film layer within the alignment mark, thereby improving the yield of the device and reducing manufacturing costs. In addition, this formation method reduces the contact resistance between the contact holes and the active area within the structure, thereby improving the functionality of the device.

[0033] The present disclosure provides a semiconductor structure comprising a substrate, a stacked structure, and a second barrier layer. The second barrier layer is formed on the surface of the stacked structure, and the second barrier layer comprises nitrogen and silicon elements. By arranging the second barrier layer within the semiconductor structure, the second barrier layer has high corrosion resistance, and during the semiconductor etching process, damage to the alignment mark within the mark area can be avoided. The structure is simple and has high alignment accuracy, thereby ensuring the alignment of the alignment mark and having a low manufacturing cost for the device. In addition, the contact resistance between the contact hole and the active area within the structure is small, and the functionality of the device is good.

[0034] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0036] Figure 1 The present invention is a flowchart of a method for forming a semiconductor structure according to an exemplary embodiment of the present disclosure.

[0037] Figure 2 Schematic diagram of a substrate and a stacked structure in an exemplary embodiment of the present disclosure.

[0038] Figure 3 Schematic diagram of the structure of a second barrier layer in an exemplary embodiment of the present disclosure.

[0039] Figure 4 Schematic diagram of the structure of a contact hole and an alignment mark in an exemplary embodiment of the present disclosure.

[0040] Figure 5 Schematic diagram of the structure of a protective layer in an exemplary embodiment of the present disclosure.

[0041] Figure 6 Schematic diagram of the structure of a damaged layer in an exemplary embodiment of the present disclosure.

[0042] Figure 7 Schematic diagram of a semiconductor structure after removing a damaged layer in an exemplary embodiment of the present disclosure.

[0043] Figure 8 The figure is a flow chart of removing a damaged layer in an exemplary embodiment of the present disclosure.

[0044] The description of the accompanying drawings is as follows:

[0045] 100, substrate; 200, stacked structure; 210, first barrier layer; 220, first semiconductor layer; 300, second barrier layer; 400, contact hole; 500, alignment mark; 610, protective layer; 620, barrier layer; 700, damage layer; A, array area; M, mark area; AA, active area. DETAILED DESCRIPTION

[0046] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0047] Although relative terms such as "upper" and "lower" are used in this specification to describe the relationship of one illustrated component to another, these terms are used herein for convenience only, such as in accordance with the orientation of the illustrations in the accompanying drawings. It will be understood that if the illustrated device were flipped upside down, the component described as "upper" would become the component "lower." When a structure is referred to as "on" another structure, this may mean that the structure is integrally formed with the other structure, that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via the other structure.

[0048] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0049] In semiconductor devices, bit lines (BLs) are the primary circuit lines used to store and read data. In memory devices (such as dynamic random access memory (DRAM) and static random access memory (SRAM)) and logic circuits (such as flash memory), bit line contacts (BLCs) are holes that connect the bit lines to underlying electronic devices or circuit elements. Through the bit line contacts, current can pass from the bit lines through the underlying layers to the desired electronic devices or circuit elements.

[0050] In related art, the process for forming a bitline contact hole includes: forming a stacked film layer on a substrate; forming a barrier layer on the stacked film layer; and etching the stacked film layer to form the bitline contact hole in the active area AA of the substrate. However, during the formation of the bitline contact hole, the substrate is exposed at the bottom of the bitline contact hole. Due to oxidation during the process, an oxide layer or damage layer is formed on the exposed substrate. When the bitline is subsequently formed, this oxide layer or damage layer increases the contact resistance between the bitline and the active area AA, thereby affecting the function of the entire device. To remove this oxide layer or damage layer, methods such as wet etching are typically used. However, the chemicals used in wet etching can damage the alignment marks on the mark area M, affecting the interlayer alignment accuracy in subsequent device processing.

[0051] Based on this, the present disclosure provides a method for forming a semiconductor structure, such as Figure 1 As shown, the forming method includes: steps S100 to S400.

[0052] Wherein, step S100: providing a substrate 100, the substrate 100 including an array area A and a marking area M;

[0053] Step S200: forming a stacked structure 200 on the surface of the substrate 100, wherein the stacked structure 200 includes a first barrier layer 210 and a first semiconductor layer 220 in a direction away from the substrate 100;

[0054] Step S300: forming a second barrier layer 300 on the surface of the stacked structure 200, wherein the second barrier layer 300 includes nitrogen and silicon elements;

[0055] Step S400: Etching the stacked structure 200 to simultaneously form a contact hole 400 in the array area A and an alignment mark 500 in the mark area M, wherein the contact hole 400 penetrates the second barrier layer 300 and the stacked structure 200 and extends into the interior of the substrate 100 to expose the active area AA in the substrate 100.

[0056] The present disclosure provides a method for forming a semiconductor structure. This method comprises forming a stacked structure 200 on a substrate 100, forming a second barrier layer 300 on the stacked structure 200, and etching the stacked structure 200 to simultaneously form contact holes 400 in the array region A of the substrate 100 and alignment marks 500 in the mark region M. The second barrier layer 300 comprises nitrogen and silicon. By providing the second barrier layer 300 within the structure and improving the corrosion resistance of the second barrier layer 300, the integrity of the alignment marks 500 can be maintained during wet etching processes, preventing damage to the film within the alignment marks 500 that would otherwise reduce alignment accuracy. This improves device yield and reduces manufacturing costs. Furthermore, this formation method reduces the contact resistance between the contact holes 400 and the active area AA within the structure, thereby enhancing device functionality.

[0057] The following is a detailed description of the various steps of the method for forming a semiconductor structure provided by the embodiment of the present disclosure with reference to the accompanying drawings:

[0058] In the embodiments provided in the present disclosure, Figure 2 As shown, in step S100 , a substrate 100 is provided, and the substrate 100 includes an array region A and a mark region M.

[0059] The substrate 100 may be a semiconductor substrate, for example, a silicon (Si) substrate, a germanium (Ge) substrate, a silicon-germanium (GeSi) substrate, SOI (Silicon On Insulator) or GOI (Germanium On Insulator). In some embodiments, the semiconductor substrate may also be a substrate comprising other elemental semiconductors or compound semiconductors, for example, silicon carbide (SiC), indium phosphide (InP) or gallium arsenide (GaAs), cadmium telluride (CdTe), indium selenide (InSe), gallium nitride (GaN), indium gallium phosphide (InGaAs), etc. The cross-section of the substrate 100 provided in the present disclosure may be rectangular, square, circular or other shapes. The shape of the substrate 100 may be selected according to the actual design requirements of the device, and is not specifically limited in the present disclosure.

[0060] Substrate 100 may include an array region A and a marking region M. The array region A on substrate 100 is the primary portion of a semiconductor device used to implement specific functions. It may consist of transistors, capacitors, resistors, and other electronic components, and is used to perform tasks such as computing, storing data, or processing signals. The structure and function of the array region A depend on the chip's design objectives and may include a processor core, memory unit, sensor interface, and so on.

[0061] The marking area M on the substrate 100 may include a mark for identifying semiconductor devices or an area providing an alignment mark 500 for the process. In the specific embodiment provided by the present disclosure, the marking area M may refer to a dicing street, wherein the dicing street is generally located at the edge of the wafer and forms a long and narrow channel along the surface of the wafer. When the semiconductor wafer completes various process steps, it will be cut into multiple independent chips. The function of the dicing street is to separate the wafer into individual chips by cutting it.

[0062] The substrate 100 also includes an active area AA. Forming the active area AA in the substrate 100 includes forming a plurality of isolation structures spaced apart on the substrate 100, wherein the orthographic projections of the plurality of isolation structures on the substrate 100 are located in the array area A, thereby forming the active area AA. The isolation structures may be shallow trench isolation (STI) structures. The shallow trench isolation structures are formed by etching trenches on the substrate 100, for example, by chemical etching or physical etching to form trenches on the surface of the substrate 100. After the trenches are etched, the substrate 100 is cleaned and planarized to remove residual impurities and surface irregularities. The trenches are filled with an insulating material, for example, silicon oxide (SiO2) or silicon nitride (SiN), to provide insulation isolation between the trenches. After filling with the insulating material, the trenches are planarized and polished to make the trench surfaces flush with the surface of the substrate 100. Of course, the above steps are merely exemplary methods for forming an isolation structure, and variations, combinations, and corresponding replacements of the above steps are all within the scope of protection of the present disclosure.

[0063] In the embodiments provided in the present disclosure, Figure 2 As shown, in step S200 , a stacked structure 200 is formed on the surface of the substrate 100 . The stacked structure 200 includes a first barrier layer 210 and a first semiconductor layer 220 in a direction away from the substrate 100 .

[0064] A stacked structure 200 is formed on the surface of the substrate 100. The stacked structure 200 may include a first barrier layer 210 and a first semiconductor layer 220 disposed in a direction away from the substrate 100. The first barrier layer 210 may be a film layer made of a material such as silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbide (SiC), or silicon oxycarbide (SiOC). Of course, the first barrier layer 210 may also be made of other materials and may have functions such as an insulating layer and a protective layer, which is not specifically limited in this disclosure. The first barrier layer 210 may be formed by a process method such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).

[0065] Among them, the first semiconductor layer 220 can be a polysilicon (Poly) layer, or other semiconductor film layer. The first semiconductor layer 220 can be selected according to the actual design requirements of the device, and this disclosure does not specifically limit it. The first semiconductor layer 220 can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), low pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD).

[0066] In some embodiments, an oxide layer, such as a silicon oxide (SiO2) layer, may be further included between the stacked structure 200 and the substrate 100, to isolate the substrate 100 from the stacked structure 200. The oxide layer may be formed by direct deposition on the surface of the substrate 100, or by forming the oxide layer and the isolation structure simultaneously when the isolation structure is formed on the substrate 100. In addition, in the present disclosure, in addition to the oxide layer, other film layers for forming a semiconductor structure may also be included between the stacked structure 200 and the substrate 100, which will not be described in detail here.

[0067] In some embodiments, the stacked structure 200 may include a single first barrier layer 210 and a single first semiconductor layer 220, or may include multiple first barrier layers 210 and multiple first semiconductor layers 220. The number of first barrier layers 210 and first semiconductor layers 220 may be selected based on the actual structure of the device and is not specifically limited in this disclosure. In the semiconductor structure provided in this disclosure, the first barrier layer 210 and the first semiconductor layer 220 are each described as a single layer.

[0068] In the embodiments provided in the present disclosure, Figure 3 As shown, in step S300 , a second barrier layer 300 is formed on the surface of the stacked structure 200 , and the second barrier layer 300 includes nitrogen and silicon elements.

[0069] After the first semiconductor layer 220 is formed in the stacked structure 200, a second barrier layer 300 can be formed on the stacked structure 200 to protect the stacked structure 200 and the structures within the substrate 100. The second barrier layer 300 covers the surface of the first semiconductor layer 220, and the orthographic projection of the second barrier layer 300 on the substrate 100 is located in both the array area A and the mark area M.

[0070] To enhance the corrosion resistance of the second barrier layer 300 and reduce damage to the second barrier layer 300 during subsequent processing, the second barrier layer 300 may include nitrogen and silicon. The weight content of nitrogen in the second barrier layer 300 is greater than or equal to 30%. For example, the weight content of nitrogen in the second barrier layer 300 may be 30%, 40%, 50%, 60%, 70%, 80%, 90%, or more. The greater the proportion of nitrogen in the second barrier layer 300, the better the corrosion resistance of the second barrier layer 300. However, it should be noted that the second barrier layer 300 also needs to have other functions. Therefore, the nitrogen content in the second barrier layer 300 needs to take into account various factors, such as insulation, hardness, and metal diffusion resistance. In other words, the specific nitrogen content in the second barrier layer 300 can be adjusted according to the specific function and structure of the second barrier layer 300, and is not specifically limited in this disclosure.

[0071] The second barrier layer 300 also includes silicon and other elements, such as oxygen. In some embodiments, the second barrier layer 300 may include silicon oxynitride (SiON) or silicon nitride (SiN). For example, when the second barrier layer 300 is a film layer formed of silicon oxynitride (SiON), the nitrogen content of the silicon oxynitride (SiON) film layer must be greater than or equal to 30% by weight; or when the second barrier layer 300 is a film layer formed of silicon nitride (SiN), the nitrogen content of the silicon nitride (SiN) film layer must be greater than or equal to 30% by weight.

[0072] It should be noted that the weight content of nitrogen in the second barrier layer 300 given in the above embodiment is greater than or equal to 30%. However, in some embodiments, when the weight content cannot be used to calibrate the nitrogen content in the second barrier layer 300, other content indicators such as mass percentage, volume percentage or molar percentage can be used to calibrate the nitrogen content in the second barrier layer 300. In other words, the above weight content can be converted into other calibration methods through adaptive changes to calibrate the nitrogen content, all of which are within the scope of protection of the present disclosure.

[0073] The second barrier layer 300 can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD). In the present disclosure, atomic layer deposition (ALD) can be used, for example, plasma-assisted atomic layer deposition (Plasma ALD) can be used to form the second barrier layer 300, because the stress of the nitrogen-containing film layer is relatively large. This can reduce the stress of the second barrier layer 300.

[0074] In some embodiments, the second barrier layer 300 can be formed on the stacked structure 200 using a plasma-assisted atomic layer deposition (Plasma ALD) process at a temperature of 600° C. to 700° C. For example, the temperature for forming the second barrier layer 300 can be 600° C., 610° C., 620° C., 630° C., 640° C., 650° C., 660° C., 670° C., 6800° C., 690° C., or 700° C. The specific temperature can be adjusted based on the manufacturing process requirements of the second barrier layer 300. The thickness of the second barrier layer 300 can be 20 nm to 40 nm, for example, 20 nm, 25 nm, 30 nm, 35 nm, or 40 nm, and the thickness can be selected based on actual needs.

[0075] The second barrier layer 300 provided in the above embodiment of the present disclosure has strong corrosion resistance and conformality. In subsequent process steps, for example, when using a wet etching process to remove the film layer, the second barrier layer 300 has good corrosion resistance and good resistance to acids used in the wet etching process (such as hydrofluoric acid). Therefore, the second barrier layer 300 will not be damaged, thereby maintaining the integrity of the film layer.

[0076] In the embodiments provided in the present disclosure, Figure 4 As shown, in step S400, the stacked structure 200 is etched to simultaneously form a contact hole 400 in the array area A and an alignment mark 500 in the mark area M, wherein the contact hole 400 penetrates the second barrier layer 300 and the stacked structure 200 and extends into the interior of the substrate 100 to expose the active area AA in the substrate 100.

[0077] After forming the second barrier layer 300, the second barrier layer 300 and the stacked structure 200 are etched simultaneously to form contact holes 400 in the array region A and alignment marks 500 in the mark region M. Figures 4 to 7 As shown, the contact hole 400 penetrates the second barrier layer 300 and the stacked structure 200 and extends into the interior of the substrate 100 to expose the active area AA in the substrate 100. After the contact hole 400 and the alignment mark 500 are formed, due to process limitations, a damaged layer 700 is formed at the bottom of the contact hole 400 and the bottom of the alignment mark 500. For example, this damaged layer 700 can be an oxide layer formed by oxidation of the exposed substrate 100, or it can be a damaged layer 700 formed during a plasma process. This damaged layer 700 is located at the bottom of the contact hole 400 and covers the surface of the substrate 100. During the subsequent fabrication of the bitline structure, this damaged layer 700 can increase the contact resistance between the bitline and the active area AA, affecting device performance. Therefore, this damaged layer 700 needs to be removed.

[0078] In some embodiments, as Figure 8 As shown, the method for removing the damaged layer 700 includes steps S501 to S503.

[0079] Wherein, step S501: forming a protective layer 610 conformally on the surface of the second barrier layer 300, in the contact hole 400 and in the alignment mark 500;

[0080] Step S502: removing a portion of the protective layer 610 to expose the surfaces of the damaged layer 700 and the second barrier layer 300;

[0081] Step S503: removing the damaged layer 700 by wet etching.

[0082] Among them, Figure 5As shown, a protective layer 610 is conformally formed on the surface of the second barrier layer 300, in the contact hole 400 and in the alignment mark 500, as shown in FIG. Figure 6 As shown, a portion of the protective layer 610 is removed to expose the surface of the damaged layer 700 and the second barrier layer 300. The protective layer 610 may be a polysilicon (Poly) layer, and is formed on the surface of the second barrier layer 300, the bottom and sidewalls of the contact hole 400, and the bottom and sidewalls of the alignment mark 500. The protective layer 610 may be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), low pressure chemical vapor deposition (LPCVD), or atomic layer deposition (ALD).

[0083] The second barrier layer 300 located on the surface of the second barrier layer 300 and the second barrier layer 300 located at the bottom of the contact hole 400 and the bottom of the alignment mark 500 are removed by dry etching or wet etching, and the second barrier layer 300 located on the sidewalls of the contact hole 400 and the sidewalls of the alignment mark 500 is retained, so that the remaining second barrier layer 300 can protect the sidewalls of the contact hole 400 and the sidewalls of the alignment mark 500, and expose the damaged layer 700 located at the bottom of the contact hole 400 and the bottom of the alignment mark 500.

[0084] like Figure 7 As shown, wet etching is used to remove the damaged layer 700. Wet etching is a common surface processing technique used to selectively remove or change the shape of specific areas of semiconductor materials. Wet etching typically uses a chemical solution (such as an acidic or alkaline solution) to etch the semiconductor material. For example, a hydrofluoric acid (HF) solution can be used to etch the damaged layer 700 to remove the damaged layer 700 and expose the active area AA of the substrate 100.

[0085] After removing the damaged layer 700, the method for forming the semiconductor structure also includes a method for forming a second semiconductor layer. In the first embodiment, the method for forming the second semiconductor layer includes: after removing the damaged layer 700, filling the contact hole 400 and the alignment mark 500 with the second semiconductor layer to form the final semiconductor structure. Alternatively, in the second embodiment, the method for forming the second semiconductor layer may include: removing the remaining portion of the protective layer 610; filling the contact hole 400 and the alignment mark 500 with the second semiconductor layer to form the final semiconductor structure. Both of the above-mentioned formation methods are applicable to the present disclosure, but in order to avoid the formation of voids in the second semiconductor layer during the deposition process and to improve the formation quality of the second semiconductor layer, the second semiconductor layer is usually formed using the formation method in the first example.

[0086] The second semiconductor layer and the protective layer 610 can be made of the same material, for example, a polysilicon (Poly) layer. The second semiconductor layer and the protective layer 610 can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), low pressure chemical vapor deposition (LPCVD), or atomic layer deposition (ALD).

[0087] It should be noted that the methods and structures provided in the above embodiments of the present disclosure also include other methods and structures for forming bit line structures, which may be commonly used methods and structures in the art and will not be described in detail here, but it should be understood that other conventional formation steps and structures of the bit line structure are within the scope of protection of the present disclosure.

[0088] The present disclosure provides a method for forming a semiconductor structure. This method comprises forming a stacked structure 200 on a substrate 100, forming a second barrier layer 300 on the stacked structure 200, and etching the stacked structure 200 to simultaneously form contact holes 400 in the array region A of the substrate 100 and alignment marks 500 in the mark region M. The second barrier layer 300 comprises nitrogen and silicon. By providing the second barrier layer 300 within the structure and improving the corrosion resistance of the second barrier layer 300, the integrity of the alignment marks 500 can be maintained during wet etching processes, preventing damage to the film within the alignment marks 500 that would otherwise reduce alignment accuracy. This improves device yield and reduces manufacturing costs. Furthermore, this formation method reduces the contact resistance between the contact holes 400 and the active area AA within the structure, thereby enhancing device functionality.

[0089] It should be noted that although the steps of the method for forming a semiconductor structure in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all steps must be performed to achieve the desired results. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps.

[0090] The present disclosure provides a semiconductor structure, such as Figure 7 As shown, the semiconductor structure includes a substrate 100 , a stacked structure 200 , a second barrier layer 300 , a contact hole 400 and an alignment mark 500 .

[0091] In which, the substrate 100 includes an array area A and a marking area M; a stacked structure 200 is formed on the substrate 100, and the stacked structure 200 includes a first barrier layer 210 and a first semiconductor layer 220 in a direction away from the substrate 100; a second barrier layer 300 is formed on the surface of the stacked structure 200, and the second barrier layer 300 includes nitrogen and silicon elements; a contact hole 400 passes through the second barrier layer 300 and the stacked structure 200 and extends into the interior of the substrate 100 to expose the active area AA in the substrate 100, wherein the orthographic projection of the contact hole 400 on the substrate 100 is located in the array area A, and the orthographic projection of the alignment mark 500 on the substrate 100 is located in the marking area M.

[0092] The present disclosure provides a semiconductor structure, which includes a substrate 100, a stacked structure 200 and a second barrier layer 300. The second barrier layer 300 is formed on the surface of the stacked structure 200, and the second barrier layer 300 includes nitrogen and silicon elements. By arranging the second barrier layer 300 in the semiconductor structure, the second barrier layer 300 has high corrosion resistance. During the semiconductor etching process, the alignment mark 500 in the mark area M can be prevented from being damaged. The structure is simple and has high alignment accuracy, which ensures the alignment of the alignment mark 500 and the manufacturing cost of the device is low. In addition, the contact resistance between the contact hole 400 and the active area AA in the structure is small, and the functionality of the device is good.

[0093] The following describes in detail the various parts of the semiconductor structure provided by the embodiment of the present disclosure with reference to the accompanying drawings:

[0094] Substrate 100 includes an array region A and a marking region M. A stacked structure 200 is formed on substrate 100. Stacked structure 200 includes, in a direction away from substrate 100, a first barrier layer 210 and a first semiconductor layer 220. In the present disclosure, other film layers for forming semiconductor structures may be included between substrate 100 and stacked structure 200, but these layers are not listed here. The type of substrate 100 and the specific structure of stacked structure 200 are as described in the above embodiment and will not be further described here.

[0095] The substrate 100 also includes multiple isolation structures, which are spaced apart and distributed on the substrate 100 to form an active area AA on the substrate 100. In a semiconductor device, the active area AA can be a region that carries current and performs functions, and is generally used to implement functions such as injection, transmission, and amplification of electrons or holes. In the embodiments provided in the present disclosure, the active area AA in the substrate 100 is isolated and formed by multiple isolation structures. For example, the isolation structures can be shallow trench isolation structures.

[0096] The second barrier layer 300 is formed on the surface of the stacked structure 200. The second barrier layer 300 includes nitrogen and silicon. To improve the corrosion resistance of the second barrier layer 300 and reduce damage to the second barrier layer 300 in subsequent processes, the second barrier layer 300 may include nitrogen and silicon. The weight content of nitrogen in the second barrier layer 300 is greater than or equal to 30%. For example, the weight content of nitrogen in the second barrier layer 300 may be 30%, 40%, 50%, 60%, 70%, 80%, 90%, or more. The greater the proportion of nitrogen in the second barrier layer 300, the better the corrosion resistance of the second barrier layer 300. However, it should be noted that the second barrier layer 300 also needs to have other functions. Therefore, the content of nitrogen in the second barrier layer 300 needs to take into account multiple factors, such as insulation, hardness, and metal diffusion resistance. That is, the specific content of nitrogen in the second barrier layer 300 can be adaptively adjusted according to the specific function and structure of the second barrier layer 300, and this disclosure does not make any specific limitations.

[0097] The second barrier layer 300 also includes silicon and other elements, such as oxygen. In some embodiments, the second barrier layer 300 may include silicon oxynitride (SiON) or silicon nitride (SiN). For example, when the second barrier layer 300 is a film layer formed of silicon oxynitride (SiON), the nitrogen content of the silicon oxynitride (SiON) film layer must be greater than or equal to 30% by weight; or when the second barrier layer 300 is a film layer formed of silicon nitride (SiN), the nitrogen content of the silicon nitride (SiN) film layer must be greater than or equal to 30% by weight.

[0098] It should be noted that the weight content of nitrogen in the second barrier layer 300 given in the above embodiment is greater than or equal to 30%. However, in some embodiments, when the weight content cannot be used to calibrate the nitrogen content in the second barrier layer 300, other content indicators such as mass percentage, volume percentage or molar percentage can be used to calibrate the nitrogen content in the second barrier layer 300. In other words, the above weight content can be converted into other calibration methods through adaptive changes to calibrate the nitrogen content, all of which are within the scope of protection of the present disclosure.

[0099] The method for forming the second barrier layer 300 is the same as the method shown in the above embodiment, and will not be repeated here.

[0100] The contact hole 400 penetrates the second barrier layer 300 and the stacked structure 200 and extends into the interior of the substrate 100 to expose the active area AA in the substrate 100. The orthographic projection of the contact hole 400 on the substrate 100 is located in the array area A, and the orthographic projection of the alignment mark 500 on the substrate 100 is located in the mark area M. The semiconductor structure further includes a second semiconductor layer, which may be a polysilicon (Poly) layer, for example. The second semiconductor layer fills the contact hole 400 and the alignment mark 500 to form the final semiconductor structure.

[0101] The specific formation methods of the various film layers and structures of the semiconductor structure provided by the present disclosure are described in the above-mentioned formation method section and will not be repeated here.

[0102] The present disclosure provides a semiconductor structure, which includes a substrate 100, a stacked structure 200 and a second barrier layer 300. The second barrier layer 300 is formed on the surface of the stacked structure 200, and the second barrier layer 300 includes nitrogen and silicon elements. By arranging the second barrier layer 300 in the semiconductor structure, the second barrier layer 300 has high corrosion resistance. During the semiconductor etching process, the alignment mark 500 in the mark area M can be prevented from being damaged. The structure is simple and has high alignment accuracy, which ensures the alignment of the alignment mark 500 and the manufacturing cost of the device is low. In addition, the contact resistance between the contact hole 400 and the active area AA in the structure is small, and the functionality of the device is good.

[0103] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising an array region and a marking region; forming a stacked structure on a surface of the substrate, wherein the stacked structure includes a first barrier layer and a first semiconductor layer in a direction away from the substrate; forming a second barrier layer on the surface of the stacked structure, wherein the second barrier layer includes nitrogen and silicon; Etching the stacked structure to simultaneously form a contact hole in the array region and an alignment mark in the mark region, wherein the contact hole penetrates the second barrier layer and the stacked structure and extends into the interior of the substrate to expose the active area in the substrate; The contact hole and the alignment mark have a damaged layer at their bottoms, and the damaged layer is removed. The method includes: Conformally forming a protective layer on the surface of the second barrier layer, in the contact hole, and in the alignment mark; removing a portion of the protective layer to expose the surfaces of the damaged layer and the second barrier layer; The damaged layer is removed by wet etching.

2. The method for forming a semiconductor structure according to claim 1, wherein: The method further comprises: A second semiconductor layer is filled in the contact hole and the alignment mark.

3. The method for forming a semiconductor structure according to claim 1, wherein: The method further comprises: removing the remaining portion of the protective layer; A second semiconductor layer is filled in the contact hole and the alignment mark.

4. The method for forming a semiconductor structure according to claim 1, wherein: The active region is formed in the substrate, the method comprising: A plurality of isolation structures distributed at intervals are formed on the substrate, wherein the orthographic projections of the plurality of isolation structures on the substrate are located in the array region to form the active region.

5. A semiconductor structure, comprising the method for forming a semiconductor structure according to any one of claims 1 to 4, wherein: include: a substrate comprising an array region and a marking region; a stacked structure formed on the substrate, the stacked structure comprising a first barrier layer and a first semiconductor layer in a direction away from the substrate; a second barrier layer formed on the surface of the stacked structure, wherein the second barrier layer comprises nitrogen and silicon; A contact hole and an alignment mark, wherein the contact hole penetrates the second barrier layer and the stacked structure and extends into the interior of the substrate to expose the active area in the substrate, wherein the orthographic projection of the contact hole on the substrate is located in the array area, and the orthographic projection of the alignment mark on the substrate is located in the mark area.

6. The semiconductor structure according to claim 5, wherein: The weight content of the nitrogen element in the second barrier layer is greater than or equal to 30%.

7. The semiconductor structure according to claim 5, wherein: The second barrier layer includes silicon oxynitride or silicon nitride.

8. The semiconductor structure according to claim 5, wherein: The semiconductor structure further includes a second semiconductor layer, wherein the second semiconductor layer is filled in the contact hole and the alignment mark.

9. The semiconductor structure according to claim 5, wherein: The semiconductor structure further includes a plurality of isolation structures, which are spaced apart and distributed on the substrate to form an active region in the substrate.

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