Semiconductor structure and method for manufacturing the same

Abstract

The disclosed embodiments relate to the field of semiconductor technology and provide a semiconductor structure and a method for manufacturing the same. The method comprises: providing a base including a substrate, a diffusion barrier film, and a conductive film; forming a mask layer having multiple openings on a side of the conductive film away from the substrate; patterning the base using the mask layer as a mask, wherein the remaining diffusion barrier film includes multiple mutually spaced first diffusion barrier layers, and the remaining conductive film includes multiple mutually spaced conductive layers, wherein a first diffusion barrier layer and a conductive layer located on the diffusion barrier layer form a conductive pillar, and grooves are defined between adjacent conductive pillars; removing the mask layer, wherein residue is present in the grooves; nitriding the surface of the exposed conductive layer to form a nitride layer on the surface of the conductive layer; and cleaning the surface of the grooves to remove the residue, wherein the cleaning process etches the residue at a higher rate than the nitride layer. The disclosed embodiments at least improve the electrical performance of the conductive pillars.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] With the continuous development of semiconductor structure manufacturing technology, the size of the semiconductor structure is gradually reduced, so that the size of each functional structure implemented in the semiconductor structure is gradually reduced, and the spacing between the functional structures is gradually reduced.

[0003] However, in order to achieve the reduction in size of each functional structure, higher requirements are placed on the process of preparing it, making the dimensional accuracy of each functional structure more difficult to control. Moreover, as the spacing between each functional structure gradually decreases, the residues formed by various preparation processes in the reduced spacing are more difficult to remove, thereby making the performance of each functional structure unstable. Summary of the Invention

[0004] The embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, which are at least beneficial to improving the electrical performance of the conductive pillar.

[0005] According to some embodiments of the present disclosure, on one hand, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, wherein the semiconductor structure includes an array region and a peripheral region, and the manufacturing method includes: providing a substrate, wherein the substrate spans the array region and the transition region sequentially arranged along a first direction; the substrate includes: a substrate, wherein the substrate in the array region has a first contact hole extending from the top surface of the substrate to the interior of the substrate, and the substrate in the transition region has a second contact hole extending from the top surface of the substrate to the interior of the substrate, wherein the hole depth of the first contact hole is greater than the hole depth of the second contact hole; a diffusion barrier film, conformally covering the inner walls of the first contact hole and the second contact hole, and being located on the top surface of the substrate; a conductive film, filling the first contact hole and the second contact hole, and being located on the diffusion barrier film. A first top surface away from the top surface of the substrate; forming a mask layer with multiple openings on a side of the conductive film away from the substrate; patterning the base using the mask layer as a mask, the remaining diffusion barrier film includes multiple first diffusion barrier layers spaced apart from each other, the remaining conductive film includes multiple conductive layers spaced apart from each other, one of the first diffusion barrier layers and one of the conductive layers located on the first diffusion barrier layer constitute a conductive column, and there are grooves between adjacent conductive columns; removing the mask layer, and there are residues in the grooves; nitriding the surface of the exposed conductive layer to form a nitride layer on the surface of the conductive layer; cleaning the surface of the grooves to remove the residues, and the etching rate of the cleaning process on the residues is greater than the etching rate on the nitride layer.

[0006] In some embodiments, the residue includes at least one of the remaining mask layer, the remaining granular conductive layer, the remaining oxidized conductive layer, or the remaining nitrided conductive layer.

[0007] In some embodiments, the semiconductor structure further includes a peripheral region, the peripheral region being located on a side of the transition region away from the array region along the first direction, the substrate further spanning the peripheral region, the substrate in the peripheral region having a third contact hole extending from the top surface of the substrate into the substrate, the depth of the first contact hole being greater than the depth of the third contact hole, the diffusion barrier film further conformally covering the inner wall of the third contact hole, and the conductive film further filling the third contact hole; in the step of performing the patterning process on the substrate using the mask layer as a mask, a plurality of mutually spaced conductive pillars are also formed in the peripheral region; the step of performing the cleaning process on the surface of the groove further includes: performing the cleaning process on the surface of the groove in the peripheral region.

[0008] In some embodiments, the surface of the exposed conductive layer is subjected to the nitridation treatment, including: providing a first gas and performing plasma treatment on the first gas, and using the first gas after the plasma treatment to perform the nitridation treatment on the surface of the conductive layer; wherein the first gas includes dihydrogen nitride gas, and the gas flow range of the dihydrogen nitride gas is 100 sccm to 15000 sccm.

[0009] In some embodiments, after the substrate is patterned and before the exposed conductive layer is nitrided, the process further includes: oxidizing the first diffusion barrier layer so that at least a portion of the width of the first diffusion barrier layer along the first direction is transformed into a second diffusion barrier layer, and the second direction is perpendicular to the first direction; and performing a first cleaning treatment on the surface of the groove to remove part of the residue, wherein the etching rate of the residue by the first cleaning treatment is greater than the etching rate of the second diffusion barrier layer.

[0010] In some embodiments, the oxidation treatment of the first diffusion barrier layer includes: providing a second gas and performing plasma treatment on the second gas, and using the second gas after the plasma treatment to perform the oxidation treatment on the surface of the first diffusion barrier layer; wherein the second gas includes oxygen, and the gas flow range of the oxygen is 100 sccm to 15000 sccm.

[0011] In some embodiments, the step of providing the base includes: providing an initial substrate, the initial substrate spanning the array area, the transition area and the peripheral area arranged in sequence along a first direction; performing patterning on the initial substrate, and the remaining initial substrate is the substrate, so as to form the first contact hole in the substrate in the array area, the second contact hole in the substrate in the transition area, and the third contact hole in the substrate in the peripheral area, the third contact hole extending from the top surface of the substrate into the substrate, and the hole depth of the first contact hole, the hole depth of the second contact hole and the hole depth of the third contact hole decreasing in sequence; forming the diffusion barrier film, the diffusion barrier film conformally covering the inner walls of the first contact hole, the second contact hole and the third contact hole, and being located on the top surface of the substrate; forming the conductive film, the conductive film filling the first contact hole, the second contact hole and the third contact hole, and being located on the first top surface of the diffusion barrier film away from the top surface of the substrate.

[0012] In some embodiments, the step of performing the cleaning treatment on the surface of the groove includes: performing a first cleaning treatment and a second cleaning treatment on the surface of the groove in sequence, wherein the cleaning liquid used in the first cleaning treatment is different from the cleaning liquid used in the second cleaning treatment.

[0013] In some embodiments, after the substrate is patterned, the first diffusion barrier layer includes a first portion and a second portion, the first portion is located on the bottom surface of the conductive layer, and the second portion surrounds a portion of the side wall of the conductive layer; after the substrate is patterned, before the exposed conductive layer is nitrided, it also includes: oxidizing the first diffusion barrier layer so that at least a portion of the thickness of the second portion along a second direction is transformed into a second diffusion barrier layer, and the second direction is perpendicular to the first direction; performing a first cleaning treatment on the surface of the groove to remove part of the residue, and the etching rate of the residue by the first cleaning treatment is greater than the etching rate of the second diffusion barrier layer.

[0014] In some embodiments, after forming the nitride layer, performing the cleaning process on the surface of the groove includes: performing a second cleaning process on the surface of the groove to remove the residue, and the cleaning solution used in the first cleaning process is different from the cleaning solution used in the second cleaning process.

[0015] In some embodiments, the second contact hole has a depth ranging from 25 nm to 35 nm.

[0016] According to some embodiments of the present disclosure, another aspect of the present disclosure further provides a semiconductor structure, comprising: a substrate, the substrate spanning an array region and a transition region sequentially arranged along a first direction, the substrate in the array region having a first through hole extending from the top surface of the substrate into the substrate; a plurality of conductive pillars spaced apart from each other, each of the conductive pillars comprising a diffusion barrier layer and a conductive layer, the diffusion barrier layer conformally covering the inner wall of the first through hole and the surface of the substrate covering the transition region, the conductive layer being located on the surface of the diffusion barrier layer away from the substrate, and with the bottom surface of the first through hole as a reference surface, the second top surface of the conductive layer away from the substrate is higher than the bottom surface of the first through hole. The diffusion barrier layer is away from the third top surface of the substrate; wherein the diffusion barrier layer located in the array area is a first diffusion barrier layer, or the diffusion barrier layer located in the array area includes the first diffusion barrier layer and the second diffusion barrier layer that are in contact and connected along the second direction; the diffusion barrier layer located in the transition area is the first diffusion barrier layer or the second diffusion barrier layer, or the diffusion barrier layer located in the transition area includes the first diffusion barrier layer and the second diffusion barrier layer that are in contact and connected along the second direction; the first diffusion barrier layer after oxidation treatment is the second diffusion barrier layer, and the second direction is perpendicular to the first direction.

[0017] In some embodiments, the substrate in the transition zone has a second through hole extending from the top surface of the substrate into the substrate, and the hole depth of the first through hole is greater than the hole depth of the second through hole; the diffusion barrier layer covering the surface of the substrate in the transition zone includes: the diffusion barrier layer conformally covering the inner wall of the second through hole, and the conductive layer filling the first through hole and the second through hole.

[0018] In some embodiments, the substrate also spans a peripheral region, the peripheral region is located on a side of the transition region away from the array region along the first direction, the substrate in the peripheral region has a third through hole extending from the top surface of the substrate into the substrate, the diffusion barrier layer also conformally covers the inner wall of the third through hole, and the conductive layer is located in the remaining third through hole; wherein the depth of the first through hole is greater than the depth of the third through hole, or the substrate in the transition region has a second through hole, and the hole depth of the first through hole, the hole depth of the second through hole and the hole depth of the third through hole decrease successively.

[0019] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0020] On the one hand, the residue in the groove may cause a short circuit between adjacent conductive pillars spaced apart from each other, that is, the conductive pillars spaced apart from each other may be electrically connected through the residue in the groove, causing the two electrically connected conductive pillars to fail and unable to perform their respective functions. Therefore, cleaning the surface of the groove to remove the residue is beneficial to avoiding short circuits between adjacent conductive pillars, thereby improving the stability of each conductive pillar and improving the electrical performance of each conductive pillar. On the other hand, before the surface of the groove is cleaned, a nitride layer is formed on the surface of the conductive layer, and the etching rate of the cleaning treatment on the residue is greater than the etching rate of the nitride layer. Therefore, during the process of cleaning the surface of the groove to remove the residue, even if the spacing between adjacent conductive pillars is small, it is beneficial to ensure that the residue is removed while protecting the conductive layer through the nitride layer to avoid damage to the conductive layer caused by the cleaning treatment, thereby avoiding significant changes in the size of the conductive layer, improving the dimensional accuracy of the conductive pillars, and further improving the electrical performance of each conductive pillar. In this way, it is beneficial to improve the electrical performance of the semiconductor structure finally formed. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] Figures 1 to 11 A schematic cross-sectional view of each step in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure;

[0023] Figure 12 A schematic diagram of a local cross-sectional structure of a substrate in a semiconductor structure provided in another embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] As known from the background art, the electrical performance of semiconductor structures needs to be improved.

[0025] The present disclosure provides a semiconductor structure and a method for manufacturing the same. In the manufacturing method, on the one hand, residue in a groove may cause a short circuit between adjacent, spaced-apart conductive pillars. That is, the spaced-apart conductive pillars may be electrically connected through the residue in the groove, causing the two electrically connected conductive pillars to fail and be unable to perform their respective functions. Therefore, cleaning the surface of the groove to remove the residue is beneficial to avoiding short circuits between adjacent conductive pillars, thereby improving the stability of each conductive pillar and improving the electrical performance of each conductive pillar. On the other hand, before cleaning the surface of the groove, a nitride layer is formed on the surface of the conductive layer, and the etching rate of the residue during the cleaning process is greater than the etching rate of the nitride layer. Therefore, during the process of cleaning the surface of the groove to remove the residue, even if the spacing between adjacent conductive pillars is small, it is beneficial to ensure that the residue is removed while protecting the conductive layer from damage caused by the cleaning process, thereby avoiding significant changes in the size of the conductive layer, improving the dimensional accuracy of the conductive pillars, and further improving the electrical performance of each conductive pillar. In this way, the electrical performance of the semiconductor structure finally formed is improved.

[0026] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to help readers better understand the embodiments of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present disclosure can be implemented.

[0027] An embodiment of the present disclosure provides a method for manufacturing a semiconductor structure. The method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. Figures 1 to 11 Schematic diagram of the cross-sectional structure corresponding to each step in the method for manufacturing a semiconductor structure provided in one embodiment of the present disclosure. It should be noted that, in order to facilitate the description and clearly illustrate the steps of the method for manufacturing a semiconductor structure, Figures 1 to 11 Both are schematic diagrams of local cross-sectional structures of semiconductor structures.

[0028] refer to Figures 1 to 11 A method for manufacturing a semiconductor structure, wherein the semiconductor structure includes an array region 110 and a transition region 120, and the manufacturing method may include at least the following steps:

[0029] S101: Reference Figure 1 , providing a substrate 100, the substrate 100 spanning the array area 110 and the transition area 120 sequentially arranged along the first direction X. It should be noted that, Figure 1 1b is a schematic diagram of a partial cross-sectional structure of the substrate 130 in 1a.

[0030] refer to Figure 1 In Figure 1b, the base 100 may include: a substrate 130, the substrate 130 of the array area 110 has a first contact hole 131 extending from the substrate top surface 130a to the inside of the substrate 130, and the substrate 130 of the transition area 120 has a second contact hole 132 extending from the substrate top surface 130a to the inside of the substrate 130, and the hole depth of the first contact hole 131 is greater than the hole depth of the second contact hole 132.

[0031] In some embodiments, the first contact holes 131 in the array region 110 may be used to form capacitor contact windows later.

[0032] refer to Figure 1 In Figure 1a, the substrate 100 may further include: a diffusion barrier film 101, conformally covering the inner walls of the first contact hole 131 and the second contact hole 132, and located on the top surface of the substrate 130; a conductive film 102, filling the first contact hole 131 and the second contact hole 132, and located on a first top surface 101a of the diffusion barrier film 101 away from the top surface 130a of the substrate;

[0033] In some embodiments, the material of the diffusion barrier film 101 includes titanium nitride, and the material of the conductive film 102 includes tungsten. Detailed description will be given below using titanium nitride as the material of the diffusion barrier film 101 and tungsten as the material of the conductive film 102 as an example.

[0034] In some embodiments, reference Figure 2 The substrate 100 also spans the peripheral region 140. The peripheral region 140 is located on a side of the transition region 120 away from the array region 110 along the first direction X. The substrate 130 of the peripheral region 140 has a third contact hole 133 extending from the substrate top surface 130a into the substrate 130. The depth of the first contact hole 131 is greater than the depth of the third contact hole 133. The diffusion barrier film 101 also conformally covers the inner wall of the third contact hole 133, and the conductive film 102 also completely fills the third contact hole 133.

[0035] It should be noted that Figure 2 2b is a schematic diagram of a partial cross-sectional structure of the substrate 130 in 2a.

[0036] refer to Figure 3 , Figure 3Figure 3b is a schematic diagram of a partial cross-sectional structure of substrate 130 in Figure 3a. Substrate 130 may further include: an electrical contact layer 160 located in array region 110, a first dielectric layer 170 located in transition region 120, and a second dielectric layer 180 located in array region 110, transition region 120, and peripheral region 140. Electrical contact layer 160 and second dielectric layer 180 in array region 110 enclose a first contact hole 131, with electrical contact layer 160 forming the bottom surface of first contact hole 131 and second dielectric layer 180 in array region 110 forming the sidewalls of first contact hole 131. First dielectric layer 170 and second dielectric layer 180 in transition region 120 enclose a second contact hole 132, with first dielectric layer 170 forming the bottom surface of first contact hole 131 and second dielectric layer 180 in array region 110 forming the sidewalls of second contact hole 132. Second dielectric layer 180 in peripheral region 140 itself encloses a third contact hole 133.

[0037] In some embodiments, the material of the electrical contact layer 160 may be polysilicon, the material of the first dielectric layer 170 may be silicon oxide, and the material of the second dielectric layer 180 may be silicon nitride.

[0038] In some embodiments, the electrical contact layer 160 may serve as a capacitor contact plug, and the electrical contact layer 160 and a conductive structure subsequently formed in the first contact hole 131 may serve together as a capacitor contact window.

[0039] S102: Reference Figure 1 and Figure 2 , a mask layer 103 having a plurality of openings 113 is formed on a side of the conductive film 102 away from the substrate 130 .

[0040] It is understood that when the substrate 130 also spans the peripheral region 140, the mask layer 103 is also located on the side of the conductive film 102 in the peripheral region 140 away from the substrate 130. In addition, the mask layer 103 having the plurality of openings 113 is subsequently patterned on the substrate 100 to form a plurality of conductive pillars 104.

[0041] It should be noted that the manufacturing method provided in one embodiment of the present disclosure will be described in detail later using the substrate 100 spanning the array area 110, the transition area 120 and the peripheral area 140 as an example. In actual applications, subsequent processing can also be performed on the substrate 100 spanning the array area 110 and the transition area 120.

[0042] S103: Reference Figures 2 to 3The substrate 100 is patterned using the mask layer 103 as a mask. The remaining diffusion barrier film 101 includes a plurality of first diffusion barrier layers 111 spaced apart from each other. The remaining conductive film 102 includes a plurality of conductive layers 112 spaced apart from each other. A first diffusion barrier layer 111 and a conductive layer 112 located on the first diffusion barrier layer 111 constitute a conductive column 104. A groove 105 is provided between adjacent conductive columns 104.

[0043] Understandably, the reference Figure 3 In the step of patterning the substrate 100 using the mask layer 103 as a mask, in the array region 110 and the transition region 120, not only the diffusion barrier film 101 and the conductive film 102 are etched, but also the second dielectric layer 180 and the first dielectric layer 179 in the substrate 100 are etched. In the peripheral region 140, only the diffusion barrier film 101 is etched. In practical applications, both the diffusion barrier film 101 and the conductive film 102 may be etched in the peripheral region 140.

[0044] Continue to refer Figure 3 For the array region 110 and the transition region 120, a first diffusion barrier layer 111 and a conductive layer 112 located on the first diffusion barrier layer 111 constitute a conductive pillar 104, and adjacent conductive pillars 104 are spaced apart from each other. Moreover, for the array region 110, the first diffusion barrier layer 111 itself forms a sub-groove, and the conductive layer 112 completely fills the sub-groove. With the bottom surface of the first contact hole 131 as a reference surface, the top surface of the conductive layer 112 away from the electrical contact layer 160 is higher than the top surface of the first diffusion barrier layer 111 away from the electrical contact layer 160. For the transition region 120, the first diffusion barrier layer 111 and the conductive layer 112 are stacked along the second direction Y, that is, the conductive layer 112 is only located on the side of the first diffusion barrier layer 111 away from the first dielectric layer 170. It can be understood that the second direction Y is perpendicular to the first direction X, that is, the second direction Y can be the first contact hole 131 (reference Figure 1 ) in the depth direction.

[0045] Continue to refer Figure 3 For the peripheral region 140, in the step of patterning the substrate 100 using the mask layer 103 as a mask, if both the diffusion barrier film 101 and the conductive film 102 are etched so that the remaining diffusion barrier film 101 and the remaining conductive film 102 are disconnected into multiple segments, a plurality of conductive pillars spaced apart from each other are also formed in the peripheral region 140 (not shown in the figure).

[0046] S104 : removing the mask layer 103 , leaving residues 106 in the groove 105 .

[0047] In some embodiments, the residue 106 includes at least one of a residual mask layer, a residual granular conductive layer, a residual oxidized conductive layer, or a residual nitrided conductive layer. It should be noted that for clarity of the diagram, the residues are uniformly labeled 106 .

[0048] It can be understood that, in the step of patterning the substrate 100 using the mask layer 103 as a mask, firstly, the mask layer 103 will form a small amount of residue in the formed groove 105, that is, the residue 106 includes the residual mask layer. For example, the material of the mask layer 103 is carbon, and the material of the residue 106 located in the groove 105 caused by the mask layer 103 can be a carbon polymer; secondly, the conductive film 102 will form a small amount of residue in the formed groove 105, that is, the residue 106 includes the residual conductive film 102. It should be noted that the residual conductive film 102 can be granular. The conductive film 102 after the graphic treatment is a conductive layer 112, that is, the residue 106 includes the residual granular conductive layer. For example, the material of the conductive film 102 is tungsten. The material of the residue 106 located in the groove 105 caused by the conductive film 102 may be granular tungsten. Thirdly, due to the etching environment of the graphic treatment, the conductive film 102 or the conductive layer 112 may be oxidized by the environment, that is, the residue 106 includes the residual oxidized conductive layer. For example, the material of the conductive layer 112 is tungsten. The material of the residue 106 located in the groove 105 caused by the etching environment of the graphic treatment may be tungsten oxide.

[0049] It is understood that the residue 106 in the groove 105 may cause a short circuit between adjacent, spaced-apart conductive pillars 104. That is, the spaced-apart conductive pillars 104 may be electrically connected via the residue 106 in the groove 105, causing the two electrically connected conductive pillars 104 to fail and be unable to perform their respective functions. Therefore, to improve the electrical stability of the conductive pillars 104 and thus enhance the electrical performance of the resulting semiconductor structure, it is necessary to remove the residue 106 in the groove 105.

[0050] S105: Combined with reference Figure 3 and Figure 4 In step 4a, the surface of the exposed conductive layer 112 is nitrided to form a nitride layer 122 on the surface of the conductive layer 112. It is understood that in the subsequent step of removing the residue 106, the nitride layer 122 can protect the conductive layer 112 covered by the nitride layer 122 from being etched.

[0051] It should be noted that, for the peripheral region 140, during the step of nitriding the surface of the exposed conductive layer 112, since the area of ​​the conductive layer 112 away from the top surface of the substrate 130 is relatively large, the top surface of the conductive layer 112 in the peripheral region 140 may not be nitrided, or the degree of nitridation is too low to form the nitride layer 122 shown in the array region 110 and the transition region 120; moreover, the top surface area of ​​the conductive layer 112 is also relatively large in the transition region between the transition region 120 and the peripheral region 140. Therefore, Figure 4 Only the nitride layer 122 is shown schematically on the inner wall of the recess 105 in the peripheral region 140 .

[0052] In some embodiments, for the nitride layer 122 formed based on the conductive layer 112 , the nitride layer 122 located on the top surface of the conductive layer 112 may be removed subsequently to reduce the contact resistance between the conductive layer 112 and other conductive structures.

[0053] In some embodiments, during the step of nitriding the surface of the exposed conductive layer 112, a mask plate may be used to cover the structure of the peripheral region 140, and only the surfaces of the conductive layer 112 in the array region 110 and the transition region 120 may be nitrided; in other embodiments, the same nitridation process may be performed on the surfaces of the conductive layer 112 in the array region 110, the transition region 120, and the peripheral region 140.

[0054] It can be understood that if the residue 106 in the groove 105 is a granular conductive layer, in the step of nitriding the surface of the exposed conductive layer 112, part of the residue 106 of the granular conductive layer may also be nitrided and converted into a nitride layer (not shown in the figure), that is, the residue 106 includes the remaining nitrided conductive layer. For example, the material of the granular conductive layer is tungsten. Because the material of the granular conductive layer is tungsten, the material of the residue 106 located in the groove 105 caused by the nitridation treatment of the granular conductive layer can be tungsten nitride.

[0055] In some embodiments, the step of performing a nitridation treatment on the surface of the exposed conductive layer 112 may include: providing a first gas and performing a plasma treatment on the first gas, and using the first gas after the plasma treatment to perform the nitridation treatment on the surface of the conductive layer 112; wherein the first gas includes dihydrogen nitride gas, and the gas flow range of the dihydrogen nitride gas is 100 sccm to 15000 sccm.

[0056] In some embodiments, the first gas includes, in addition to the dihydrogen nitride gas, auxiliary gases such as nitrogen and argon.

[0057] It can be understood that in the step of nitriding the surface of the exposed conductive layer 112, the semiconductor structure will be placed in a reaction chamber, a first gas will be introduced into the reaction chamber and the first gas will be plasma treated, the gas pressure of the first gas in the reaction chamber is 100mtorr~4000mtorr, and the power of the plasma treatment of the first gas is 1000W~10000W.

[0058] S106: Combined with reference Figure 4 In steps 4 a and 4 b , the surface of the groove 105 is cleaned to remove the residue 106 . The etching rate of the residue 106 during the cleaning process is greater than the etching rate of the nitride layer 122 .

[0059] In some embodiments, the cleaning process includes a first cleaning process and a second cleaning process. The first cleaning process includes providing a first cleaning liquid into the groove 105, wherein the first cleaning liquid is mainly used to remove the residual mask layer and the residual oxidized conductive layer as the residue 106. In one example, the first cleaning liquid can be ammonia water. The second cleaning process includes providing a second cleaning liquid into the groove 105, wherein the second cleaning liquid is mainly used to remove the residual granular conductive layer, the residual oxidized conductive layer or the residual nitrided conductive layer as the residue 106. In one example, the second cleaning liquid can be a mixed liquid of sulfuric acid, hydrogen peroxide and water. In this way, it is beneficial to remove the residue 106 through the combined action of the first cleaning process and the second cleaning process.

[0060] On the one hand, it can be seen from the above analysis that cleaning the surface of the groove 105 to remove the residue 106 is beneficial to avoid short circuits between adjacent conductive pillars 104, thereby improving the stability of each conductive pillar 104 and improving the electrical performance of each conductive pillar 104; on the other hand, before the surface of the groove 105 is cleaned, the nitride layer 122 is formed on the surface of the conductive layer 112, and the etching rate of the residue 106 by the cleaning process is greater than the etching rate of the nitride layer 122, so that the residue 106 is removed after cleaning the surface of the groove 105. During the cleaning process, the nitride layer 122 can be used to prevent the remaining conductive layer 112 from being etched. Even if the distance between adjacent conductive pillars 104 is small, while ensuring the removal of the residue 106, the nitride layer 122 is difficult to etch and the conductive layer 112 is not easily exposed. The nitride layer 122 protects the conductive layer 112 and prevents damage to the conductive layer 112 during the cleaning process. This helps prevent significant changes in the size of the conductive layer 112, thereby improving the dimensional accuracy of the conductive pillars 104 and further improving the electrical performance of each conductive pillar 104. This helps improve the electrical performance of the ultimately formed semiconductor structure.

[0061] In some embodiments, when the substrate 100 further spans the peripheral region 140 and the substrate 100 is patterned using the mask layer 103 as a mask, a groove 105 is also formed in the peripheral region 140. The step of cleaning the surface of the groove 105 may further include cleaning the surface of the groove 105 in the peripheral region 140.

[0062] In some embodiments, reference Figure 4 In FIG4 b , in the conductive pillars 104 finally formed, the conductive pillars 104 in the array region 110 and the transition region 120 both include a nitride layer 122 formed based on the conductive layer 112 , the conductive layer 112 that has not been nitrided, and the first diffusion barrier layer 111 .

[0063] The manufacturing method provided in one embodiment of the present disclosure may further include the following embodiments. It should be noted that the parts identical or corresponding to the above embodiments are not described in detail here.

[0064] In some embodiments, reference Figure 3 、 Figure 5 and Figure 6 After the substrate 100 is patterned and before the exposed conductive layer 112 is nitrided, that is, between step S104 and step S105, the manufacturing method may further include the following steps:

[0065] Combined with reference Figure 3 and Figure 5 In step 5 a , the first diffusion barrier layer 111 is oxidized so that at least a portion of the width of the first diffusion barrier layer 111 along the first direction X is transformed into the second diffusion barrier layer 121 .

[0066] In some embodiments, the first diffusion barrier layer 111 is oxidized, including: providing a second gas and performing plasma treatment on the second gas, and using the second gas after the plasma treatment to oxidize the surface of the first diffusion barrier layer 111; wherein the second gas includes oxygen, and the gas flow range of oxygen is 100 sccm to 15000 sccm.

[0067] In some embodiments, the second gas includes, in addition to oxygen, auxiliary gases such as dihydrogen nitride, nitrogen, and argon.

[0068] It can be understood that in the step of oxidizing the exposed first diffusion barrier layer 111, the semiconductor structure will be placed in a reaction chamber, a second gas will be introduced into the reaction chamber and the second gas will be plasma treated, the gas pressure of the second gas in the reaction chamber is 100mtorr~5000mtorr, and the power of the plasma treatment of the second gas is 1000W~10000W.

[0069] In some embodiments, the material of the first diffusion barrier layer 111 is titanium nitride, and the material of the second diffusion barrier layer 121 is titanium oxynitride.

[0070] It should be noted that, in the step of oxidizing the first diffusion barrier layer 111, the first diffusion barrier layer 111 exposed by the groove 105 in the array region 110 is close to the bottom of the groove 105. The first diffusion barrier layer 111 in the array region 110 may not be oxidized or may be oxidized to a low degree. Figure 5 and Figure 6 It is not shown whether the first diffusion barrier layer 111 in the array region 110 is oxidized. Moreover, taking the top surface of the electrical contact layer 160 as a reference surface, the first diffusion barrier layer 111 in the transition region 120 is higher than the first diffusion barrier layer 111 in the array region 110. Therefore, the oxidation treatment can more easily oxidize the first diffusion barrier layer 111 in the transition region 120. Figure 5 and Figure 6 In the example, the first diffusion barrier layer 111 in the transition region 120, which is used to form the conductive pillar 104, is completely converted into the second diffusion barrier layer 121, and a portion of the width of the first diffusion barrier layer 111 near the peripheral region 140 is converted into the second diffusion barrier layer 121. In actual applications, along the first direction X, only a portion of the width of the first diffusion barrier layer 111 in the transition region 120, which is used to form the conductive pillar 104, may be converted into the second diffusion barrier layer 121, and another portion of the width of the first diffusion barrier layer 111 may remain unoxidized.

[0071] In some embodiments, if the residue 106 in the groove 105 is a granular conductive layer, during the step of oxidizing the first diffusion barrier layer 111, part of the residue 106 that is a granular conductive layer may also be oxidized and converted into an oxide layer (not shown in the figure), that is, the residue 106 includes the remaining oxidized conductive layer.

[0072] Combined with reference Figure 5 In steps 5 a and 5 b , a first cleaning process is performed on the surface of the groove 105 to remove a portion of the residue 106 . The etching rate of the residue 106 in the first cleaning process is greater than the etching rate of the second diffusion barrier layer 121 .

[0073] It can be understood that the first diffusion barrier layer 111 and the conductive layer 112 in the transition region 120 are stacked along the second direction Y. This means that the contact area between the first diffusion barrier layer 111 and the conductive layer 112 in the transition region 120 is relatively small, unlike in the array region 110 where the first diffusion barrier layer 111 partially wraps around the conductive layer 112. Consequently, the connection strength between the first diffusion barrier layer 111 and the conductive layer 112 in the transition region 120 is weak. In other words, the first diffusion barrier layer 111 in the transition region 120 provides limited support for the conductive layer 112. In this case, the first cleaning process, when cleaning the residue 106, also has a relatively high etching rate on the first diffusion barrier layer 111. This can easily over-etch the first diffusion barrier layer 111 exposed in the recess 105, resulting in excessive consumption of the first diffusion barrier layer 111 in the transition region 120, which can easily lead to collapse of the conductive layer 112 and failure of the conductive pillar 104.

[0074] In this manner, the first diffusion barrier layer 111 is oxidized, so that at least a portion of the first diffusion barrier layer 111 exposed by the recess 105 in the transition region 120 is converted into a second diffusion barrier layer 121. By utilizing the characteristic that the etching rate of the residue 106 during the first cleaning process is greater than the etching rate of the second diffusion barrier layer 121, over-etching of the second diffusion barrier layer 121 is avoided during the first cleaning process of the residue 106. In other words, the second diffusion barrier layer 121 is used to prevent the remaining first diffusion barrier layer 111 from being etched. This helps ensure a sufficiently large contact area between the first diffusion barrier layer 111 and the conductive layer 112 in the transition region 120, thereby increasing the support strength of the first diffusion barrier layer 111 in the transition region 120 for the conductive layer 112 and preventing collapse of the conductive layer 112. This helps further ensure the dimensional accuracy of the ultimately formed conductive pillar 104 while removing the residue 106.

[0075] In some embodiments, the first cleaning step includes providing a first cleaning solution into the groove 105, wherein the first cleaning solution is mainly used to remove the remaining mask layer and the remaining oxidized conductive layer as the residue 106. In one example, the first cleaning solution can be ammonia water.

[0076] Combined with reference Figure 5 5b and Figure 6 In step 6a, the exposed surface of the conductive layer 112 is nitrided to form a nitride layer 122 on the surface of the conductive layer 112. It should be noted that the parts identical or corresponding to the above embodiment are not described in detail here.

[0077] In some embodiments, in conjunction with reference Figure 6In steps 6a and 6b, after forming the nitride layer 122, cleaning the surface of the groove 105 may further include performing a second cleaning process on the surface of the groove 105 to remove the residue 106, wherein the cleaning solution used in the first cleaning process is different from the cleaning solution used in the second cleaning process.

[0078] In some embodiments, the second cleaning step may include providing a second cleaning liquid into the groove 105. The second cleaning liquid is primarily used to remove residual granular conductive layer, residual oxidized conductive layer, or residual nitrided conductive layer, which constitutes the residue 106. In one example, the second cleaning liquid may be a mixture of sulfuric acid, hydrogen peroxide, and water. This facilitates the removal of the residue 106 through the combined effects of the first and second cleaning processes.

[0079] In some embodiments, reference Figure 6 In Figure 6b, among the conductive pillars 104 finally formed, the conductive pillars 104 in the array area 110 include a nitride layer 122 formed based on the conductive layer 112, the conductive layer 112 that has not been nitrided, and the first diffusion barrier layer 111; the conductive pillars 104 in the transition area 120 all include a nitride layer 122 formed based on the conductive layer 112, the conductive layer 112 that has not been nitrided, and the second diffusion barrier layer 121.

[0080] In other embodiments, reference Figure 7 and Figure 8 , Figure 7 7b is a schematic diagram of the cross-sectional structure of the substrate 130 in 7a. The step of providing the base 100 may include: providing an initial substrate (not shown), the initial substrate spanning the array area 110, the transition area 120 and the peripheral area 140 arranged in sequence along the first direction X; performing patterning on the initial substrate, and the remaining initial substrate is the substrate 130, so as to form a first contact hole 131 in the substrate 130 of the array area 110, a second contact hole 132 in the substrate 130 of the transition area 120, and a third contact hole 133 in the substrate 130 of the peripheral area 140, the third contact hole 133 extending from the top surface of the substrate 130 into the substrate 130, and the hole depths of the first contact hole 131, the second contact hole 132 and the third contact hole 133 decreasing in sequence. A diffusion barrier film 101 is formed, conformally covering the inner walls of the first contact hole 131, the second contact hole 132, and the third contact hole 133, and located on the top surface of the substrate 130. A conductive film 102 is formed, completely filling the first contact hole 131, the second contact hole 132, and the third contact hole 133, and located on a first top surface 101a of the diffusion barrier film 101 away from the top surface of the substrate 130. It should be noted that portions of the substrate 100 that are identical or corresponding to those in the above embodiment are not described in detail here.

[0081] It is understandable that in the step of patterning the initial substrate, the depth of the second contact hole 132 is deepened, so that the depths of the first contact hole 131, the second contact hole 132 and the third contact hole 133 decrease in sequence.

[0082] In some embodiments, the second contact hole 132 has a depth ranging from 25 nm to 35 nm.

[0083] refer to Figure 8 In Figures 8a and 8b, in the step of patterning the substrate 100 using the mask layer 103 as a mask, that is, in step S103, the first diffusion barrier layer 111 formed in the transition region 120 is similar to the first diffusion barrier layer 111 formed in the array region 110, that is, in the transition region 120, the first diffusion barrier layer 111 itself also forms a sub-groove, and the conductive layer 112 fills the sub-groove, and with the bottom surface of the second contact hole 132 as a reference surface, the top surface of the conductive layer 112 away from the electrical contact layer 160 is higher than the top surface of the first diffusion barrier layer 111 away from the electrical contact layer 160.

[0084] In this way, the first diffusion barrier layer 111 in the transition zone 120 wraps a partial thickness of the conductive layer 112, so as to increase the contact area between the first diffusion barrier layer 111 and the conductive layer 112 in the transition zone 120, which is beneficial to improving the connection strength between the first diffusion barrier layer 111 and the conductive layer 112 in the transition zone 120, that is, improving the supporting effect of the first diffusion barrier layer 111 in the transition zone 120 on the conductive layer 112. In this case, even if the etching rate of the first diffusion barrier layer 111 is relatively high when the subsequent cleaning process is performing the cleaning process on the residue 106, since the contact area between the first diffusion barrier layer 111 and the conductive layer 112 in the transition region 120 is large enough, the supporting effect of the first diffusion barrier layer 111 in the transition region 120 on the conductive layer 112 is more stable, and the collapse of the conductive layer 112 due to the etching of the first diffusion barrier layer 111 is effectively avoided. This is beneficial for ensuring a sufficiently large contact area between the first diffusion barrier layer 111 and the conductive layer 112 in the transition region 120 while improving the supporting strength of the first diffusion barrier layer 111 in the transition region 120 on the conductive layer 112, which is beneficial for further ensuring the dimensional accuracy of the conductive column 104 formed in the subsequent removal of the residue 106.

[0085] Combined with reference Figure 8 8b and Figure 9 In step 9a, the exposed surface of the conductive layer 112 is nitrided to form a nitride layer 122 on the surface of the conductive layer 112. It should be noted that the parts identical or corresponding to the above embodiment are not described in detail here.

[0086] In some embodiments, the step of cleaning the surface of the groove 105 may include: sequentially performing a first cleaning process and a second cleaning process on the surface of the groove 105, wherein the cleaning liquid used in the first cleaning process is different from the cleaning liquid used in the second cleaning process. It should be noted that the first cleaning process in this embodiment is the same as the first cleaning process in the above-mentioned embodiment, except that the timing of the cleaning is different, which is not described in detail here; the second cleaning process in this embodiment is the same as the second cleaning process in the above-mentioned embodiment, except that the timing of the cleaning is different, which is not described in detail here. In this way, the combined action of the first cleaning process and the second cleaning process facilitates the complete removal of the residue 106 without affecting the dimensional accuracy of the conductive pillar 104 ultimately formed.

[0087] In some embodiments, reference Figure 9 In Figure 9b, among the conductive pillars 104 finally formed, the conductive pillars 104 in the array area 110 include a nitride layer 122 formed based on the conductive layer 112, the conductive layer 112 that has not been nitrided, and the first diffusion barrier layer 111; the conductive pillars 104 in the transition area 120 all include a nitride layer 122 formed based on the conductive layer 112, the conductive layer 112 that has not been nitrided, and the first diffusion barrier layer 111.

[0088] In some other embodiments, after the substrate 100 is patterned, Figure 8 In the semiconductor structure shown in Figure 8b, the first diffusion barrier layer 111 includes a first portion 141 and a second portion 151. The first portion 141 is located on the bottom surface of the conductive layer 112, and the second portion 151 surrounds a portion of the sidewall of the conductive layer 112. It should be noted that the first diffusion barrier layer 111 herein refers to the first diffusion barrier layer 111 located in the array region 110 and the transition region 120.

[0089] After the substrate 100 is patterned and before the exposed conductive layer 112 is nitrided, that is, between step S104 and step S105, the manufacturing method may further include the following steps:

[0090] Combined with reference Figure 8 8b and Figure 10 In step 10a, the first diffusion barrier layer 111 is oxidized so that the second portion 151 along at least a portion of the thickness in the second direction Y is transformed into the second diffusion barrier layer 121. The second direction Y is perpendicular to the first direction X.

[0091] It should be noted that Figure 10Figure 10a illustrates an example in which a partial thickness of the second portion 151 in the array region 110 along the second direction Y is transformed into the second diffusion barrier layer 121, and the entire second portion 151 in the transition region 120 is transformed into the second diffusion barrier layer 121, i.e., the transition region 120 includes the first portion 141 and the second diffusion barrier layer 121 together covering a partial thickness of the conductive layer 112. In actual applications, along the second direction Y, only a partial thickness of the second portion 151 in the transition region 120 may be transformed into the second diffusion barrier layer 121, and a partial thickness of the second portion 151 may remain unoxidized. Figure 8 and Figure 10 The first portion 141 and the second portion 151 of the first diffusion barrier layer 111 are divided by a dotted line.

[0092] Thus, on the one hand, the first diffusion barrier layer 111 in the transition region 120 wraps a portion of the conductive layer 112, thereby increasing the contact area between the first diffusion barrier layer 111 and the conductive layer 112 in the transition region 120, which is beneficial to improving the connection strength between the first diffusion barrier layer 111 and the conductive layer 112 in the transition region 120, that is, improving the supporting effect of the first diffusion barrier layer 111 in the transition region 120 on the conductive layer 112, thereby ensuring a sufficiently large contact area between the first diffusion barrier layer 111 and the conductive layer 112 in the transition region 120, while improving the supporting strength of the first diffusion barrier layer 111 in the transition region 120 on the conductive layer 112; on the other hand, at least the first diffusion barrier layer 111 in the transition region 120 is covered with At least a portion of the width of the first diffusion barrier layer 111 exposed in the groove 105 is transformed into a second diffusion barrier layer 121. By utilizing the characteristic that the etching rate of the residue 106 during the first cleaning process is greater than the etching rate of the second diffusion barrier layer 121, over-etching of the second diffusion barrier layer 121 is avoided during the first cleaning process of the residue 106. In other words, the second diffusion barrier layer 121 is used to prevent the remaining first diffusion barrier layer 111 from being etched. This helps ensure a sufficiently large contact area between the first diffusion barrier layer 111 and the conductive layer 112 in the transition region 120, thereby increasing the support strength of the first diffusion barrier layer 111 in the transition region 120 for the conductive layer 112 and preventing collapse of the conductive layer 112. Therefore, these two aspects work together to remove the residue 106 while further ensuring the dimensional accuracy of the ultimately formed conductive pillar 104.

[0093] It should be noted that the oxidation treatment performed on the first diffusion barrier layer 111 in this embodiment is the same as the oxidation treatment performed on the first diffusion barrier layer 111 in the above embodiment.

[0094] Combined with reference Figure 10In steps 10 a and 10 b , a first cleaning process is performed on the surface of the groove 105 to remove a portion of the residue 106 . The etching rate of the residue 106 in the first cleaning process is greater than the etching rate of the second diffusion barrier layer 121 .

[0095] Combined with reference Figure 10 10b and Figure 11 In step 11 a , the exposed surface of the conductive layer 112 is nitrided to form a nitride layer 122 on the surface of the conductive layer 112 .

[0096] It is understood that during the cleaning process of the surface of the groove 105 to remove the residue 106, the nitride layer 122 can be used to prevent the remaining conductive layer 112 from being etched. Even if the spacing between adjacent conductive pillars 104 is small, while ensuring the removal of the residue 106, the nitride layer 122 is difficult to etch and the conductive layer 112 is not easily exposed. The nitride layer 122 protects the conductive layer 112, thereby preventing damage to the conductive layer 112 caused by the cleaning process. This helps to prevent significant changes in the size of the conductive layer 112, thereby improving the dimensional accuracy of the conductive pillars 104 and further improving the electrical performance of each conductive pillar 104. In this way, these three aspects work together to improve the electrical performance of the ultimately formed semiconductor structure.

[0097] In some embodiments, in conjunction with reference Figure 11 In steps 11a and 11b , after forming the nitride layer 122 , cleaning the surface of the groove 105 includes performing a second cleaning process on the surface of the groove 105 to remove the residue 106 , wherein the cleaning solution used in the first cleaning process is different from the cleaning solution used in the second cleaning process.

[0098] In some embodiments, reference Figure 11 In Figure 11b, in the conductive pillars 104 finally formed, the conductive pillars 104 in the array area 110 include a nitride layer 122 formed based on the conductive layer 112, the conductive layer 112 that has not been nitrided, the second diffusion barrier layer 121 and the first diffusion barrier layer 111 that has not been oxidized; the conductive pillars 104 in the transition area 120 all include a nitride layer 122 formed based on the conductive layer 112, the conductive layer 112 that has not been nitrided, the second diffusion barrier layer 121 and the first portion 141. It can be understood that the first portion 141 is the first diffusion barrier layer 111 in the transition area 120 that has not been oxidized.

[0099] In summary, on the one hand, cleaning the surface of the groove 105 to remove the residue 106 is beneficial to avoid short circuits between adjacent conductive pillars 104, thereby improving the stability of each conductive pillar 104 and improving the electrical performance of each conductive pillar 104; on the other hand, before the surface of the groove 105 is cleaned, the nitride layer 122 is formed on the surface of the conductive layer 112, and the etching rate of the cleaning process on the residue 106 is greater than the etching rate of the nitride layer 122, so that the surface of the groove 105 is cleaned to remove the residue 106. During the cleaning process, the nitride layer 122 can be used to prevent the remaining conductive layer 112 from being etched. Even if the distance between adjacent conductive pillars 104 is small, while ensuring the removal of the residue 106, the nitride layer 122 is difficult to etch and the conductive layer 112 is not easily exposed. The nitride layer 122 protects the conductive layer 112 and prevents damage to the conductive layer 112 during the cleaning process. This helps prevent significant changes in the size of the conductive layer 112, thereby improving the dimensional accuracy of the conductive pillars 104 and further improving the electrical performance of each conductive pillar 104. This helps improve the electrical performance of the ultimately formed semiconductor structure.

[0100] Another embodiment of the present disclosure further provides a semiconductor structure, which is formed by the manufacturing method provided in the above embodiment. The semiconductor structure provided in another embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. Figure 12 This is a schematic diagram of a partial cross-sectional structure of a substrate in a semiconductor structure provided by another embodiment of the present disclosure. It should be noted that: Figure 12 for Figure 11 The diagram shows a partial cross-sectional structure of a substrate in a semiconductor structure. In addition, parts identical or corresponding to the above-mentioned embodiments are not described in detail here.

[0101] refer to Figure 4 Middle 4b, Figure 6 6b, Figure 9 9b or Figure 11 In FIG11b, the semiconductor structure may include: a substrate 130, the substrate 130 spanning the array region 110 and the transition region 120 sequentially arranged along the first direction X, Figure 12The substrate 130 of the array region 110 includes a first through hole 134 extending from the top surface of the substrate 130 into the substrate 130; a plurality of conductive pillars 104 are spaced apart from each other, each conductive pillar 104 includes a diffusion barrier layer 161 and a conductive layer 112, the diffusion barrier layer 161 conformally covers the inner wall of the first through hole 134 and covers the surface of the substrate 130 in the transition region 120, the conductive layer 112 is located on the surface of the diffusion barrier layer 161 away from the substrate 130, and with the bottom surface of the first through hole 134 as a reference surface, a second top surface 112a of the conductive layer 112 away from the substrate 130 is higher than a third top surface 161a of the diffusion barrier layer 161 away from the substrate 130; wherein, The diffusion barrier layer 161 located in the array region 110 is the first diffusion barrier layer 111, or the diffusion barrier layer 161 located in the array region 110 includes the first diffusion barrier layer 111 and the second diffusion barrier layer 121 that are in contact with each other along the second direction Y; the diffusion barrier layer 161 located in the transition region 120 is the first diffusion barrier layer 111 or the second diffusion barrier layer 121, or the diffusion barrier layer 161 located in the transition region 120 includes the first diffusion barrier layer 111 and the second diffusion barrier layer 121 that are in contact with each other along the second direction Y; the first diffusion barrier layer 111 after oxidation treatment is the second diffusion barrier layer 121, and the second direction Y is perpendicular to the first direction X.

[0102] The diffusion barrier layer 161 located in the array region 110 and the transition region 120 will be described in detail later.

[0103] In some embodiments, reference Figure 12 , the substrate 130 of the transition region 120 has a second through hole 135 extending from the top surface of the substrate 130 to the inside of the substrate 130, and the depth of the first through hole 134 is greater than the depth of the second through hole 135; combined with reference Figure 12 and Figure 9 9b, or in conjunction with reference Figure 12 and Figure 11 In FIG11 b , the diffusion barrier layer 161 covers the surface of the substrate 130 in the transition region 120 , including: the diffusion barrier layer 161 conformally covers the inner wall of the second through hole 135 , and the conductive layer 112 completely fills the first through hole 134 and the second through hole 135 .

[0104] In some embodiments, reference Figure 12 The substrate 130 also spans the peripheral region 140. The peripheral region 140 is located on the side of the transition region 120 away from the array region 110 along the first direction X. The substrate 130 of the peripheral region 140 has a third through hole 136 extending from the top surface of the substrate 130 to the inside of the substrate 130. Figure 12 and Figure 4 Middle 4b, Figure 6 6b, Figure 9 9b or Figure 11In one of the four through holes 11 b , the diffusion barrier layer 161 also conformally covers the inner wall of the third through hole 136 , and the conductive layer 112 is located in the remaining third through hole 136 .

[0105] It should be noted that Figure 12 In the example, the hole depths of the first through hole 134, the second through hole 135, and the third through hole 136 decrease in sequence. In actual applications, the depth of the first through hole 134 can be greater than the depth of the third through hole 136, but the hole depths of the second through hole 135 and the third through hole 136 have no fixed size relationship, and the hole depths of the two can be flexibly adjusted.

[0106] The diffusion barrier layer 161 located in the array region 110 and the transition region 120 will be described in detail below.

[0107] In some embodiments, reference Figure 4 In FIG. 4b , the diffusion barrier layer 161 in the array region 110 is the first diffusion barrier layer 111, and the diffusion barrier layer 161 in the transition region 120 is also the first diffusion barrier layer 111. Furthermore, the conductive pillars 104 in the array region 110 and the transition region 120 both include a nitride layer 122 covering the surface of the conductive layer 112, the conductive layer 112, and the first diffusion barrier layer 111.

[0108] In other embodiments, reference Figure 6 In Figure 6b, the diffusion barrier layer 161 located in the array region 110 is the first diffusion barrier layer 111, and the diffusion barrier layer 161 located in the transition region 120 is the second diffusion barrier layer 121. Furthermore, the conductive pillars 104 located in the array region 110 include a nitride layer 122 covering the surface of the conductive layer 112, the conductive layer 112, and the first diffusion barrier layer 111; the conductive pillars 104 located in the transition region 120 also include a nitride layer 122 covering the surface of the conductive layer 112, the conductive layer 112, and the second diffusion barrier layer 121.

[0109] In some other embodiments, reference Figure 9 In Figure 9b, the diffusion barrier layer 161 in the array region 110 is the first diffusion barrier layer 111, and the diffusion barrier layer 161 in the transition region 120 is the first diffusion barrier layer 111. The first diffusion barrier layer 111, after oxidation, is the second diffusion barrier layer 121. Furthermore, the conductive pillars 104 in the array region 110 include a nitride layer 122 covering the surface of the conductive layer 112, the conductive layer 112, and the first diffusion barrier layer 111; the conductive pillars 104 in the transition region 120 also include a nitride layer 122 covering the surface of the conductive layer 112, the conductive layer 112, and the first diffusion barrier layer 111.

[0110] In some embodiments, reference Figure 11In Figure 11b, the diffusion barrier layer 161 in the array region 110 includes a first diffusion barrier layer 111 and a second diffusion barrier layer 121 that are in contact with each other along the second direction Y. The diffusion barrier layer 161 in the transition region 120 includes the first diffusion barrier layer 111 and the second diffusion barrier layer 121 that are in contact with each other along the second direction Y. Furthermore, the conductive pillars 104 in the array region 110 include a nitride layer 122 covering the surface of the conductive layer 112, the conductive layer 112, the second diffusion barrier layer 121, and the first diffusion barrier layer 111. The conductive pillars 104 in the transition region 120 also include a nitride layer 122 covering the surface of the conductive layer 112, the conductive layer 112, the second diffusion barrier layer 121, and the first diffusion barrier layer 111.

[0111] In the above-mentioned various embodiments, the first diffusion barrier layer 111 after oxidation treatment is the second diffusion barrier layer 121 .

[0112] In summary, adjacent conductive pillars 104 located in the array region 110 and the transition region 120 are spaced apart from each other, which helps to avoid short circuits between adjacent conductive pillars 104. Moreover, the surface of the conductive layer 112 is covered with a nitride layer 122, which helps to prevent the conductive layer 112 from being oxidized by oxygen in the environment through the nitride layer 122, thereby ensuring the dimensional accuracy of the conductive layer 112, and further ensuring the dimensional accuracy of the conductive pillars 104, thereby improving the electrical performance of the semiconductor structure.

[0113] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present disclosure, and in actual applications, various changes may be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the scope of protection of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: The semiconductor structure includes an array region and a transition region, and the manufacturing method includes: Providing a substrate, the substrate spanning the array region and the transition region sequentially arranged along a first direction; The base comprises: a substrate, wherein the substrate in the array region has a first contact hole extending from the top surface of the substrate into the interior of the substrate, and the substrate in the transition region has a second contact hole extending from the top surface of the substrate into the interior of the substrate, wherein the hole depth of the first contact hole is greater than the hole depth of the second contact hole; a diffusion barrier film conformally covering the inner walls of the first contact hole and the second contact hole and located on the top surface of the substrate; and a conductive film filling the first contact hole and the second contact hole and located on a first top surface of the diffusion barrier film away from the top surface of the substrate. forming a mask layer having a plurality of openings on a side of the conductive film away from the substrate; The substrate is patterned using the mask layer as a mask, wherein the remaining diffusion barrier film includes a plurality of first diffusion barrier layers spaced apart from each other, and the remaining conductive film includes a plurality of conductive layers spaced apart from each other, wherein the first diffusion barrier layer and the conductive layer located on the first diffusion barrier layer constitute a conductive column, and grooves are provided between adjacent conductive columns; removing the mask layer, leaving residue in the groove; performing a nitriding treatment on the exposed surface of the conductive layer to form a nitride layer on the surface of the conductive layer; The surface of the groove is cleaned to remove the residue, and the etching rate of the residue by the cleaning process is greater than the etching rate of the nitride layer.

2. The manufacturing method according to claim 1, characterized in that The residue includes at least one of the remaining mask layer, the remaining granular conductive layer, the remaining oxidized conductive layer, or the remaining nitrided conductive layer.

3. The manufacturing method according to claim 1, characterized in that The semiconductor structure further includes a peripheral region, the peripheral region being located on a side of the transition region away from the array region along the first direction, the base further spanning the peripheral region, the substrate in the peripheral region having a third contact hole extending from a top surface of the substrate into the substrate, the depth of the first contact hole being greater than a depth of the third contact hole, the diffusion barrier film further conformally covering an inner wall of the third contact hole, and the conductive film further completely filling the third contact hole; In the step of patterning the substrate using the mask layer as a mask, a plurality of conductive pillars spaced apart from each other are also formed in the peripheral area; The step of performing the cleaning process on the surface of the groove further includes: performing the cleaning process on the surface of the groove in the peripheral area.

4. The manufacturing method according to claim 1, characterized in that The exposed surface of the conductive layer is subjected to the nitridation treatment, comprising: providing a first gas and performing plasma treatment on the first gas, and using the first gas after the plasma treatment to perform the nitridation treatment on the surface of the conductive layer; wherein the first gas comprises dihydrogen nitride gas, and the gas flow range of the dihydrogen nitride gas is 100 sccm~15000 sccm.

5. The manufacturing method according to any one of claims 1 to 4, characterized in that After performing the patterning process on the substrate and before performing the nitriding process on the exposed conductive layer, the method further includes: performing an oxidation treatment on the first diffusion barrier layer so that at least a portion of the width of the first diffusion barrier layer along the first direction is transformed into a second diffusion barrier layer; A first cleaning process is performed on the surface of the groove to remove a portion of the residue, wherein an etching rate of the residue by the first cleaning process is greater than an etching rate of the second diffusion barrier layer.

6. The manufacturing method according to claim 5, characterized in that The oxidation treatment of the first diffusion barrier layer includes: providing a second gas and performing plasma treatment on the second gas, and using the second gas after the plasma treatment to perform the oxidation treatment on the surface of the first diffusion barrier layer; wherein the second gas includes oxygen, and the gas flow range of the oxygen is 100 sccm~15000 sccm.

7. The manufacturing method according to any one of claims 1 to 4, characterized in that The step of providing the substrate comprises: Providing an initial substrate, the initial substrate spanning the array region, the transition region, and the peripheral region sequentially arranged along a first direction; Performing a patterning process on the initial substrate, with the remaining initial substrate being the substrate, to form the first contact hole in the substrate in the array region, the second contact hole in the substrate in the transition region, and the third contact hole in the substrate in the peripheral region, wherein the third contact hole extends from the top surface of the substrate into the interior of the substrate, and the hole depths of the first contact hole, the second contact hole, and the third contact hole decrease in sequence; forming the diffusion barrier film, wherein the diffusion barrier film conformally covers the inner walls of the first contact hole, the second contact hole, and the third contact hole, and is located on the top surface of the substrate; The conductive film is formed to fill the first contact hole, the second contact hole, and the third contact hole and is located on a first top surface of the diffusion barrier film away from a top surface of the substrate.

8. The manufacturing method according to claim 7, characterized in that The step of performing the cleaning treatment on the surface of the groove includes: performing a first cleaning treatment and a second cleaning treatment on the surface of the groove in sequence, wherein a cleaning liquid used in the first cleaning treatment is different from a cleaning liquid used in the second cleaning treatment.

9. The manufacturing method according to claim 7, characterized in that: After the substrate is patterned, the first diffusion barrier layer includes a first portion and a second portion, the first portion is located on the bottom surface of the conductive layer, and the second portion surrounds a portion of the sidewall of the conductive layer; After the substrate is patterned and before the exposed conductive layer is nitrided, the method further includes: performing an oxidation treatment on the first diffusion barrier layer so that at least a portion of the thickness of the second portion along a second direction is transformed into a second diffusion barrier layer, wherein the second direction is perpendicular to the first direction; A first cleaning process is performed on the surface of the groove to remove a portion of the residue, wherein an etching rate of the residue by the first cleaning process is greater than an etching rate of the second diffusion barrier layer.

10. The manufacturing method according to claim 9, characterized in that: After forming the nitride layer, performing the cleaning process on the surface of the groove includes: performing a second cleaning process on the surface of the groove to remove the residue, and a cleaning solution used in the first cleaning process is different from a cleaning solution used in the second cleaning process.

11. The manufacturing method according to claim 9, characterized in that: The second contact hole has a depth ranging from 25 nm to 35 nm.

12. A semiconductor structure, characterized in that: include: A substrate, the substrate spanning an array region and a transition region sequentially arranged along a first direction, the substrate in the array region having a first through hole extending from a top surface of the substrate into the interior of the substrate; a plurality of conductive pillars spaced apart from each other, each of the conductive pillars comprising a diffusion barrier layer and a conductive layer, the diffusion barrier layer conformally covering an inner wall of the first through-hole and a surface of the substrate covering the transition region, the conductive layer being located on a surface of the diffusion barrier layer away from the substrate, and with the bottom surface of the first through-hole as a reference surface, a second top surface of the conductive layer away from the substrate is higher than a third top surface of the diffusion barrier layer away from the substrate; The diffusion barrier layer located in the array region is a first diffusion barrier layer, or the diffusion barrier layer located in the array region includes the first diffusion barrier layer and the second diffusion barrier layer that are in contact with each other along the second direction; The diffusion barrier layer located in the transition region is the first diffusion barrier layer or the second diffusion barrier layer, or the diffusion barrier layer located in the transition region includes the first diffusion barrier layer and the second diffusion barrier layer that are in contact with each other along the second direction; The first diffusion barrier layer after oxidation treatment is the second diffusion barrier layer, and the second direction is perpendicular to the first direction; The substrate in the transition region has a second through hole extending from the top surface of the substrate into the interior of the substrate, and the depth of the first through hole is greater than the depth of the second through hole; The diffusion barrier layer covers the surface of the substrate in the transition region, including: the diffusion barrier layer conformally covers the inner wall of the second through hole, and the conductive layer completely fills the first through hole and the second through hole.

13. The semiconductor structure according to claim 12, wherein: The substrate further spans a peripheral region, the peripheral region being located on a side of the transition region away from the array region along the first direction. The substrate in the peripheral region has a third through hole extending from the top surface of the substrate into the substrate. The diffusion barrier layer conformally covers an inner wall of the third through hole. The conductive layer is located in the remaining third through hole. The depth of the first through hole is greater than that of the third through hole, or the substrate in the transition zone has a second through hole, and the depths of the first through hole, the second through hole and the third through hole decrease in sequence.

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