Power semiconductor device and method of manufacturing the same

Abstract

The application provides a power semiconductor device and a manufacturing method thereof. The manufacturing method comprises the following steps: forming a first trench in a base of a cell region and forming a second trench in a base of a terminal region; forming a first dielectric layer to cover inner walls of the first trench and the second trench; filling a first polysilicon layer into the first trench and the second trench; removing part of the first polysilicon layer and part of the first dielectric layer in the first trench, and forming an isolation layer on the remaining first polysilicon layer in the first trench; forming a second dielectric layer on a side wall of the first trench; filling a second polysilicon layer into the first trench; forming a third dielectric layer on a top surface of the base, and the third dielectric layer covers the first trench and the second trench; etching the third dielectric layer to form a first contact hole which exposes the second polysilicon layer and the first polysilicon layer in the second trench; and etching the third dielectric layer and the base around the first trench to form a second contact hole. The technical scheme of the application can avoid electrical failure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a power semiconductor device and its manufacturing method. Background Technology

[0002] As power semiconductor devices, shielded gate trench (SGT) MOS devices encounter electrical failure risks due to contact hole morphology during development, leading to electrical failure issues such as gate-source leakage current failure (IGSS fail) during electrical testing:

[0003] 1) When using a dry etching process to simultaneously etch the gate electrode in the trench and the corresponding contact hole in the body region outside the trench, the etching rate of the gate electrode, which is made of polycrystalline silicon, is faster than the etching rate of the monocrystalline silicon in the body region. As a result, when the contact hole at the corresponding position in the body region is etched to the required position, the contact hole at the corresponding position of the gate electrode has already etched through the gate electrode, which leads to increased contact resistance and leakage.

[0004] 2) The contact hole width at the corresponding position of the pressure ring in the terminal area is too large, which is prone to displacement during etching, resulting in the pressure ring width between the contact hole and the trench sidewall being too small, which in turn leads to difficulty in contact with the field plate.

[0005] Therefore, how to avoid electrical failure is an urgent problem to be solved. Summary of the Invention

[0006] The purpose of this invention is to provide a power semiconductor device and a method for manufacturing the same, which enables the avoidance of electrical failure.

[0007] To achieve the above objectives, the present invention provides a method for manufacturing a power semiconductor device, comprising:

[0008] A substrate is provided, the substrate having cellular regions and terminal regions;

[0009] A first trench is formed in the substrate of the cell region, and a second trench is formed in the substrate of the terminal region;

[0010] A first dielectric layer is formed to cover the inner walls of the first trench and the second trench;

[0011] A first polysilicon layer is filled in the first trench and the second trench;

[0012] Remove a portion of the first polysilicon layer and a portion of the first dielectric layer in the first trench, and form an isolation layer on the remaining first polysilicon layer in the first trench.

[0013] A second dielectric layer is formed on the sidewall of the first trench, and the thickness of the second dielectric layer is less than the thickness of the first dielectric layer;

[0014] A second polysilicon layer is filled into the first trench;

[0015] A third dielectric layer is formed on the top surface of the substrate, and the third dielectric layer covers the first trench and the second trench;

[0016] The third dielectric layer is etched to form a first contact hole exposing the second polysilicon layer and the first polysilicon layer in the second trench; and the third dielectric layer and the substrate surrounding the first trench are etched to form a second contact hole, the depth of the second contact hole being greater than the depth of the first contact hole.

[0017] Optionally, the top surface of the second polysilicon layer does not exceed the top surface of the first polysilicon layer in the second trench.

[0018] Optionally, the height difference between the top surface of the second polysilicon layer and the top surface of the first polysilicon layer in the second trench is 0.02μm-0.1μm.

[0019] Optionally, the width of the first contact hole is 80% to 95% of the width of the second contact hole.

[0020] Optionally, after filling the second polysilicon layer in the first trench and before forming the third dielectric layer on the top surface of the substrate, the method of manufacturing the power semiconductor device further includes:

[0021] The formed body is located in the substrate surrounding the first trench and the second trench;

[0022] A source region is formed in the body region surrounding the first trench, and the second contact hole exposes at least the body region at the bottom surface of the source region.

[0023] Optionally, the width of the second trench is greater than the width of the first trench, and the depth of the second trench is greater than the depth of the first trench.

[0024] The present invention also provides a power semiconductor device, comprising:

[0025] A substrate having a cell region and a terminal region, wherein a first trench is formed in the substrate of the cell region and a second trench is formed in the substrate of the terminal region;

[0026] A first dielectric layer is formed on the inner wall of a portion of the height of the first trench and on the entire inner wall of the second trench;

[0027] A first polysilicon layer is filled in the first trench and the second trench at a certain height, wherein the top surface of the first polysilicon layer in the second trench is higher than the top surface of the first polysilicon layer in the first trench.

[0028] An isolation layer is formed on the first polysilicon layer in the first trench;

[0029] A second dielectric layer is formed on the sidewall of the remaining height of the first trench, and the thickness of the second dielectric layer is less than the thickness of the first dielectric layer;

[0030] A second polysilicon layer is filled in the first trench;

[0031] A third dielectric layer is formed on the top surface of the substrate, and the third dielectric layer covers the first trench and the second trench;

[0032] A first contact hole and a second contact hole, wherein the first contact hole penetrates the third dielectric layer and exposes the second polysilicon layer and the first polysilicon layer in the second trench, and the second contact hole penetrates the third dielectric layer surrounding the first trench and enters the substrate, and the depth of the second contact hole is greater than the depth of the first contact hole.

[0033] Optionally, the top surface of the second polysilicon layer does not exceed the top surface of the first polysilicon layer in the second trench.

[0034] Optionally, the height difference between the top surface of the second polysilicon layer and the top surface of the first polysilicon layer in the second trench is 0.02μm-0.1μm.

[0035] Optionally, the width of the first contact hole is 80% to 95% of the width of the second contact hole.

[0036] Optionally, the power semiconductor device further includes:

[0037] The body region is formed in the substrate surrounding the first trench and the second trench;

[0038] The source region is formed in the body region surrounding the first trench, and the second contact hole exposes at least the body region at the bottom surface of the source region.

[0039] Optionally, the width of the second trench is greater than the width of the first trench, and the depth of the second trench is greater than the depth of the first trench.

[0040] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0041] 1. A method for manufacturing a power semiconductor device according to the present invention includes: providing a substrate having a cell region and a terminal region; forming a first trench in the substrate of the cell region and forming a second trench in the substrate of the terminal region; forming a first dielectric layer covering the inner walls of the first trench and the second trench; filling the first trench and the second trench with a first polysilicon layer; removing a portion of the height of the first polysilicon layer and a portion of the height of the first dielectric layer in the first trench, and forming an isolation layer on the remaining first polysilicon layer in the first trench; forming a second dielectric layer on the sidewall of the first trench, the thickness of the second dielectric layer being less than the thickness of the first dielectric layer; filling the first trench with a second polysilicon layer; and forming a third dielectric layer on the top surface of the substrate. Furthermore, the third dielectric layer covers the first trench and the second trench; the third dielectric layer is etched to form a first contact hole exposing the second polysilicon layer and the first polysilicon layer in the second trench; and the third dielectric layer and the substrate surrounding the first trench are etched to form a second contact hole, the depth of the second contact hole being greater than the depth of the first contact hole, that is, the first contact hole and the second contact hole are formed in different etching processes, which enables the second contact hole to reach the required depth while preventing the first contact hole from penetrating the second polysilicon layer, that is, preventing the second polysilicon layer from being etched through, thereby avoiding increased contact resistance and leakage current, and thus avoiding electrical failure problems such as gate-source leakage current failure during electrical testing.

[0042] 2. The power semiconductor device of the present invention comprises: a substrate having a cell region and a termination region, wherein a first trench is formed in the substrate of the cell region and a second trench is formed in the substrate of the termination region; a first dielectric layer formed on the inner wall of a portion of the height of the first trench and the entire inner wall of the second trench; a first polysilicon layer filling the first trench and the second trench at a portion of the height, wherein the top surface of the first polysilicon layer in the second trench is higher than the top surface of the first polysilicon layer in the first trench; an isolation layer formed on the first polysilicon layer in the first trench; a second dielectric layer formed on the sidewall of the remaining height of the first trench, wherein the thickness of the second dielectric layer is less than the thickness of the first dielectric layer; a second polysilicon layer filling the first trench; and a third dielectric layer formed on the substrate. The top surface, and the third dielectric layer covers the first trench and the second trench; a first contact hole and a second contact hole, the first contact hole penetrating the third dielectric layer and exposing the second polysilicon layer and the first polysilicon layer in the second trench, the second contact hole penetrating the third dielectric layer surrounding the first trench and entering the substrate, the depth of the second contact hole being greater than the depth of the first contact hole, that is, the first contact hole and the second contact hole are formed in different etching processes, so that the second contact hole reaches the required depth, while also preventing the first contact hole from penetrating the second polysilicon layer, that is, preventing the second polysilicon layer from being etched through, thereby avoiding increased contact resistance and leakage current, and thus avoiding electrical failure problems such as gate-source leakage current failure during electrical testing. Attached Figure Description

[0043] Figure 1 This is a flowchart of a method for manufacturing a power semiconductor device according to an embodiment of the present invention;

[0044] Figures 2a to 2m yes Figure 1 A schematic diagram of the device in the manufacturing method of the power semiconductor device shown.

[0045] Among them, the appendix Figures 1-2m The annotations in the attached figures are explained as follows:

[0046] 10-Substrate; 101-First trench; 102-Second trench; 103-Silicon oxide layer; 104-Silicon nitride layer; 11-First dielectric layer; 12-First polysilicon layer; 121-First patterned photoresist layer; 122-First polysilicon material layer; 13-Isolation layer; 131-Second patterned photoresist layer; 132-Isolation material layer; 14-Second dielectric layer; 15-Second polysilicon layer; 16-Third dielectric layer; 171-First contact hole; 172-Second contact hole; 181-Bulk region; 182-Source region; 19-Contact plug. Detailed Implementation

[0047] To make the objectives, advantages, and features of the present invention clearer, the power semiconductor device and its manufacturing method proposed in this invention will be further described in detail below. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0048] One embodiment of the present invention provides a method for manufacturing a power semiconductor device, see reference. Figure 1 , Figure 1 This is a flowchart of a method for manufacturing a power semiconductor device according to an embodiment of the present invention. The method for manufacturing the power semiconductor device includes:

[0049] Step S1, providing a substrate having a cellular region and a terminal region;

[0050] Step S2: Form a first trench in the substrate of the cell region and form a second trench in the substrate of the terminal region;

[0051] Step S3: Form a first dielectric layer to cover the inner walls of the first trench and the second trench;

[0052] Step S4: Fill the first polysilicon layer in the first trench and the second trench;

[0053] Step S5: Remove a portion of the first polysilicon layer and a portion of the first dielectric layer in the first trench, and form an isolation layer on the remaining first polysilicon layer in the first trench.

[0054] Step S6: A second dielectric layer is formed on the sidewall of the first trench, wherein the thickness of the second dielectric layer is less than the thickness of the first dielectric layer;

[0055] Step S7: Fill the first trench with a second polysilicon layer;

[0056] Step S8: A third dielectric layer is formed on the top surface of the substrate, and the third dielectric layer covers the first trench and the second trench;

[0057] Step S9: Etch the third dielectric layer to form a first contact hole exposing the second polysilicon layer and the first polysilicon layer in the second trench; and etch the third dielectric layer and the substrate around the first trench to form a second contact hole, the depth of the second contact hole being greater than the depth of the first contact hole.

[0058] See below. Figures 2a to 2m This embodiment provides a more detailed description of the manufacturing method of the power semiconductor device. Figures 2a to 2m It is also a schematic diagram of a longitudinal cross-section of a power semiconductor device.

[0059] According to step S1, a substrate 10 is provided, the substrate 10 having a cell region A1 and a terminal region A2.

[0060] The terminal region A2 surrounds a cell array composed of multiple cell regions A1.

[0061] The substrate 10 includes a substrate and an epitaxial layer formed on the substrate.

[0062] The substrate 10 can be made of any suitable material known to those skilled in the art, such as single-crystal silicon, silicon germanide, silicon carbide, etc.

[0063] Following step S2, as Figure 2a As shown, a first trench 101 is formed in the substrate 10 of the cell region A1, and a second trench 102 is formed in the substrate 10 of the terminal region A2.

[0064] The steps of forming the first trench 101 and the second trench 102 include: forming a patterned mask layer on the substrate 10, and etching the substrate 10 with the patterned mask layer as a mask to form the first trench 101 and the second trench 102.

[0065] The mask layer can be a single-layer structure or a structure with at least two layers, for example, Figure 2a The mask layer shown includes a silicon oxide layer 103 and a silicon nitride layer 104 sequentially covering the substrate 10. The silicon oxide layer 103 can be formed by a thermal oxidation process, and the silicon nitride layer 104 can be formed by a deposition process. The required thickness of the silicon oxide layer 103 and the silicon nitride layer 104 can be obtained by adjusting the process parameters.

[0066] After the first trench 101 and the second trench 102 are formed, the mask layer on the substrate 10 surrounding the first trench 101 and the second trench 102 can be retained, or the mask layer can be removed before the subsequent formation of the first dielectric layer 11. Figures 2b to 2m The example shown is one that retains the mask layer.

[0067] Preferably, the width of the second trench 102 is greater than the width of the first trench 101, and the depth of the second trench 102 is greater than the depth of the first trench 101, so that the voltage withstand ring subsequently formed in the second trench 102 has a larger width and a deeper depth, thereby improving the voltage withstand performance of the power semiconductor device.

[0068] Following step S3, as follows Figure 2b As shown, a first dielectric layer 11 is formed to cover the inner walls of the first trench 101 and the second trench 102.

[0069] The first dielectric layer 11 may also extend to the substrate 10 surrounding the first trench 101 and the second trench 102.

[0070] After the first trench 101 and the second trench 102 are formed, if the mask layer on the substrate 10 surrounding the first trench 101 and the second trench 102 is retained, the mask layer is sandwiched between the first dielectric layer 11 on the top surface of the substrate 10 and the substrate 10; after the first trench 101 and the second trench 102 are formed, if the mask layer is removed, the bottom surface of the first dielectric layer 11 on the top surface of the substrate 10 is in direct contact with the top surface of the substrate 10.

[0071] The first dielectric layer 11 can be made of insulating materials such as silicon oxide or silicon oxynitride.

[0072] According to step S4, as Figure 2c and Figure 2d As shown, a first polysilicon layer 12 is filled in the first trench 101 and the second trench 102.

[0073] The steps of forming the first polysilicon layer 12 may include: Figure 2c As shown, a first polysilicon material layer 122 is filled in the first trench 101 and the second trench 102, completely filling the first trench 101 and the second trench 102 and burying the first dielectric layer 11 within it. A chemical mechanical polishing process is used to planarize the first polysilicon material layer 122 until the top surface of the first dielectric layer 11 on the top surface of the substrate 10 is exposed; then, as... Figure 2d As shown, a portion of the height of the first polysilicon material layer 122 is removed until the top surface of the remaining first polysilicon material layer 122 is flush with the top surface of the substrate 10. The remaining first polysilicon material layer 122 serves as the first polysilicon layer 12.

[0074] In other embodiments, the top surface of the first polysilicon layer 12 may be slightly higher or slightly lower than the top surface of the substrate 10.

[0075] Following step S5, as follows Figures 2e to 2g As shown, a portion of the first polysilicon layer 12 and a portion of the first dielectric layer 11 in the first trench 101 are removed, and an isolation layer 13 is formed on the remaining first polysilicon layer 12 in the first trench 101.

[0076] The steps may include: Figure 2eAs shown, a first patterned photoresist layer 121 is formed on the first dielectric layer 11 and the first polysilicon layer 12. The first patterned photoresist layer 121 exposes the cell region A1. Using the first patterned photoresist layer 121 as a mask, the first polysilicon layer 12 of a portion of the height in the first trench 101 and the first dielectric layer 11 on the top surface of the substrate 10 of the cell region A1 are etched away. At this time, the silicon nitride layer 104 can serve as an etching stop layer. Then, the first patterned photoresist layer 121 is removed. Then, as... Figure 2f As shown, an isolation material layer 132 is formed and filled in the first trench 101, and the isolation material layer 132 also extends to cover the silicon nitride layer 104 of the cell region A1 and the first dielectric layer 11 and the first polysilicon layer 12 of the terminal region A2, and the isolation material layer 132 and the first dielectric layer 11 of the terminal region A2 are polished until the silicon nitride layer 104 is exposed, that is, the silicon nitride layer 104 serves as a polishing stop layer; then, as Figure 2g As shown, a second patterned photoresist layer 131 is formed, which exposes the cell region A1. Using the second patterned photoresist layer 131 as a mask, the mask layer (i.e., the silicon nitride layer 104 and the silicon oxide layer 103) on the substrate 10 of the cell region A1, as well as a portion of the height of the first dielectric layer 11 and a portion of the height of the isolation material layer 132 in the first trench 101, are etched away. The remaining isolation material layer 132 on the first polysilicon layer 12 in the first trench 101 serves as the isolation layer 13. The isolation material layer 132 on the first polysilicon layer 12 in the second trench 102 can also serve as the isolation layer 13. Then, the second patterned photoresist layer 131 is removed.

[0077] It should be noted that step S5 may not be limited to... Figures 2e to 2g In the illustrated embodiment, for example, in the above steps, when etching away a portion of the height of the first polysilicon layer 12 in the first trench 101 using the first patterned photoresist layer 121 as a mask, a portion of the height of the first dielectric layer 11 in the first trench 101 can also be etched away simultaneously. Then, when etching away the structure in the first trench 101 using the second patterned photoresist layer 131 as a mask, only a portion of the height of the isolation material layer 132 needs to be etched away, so that the isolation layer 13 formed in the first trench 101 can extend from the first polysilicon layer 12 to the first dielectric layer 11.

[0078] The material of the isolation layer 13 can be insulating materials such as silicon oxide or silicon oxynitride.

[0079] According to step S6, as Figure 2hAs shown, a second dielectric layer 14 is formed on the sidewall of the first trench 101, and the thickness of the second dielectric layer 14 is less than the thickness of the first dielectric layer 11.

[0080] The second dielectric layer 14 can be formed using a thermal oxidation process.

[0081] The second dielectric layer 14 may also extend to the top surface of the substrate 10 surrounding the first trench 101.

[0082] The material of the second dielectric layer 14 can be insulating materials such as silicon oxide or silicon oxynitride.

[0083] According to step S7, as Figure 2i As shown, a second polysilicon layer 15 is filled in the first trench 101.

[0084] The step of forming the second polysilicon layer 15 may include: filling the first trench 101 with a second polysilicon material layer (not shown), the second polysilicon material layer filling the first trench 101 and extending to the second dielectric layer 14 and the silicon nitride layer 104 on the top surface of the substrate 10, and the first dielectric layer 11 and the isolation layer 13 in the second trench 102, and etching the second polysilicon material layer until the remaining second polysilicon material layer in the first trench 101 reaches the required thickness, the remaining second polysilicon material layer serving as the second polysilicon layer 15. At this time, the silicon nitride layer 104 can be etched away, and the top of the silicon oxide layer 103, the first dielectric layer 11 and the isolation layer 13 in the second trench 102 are also partially removed, so that the top surface of the second dielectric layer 14 is flush with the top surface of the silicon oxide layer 103 and the top surface of the first dielectric layer 11 and the isolation layer 13 in the second trench 102.

[0085] At this time, the remaining first polysilicon layer 12 in the first trench 101 is used to form the shielding electrode of the transistor unit, and the second polysilicon layer 15 in the first trench 101 is used to form the gate electrode of the transistor unit. The gate electrode and the shielding electrode are isolated by the isolation layer 13. The first polysilicon layer 12 in the second trench 102 is used to form the withstand ring of the terminal structure.

[0086] Preferably, the top surface of the second polysilicon layer 15 does not exceed the top surface of the first polysilicon layer 12 in the second trench 102. This ensures that when etching to form the first contact hole 171, etching can be stopped as soon as the first contact hole 171 just exposes the top surface of the second polysilicon layer 15. This prevents the top surface of the first polysilicon layer 12 in the second trench 102 from being too low to the top surface of the second polysilicon layer 15, which would result in the first contact hole 171 penetrating the second polysilicon layer 15 when the first contact hole 171 just exposes the top surface of the first polysilicon layer 12 in the second trench 102 and etching is stopped. In other words, it prevents the second polysilicon layer 15 from being etched through.

[0087] Further preferred, such as Figure 2i As shown, the height difference h1 between the top surface of the second polysilicon layer 15 and the top surface of the first polysilicon layer 12 in the second trench 102 is 0.02μm-0.1μm, that is, the top surface of the second polysilicon layer 15 is 0.02μm-0.1μm lower than the top surface of the first polysilicon layer 12 in the second trench 102.

[0088] In other embodiments, the top surface of the second polysilicon layer 15 may be higher than the top surface of the first polysilicon layer 12 in the second trench 102. In this case, it is preferable that the top surface of the second polysilicon layer 15 is 0.02μm-0.1μm higher than the top surface of the first polysilicon layer 12 in the second trench 102, so that when the first contact hole 171 is etched to form the first contact hole 171, when the first contact hole 171 just exposes the first polysilicon layer 12 in the second trench 102 and the etching stops, the first contact hole 171 will enter the second polysilicon layer 15 but will not penetrate the second polysilicon layer 15.

[0089] like Figure 2j As shown, after filling the second polysilicon layer 15 into the first trench 101 and before forming the third dielectric layer 16 on the top surface of the substrate 10, the method of manufacturing the power semiconductor device further includes:

[0090] The forming region 181 is located in the substrate 10 surrounding the first trench 101 of the cell region A1 and in the substrate 10 surrounding the second trench 102 of the terminal region A2;

[0091] The source region 182 is formed in the body region 181 surrounding the first trench 101 of the cell region A1.

[0092] The substrate 10 and the source region 182 have the same doping type, while the source region 182 and the body region 181 have opposite doping types.

[0093] According to step S8, as Figure 2k As shown, a third dielectric layer 16 is formed on the top surface of the substrate 10, and the third dielectric layer 16 covers the first trench 101 and the second trench 102.

[0094] exist Figure 2k In the illustrated embodiment, the third dielectric layer 16 covers the second polysilicon layer 15, the second dielectric layer 14, the silicon oxide layer 103, and the first dielectric layer 11 and the isolation layer 13 in the second trench 102.

[0095] The material of the third dielectric layer 16 can be insulating materials such as silicon oxide or silicon oxynitride.

[0096] Following step S9, as Figure 2k and Figure 2l As shown, the third dielectric layer 16 is etched to form a first contact hole 171 that exposes the second polysilicon layer 15 and the first polysilicon layer 12 in the second trench 102; and the third dielectric layer 16 and the substrate 10 surrounding the first trench 101 are etched to form a second contact hole 172, the depth of the second contact hole 172 being greater than the depth of the first contact hole 171.

[0097] like Figure 2l As shown, there is a height difference h2 between the bottom surface of the second contact hole 172 and the bottom surface of the first contact hole 171, and the bottom surface of the second contact hole 172 is lower than the bottom surface of the first contact hole 171.

[0098] The second contact hole 172 exposes at least the body region 181 on the bottom surface of the source region 182, that is, the second contact hole 172 can just penetrate the source region 182 and expose the body region 181, or the second contact hole 172 can penetrate the source region 182 and enter the body region 181, so that the contact plug 19 subsequently formed in the second contact hole 172 is electrically connected to the body region 181.

[0099] Alternatively, the first contact hole 171 can be formed first, followed by the second contact hole 172; or the second contact hole 172 can be formed first, followed by the first contact hole 171.

[0100] Taking the formation of the first contact hole 171 first and then the second contact hole 172 as an example, the steps of forming the first contact hole 171 and the second contact hole 172 include: Figure 2kA third patterned photoresist layer (not shown) is formed on the cell region A1 and the terminal region A2. The third patterned photoresist layer exposes the third dielectric layer 16 above the first polysilicon layer 12 in the second trench 102 and the second polysilicon layer 15. The third dielectric layer 16 is etched using the third patterned photoresist layer as a mask to form a first contact hole 171. The first contact hole 171 on the second polysilicon layer 15 penetrates the third dielectric layer 16 and exposes the second polysilicon layer 15. The first contact hole 171 on the first polysilicon layer 12 in the second trench 102 penetrates the third dielectric layer 16 and the isolation layer 13 and enters the first polysilicon layer 12. Then, the third patterned photoresist layer is removed. Then, as... Figure 2l As shown, a fourth patterned photoresist layer (not shown) is formed on the cell region A1 and the terminal region A2. The fourth patterned photoresist layer fills the first contact hole 171. The fourth patterned photoresist layer exposes the third dielectric layer 16 above the source region 182. The third dielectric layer 16 is etched using the fourth patterned photoresist layer as a mask to form a second contact hole 172. The second contact hole 172 penetrates the third dielectric layer 16, the second dielectric layer 14, and the source region 182 and enters the body region 181. Then, the fourth patterned photoresist layer is removed.

[0101] Since the first contact hole 171 and the second contact hole 172 are formed in different etching processes, the depth of the second contact hole 172 can be greater than the depth of the first contact hole 171. This allows the second contact hole 172 to reach the required depth while preventing the first contact hole 171 from penetrating the second polysilicon layer 15, thus preventing the second polysilicon layer 15 from being etched through. This avoids increasing contact resistance and causing leakage current, and consequently avoids electrical failure problems such as gate-source leakage current failure during electrical testing.

[0102] Preferably, the width of the first contact hole 171 is 80% to 95% of the width of the second contact hole 172. That is, by modifying the layout, the width of the first contact hole 171 is 5% to 20% smaller than the width of the second contact hole 172. This avoids the first contact hole 171 being too wide, which could easily cause misalignment during etching. It also avoids the pressure ring between the first contact hole 171 and the sidewall of the second trench 102 being too narrow, thus avoiding difficulties in contact between the field plates.

[0103] like Figure 2m As shown, the manufacturing method of the power semiconductor device further includes: forming contact plugs 19 in the first contact hole 171 and the second contact hole 172.

[0104] In summary, the method for manufacturing a power semiconductor device provided by the present invention includes: providing a substrate having a cell region and a termination region; forming a first trench in the substrate of the cell region and forming a second trench in the substrate of the termination region; forming a first dielectric layer covering the inner walls of the first trench and the second trench; filling the first trench and the second trench with a first polysilicon layer; removing a portion of the height of the first polysilicon layer and a portion of the height of the first dielectric layer in the first trench, and forming an isolation layer on the remaining first polysilicon layer in the first trench; forming a second... A dielectric layer is formed on the sidewall of the first trench, and the thickness of the second dielectric layer is less than the thickness of the first dielectric layer; a second polysilicon layer is filled in the first trench; a third dielectric layer is formed on the top surface of the substrate, and the third dielectric layer covers the first trench and the second trench; the third dielectric layer is etched to form a first contact hole exposing the second polysilicon layer and the first polysilicon layer in the second trench; and the third dielectric layer and the substrate surrounding the first trench are etched to form a second contact hole, the depth of the second contact hole being greater than the depth of the first contact hole. The method for manufacturing a power semiconductor device according to the present invention can avoid electrical failure.

[0105] An embodiment of the present invention provides a power semiconductor device, comprising: a substrate having a cell region and a termination region, wherein a first trench is formed in the substrate of the cell region and a second trench is formed in the substrate of the termination region; a first dielectric layer formed on the inner wall of a portion of the height of the first trench and the entire inner wall of the second trench; a first polysilicon layer filling the first trench and the second trench at a portion of the height, wherein the top surface of the first polysilicon layer in the second trench is higher than the top surface of the first polysilicon layer in the first trench; an isolation layer formed on the first polysilicon layer in the first trench; and a second dielectric layer formed on the substrate. The remaining height of the first trench sidewall, the thickness of the second dielectric layer is less than the thickness of the first dielectric layer; a second polysilicon layer, filling the first trench; a third dielectric layer, formed on the top surface of the substrate, and the third dielectric layer covering the first trench and the second trench; a first contact hole and a second contact hole, the first contact hole penetrating the third dielectric layer and exposing the second polysilicon layer and the first polysilicon layer in the second trench, the second contact hole penetrating the third dielectric layer around the first trench and entering the substrate, the depth of the second contact hole being greater than the depth of the first contact hole.

[0106] See below. Figure 2m The power semiconductor device of this embodiment will be described in more detail.

[0107] The substrate 10 has a cell region A1 and a terminal region A2, and a first trench (i.e., ...) is formed in the substrate 10 of the cell region A1. Figure 2a The first trench 101 shown in the figure, and the second trench 102 (i.e., the first trench 101 shown in the figure) are formed in the substrate 10 of the terminal region A2. Figure 2a The second trench 102 shown in the figure.

[0108] The terminal region A2 surrounds a cell array composed of multiple cell regions A1.

[0109] The substrate 10 includes a substrate and an epitaxial layer formed on the substrate.

[0110] The substrate 10 can be made of any suitable material known to those skilled in the art, such as single-crystal silicon, silicon germanide, silicon carbide, etc.

[0111] Preferably, the width of the second trench 102 is greater than the width of the first trench 101, and the depth of the second trench 102 is greater than the depth of the first trench 101, so that the voltage-resistant ring formed in the second trench 102 has a larger width and a deeper depth, thereby improving the voltage resistance performance of the power semiconductor device.

[0112] The first dielectric layer 11 is formed on the inner wall of a portion of the height of the first trench 101 and on the entire inner wall of the second trench 102.

[0113] The first dielectric layer 11 can be made of insulating materials such as silicon oxide or silicon oxynitride.

[0114] The first polysilicon layer 12 fills a portion of the height of the first trench 101 and the second trench 102, wherein the top surface of the first polysilicon layer 12 in the second trench 102 is higher than the top surface of the first polysilicon layer 12 in the first trench 101.

[0115] Preferably, the top surface of the first polysilicon layer 12 in the second trench 102 is flush with the top surface of the substrate 10 surrounding the second trench 102. In other embodiments, the top surface of the first polysilicon layer 12 in the second trench 102 may be slightly higher or slightly lower than the top surface of the substrate 10.

[0116] The isolation layer 13 is formed on the first polysilicon layer 12 in the first trench 101.

[0117] In one embodiment, the isolation layer 13 in the first trench 101 can also extend from the first polysilicon layer 12 to the first dielectric layer 11.

[0118] In one embodiment, the isolation layer 13 may also be formed on the first polysilicon layer 12 in the second trench 102.

[0119] The material of the isolation layer 13 can be insulating materials such as silicon oxide or silicon oxynitride.

[0120] The second dielectric layer 14 is formed on the sidewall of the remaining height of the first trench 101, and the thickness of the second dielectric layer 14 is less than the thickness of the first dielectric layer 12.

[0121] In one embodiment, the second dielectric layer 14 may also extend to the top surface of the substrate 10 of the cell region A1 surrounding the first trench 101.

[0122] In one embodiment, a mask layer may also be formed on the top surface of the substrate 10 of the terminal region A2 surrounding the second trench 102, such as a mask layer. Figure 2m The silicon oxide layer 103 shown is flush with the top surfaces of the first dielectric layer 11 and the isolation layer 13 in the second trench 102.

[0123] The material of the second dielectric layer 14 can be insulating materials such as silicon oxide or silicon oxynitride.

[0124] The second polysilicon layer 15 is filled in the first trench 101.

[0125] The first polysilicon layer 12 in the first trench 101 is used to form the shielding electrode of the transistor unit, and the second polysilicon layer 15 in the first trench 101 is used to form the gate electrode of the transistor unit. The gate electrode and the shielding electrode are isolated by the isolation layer 13. The first polysilicon layer 12 in the second trench 102 is used to form the withstand ring of the terminal structure.

[0126] Preferably, the top surface of the second polysilicon layer 15 does not exceed the top surface of the first polysilicon layer 12 in the second trench 102, to ensure that the first contact hole (i.e., ...) is formed during subsequent etching. Figure 2l When etching is performed on the first contact hole 171 in the second trench 102, the etching can be stopped when the first contact hole 171 just exposes the top surface of the second polysilicon layer 15. This prevents the top surface of the first polysilicon layer 12 in the second trench 102 from being too low than the top surface of the second polysilicon layer 15, which would result in the first contact hole 171 penetrating the second polysilicon layer 15 when the first contact hole 171 just exposes the top surface of the first polysilicon layer 12 in the second trench 102 and the etching is stopped. In other words, this prevents the second polysilicon layer 15 from being etched through.

[0127] Further preferred, such as Figure 2iAs shown, the height difference h1 between the top surface of the second polysilicon layer 15 and the top surface of the first polysilicon layer 12 in the second trench 102 is 0.02μm-0.1μm, that is, the top surface of the second polysilicon layer 15 is 0.02μm-0.1μm lower than the top surface of the first polysilicon layer 12 in the second trench 102.

[0128] In other embodiments, the top surface of the second polysilicon layer 15 may be higher than the top surface of the first polysilicon layer 12 in the second trench 102. In this case, it is preferable that the top surface of the second polysilicon layer 15 is 0.02μm-0.1μm higher than the top surface of the first polysilicon layer 12 in the second trench 102, so that when the first contact hole 171 is etched to form the first contact hole 171, when the first contact hole 171 just exposes the first polysilicon layer 12 in the second trench 102 and the etching stops, the first contact hole 171 will enter the second polysilicon layer 15 but will not penetrate the second polysilicon layer 15.

[0129] The power semiconductor device further includes:

[0130] Body region 181 is formed in the substrate 10 surrounding the first trench 101 of the cell region A1 and in the substrate 10 surrounding the second trench 102 of the terminal region A2;

[0131] Source region 182 is formed in body region 181 surrounding the first trench 101 of cell region A1.

[0132] The substrate 10 and the source region 182 have the same doping type, while the source region 182 and the body region 181 have opposite doping types.

[0133] The third dielectric layer 16 is formed on the top surface of the substrate 10, and the third dielectric layer 16 covers the first trench 101 and the second trench 102.

[0134] exist Figure 2m In the illustrated embodiment, the third dielectric layer 16 covers the second polysilicon layer 15, the second dielectric layer 14, the silicon oxide layer 103, and the first dielectric layer 11 and the isolation layer 13 in the second trench 102.

[0135] The material of the third dielectric layer 16 can be insulating materials such as silicon oxide or silicon oxynitride.

[0136] The first contact hole 171 penetrates the third dielectric layer 16 and exposes the second polysilicon layer 15 and the first polysilicon layer 12 in the second trench 102, the second contact hole (i.e. Figure 2lThe second contact hole 172 penetrates the third dielectric layer 16 surrounding the first trench 101 and enters the substrate 10. The depth of the second contact hole 172 is greater than the depth of the first contact hole 171.

[0137] like Figure 2l As shown, there is a height difference h2 between the bottom surface of the second contact hole 172 and the bottom surface of the first contact hole 171, and the bottom surface of the second contact hole 172 is lower than the bottom surface of the first contact hole 171.

[0138] It should be noted that the first contact hole 171 on the second polysilicon layer 15 has the same depth as the first contact hole 171 on the first polysilicon layer 12 in the second trench 102.

[0139] The second contact hole 172 exposes at least the body region 181 on the bottom surface of the source region 182, that is, the second contact hole 172 can just penetrate the source region 182 and expose the body region 181, or the second contact hole 172 can penetrate the source region 182 and enter the body region 181, so that the contact plug 19 subsequently formed in the second contact hole 172 is electrically connected to the body region 181.

[0140] exist Figure 2m In the illustrated embodiment, the top surface of the second polysilicon layer 15 is lower than the top surface of the first polysilicon layer 12 in the second trench 102. The first contact hole 171 on the second polysilicon layer 15 just penetrates the third dielectric layer 16 and exposes the second polysilicon layer 15. The first contact hole 171 on the first polysilicon layer 12 in the second trench 102 penetrates the third dielectric layer 16 and the isolation layer 13 and enters the first polysilicon layer 12. The second contact hole 172 penetrates the third dielectric layer 16, the second dielectric layer 14 and the source region 182 and enters the body region 181.

[0141] Since the depth of the second contact hole 172 is greater than the depth of the first contact hole 171, that is, the first contact hole 171 and the second contact hole 172 are formed in different etching processes, the second contact hole 172 can reach the required depth while preventing the first contact hole 171 from penetrating the second polysilicon layer 15, that is, preventing the second polysilicon layer 15 from being etched through, thereby avoiding increased contact resistance and leakage current, and thus avoiding electrical failure problems such as gate-source leakage current failure during electrical testing.

[0142] Preferably, the width of the first contact hole 171 is 80% to 95% of the width of the second contact hole 172. That is, by modifying the layout, the width of the first contact hole 171 is 5% to 20% smaller than the width of the second contact hole 172. This avoids the first contact hole 171 being too wide, which could easily cause misalignment during etching. It also avoids the pressure ring between the first contact hole 171 and the sidewall of the second trench 102 being too narrow, thus avoiding difficulties in contact between the field plates.

[0143] The power semiconductor device further includes a contact plug 19 formed in the first contact hole 171 and the second contact hole 172.

[0144] In summary, the power semiconductor device provided by the present invention includes: a substrate having a cell region and a termination region, wherein a first trench is formed in the substrate of the cell region and a second trench is formed in the substrate of the termination region; a first dielectric layer formed on the inner wall of a portion of the height of the first trench and the entire inner wall of the second trench; a first polysilicon layer filling the first trench and the second trench at a portion of the height, wherein the top surface of the first polysilicon layer in the second trench is higher than the top surface of the first polysilicon layer in the first trench; an isolation layer formed on the first polysilicon layer in the first trench; and a second dielectric layer forming... At the sidewall of the remaining height of the first trench, the thickness of the second dielectric layer is less than the thickness of the first dielectric layer; a second polysilicon layer fills the first trench; a third dielectric layer is formed on the top surface of the substrate, and the third dielectric layer covers the first trench and the second trench; a first contact hole and a second contact hole are provided, the first contact hole penetrating the third dielectric layer and exposing the second polysilicon layer and the first polysilicon layer in the second trench, the second contact hole penetrating the third dielectric layer surrounding the first trench and entering the substrate, and the depth of the second contact hole is greater than the depth of the first contact hole. The power semiconductor device provided by the present invention can avoid electrical failure.

[0145] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for manufacturing a power semiconductor device, characterized in that, include: A substrate is provided, the substrate having cellular regions and terminal regions; A first trench is formed in the substrate of the cell region, and a second trench is formed in the substrate of the terminal region; A first dielectric layer is formed to cover the inner walls of the first trench and the second trench; A first polysilicon layer is filled in the first trench and the second trench; Remove a portion of the first polysilicon layer and a portion of the first dielectric layer in the first trench, and form an isolation layer on the remaining first polysilicon layer in the first trench. A second dielectric layer is formed on the sidewall of the first trench, and the thickness of the second dielectric layer is less than the thickness of the first dielectric layer; A second polysilicon layer is filled into the first trench; A third dielectric layer is formed on the top surface of the substrate, and the third dielectric layer covers the first trench and the second trench; The third dielectric layer is etched to form a first contact hole that exposes the second polysilicon layer and the first polysilicon layer in the second trench, the first contact hole not penetrating the second polysilicon layer; and the third dielectric layer and the substrate surrounding the first trench are etched to form a second contact hole, the depth of the second contact hole being greater than the depth of the first contact hole, and the width of the first contact hole being 80% to 95% of the width of the second contact hole.

2. The method for manufacturing a power semiconductor device as described in claim 1, characterized in that, The top surface of the second polysilicon layer does not exceed the top surface of the first polysilicon layer in the second trench.

3. The method for manufacturing a power semiconductor device as described in claim 2, characterized in that, The height difference between the top surface of the second polysilicon layer and the top surface of the first polysilicon layer in the second trench is 0.02μm-0.1μm.

4. The method for manufacturing a power semiconductor device as described in claim 1, characterized in that, After filling the second polysilicon layer in the first trench and before forming the third dielectric layer on the top surface of the substrate, the method of manufacturing the power semiconductor device further includes: The formed body is located in the substrate surrounding the first trench and the second trench; A source region is formed in the body region surrounding the first trench, and the second contact hole exposes at least the body region at the bottom surface of the source region.

5. The method for manufacturing a power semiconductor device as described in claim 1, characterized in that, The width of the second groove is greater than the width of the first groove, and the depth of the second groove is greater than the depth of the first groove.

6. A power semiconductor device, characterized in that, include: A substrate having a cell region and a terminal region, wherein a first trench is formed in the substrate of the cell region and a second trench is formed in the substrate of the terminal region; A first dielectric layer is formed on the inner wall of a portion of the height of the first trench and on the entire inner wall of the second trench; A first polysilicon layer is filled in the first trench and the second trench at a certain height, wherein the top surface of the first polysilicon layer in the second trench is higher than the top surface of the first polysilicon layer in the first trench. An isolation layer is formed on the first polysilicon layer in the first trench; A second dielectric layer is formed on the sidewall of the remaining height of the first trench, and the thickness of the second dielectric layer is less than the thickness of the first dielectric layer; A second polysilicon layer is filled in the first trench; A third dielectric layer is formed on the top surface of the substrate, and the third dielectric layer covers the first trench and the second trench; A first contact hole and a second contact hole, wherein the first contact hole penetrates the third dielectric layer and exposes the second polysilicon layer and the first polysilicon layer in the second trench, the first contact hole does not penetrate the second polysilicon layer, and the second contact hole penetrates the third dielectric layer surrounding the first trench and enters the substrate, the depth of the second contact hole is greater than the depth of the first contact hole, and the width of the first contact hole is 80% to 95% of the width of the second contact hole.

7. The power semiconductor device as described in claim 6, characterized in that, The top surface of the second polysilicon layer does not exceed the top surface of the first polysilicon layer in the second trench.

8. The power semiconductor device as described in claim 7, characterized in that, The height difference between the top surface of the second polysilicon layer and the top surface of the first polysilicon layer in the second trench is 0.02μm-0.1μm.

9. The power semiconductor device as described in claim 6, characterized in that, The power semiconductor device further includes: The body region is formed in the substrate surrounding the first trench and the second trench; The source region is formed in the body region surrounding the first trench, and the second contact hole exposes at least the body region at the bottom surface of the source region.

10. The power semiconductor device as claimed in claim 6, characterized in that, The width of the second groove is greater than the width of the first groove, and the depth of the second groove is greater than the depth of the first groove.

Images