Adapter plate structure and manufacturing method thereof, and packaging structure and manufacturing method thereof

Abstract

The embodiment of the invention provides an adapter plate structure and a manufacturing method thereof, and a packaging structure and a manufacturing method thereof. The adapter plate structure comprises a first adapter plate core particle which comprises a first sub-rewiring structure and a second sub-rewiring structure connected with the first sub-rewiring structure; the sub-adapter plate is arranged on one side of the first adapter plate core particle, comprises a first substrate and is provided with a first surface and a second surface which are opposite to each other; the first conductive column is arranged in the first substrate and penetrates through the first substrate, and the first conductive column is provided with a first end and a second end which are opposite; the third rewiring structure is arranged on the first surface, and the first end of the first conductive column is connected with the third rewiring structure; the third re-wiring structure is located between the second sub-re-wiring structure and the first substrate and is connected with the second sub-re-wiring structure; the bump is arranged on the second surface, and the second end of the first conductive column is connected with the bump; wherein the orthographic projection size of the first adapter plate core grain on the third rewiring structure is smaller than the size of the third rewiring structure.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a transfer board structure and manufacturing method, and a packaging structure and manufacturing method. Background Art

[0002] At present, different chips, such as radio frequency chips, logic chips, micro-electro-mechanical system (MEMS) chips and memory chips, can be integrated into an independent system to realize the functions of transmitting and receiving signals. In the packaging structure, these different chips can be arranged on the adapter plate structure and electrically connected to the adapter plate structure. However, different chips require different numbers of wiring layers, and the current adapter plate structure cannot meet the use requirements.

[0003] Therefore, there is an urgent need to improve the structure of the adapter plate. Summary of the invention

[0004] In view of this, embodiments of the present disclosure provide a transfer board structure and manufacturing method and a packaging structure and manufacturing method.

[0005] To achieve the above objectives, the technical solution of the present disclosure is implemented as follows:

[0006] In a first aspect, an embodiment of the present disclosure provides an adapter board structure, the adapter board structure comprising: a first adapter board core particle, comprising a first sub-rewiring structure and a second sub-rewiring structure connected to the first sub-rewiring structure; a sub-adapter board arranged on one side of the first adapter board core particle, comprising: a first substrate, having a first surface and a second surface relative to each other; a first conductive column arranged in and passing through the first substrate, the first conductive column having a first end and a second end relative to each other; a third rewiring structure arranged on the first surface, the first end of the first conductive column being connected to the third rewiring structure; the third rewiring structure is located between the second sub-rewiring structure and the first substrate and connected to the second sub-rewiring structure; a bump arranged on the second surface, the second end of the first conductive column being connected to the bump; wherein the orthographic projection size of the first adapter board core particle on the third rewiring structure is smaller than the size of the third rewiring structure.

[0007] In some embodiments, the first sub-rewiring structure and the second sub-rewiring structure each include a first surface and a second surface relative to each other, wherein the first surface of the first sub-rewiring structure is bonded to the first surface of the second sub-rewiring structure, and the second surface of the second sub-rewiring structure is connected to the third rewiring structure.

[0008] In some embodiments, the first adapter board core particle also includes: a second substrate disposed between the first sub-rewiring structure and the second sub-rewiring structure; a second conductive column disposed in and passing through the second substrate, the second conductive column having a first end and a second end opposite to each other; the first end of the second conductive column is connected to the first sub-rewiring structure, and the second end of the second conductive column is connected to the second sub-rewiring structure.

[0009] In some embodiments, the first sub-rewiring structure includes a first dielectric layer and at least one first wiring layer arranged in the first dielectric layer, the second sub-rewiring structure includes a second dielectric layer and at least one second wiring layer arranged in the second dielectric layer, and the third rewiring structure includes a third dielectric layer and at least one third wiring layer arranged in the third dielectric layer; the adapter board structure includes a first area and a second area, the first area is the positive projection area of ​​the first adapter board core particle on the third rewiring structure, and the second area is other areas of the adapter board structure except the first area; wherein the number of wiring layers in the first area is greater than the number of wiring layers in the second area.

[0010] In some embodiments, the sub-adapter board further includes: a fourth rewiring structure disposed between the first substrate and the bump, wherein the fourth rewiring structure connects the second end of the first conductive column and the bump.

[0011] In some embodiments, the adapter board structure also includes: a second adapter board core particle arranged on the side of the first adapter board core particle away from the sub-adapter board, the second adapter board core particle includes a third sub-rewiring structure and a fourth sub-rewiring structure connected to the third sub-rewiring structure, the fourth sub-rewiring structure is located between the first sub-rewiring structure and the third sub-rewiring structure and is connected to the first sub-rewiring structure; wherein the orthographic projection size of the second adapter board core particle on the first adapter board core particle is smaller than the size of the first adapter board core particle.

[0012] In a second aspect, an embodiment of the present disclosure provides a method for manufacturing an adapter board structure, the method comprising: providing an initial adapter board, the initial adapter board comprising a first rewiring structure and a second rewiring structure connected to the first rewiring structure; cutting the initial adapter board to obtain a plurality of adapter board core particles; the first rewiring structure is cut to form a first sub-rewiring structure, and the second rewiring structure is cut to form a second sub-rewiring structure; the plurality of adapter board core particles include a first adapter board core particle, the first adapter board core particle includes the first sub-rewiring structure and the second sub-rewiring structure connected to the first sub-rewiring structure; providing a sub-adapter board, the sub-adapter board comprising: a first substrate having There are a first surface and a second surface relative to each other; a first conductive column arranged in the first substrate and passing through the first substrate, the first conductive column having a first end and a second end relative to each other; a third rewiring structure arranged on the first surface, the first end of the first conductive column being connected to the third rewiring structure; a bump arranged on the second surface, the second end of the first conductive column being connected to the bump; the first adapter board core particle is arranged on one side of the sub-adapter board, the third rewiring structure is located between the second sub-rewiring structure and the first substrate and is connected to the second sub-rewiring structure; wherein the orthographic projection size of the first adapter board core particle on the third rewiring structure is smaller than the size of the third rewiring structure.

[0013] In some embodiments, the first rewiring structure is cut to form a third sub-rewiring structure, and the second rewiring structure is cut to form a fourth sub-rewiring structure; the plurality of adapter board core particles also include a second adapter board core particle, and the second adapter board core particle includes the third sub-rewiring structure and a fourth sub-rewiring structure connected to the third sub-rewiring structure; the second adapter board core particle is arranged on the side of the first adapter board core particle away from the sub-adapter board, and the fourth sub-rewiring structure is located between the first sub-rewiring structure and the third sub-rewiring structure and is connected to the first sub-rewiring structure; wherein the orthographic projection size of the second adapter board core particle on the first adapter board core particle is smaller than the size of the first adapter board core particle.

[0014] In a third aspect, an embodiment of the present disclosure provides a packaging structure, which includes: an adapter board structure as in the above technical solution; a first chip disposed on one side of the sub-adapter board and connected to the third redistribution structure; and a second chip disposed on a side of the first adapter board core particle away from the sub-adapter board and connected to the first sub-redistribution structure.

[0015] In a fourth aspect, an embodiment of the present disclosure provides a method for manufacturing a packaging structure, the method comprising: providing an initial adapter board, the initial adapter board comprising a first rewiring structure and a second rewiring structure connected to the first rewiring structure; cutting the initial adapter board to obtain a plurality of adapter board core particles; the first rewiring structure is cut to form a first sub-rewiring structure, and the second rewiring structure is cut to form a second sub-rewiring structure; the plurality of adapter board core particles include a first adapter board core particle, the first adapter board core particle includes the first sub-rewiring structure and a second sub-rewiring structure connected to the first sub-rewiring structure; providing a first substrate, a first conductive column disposed in the first substrate and passing through the first substrate, and a third rewiring structure disposed on one side of the substrate, the first substrate having a first surface and a second surface opposite to each other, the first conductive column being The column has a first end and a second end opposite to each other, and the first end of the first conductive column is connected to the third rewiring structure; the second surface of the first substrate is bonded to a carrier substrate; the first adapter board core particle is arranged on the side of the third rewiring structure away from the first substrate, and the third rewiring structure is located between the second sub-rewiring structure and the first substrate and connected to the second sub-rewiring structure; the first chip is arranged on the side of the third rewiring structure away from the first substrate, and the third rewiring structure is connected to the first chip; the second chip is arranged on the side of the first adapter board core particle away from the third rewiring structure, and the first sub-rewiring structure is connected to the second chip; the second surface of the first substrate and the carrier substrate are debonded; a bump is formed on the second surface of the first substrate, and the second end of the first conductive column is connected to the bump.

[0016] The disclosed embodiments provide an adapter plate structure and manufacturing method and a packaging structure and manufacturing method. In the disclosed embodiments, a first adapter plate core particle is arranged on one side of a sub-adapter plate, and the first adapter plate core particle includes a first sub-rewiring structure and a second sub-rewiring structure connected to each other, and the sub-adapter plate includes a first substrate, a first conductive column, a third rewiring structure and a bump, so that the second sub-rewiring structure and the third rewiring structure are connected, thereby forming a first area with a larger number of wiring layers and a second area with a smaller number of wiring layers. In this way, the adapter plate structure can simultaneously meet the different requirements of different chips for different numbers of wiring layers, so as to solve the quality problems such as warping and delamination of the adapter plate structure caused by the large number of wiring layers, and can also directly connect the first adapter plate core particle and the sub-adapter plate to reduce the process difficulty. In addition, the packaging structure obtained by manufacturing the above-mentioned adapter plate structure can enable different chips to form a three-dimensional vertical stacking arrangement, improve the integration of the packaging structure, and reduce the packaging area. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1A schematic diagram of a packaging structure provided for a related technical solution;

[0018] Figure 2A Schematic diagram of the adapter plate structure provided in the embodiment of the present disclosure Figure 1 ;

[0019] Figure 2B Schematic diagram 2 of the adapter plate structure provided in the embodiment of the present disclosure;

[0020] Figure 2C Schematic diagram of the adapter plate structure provided in the embodiment of the present disclosure Figure 3 ;

[0021] Figure 3 A schematic diagram of a process for manufacturing a transfer plate structure provided by an embodiment of the present disclosure;

[0022] Figure 4 A schematic diagram of a process for manufacturing a packaging structure provided by an embodiment of the present disclosure;

[0023] FIG. 5A to FIG. 5G A cross-sectional view of the packaging structure provided in an embodiment of the present disclosure during the manufacturing process.

[0024] The figure includes: 100, packaging structure; 102, packaging substrate; 104, adapter board structure; 106, substrate; 108, conductive pillar; 110, bump; 112, RF chip; 114, logic chip; 116, micro-electromechanical system chip; 118, memory chip; 200a, adapter board structure; 200b, adapter board structure; 200c, adapter board structure; 202a, first adapter board core grain; 202b, first adapter board core grain; 204, first sub-rewiring structure; 206, first dielectric layer; 208, first wiring layer; 210, second sub-rewiring structure; 212, second dielectric layer; 214, second wiring layer; 216a, sub-adapter board; 216b, sub-adapter board; 218 , first substrate; 220, first conductive pillar; 222, bump; 224, third redistribution structure; 226, third dielectric layer; 228, third wiring layer; 230, second substrate; 232, second conductive pillar; 234, fourth redistribution structure; 236, fourth dielectric layer; 238, fourth wiring layer; 240, second adapter core; 242, third sub-redistribution structure; 244, fourth sub-redistribution structure; 500, packaging structure; 502, initial adapter; 504, first redistribution structure; 506, second redistribution structure; 508, carrier substrate; 510, bonding layer; 512, first chip; 514, first filling layer; 516, second chip; 518, second filling layer. DETAILED DESCRIPTION

[0025] The following will be combined with the embodiments of the present disclosure and the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0026] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0027] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0028] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0029] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0030] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0031] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but in addition to these detailed descriptions, the present disclosure may also have other implementations.

[0032] refer to Figure 1 , Figure 1 A schematic diagram of a packaging structure provided by a related technical solution. Figure 1 As shown, the packaging structure 100 includes: a packaging substrate 102; an adapter plate structure 104 arranged on the packaging substrate 102, the adapter plate structure 104 includes a base 106, a conductive column 108 arranged in the base 106, the first end of the conductive column 108 is electrically connected to the chip, and the second end of the conductive column 108 is connected to the packaging substrate 102 through a bump 110; a radio frequency chip 112, a logic chip 114, a micro-electromechanical system chip 116 and a memory chip 118 arranged on the adapter plate structure 104.

[0033] 2.5D packaging is to place RF chips, logic chips, MEMS chips and memory chips horizontally on an adapter board structure (also called an interposer) to achieve high-density line connection. However, different chips require different numbers of wiring layers. Among them, logic chips, MEMS chips and memory chips have lower requirements for the number of wiring layers, while the transmission of RF signals in RF chips requires cross-layers, and RF chips have higher requirements for the number of wiring layers. Setting one area of ​​the adapter board structure as an area with a large number of wiring layers and setting another area as an area with a small number of wiring layers is a setting method for the adapter board structure that is more difficult in terms of process. In addition, the large number of wiring layers can easily cause greater stress, resulting in quality problems such as warping and delamination of the adapter board structure.

[0034] In view of this, embodiments of the present disclosure provide a transfer board structure and manufacturing method and a packaging structure and manufacturing method.

[0035] refer to FIG. 2A to FIG. 2C , FIG. 2A to FIG. 2C This is a schematic diagram of the adapter plate structure provided in the embodiment of the present disclosure. FIG. 2A to FIG. 2C , the adapter plate structure is described in detail.

[0036] like Figure 2A As shown, an embodiment of the present disclosure provides an adapter plate structure, and the adapter plate structure 200a includes: a first adapter plate core particle 202a, including a first sub-rewiring structure 204 and a second sub-rewiring structure 210 connected to the first sub-rewiring structure 204. The first sub-rewiring structure 204 includes a first dielectric layer 206 and a first wiring layer 208 disposed in the first dielectric layer 206; the second sub-rewiring structure 210 includes a second dielectric layer 212 and a second wiring layer 214 disposed in the second dielectric layer 212.

[0037] Here, the first transfer board core particle may have different structures. In some embodiments, the first transfer board core particle may include a first sub-rewiring structure and a second sub-rewiring structure bonded to each other, referring to Figure 2A In some other embodiments, the first transfer board core may include a first sub-rewiring structure, a second sub-rewiring structure, and a second conductive column for connecting the first sub-rewiring structure and the second sub-rewiring structure, referring to Figure 2B shown.

[0038] In some embodiments, Figure 2AAs shown, the first transfer board core particle 202a may include: a first sub-rewiring structure 204 and a second sub-rewiring structure 210 bonded to each other. The first sub-rewiring structure 204 has a first surface and a second surface opposite to each other, and the second sub-rewiring structure 210 also has a first surface and a second surface opposite to each other, and the first surface of the first sub-rewiring structure 204 and the first surface of the second sub-rewiring structure 210 are bonded to each other.

[0039] In other embodiments, Figure 2B As shown, the first transfer board core particle 202b may include: a first sub-rewiring structure 204, a second sub-rewiring structure 210, and a second substrate 230 located between the first sub-rewiring structure 204 and the second sub-rewiring structure 210, and a second conductive pillar 232 disposed in the second substrate 230 and penetrating the second substrate 230. The second substrate 230 has a first surface and a second surface opposite to each other, the second conductive pillar 232 has a first end and a second end opposite to each other, the first surface of the second substrate 230 exposes the first end of the second conductive pillar 232, and the second surface of the second substrate 230 exposes the second end of the second conductive pillar 232. The first sub-rewiring structure 204 is disposed on the first surface of the second substrate 230, and the first end of the second conductive pillar 232 is electrically connected to the first sub-rewiring structure 204. The second sub-rewiring structure 210 is also disposed on the second surface of the second substrate 230, and the second end of the second conductive pillar 232 is electrically connected to the second sub-rewiring structure 210.

[0040] Here, the second conductive pillar 232 extends along the thickness direction of the second substrate 230, and the second conductive pillar 232 penetrates the second substrate 230 along the extension direction. The second conductive pillar 232 may also be referred to as a through-silicon via (TSV) structure. The present disclosure does not specifically limit the size and number of the second conductive pillars 232 provided in the second substrate 230, and may be selected according to actual needs.

[0041] Here, the material of the second substrate 230 may include, but is not limited to, silicon material. The material of the second conductive pillar 232 may include, but is not limited to, conductive materials, such as metal materials, for example, titanium, copper, aluminum, gold, tin, and nickel. The present disclosure has no particular limitation on the materials of the second substrate 230 and the second conductive pillar 232, and they can be selected according to actual needs.

[0042] Here, the first sub-rewiring structure 204 and the second sub-rewiring structure 210 can respectively transmit signals through the first wiring layer 208 and the second wiring layer 214. The materials of the first dielectric layer 206 and the second dielectric layer 212 can include but are not limited to silicon oxide. The materials of the first wiring layer 208 and the second wiring layer 214 can include but are not limited to metal materials, such as copper. The present disclosure has no special restrictions on the manufacturing method, materials and number of wiring layers of the first sub-rewiring structure 204 and the second sub-rewiring structure 210, which can be selected according to actual needs.

[0043] Here, the sub-interposer may have different structures. In some embodiments, the sub-interposer may include a third redistribution structure, a bump, and a first conductive column for connecting the third redistribution structure and the bump, referring to Figure 2A In some other embodiments, the sub-adapter board may include a third rewiring structure, a fourth rewiring structure, and a first conductive column for connecting the third rewiring structure and the fourth rewiring structure. The fourth rewiring structure is further provided with a bump on a side away from the first conductive column. Figure 2B shown.

[0044] In some embodiments, Figure 2A As shown, the sub-adapter board 216a includes: a first substrate 218, having a first surface and a second surface relative to each other; a first conductive column 220 disposed in and penetrating the first substrate 218, the first conductive column 220 having a first end and a second end relative to each other, the first surface of the first substrate 218 exposing the first end of the first conductive column 220 and the second surface of the first substrate 218 exposing the second end of the first conductive column 220; a third rewiring structure 224 disposed on the first surface of the first substrate 218, the first end of the first conductive column 220 and the third rewiring structure 224 being electrically connected; a bump 222 disposed on the second surface of the first substrate 218, the second end of the first conductive column 220 and the bump 222 being electrically connected.

[0045] Here, the first conductive pillar 220 extends along the thickness direction of the first substrate 218, and the first conductive pillar 220 penetrates the first substrate 218 along the extension direction. The first conductive pillar 220 can also be called a TSV structure. The present disclosure has no special restrictions on the size and number of the first conductive pillars 220 provided in the first substrate 218, which can be selected according to actual needs.

[0046] Here, the material of the first substrate 218 may include but is not limited to silicon material. The material of the first conductive pillar 220 may include but is not limited to conductive material, such as metal material. The present disclosure has no special limitation on the materials of the first substrate 218 and the first conductive pillar 220, and they can be selected according to actual needs.

[0047] Here, the bumps 222 may include solder balls.

[0048] In other embodiments, Figure 2B As shown, the sub-adapter board 216b includes: a first substrate 218, the first substrate 218 has a first surface and a second surface opposite to each other; a first conductive column 220 disposed in the first substrate 218 and penetrating the first substrate 218, the first conductive column 220 has a first end and a second end opposite to each other, that is, the first surface of the first substrate 218 exposes the first end of the first conductive column 220 and the second surface of the first substrate 218 exposes the second end of the first conductive column 220; a third rewiring structure 224 disposed on the first surface of the first substrate 218, The first end of the first conductive column 220 is electrically connected to the third rewiring structure 224; and the fourth rewiring structure 234 is arranged on the second surface of the first substrate 218, and the second end of the first conductive column 220 is electrically connected to the fourth rewiring structure 234; the bump 222 is arranged on the side of the fourth rewiring structure 234 away from the first conductive column 220, that is, the fourth rewiring structure 234 is located between the first substrate 218 and the bump 222, and the fourth rewiring structure 234 electrically connects the second end of the first conductive column 220 and the bump 222.

[0049] Here, the third rewiring structure 224 may include a third dielectric layer 226 and a third wiring layer 228 disposed in the third dielectric layer 226, and the fourth rewiring structure 234 may include a fourth dielectric layer 236 and a fourth wiring layer 238 disposed in the fourth dielectric layer 236. The third rewiring structure 224 and the fourth rewiring structure 234 may respectively transmit signals through the third wiring layer 228 and the fourth wiring layer 238. The materials of the third dielectric layer 226 and the fourth dielectric layer 236 may include but are not limited to silicon oxide. The materials of the third wiring layer 228 and the fourth wiring layer 238 may include but are not limited to metal materials, such as copper. The present disclosure does not specifically limit the manufacturing method, materials, and number of wiring layers of the third rewiring structure 224 and the fourth rewiring structure 234, and can be selected according to actual needs.

[0050] Still Figure 2A As shown, the adapter board structure 200a may include: a first adapter board core particle 202a and a sub-adapter board 216a arranged on one side of the first adapter board core particle 202a, and the second sub-rewiring structure 210 in the first adapter board core particle 202a and the third rewiring structure 224 in the sub-adapter board 216a are electrically connected; wherein, the second sub-rewiring structure 210 is located between the first sub-rewiring structure 204 and the third rewiring structure 224, and the orthographic projection size of the first adapter board core particle 202a on the third rewiring structure 224 is smaller than the size of the third rewiring structure 224.

[0051] Here, the first adapter plate core particle and the sub-adapter plate may be connected to each other by bonding, for example, hybrid bonding.

[0052] Here, at least one first adapter board core particle may be disposed on the sub-adapter board. Of course, two, three or even more first adapter board core particles may be disposed on the sub-adapter board. The present disclosure does not specifically limit the number of first adapter board core particles disposed on the sub-adapter board.

[0053] Here, the orthographic projection size of the first transfer board core particle on the third redistribution structure is smaller than the size of the third redistribution structure. At this time, there is still free space on the third redistribution structure for arranging chips to form a packaging structure.

[0054] Here, the transfer board structure can be divided into a first area and a second area, the first area is the positive projection area of ​​the first transfer board core grain on the third rewiring structure, and the second area is other areas in the transfer board structure except the first area; wherein the number of wiring layers in the first area includes the sum of the number of wiring layers in the first sub-rewiring structure, the second sub-rewiring structure and the third rewiring structure, and the number of wiring layers in the second area includes the number of wiring layers in the third rewiring structure. Therefore, the number of wiring layers in the first area is greater than the number of wiring layers in the second area.

[0055] In the disclosed embodiment, the first adapter board core particle is arranged on one side of the sub-adapter board, the first adapter board core particle includes at least a first sub-rewiring structure and a second sub-rewiring structure, and the sub-adapter board includes at least a first substrate, a first conductive column, a third rewiring structure and a bump, so that the second sub-rewiring structure and the third rewiring structure are connected, thereby forming a first area with a larger number of wiring layers and a second area with a smaller number of wiring layers. In this way, the adapter board structure can simultaneously meet the different requirements of different chips for the number of wiring layers, so as to solve the quality problems such as warping and delamination of the adapter board structure caused by the large number of wiring layers, and the first adapter board core particle and the sub-adapter board can also be directly connected to reduce the process difficulty.

[0056] like Figure 2B As shown, the adapter board structure 200b may include: a first adapter board core particle 202b and a sub-adapter board 216b, the first adapter board core particle 202b includes a first sub-rewiring structure 204, a second sub-rewiring structure 210 and a second conductive column 232 for connecting the first sub-rewiring structure 204 and the second sub-rewiring structure 210; the sub-adapter board 216b includes a third rewiring structure 224, a fourth rewiring structure 234, a first conductive column 220 for connecting the third rewiring structure 224 and the fourth rewiring structure 234, and a bump 222 connected to the fourth rewiring structure 234.

[0057] Here, the adapter plate structure may have different structures, and the first adapter plate core particles with different structures and the sub-adapter plates with different structures are stacked. In some embodiments, Figure 2A It is shown that the first adapter board core particle without the second conductive column is arranged on the sub-adapter board without the fourth redistribution structure. In some other embodiments, the first adapter board core particle without the second conductive column can also be arranged on the sub-adapter board with the fourth redistribution structure. In some embodiments, Figure 2B The diagram shows that the first adapter board core particle with the second conductive column is disposed on the sub-adapter board with the fourth redistribution structure. In other embodiments, the first adapter board core particle with the second conductive column can also be disposed on the sub-adapter board without the fourth redistribution structure.

[0058] like Figure 2C As shown, the adapter board structure 200c also includes: a second adapter board core particle 240 arranged on the side of the first adapter board core particle 202a away from the sub-adapter board 216b, that is, the first adapter board core particle 202a is located between the sub-adapter board 216b and the second adapter board core particle 240; the second adapter board core particle 240 includes a third sub-rewiring structure 242 and a fourth sub-rewiring structure 244 connected to the third sub-rewiring structure 242, and the fourth sub-rewiring structure 244 is located between the first sub-rewiring structure 204 and the third sub-rewiring structure 242 and is connected to the first sub-rewiring structure 204; wherein, the orthographic projection size of the second adapter board core particle 240 on the first adapter board core particle 202a is smaller than the size of the first adapter board core particle 202a.

[0059] Here, the orthographic projection size of the second adapter board core particle on the third rewiring structure is smaller than the orthographic projection size of the first adapter board core particle on the third rewiring structure. At this time, there is still free space on the first adapter board core particle for arranging chips to form a packaging structure.

[0060] In the disclosed embodiment, the first adapter board core particle and the second adapter board core particle are stacked and arranged on the sub-adapter board, the number of wiring layers in the orthographic projection area of ​​the second adapter board core particle includes the sum of the number of wiring layers in the third sub-rewiring structure, the fourth sub-rewiring structure, the first sub-rewiring structure, the second sub-rewiring structure and the third rewiring structure; the number of wiring layers in the orthographic projection area of ​​the first adapter board core particle includes the sum of the number of wiring layers in the first sub-rewiring structure, the second sub-rewiring structure and the third rewiring structure; the number of wiring layers in the orthographic projection area of ​​the sub-adapter board includes the number of wiring layers in the third rewiring structure. Therefore, the adapter board structure can simultaneously meet the different requirements of different chips for the number of wiring layers, so as to solve the quality problems such as warping and delamination of the adapter board structure caused by the large number of wiring layers.

[0061] Here, the second adapter plate core particle may have a different structure. In some embodiments, the second adapter plate core particle may include a third sub-rewiring structure and a fourth sub-rewiring structure bonded to each other. In other embodiments, the second adapter plate core particle may include a third sub-rewiring structure, a fourth sub-rewiring structure, a third substrate disposed between the third sub-rewiring structure and the fourth sub-rewiring structure, and a third conductive column disposed in the third substrate and passing through the third substrate. Among them, the third substrate has a first surface and a second surface relative to each other, the third conductive column has a first end and a second end relative to each other, the first surface of the third substrate exposes the first end of the third conductive column, and the first end of the third conductive column is connected to the third sub-rewiring structure; the second surface of the third substrate exposes the second end of the third conductive column, and the second end of the third conductive column is connected to the fourth sub-rewiring structure.

[0062] Here, the first interposer die and the second interposer die may have different stacking arrangements. Figure 2C The diagram shows a first adapter board core particle without a second conductive column and a second adapter board core particle without a third conductive column being stacked. In other embodiments, the first adapter board core particle without a second conductive column and the second adapter board core particle with a third conductive column can also be stacked; or, the first adapter board core particle with a second conductive column and the second adapter board core particle without a third conductive column can be stacked; or, the first adapter board core particle with a second conductive column and the second adapter board core particle with a third conductive column can be stacked.

[0063] Figure 2A and Figure 2B It shows that a first adapter board core particle is set on the sub-adapter board. Figure 2C The diagram shows that the first adapter board core particles and the second adapter board core particles are stacked on the sub-adapter board. In fact, the present disclosure has no special limitation on the number of adapter board core particles stacked on the sub-adapter board, and the number can be selected according to actual needs.

[0064] refer to Figure 3 , Figure 3 The flowchart of the manufacturing method of the adapter plate structure provided by the embodiment of the present disclosure is as follows. Figure 3 As shown, an embodiment of the present disclosure provides a method for manufacturing an adapter plate structure, the method comprising:

[0065] Step S301: providing an initial adapter board, the initial adapter board comprising a first rewiring structure and a second rewiring structure connected to the first rewiring structure;

[0066] Step S302: cutting the initial adapter board to obtain a plurality of adapter board core particles; the first redistribution structure is cut to form a first sub-redistribution structure, and the second redistribution structure is cut to form a second sub-redistribution structure; the plurality of adapter board core particles include a first adapter board core particle, and the first adapter board core particle includes a first sub-redistribution structure and a second sub-redistribution structure connected to the first sub-redistribution structure;

[0067] Step S303: providing a sub-adapter board, the sub-adapter board comprising: a first substrate having a first surface and a second surface opposite to each other; a first conductive column disposed in and penetrating the first substrate, the first conductive column having a first end and a second end opposite to each other; a third redistribution structure disposed on the first surface, the first end of the first conductive column being connected to the third redistribution structure; and a bump disposed on the second surface, the second end of the first conductive column being connected to the bump;

[0068] Step S304: The first adapter board core particle is set on one side of the sub-adapter board, and the third redistribution structure is located between the second sub-redistribution structure and the first substrate and connected to the second sub-redistribution structure; wherein the orthographic projection size of the first adapter board core particle on the third redistribution structure is smaller than the size of the third redistribution structure.

[0069] Exemplarily, the formation of a first transfer board core particle without a second conductive column is taken as an example for explanation. Here, in step S301, forming an initial transfer board may include the following steps: forming a first rewiring structure on a first wafer, the first rewiring structure including a first surface and a second surface relative to each other, the first surface of the first rewiring structure being away from the first wafer, and the second surface of the first rewiring structure being close to the first wafer; thinning the first wafer to retain the first rewiring structure; forming a second rewiring structure on a second wafer, the second rewiring structure including a first surface and a second surface relative to each other, the first surface of the second rewiring structure being away from the second wafer, and the second surface of the second rewiring structure being close to the second wafer; thinning the second wafer to retain the second rewiring structure; bonding the first surface of the first rewiring structure to the first surface of the second rewiring structure.

[0070] In step S302, the initial adapter board can be cut along a direction perpendicular to the first rewiring structure to obtain a first adapter board core particle; wherein the size of the first sub-rewiring structure is smaller than the first rewiring structure, and the size of the second sub-rewiring structure is smaller than the second rewiring structure; thus, the first adapter board core particle includes the first sub-rewiring structure and the second sub-rewiring structure which are bonded to each other.

[0071] Here, the number of first wiring layers in the first redistribution structure is the same as the number of first wiring layers in the first sub-redistribution structure. The number of second wiring layers in the second redistribution structure is the same as the number of second wiring layers in the second sub-redistribution structure.

[0072] Exemplarily, the formation of a first adapter plate core particle having a second conductive column is used as an example for explanation. Here, in step S301, forming the initial adapter plate may include the following steps: etching the second substrate along the thickness direction of the second substrate from the first surface of the second substrate to form a second etching hole; filling the second etching hole with a conductive material to form a second conductive column; forming a first redistribution structure on the first surface of the second substrate; thinning the second substrate to expose the second end of the second conductive column; and forming a second redistribution structure on the second surface of the second substrate.

[0073] Here, the second substrate is etched to form second etched holes. The present disclosure has no special restrictions on the process of forming the second etched holes, the size, number and distribution of the second etched holes in the second substrate, and they can be selected according to actual needs.

[0074] Here, the process of forming the second conductive column in the second etched hole may be, for example, physical sputtering, magnetron sputtering or evaporation, etc. The present disclosure has no special limitation on the process of forming the second conductive column and the material of the second conductive column, which can be selected according to actual needs.

[0075] In step S302, the initial adapter board can be cut along the thickness direction of the second substrate to obtain a first adapter board core particle; wherein the size of the first sub-rewiring structure is smaller than the size of the first rewiring structure, and the size of the second sub-rewiring structure is smaller than the size of the second rewiring structure; thus, the first adapter board core particle includes the first sub-rewiring structure, the second sub-rewiring structure, and a second conductive column for connecting the first sub-rewiring structure and the second sub-rewiring structure.

[0076] In step S303, forming a sub-adapter board may include the following steps: etching the first substrate along the thickness direction of the first substrate from the first surface of the first substrate to form a first etching hole; filling the first etching hole with a conductive material to form a first conductive column, and the first surface of the first substrate exposes the first end of the first conductive column; forming a third redistribution structure on the first surface of the first substrate; thinning the first substrate to expose the second end of the first conductive column; and forming a bump on the second surface of the first substrate.

[0077] Here, the first substrate may include a silicon substrate. The first substrate may use a wafer-level substrate, and the size of the wafer-level substrate may include 4 inches, 6 inches, 8 inches or 12 inches. The present disclosure has no special restrictions on the material, thickness and size of the first substrate.

[0078] In the above technical solution, the process of etching to form the first etched hole and the process of forming the first conductive column can refer to the relevant description of the process of etching to form the second etched hole and the process of forming the second conductive column in step S301, which will not be repeated here.

[0079] In step S304, the first adapter board core particle is disposed on one side of the sub-adapter board, and the second sub-rewiring structure in the first adapter board core particle is connected to the third rewiring structure in the sub-adapter board.

[0080] In some embodiments, a second adapter board core particle can be formed after the initial adapter board is cut. The difference between the first adapter board core particle and the second adapter board core particle lies in the size difference. The size of the second adapter board core particle is smaller than that of the first adapter board core particle. On the other hand, the first adapter board core particle is directly arranged on the sub-adapter board, and the second adapter board core particle is arranged on the first adapter board core particle.

[0081] refer to Figure 4 , Figure 4 A schematic flow chart of a method for manufacturing a packaging structure provided in an embodiment of the present disclosure.

[0082] like Figure 4 As shown, an embodiment of the present disclosure provides a method for manufacturing a packaging structure, the method comprising:

[0083] Step S401: providing an initial adapter board, the initial adapter board comprising a first rewiring structure and a second rewiring structure connected to the first rewiring structure;

[0084] Step S402: cutting the initial adapter board to obtain a plurality of adapter board core particles; the first redistribution structure is cut to form a first sub-redistribution structure, and the second redistribution structure is cut to form a second sub-redistribution structure; the plurality of adapter board core particles include a first adapter board core particle, and the first adapter board core particle includes a first sub-redistribution structure and a second sub-redistribution structure connected to the first sub-redistribution structure;

[0085] Step S403: providing a first substrate, a first conductive column disposed in the first substrate and penetrating the first substrate, and a third redistribution structure disposed on one side of the first substrate, wherein the first substrate has a first surface and a second surface opposite to each other, the first conductive column has a first end and a second end opposite to each other, and the first end of the first conductive column is connected to the third redistribution structure;

[0086] Step S404: bonding the second surface of the first substrate to the carrier substrate;

[0087] Step S405: disposing the first transfer board chip on a side of the third redistribution structure away from the first substrate, wherein the third redistribution structure is located between the second sub-redistribution structure and the first substrate and connected to the second sub-redistribution structure;

[0088] Step S406: disposing the first chip on a side of the third redistribution structure away from the first substrate, and connecting the third redistribution structure to the first chip;

[0089] Step S407: placing the second chip on a side of the first transfer board core away from the third redistribution structure, and connecting the first sub-redistribution structure to the second chip;

[0090] Step S408: debonding the second surface of the first substrate and the carrier substrate;

[0091] Step S409: forming a bump on the second surface of the first substrate, and connecting the second end of the first conductive column to the bump.

[0092] refer to FIG. 5A to FIG. 5G , FIG. 5A to FIG. 5G This is a cross-sectional view of the packaging structure provided in the embodiment of the present disclosure during the manufacturing process. Figure 4 as well as FIG. 5A to FIG. 5G , a method for manufacturing a packaging structure is described in detail.

[0093] like Figure 5A As shown, in step S401, an initial adapter plate 502 is provided, and the initial adapter plate 502 includes: a second substrate 230, the second substrate 230 having a first surface and a second surface relative to each other; a second conductive column 232 is provided in the second substrate 230 and passes through the second substrate 230, the second conductive column 232 has a first end and a second end relative to each other, the first surface of the second substrate 230 exposes the first end of the second conductive column 232, and the second surface of the second substrate 230 exposes the second end of the second conductive column 232; a first rewiring structure 504 is provided on the first surface of the second substrate 230, and the first end of the second conductive column 232 is electrically connected to the first rewiring structure 504; a second rewiring structure 506 is provided on the second surface of the second substrate 230, and the second end of the second conductive column 232 is electrically connected to the second rewiring structure 506.

[0094] like Figure 5A As shown, in step S402, the initial transfer plate 502 is cut along the thickness direction of the second substrate 230 to obtain a plurality of transfer plate core particles, for example, the first transfer plate core particle 202b. The size of the first transfer plate core particle 202b is smaller than the size of the initial transfer plate 502, and the number of the second conductive pillars 232 in the first transfer plate core particle 202b is smaller than the number of the second conductive pillars 232 in the initial transfer plate 502.

[0095] like Figure 5BAs shown, in step S403, a first substrate 218 is provided, the first substrate 218 having a first surface and a second surface relative to each other; a first conductive column 220 is arranged in the first substrate 218 and passes through the first substrate 218, the first conductive column 220 has a first end and a second end relative to each other, the first surface of the first substrate 218 exposes the first end of the first conductive column 220, and the second surface of the first substrate 218 exposes the second end of the first conductive column 220; and a third rewiring structure 224 is arranged on the first surface of the first substrate 218, and the first end of the first conductive column 220 is connected to the third rewiring structure 224.

[0096] like Figure 5C As shown, in step S404 , the second surface of the first substrate 218 is bonded to the carrier substrate 508 to form a bonding layer 510 between the first substrate 218 and the carrier substrate 508 .

[0097] Here, a temporary bonding process can be used to bond the carrier substrate and the first substrate, and the carrier substrate is used as a support to perform subsequent process steps. The carrier substrate may include, but is not limited to, an organic material (e.g., epoxy resin), an inorganic material (e.g., glass, silicon carbide, or aluminum oxide), a metal material (e.g., titanium, copper, aluminum, silver, gold, tin, or nickel), or other materials. The present disclosure does not specifically limit the material, thickness, and bonding process between the carrier substrate and the first substrate.

[0098] like Figure 5D As shown, in step S405, the first transfer board core particle 202b is disposed on the side of the third redistribution structure 224 away from the first substrate 218; wherein the second sub-redistribution structure 210 and the third redistribution structure 224 in the first transfer board core particle 202b are electrically connected.

[0099] like Figure 5D As shown, in step S406 , the first chip 512 is disposed on a side of the third redistribution structure 224 away from the first substrate 218 , and the first chip 512 and the third redistribution structure 224 are electrically connected.

[0100] Here, the process of placing the first chip 512 and the first adapter core particle 202b on the third rewiring structure 224 can be referred to as a die to wafer (D2W) bonding process. The first chip 512 and the third rewiring structure 224 can be connected by mutual bonding, and the first adapter core particle 202b and the third rewiring structure 224 can be connected by mutual bonding.

[0101] like Figure 5EAs shown, a material is filled in the gap between the first chip 512 and the first interposer die 202 b on the third redistribution structure 224 to form a first filling layer 514 .

[0102] Here, the gap between the first chip and the first adapter core particle is filled, the first filling material layer can fill the gap and cover the surface of the first chip and the first adapter core particle, and the first filling material layer is planarized to form a first filling layer and expose the surface of the first chip and the first adapter core particle. The planarization process may include but is not limited to chemical mechanical polishing (CMP) processing.

[0103] Here, the first chip, the first transfer plate core particle and the first filling layer surface are substantially flush.

[0104] like Fig. 5F As shown, in step S407 , the second chip 516 is disposed on a side of the first transfer board core 202 b away from the third redistribution structure 224 , and the first sub-redistribution structure 204 and the second chip 516 are electrically connected.

[0105] Here, the process of placing the second chip 516 on the first transfer board core 202b and the first chip 512 may be referred to as a die to wafer (D2W) bonding process. The second chip 516 and the first sub-rewiring structure 204 may be connected by mutual bonding.

[0106] In some embodiments, the second chip 516 may also be electrically connected to the first chip 512 and the first sub-rewiring structure 204 at the same time.

[0107] Here, the first chip 512 is disposed in the second region of the interposer structure, and the second chip 516 is disposed in the first region of the interposer structure. That is, the first chip 512 may include a chip with a lower requirement for the number of wiring layers, and the second chip 516 may include a chip with a higher requirement for the number of wiring layers.

[0108] like Fig. 5F As shown, a material is filled in the gap between the first interposer die 202 b and the second chip 516 on the first chip 512 to form a second filling layer 518 .

[0109] like Figure 5G As shown, in step S408 , the second surface of the first substrate 218 and the carrier substrate 508 are debonded to expose the second surface of the first substrate 218 and the second end of the first conductive pillar 220 .

[0110] like Figure 5GAs shown, a fourth rewiring structure 234 is formed on the second surface of the first substrate 218 ; in step S409 , a bump 222 is formed on one side of the fourth rewiring structure 234 ; wherein the second end of the first conductive column 220 is connected to the bump 222 via the fourth rewiring structure 234 .

[0111] In the disclosed embodiment, different chips in the packaging structure can be arranged in a three-dimensional vertical stack, thereby improving the integration of the packaging structure and reducing the packaging area.

[0112] like Figure 5G As shown, an embodiment of the present disclosure provides a packaging structure, which packaging structure 500 includes: a transfer board structure as in the above technical solution; a first chip 512 arranged on one side of the sub-transfer board 216b and connected to the third rewiring structure 224; and a second chip 516 arranged on the side of the first transfer board core particle 202b away from the sub-transfer board 216b and connected to the first sub-rewiring structure 204.

[0113] The disclosed embodiments provide an adapter plate structure and manufacturing method and a packaging structure and manufacturing method. In the disclosed embodiments, a first adapter plate core particle is arranged on one side of a sub-adapter plate, and the first adapter plate core particle includes a first sub-rewiring structure and a second sub-rewiring structure connected to each other, and the sub-adapter plate includes a first substrate, a first conductive column, a third rewiring structure and a bump, so that the second sub-rewiring structure and the third rewiring structure are connected, thereby forming a first area with a larger number of wiring layers and a second area with a smaller number of wiring layers. In this way, the adapter plate structure can simultaneously meet the different requirements of different chips for different numbers of wiring layers, so as to solve the quality problems such as warping and delamination of the adapter plate structure caused by the large number of wiring layers, and can also directly connect the first adapter plate core particle and the sub-adapter plate to reduce the process difficulty. In addition, the packaging structure obtained by manufacturing the above-mentioned adapter plate structure can enable different chips to form a three-dimensional vertical stacking arrangement, improve the integration of the packaging structure, and reduce the packaging area.

[0114] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0115] The above description is only a preferred embodiment of the present disclosure, and does not limit the patent scope of the present disclosure. All equivalent structural changes made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A transfer plate structure, characterized in that: The adapter plate structure comprises: A first adapter core particle includes a first sub-rewiring structure and a second sub-rewiring structure connected to the first sub-rewiring structure; A sub-adapter board disposed on one side of the first adaptor board core grain comprises: a first substrate having a first surface and a second surface opposite to each other; a first conductive column disposed in and penetrating the first substrate, the first conductive column having a first end and a second end opposite to each other; a third rewiring structure disposed on the first surface, the first end of the first conductive column being connected to the third rewiring structure; the third rewiring structure being located between the second sub-rewiring structure and the first substrate and being connected to the second sub-rewiring structure; a bump disposed on the second surface, the second end of the first conductive column being connected to the bump; The orthographic projection size of the first adapter plate core particle on the third rewiring structure is smaller than the size of the third rewiring structure.

2. The adapter plate structure according to claim 1, characterized in that: The first sub-rewiring structure and the second sub-rewiring structure each include a first surface and a second surface opposite to each other, wherein the first surface of the first sub-rewiring structure is bonded to the first surface of the second sub-rewiring structure, and the second surface of the second sub-rewiring structure is connected to the third rewiring structure.

3. The adapter plate structure according to claim 1, characterized in that: The first adapter plate core also includes: a second substrate disposed between the first sub-rewiring structure and the second sub-rewiring structure; A second conductive column is disposed in the second substrate and penetrates the second substrate, the second conductive column having a first end and a second end opposite to each other; the first end of the second conductive column is connected to the first sub-rewiring structure, and the second end of the second conductive column is connected to the second sub-rewiring structure.

4. The adapter plate structure according to claim 1, characterized in that: The first sub-rewiring structure includes a first dielectric layer and at least one first wiring layer arranged in the first dielectric layer, the second sub-rewiring structure includes a second dielectric layer and at least one second wiring layer arranged in the second dielectric layer, and the third rewiring structure includes a third dielectric layer and at least one third wiring layer arranged in the third dielectric layer; The adapter board structure includes a first area and a second area, the first area is the positive projection area of ​​the first adapter board core particle on the third rewiring structure, and the second area is other areas in the adapter board structure except the first area; wherein the number of wiring layers in the first area is greater than the number of wiring layers in the second area.

5. The adapter plate structure according to claim 1, characterized in that: The sub-adapter board also includes: A fourth rewiring structure is disposed between the first substrate and the bump, and the fourth rewiring structure connects the second end of the first conductive column and the bump.

6. The adapter plate structure according to claim 1, characterized in that: The adapter plate structure also includes: A second adapter board core particle is provided on a side of the first adapter board core particle away from the sub-adapter board, the second adapter board core particle comprises a third sub-rewiring structure and a fourth sub-rewiring structure connected to the third sub-rewiring structure, the fourth sub-rewiring structure is located between the first sub-rewiring structure and the third sub-rewiring structure and is connected to the first sub-rewiring structure; The orthographic projection size of the second adapter plate core particle on the first adapter plate core particle is smaller than the size of the first adapter plate core particle.

7. A method for manufacturing an adapter plate structure, characterized in that: The method comprises: Providing an initial adapter plate, the initial adapter plate comprising a first rewiring structure and a second rewiring structure connected to the first rewiring structure; The initial adapter plate is cut to obtain a plurality of adapter plate core particles; the first rewiring structure is cut to form a first sub-rewiring structure, and the second rewiring structure is cut to form a second sub-rewiring structure; the plurality of adapter plate core particles include a first adapter plate core particle, and the first adapter plate core particle includes the first sub-rewiring structure and a second sub-rewiring structure connected to the first sub-rewiring structure; A sub-adapter board is provided, the sub-adapter board comprising: a first substrate having a first surface and a second surface opposite to each other; a first conductive column disposed in and penetrating the first substrate, the first conductive column having a first end and a second end opposite to each other; a third rewiring structure disposed on the first surface, the first end of the first conductive column being connected to the third rewiring structure; and a bump disposed on the second surface, the second end of the first conductive column being connected to the bump; The first adapter board core particle is arranged on one side of the sub-adapter board, and the third rewiring structure is located between the second sub-rewiring structure and the first substrate and is connected to the second sub-rewiring structure; wherein, the orthographic projection size of the first adapter board core particle on the third rewiring structure is smaller than the size of the third rewiring structure.

8. The manufacturing method according to claim 7, characterized in that: The first rewiring structure is cut to form a third sub-rewiring structure, and the second rewiring structure is cut to form a fourth sub-rewiring structure; the plurality of adapter plate core particles further include a second adapter plate core particle, and the second adapter plate core particle includes the third sub-rewiring structure and a fourth sub-rewiring structure connected to the third sub-rewiring structure; The second adapter board core particle is arranged on the side of the first adapter board core particle away from the sub-adapter board, and the fourth sub-rewiring structure is located between the first sub-rewiring structure and the third sub-rewiring structure and is connected to the first sub-rewiring structure; wherein the orthographic projection size of the second adapter board core particle on the first adapter board core particle is smaller than the size of the first adapter board core particle.

9. A packaging structure, characterized in that: The packaging structure comprises: The adapter plate structure according to any one of claims 1 to 6; A first chip disposed on one side of the sub-adapter board and connected to the third rewiring structure; A second chip is disposed on a side of the first adapter board core grain away from the sub-adapter board and connected to the first sub-rewiring structure.

10. A method for manufacturing a packaging structure, characterized in that: The method comprises: Providing an initial adapter plate, the initial adapter plate comprising a first rewiring structure and a second rewiring structure connected to the first rewiring structure; The initial adapter plate is cut to obtain a plurality of adapter plate core particles; the first rewiring structure is cut to form a first sub-rewiring structure, and the second rewiring structure is cut to form a second sub-rewiring structure; the plurality of adapter plate core particles include a first adapter plate core particle, and the first adapter plate core particle includes the first sub-rewiring structure and a second sub-rewiring structure connected to the first sub-rewiring structure; A first substrate, a first conductive column disposed in and penetrating the first substrate, and a third redistribution structure disposed on one side of the substrate are provided, wherein the first substrate has a first surface and a second surface opposite to each other, the first conductive column has a first end and a second end opposite to each other, and the first end of the first conductive column is connected to the third redistribution structure; bonding the second surface of the first substrate to a carrier substrate; The first transfer plate core is arranged on a side of the third redistribution structure away from the first substrate, wherein the third redistribution structure is located between the second sub-redistribution structure and the first substrate and is connected to the second sub-redistribution structure; Disposing a first chip on a side of the third rewiring structure away from the first substrate, wherein the third rewiring structure is connected to the first chip; The second chip is arranged on a side of the first transfer board core grain away from the third rewiring structure, and the first sub-rewiring structure is connected to the second chip; Debonding the second surface of the first substrate and the carrier substrate; A bump is formed on the second surface of the first substrate, and the second end of the first conductive column is connected to the bump.

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