Semiconductor structure and method for manufacturing the same

Abstract

The present application provides a semiconductor structure and a manufacturing method thereof, the manufacturing method comprising: sequentially forming a first supporting layer, a first sacrificial layer, and a second supporting layer on a substrate; forming a plurality of first capacitor holes on the first supporting layer, the first sacrificial layer, and the second supporting layer; filling a first sub-electrode in the first capacitor hole; forming at least one first through hole in the second supporting layer; sequentially forming a second sacrificial layer and a third supporting layer on the second supporting layer; forming a second capacitor hole on the third supporting layer and the second sacrificial layer, wherein the orthographic projection of the second capacitor hole on the substrate falls within the orthographic projection of the first capacitor hole on the substrate, and the second capacitor hole exposes the first sub-electrode; filling the second capacitor hole with a second sub-electrode, and the second sub-electrode and the first sub-electrode are combined to form a lower electrode layer.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] In memory capacitor manufacturing technology, the shrinking spacing between capacitors and increasing density have resulted in a narrower window for etching downward. As the height of the capacitors increases, the difficulty of opening the middle support layer also increases. Furthermore, since the support layers are all made of the same material, forcing the middle support layer to open would inevitably result in excessive loss or even damage to the top support layer. Summary of the Invention

[0003] In view of this, the main purpose of this application is to provide a semiconductor structure and a manufacturing method thereof.

[0004] To achieve the above objectives, the technical solution of this application is implemented as follows:

[0005] An embodiment of the present application provides a method for manufacturing a semiconductor structure, comprising:

[0006] forming a first supporting layer, a first sacrificial layer and a second supporting layer in sequence on the substrate;

[0007] forming a plurality of first capacitor holes on the first supporting layer, the first sacrificial layer, and the second supporting layer;

[0008] Filling the first sub-electrode in the first capacitor hole;

[0009] forming at least one first through hole on the second supporting layer;

[0010] forming a second sacrificial layer and a third supporting layer in sequence on the second supporting layer;

[0011] forming a second capacitor hole on the third supporting layer and the second sacrificial layer, wherein an orthographic projection of the second capacitor hole on the substrate falls within an orthographic projection of the first capacitor hole on the substrate, and the second capacitor hole exposes the first sub-electrode;

[0012] A second sub-electrode is filled in the second capacitor hole, and the second sub-electrode and the first sub-electrode are combined to form a lower electrode layer.

[0013] In some embodiments, filling the first sub-electrode in the first capacitor hole and forming at least one first through hole on the second supporting layer includes:

[0014] Filling the first capacitor hole with an electrode material layer, wherein the electrode material layer completely fills the first capacitor hole and covers the second supporting layer;

[0015] forming at least one first hole on the electrode material layer and the second supporting layer;

[0016] The electrode material layer located on a side of the second supporting layer away from the substrate is removed to obtain a first sub-electrode and at least one first through hole located on the second supporting layer.

[0017] In some embodiments, removing the electrode material layer located on a side of the second supporting layer away from the substrate to obtain a first sub-electrode and at least one first through hole located on the second supporting layer includes:

[0018] coating a hard mask material on the electrode material layer, wherein the hard mask material covers the electrode material layer and fills the first hole;

[0019] removing the hard mask material and the electrode material layer located on a side of the second supporting layer away from the substrate to obtain a first sub-electrode, at least one first through hole located on the second supporting layer, and a hard mask layer located within the first through hole, wherein a surface of the first sub-electrode away from the substrate, a surface of the second supporting layer away from the substrate, and a surface of the hard mask layer away from the substrate are coplanar;

[0020] The hard mask layer is removed.

[0021] In some embodiments, in a direction parallel to the plane where the substrate is located, the aperture of the second capacitor hole is smaller than the aperture of the first capacitor hole.

[0022] In some embodiments, the manufacturing method further comprises:

[0023] forming at least one second through hole on the third supporting layer, wherein an orthographic projection of the first through hole on the substrate falls within an orthographic projection of the second through hole on the substrate;

[0024] The second sacrificial layer and the first sacrificial layer are removed.

[0025] In some embodiments, the manufacturing method further comprises:

[0026] forming a capacitor dielectric layer on the surface of the lower electrode layer;

[0027] An upper electrode layer is formed on a surface of the capacitor dielectric layer away from the lower electrode layer.

[0028] An embodiment of the present application provides a semiconductor structure, including a substrate, a primary supporting structure and a lower electrode layer, wherein the primary supporting structure is located on the substrate, and the primary supporting structure includes a first supporting layer, a first sacrificial layer, a second supporting layer, a second sacrificial layer and a third supporting layer arranged in sequence from bottom to top; a plurality of capacitor through-holes penetrating the primary supporting structure are also provided in the primary supporting structure; wherein the capacitor through-holes include a first capacitor hole and a second capacitor hole that are connected, the first capacitor hole penetrating the second supporting layer, the first sacrificial layer and the first supporting layer, and the second capacitor hole penetrating the third supporting layer and the second sacrificial layer; and in a direction parallel to the plane where the substrate is located, the aperture of the second capacitor hole is smaller than the aperture of the first capacitor hole; the lower electrode layer is located in the capacitor through-hole; wherein at least one first through-hole is also provided on the second supporting layer, and the first sacrificial layer and the second sacrificial layer are connected through the first through-hole.

[0029] An embodiment of the present application also provides a semiconductor structure, including a substrate, a support structure and a lower electrode layer, wherein the support structure is located on the substrate, and the support structure includes a first support layer, a second support layer and a third support layer arranged in sequence from bottom to top; a plurality of capacitor through-holes penetrating the support structure are also provided in the support structure; wherein the capacitor through-holes include a first capacitor hole and a second capacitor hole that are connected, the first capacitor hole penetrating the second support layer and the first support layer, the second capacitor hole is located above the first capacitor hole and penetrating the third support layer, and in a direction parallel to the plane where the substrate is located, the aperture of the second capacitor hole is smaller than the aperture of the first capacitor hole; the lower electrode layer is located in the capacitor through-hole; wherein at least one first through-hole is also provided on the second support layer, and at least one second through-hole is also provided on the third support layer, and the orthographic projection of the first through-hole on the substrate falls within the orthographic projection of the second through-hole on the substrate.

[0030] In some embodiments, the semiconductor structure further includes a capacitor dielectric layer and an upper electrode layer, wherein the capacitor dielectric layer is located on the surface of the lower electrode layer; and the upper electrode layer is located on the surface of the capacitor dielectric layer away from the lower electrode layer.

[0031] In some embodiments, in a direction parallel to the plane where the substrate is located, the aperture of the first through hole is greater than 0 and less than or equal to the distance between two adjacent lower electrode layers.

[0032] An embodiment of the present application provides a method for manufacturing a semiconductor structure, comprising: sequentially forming a first supporting layer, a first sacrificial layer, and a second supporting layer on a substrate; forming a plurality of first capacitor holes on the first supporting layer, the first sacrificial layer, and the second supporting layer; filling a first sub-electrode in the first capacitor hole; forming at least one first through hole in the second supporting layer; sequentially forming a second sacrificial layer and a third supporting layer on the second supporting layer; forming a second capacitor hole on the third supporting layer and the second sacrificial layer, wherein the orthographic projection of the second capacitor hole on the substrate falls within the orthographic projection of the first capacitor hole on the substrate, and the second capacitor hole exposes the first sub-electrode; filling a second sub-electrode in the second capacitor hole, and the second sub-electrode and the first sub-electrode are combined to form a lower electrode layer; in the present application, by forming at least one first through hole on the second supporting layer before forming the second sacrificial layer and the third supporting layer, the second sacrificial layer can be connected to the first sacrificial layer through the first through hole. When the sacrificial layer is subsequently removed, only the top third supporting layer needs to be etched to remove the second sacrificial layer and the first sacrificial layer at one time, without etching the middle second supporting layer. This not only reduces the process difficulty, but also reduces the number of process steps and saves costs. Moreover, it avoids the situation where the third supporting layer is lost too much or even damaged, and is beneficial to increase the capacity (Cs) of the formed capacitor and the overall height of the capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1a to Figure 1d A schematic diagram of the basic structure of each component in the manufacturing process flow of a semiconductor structure in the related art;

[0034] Figure 2 A flowchart of a method for manufacturing a semiconductor structure provided in an embodiment of the present application;

[0035] Figure 3a to Figure 3i A schematic diagram of the basic structure of each component in the manufacturing process flow of the semiconductor structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0036] The following describes exemplary embodiments of the present application in more detail with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0037] In the following description, numerous specific details are provided to provide a more thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present application; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0038] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0039] It should be understood that spatial relational terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatial relational terms are intended to also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, then the elements or features described as "under the other elements" or "beneath" or "beneath" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0040] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0041] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present application, the implementation of the embodiments of the present application is described in detail below with reference to the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present application.

[0042] like Figure 1a to Figure 1d As shown in FIG. 1 , a basic structural diagram of each component in the manufacturing process flow of a semiconductor structure in the related art is shown. In the manufacturing process flow of a semiconductor structure in the related art, first, as shown in FIG. Figure 1aAs shown in the figure on the left, a first supporting layer 21, a first sacrificial layer 22, a second supporting layer 23, a second sacrificial layer 24, a third supporting layer 25, an etching protection layer 300 and a mask material layer 400 are sequentially formed on a substrate 100. Then, a first mask assembly 500 is used to perform a photolithography process on the mask material layer 400 to obtain the following: Figure 1a The components shown in the figure on the right, where Figure 1a The pattern on the mask material layer 400 shown in the middle right figure is the pattern corresponding to the capacitor through hole 26.

[0043] Next, if Figure 1b As shown in the left figure, the mask material layer 400 is used as a mask to etch the etching protection layer 300 to transfer the pattern on the mask material layer 400 to the etching protection layer 300. Figure 1b As shown in the figure on the right side, the etching protection layer 300 is used as a mask to etch the third support layer 25, the second sacrificial layer 24, the second support layer 23, the first sacrificial layer 22 and the first support layer 21 respectively to form a capacitor through hole 26 that penetrates the third support layer 25, the second sacrificial layer 24, the second support layer 23, the first sacrificial layer 22 and the first support layer 21. In the etching process, the etching protection layer 300 is lost, so Figure 1b In the right side of the figure, the thickness of the etching protection layer 300 is reduced compared to the left side of the figure.

[0044] Next, if Figure 1c As shown in the left side of the figure, the etching protection layer 300 is removed by etching process. Figure 1c As shown in the figure on the right side of the middle, an atomic deposition process is used to form a lower electrode layer 600 in the capacitor through hole 26 and a second mask assembly 700 is formed.

[0045] Next, if Figure 1d As shown, the third supporting layer 25 is photolithographically processed using a second mask assembly 700 to form at least one second through hole 251 on the third supporting layer 25, and the second sacrificial layer 24 is etched through the second through hole 251 to remove the second sacrificial layer 24; then the second supporting layer 23 is photolithographically processed to form at least one first through hole 231 on the second supporting layer 23, and the first sacrificial layer 22 is etched through the first through hole 231 to remove the first sacrificial layer 22.

[0046] It is understandable that as the spacing between capacitors continues to shrink and density increases, the window for etching downward becomes increasingly narrow. As the height of the capacitors increases, the difficulty of opening the middle second support layer 23 increases. Furthermore, since the support layers are all made of the same material, forcibly opening the middle second support layer 23 would inevitably result in excessive loss or even damage to the top third support layer 25. The embodiments of the present application can address these drawbacks.

[0047] like Figure 2 FIG. 1 is a flow chart of a method for manufacturing a semiconductor structure provided in an embodiment of the present application, wherein the method comprises:

[0048] S1, forming a first supporting layer, a first sacrificial layer and a second supporting layer in sequence on a substrate;

[0049] S2, forming a plurality of first capacitor holes on the first supporting layer, the first sacrificial layer, and the second supporting layer;

[0050] S3, filling the first sub-electrode in the first capacitor hole;

[0051] S4, forming at least one first through hole on the second supporting layer;

[0052] S5. forming a second sacrificial layer and a third supporting layer in sequence on the second supporting layer;

[0053] S6. Forming a second capacitor hole on the third supporting layer and the second sacrificial layer, wherein the orthographic projection of the second capacitor hole on the substrate falls within the orthographic projection of the first capacitor hole on the substrate, and the second capacitor hole exposes the first sub-electrode;

[0054] S7. Fill the second capacitor hole with a second sub-electrode, where the second sub-electrode and the first sub-electrode are combined to form a lower electrode layer.

[0055] It should be noted that, because the orthographic projection of the second capacitor hole on the substrate falls within the orthographic projection of the first capacitor hole on the substrate, and the second capacitor hole exposes the first sub-electrode, the second capacitor hole is located directly above the first capacitor hole, and the second capacitor hole and the first capacitor hole are interconnected. Therefore, the second sub-electrode formed in the second capacitor hole is bound and connected to the first sub-electrode in the first capacitor hole to form a lower electrode layer.

[0056] It can be understood that the present application etches the connected first capacitor hole and the second capacitor hole in two steps. The first step is to make the first supporting layer, the first sacrificial layer and the second supporting layer, and then form the first capacitor hole on the first supporting layer, the first sacrificial layer and the second supporting layer, and form the first sub-electrode in the first capacitor hole; the second step is to make the second sacrificial layer and the third supporting layer, and then form the second capacitor hole on the second sacrificial layer and the third supporting layer, and form the second sub-electrode in the second capacitor hole. The second sub-electrode is bound and connected to the first sub-electrode, thereby forming a lower electrode layer. At the same time, before performing the second step, at least one first through hole is formed on the second supporting layer, so that the second sacrificial layer can be connected to the first sacrificial layer through the first through hole. When the sacrificial layer is subsequently removed, only the top third supporting layer needs to be etched to remove the second sacrificial layer and the first sacrificial layer at one time. There is no need to etch the middle second supporting layer, that is, there is no problem of etching the middle supporting layer downward, which not only reduces the process difficulty, but also reduces the process steps and saves costs. Moreover, it avoids the situation where the third supporting layer is lost too much or even damaged, and is conducive to increasing the capacity (Cs) of the formed capacitor and the overall height of the capacitor.

[0057] Specifically, in the related art, the top third supporting layer is first etched, then the second sacrificial layer is removed, then the middle second supporting layer is etched, and then the first sacrificial layer is removed. That is, in the related art, the second sacrificial layer and the first sacrificial layer are removed separately. However, the present application first forms at least one first through hole in the second supporting layer, and then forms the second sacrificial layer on the second supporting layer, so that the second sacrificial layer is connected to the first sacrificial layer. The second sacrificial layer and the first sacrificial layer can be removed together through a single etching process, thus reducing the number of steps in the sacrificial layer removal process and saving costs.

[0058] It should be noted that the embodiment of the present application is described by taking the semiconductor structure including only the first sacrificial layer and the second sacrificial layer as an example, and the present application is not limited to this. In practical applications, the semiconductor structure may include more than two sacrificial layers to obtain a higher capacitor. That is, a third sacrificial layer and a fourth supporting layer can also be made on the third supporting layer, and then a third capacitor hole is formed on the third sacrificial layer and the fourth supporting layer, and a third sub-electrode is formed in the third capacitor hole. The third sub-electrode is bound and connected to the second sub-electrode, and the third sub-electrode is combined with the second sub-electrode and the first sub-electrode to form a lower electrode layer. At the same time, before forming the third sacrificial layer, at least one second through hole is first made on the third supporting layer, so that the third sacrificial layer is connected to the second sacrificial layer through the second through hole, so that the third sacrificial layer, the second sacrificial layer and the first sacrificial layer can be removed together through a single etching process. By analogy, the height of the capacitor can be increased indefinitely, thereby increasing the capacity (Cs) of the capacitor and the overall height of the capacitor, and there is no problem of the middle supporting layer being difficult to open, and the top supporting layer will not be damaged.

[0059] It should be noted that in the process flow corresponding to the manufacturing method provided in the embodiment of the present application, a photolithography machine can be used to perform photolithography on the film layer, so there is no need to form the corresponding etching pattern through multiple exposures, and the process steps can also be reduced.

[0060] Next, combine Figure 3a to Figure 3i The method for manufacturing the semiconductor structure provided in the embodiment of the present application is described in detail. Figure 3a to Figure 3i A schematic diagram of the basic structure of each component in the manufacturing process flow of the semiconductor structure provided in an embodiment of the present application.

[0061] In step S1, Figure 3a As shown, a first supporting layer 21, a first sacrificial layer 22, a second supporting layer 23, an etching protection layer 300 and a mask material layer 400 are sequentially formed on the substrate 100, and then the mask material layer 400 is photolithographically processed using a third mask assembly 501 to obtain the following: Figure 3a The components shown in the figure on the right, where Figure 3a The pattern on the mask material layer 400 shown in the middle right figure is the pattern corresponding to the first capacitor hole 261 .

[0062] It should be noted that the material of the substrate 100 is, for example, silicon, the material of the first supporting layer 21 and the second supporting layer 23 is, for example, silicon nitride, the material of the first sacrificial layer 22 is, for example, silicon oxide, the material of the etching protection layer 300 is, for example, polysilicon, and the mask material layer 400 is, for example, silicon oxide.

[0063] In step S2, as Figure 3b As shown, the mask material layer 400 is used as a mask to etch the etching protection layer 300, the second supporting layer 23, the first sacrificial layer 22 and the first supporting layer 21 to form a plurality of first capacitor holes 261 on the first supporting layer 21, the first sacrificial layer 22 and the second supporting layer 23; and then the etching protection layer 300 is removed.

[0064] In steps S3 and S4, as Figure 3e As shown in the figure on the left side, the first sub-electrode 61 is filled in the first capacitor hole 261 by an atomic deposition process. The first sub-electrode 61 can only fill the first capacitor hole 261. The material of the first sub-electrode 61 is, for example, titanium nitride; then, at least one first through hole 231 is formed on the second supporting layer 23 by an etching process. This application does not impose any restrictions on the number and setting position of the first through holes 231.

[0065] In steps S5 and S6, as Figure 3eAs shown in the figure on the right side of the middle, a second sacrificial layer 24, a third supporting layer 25, an etching protection layer 300 and a mask material layer 400 are sequentially formed on the second supporting layer 23, wherein the second sacrificial layer 24 is connected to the first sacrificial layer 22 through the first through hole 231, and the second sacrificial layer 24 and the first sacrificial layer 22 can be removed together through a single etching process. Then, a fourth mask assembly 801 is used to perform photolithography on the mask material layer 400, and the mask material layer 400 is used as a mask to etch the etching protection layer 300, the third supporting layer 25 and the second sacrificial layer 24 to form a second capacitor hole 262 on the third supporting layer 25 and the second sacrificial layer 24, as shown in FIG. Figure 3f As shown in the figure on the left, the orthographic projection of the second capacitor hole 262 on the substrate 100 falls within the orthographic projection of the first capacitor hole 261 on the substrate 100, and the second capacitor hole 262 exposes the first sub-electrode 61, that is, the second capacitor hole 262 is located directly above the first capacitor hole 261, and the second capacitor hole 262 and the first capacitor hole 261 are interconnected. The material of the second sacrificial layer 24 is, for example, silicon oxide, and the material of the third supporting layer 25 is, for example, silicon nitride.

[0066] In step S7, Figure 3f As shown in the figure on the right side of the center, an atomic deposition process is used to fill the second capacitor hole 262 with a second sub-electrode 62, made of, for example, titanium nitride. The second sub-electrode 62 is bound and connected to the first sub-electrode 61 to form the lower electrode layer 600. Because the second sacrificial layer 24 is connected to the first sacrificial layer 22 via the first through-hole 231, subsequent removal of the sacrificial layer requires only etching the top third support layer 25 to remove the second sacrificial layer 24 and the first sacrificial layer 22 at once, eliminating the need to etch the middle second support layer 23. This eliminates the need to etch downwards into the middle support layer, reducing both process difficulty and process steps, thus saving costs.

[0067] In some embodiments, filling the first sub-electrode 61 in the first capacitor hole 261 and forming at least one first through hole 231 on the second supporting layer 23 includes:

[0068] Filling the first capacitor hole 261 with an electrode material layer 601 , wherein the electrode material layer 601 completely fills the first capacitor hole 261 and covers the second supporting layer 23 ;

[0069] forming at least one first hole 230 on the electrode material layer 601 and the second supporting layer 23;

[0070] The electrode material layer 601 located on a side of the second supporting layer 23 away from the substrate 100 is removed to obtain a first sub-electrode 61 and at least one first through hole 231 located on the second supporting layer 23 .

[0071] Specifically, such as Figure 3c As shown in the left figure, when the first sub-electrode 61 is filled in the first capacitor hole 261, the electrode material layer 601 corresponding to the first sub-electrode 61 can fill the first capacitor hole 261 and cover the second supporting layer 23; then Figure 3c As shown in the figure on the right side of the middle, at least one first hole 230 (such as Figure 3d (as shown in the figure on the left in the figure); then Figure 3e As shown in the figure on the left side, the electrode material layer 601 located on the side of the second supporting layer 23 away from the substrate 100 is removed by an etching process to obtain a first sub-electrode 61 and at least one first through hole 231 located on the second supporting layer 23 .

[0072] It should be noted that, in other embodiments, the electrode material layer 601 located on the side of the second supporting layer 23 away from the substrate 100 may be removed first, and then at least one first through hole 231 may be formed on the second supporting layer 23 .

[0073] It should be noted that, in this embodiment, the electrode material layer 601 corresponding to the first sub-electrode 61 fills the first capacitor hole 261 and covers the second supporting layer 23, and then removes the electrode material layer 601 located on the side of the second supporting layer 23 away from the substrate 100. This allows the surface of the first sub-electrode 61 away from the substrate 100 to be coplanar with the surface of the second supporting layer 23 away from the substrate 100, thereby providing a relatively flat surface for the subsequent production of the second sacrificial layer 24 and the third supporting layer 25, thereby improving the overall performance of the capacitor.

[0074] In some embodiments, removing the electrode material layer 601 located on a side of the second supporting layer 23 away from the substrate 100 to obtain the first sub-electrode 61 and at least one first through hole 231 located on the second supporting layer 23 includes:

[0075] Coating a hard mask material 800 on the electrode material layer 601 , wherein the hard mask material 800 covers the electrode material layer 601 and fills the first hole 230 ;

[0076] removing the hard mask material 800 and the electrode material layer 601 located on a side of the second supporting layer 23 away from the substrate 100 to obtain a first sub-electrode 61, at least one first through hole 231 located on the second supporting layer 23, and a hard mask layer located within the first through hole 231, wherein a surface of the first sub-electrode 61 away from the substrate 100, a surface of the second supporting layer 23 away from the substrate 100, and a surface of the hard mask layer away from the substrate 100 are coplanar;

[0077] The hard mask layer is removed.

[0078] Specifically, such as Figure 3d As shown in the figure on the right side, a hard mask material 800 is coated on the electrode material layer 601, and the hard mask material 800 covers the electrode material layer 601 and fills the first hole 230; then a push etching process or a chemical mechanical polishing process is used to remove the hard mask material 800 and the electrode material layer 601 located on the side of the second supporting layer 23 away from the substrate 100 to obtain a first sub-electrode 61, at least one first through hole 231 located on the second supporting layer 23, and a hard mask layer (not shown) located in the first through hole 231, wherein the surface of the first sub-electrode 61 away from the substrate 100, the surface of the second supporting layer 23 away from the substrate 100, and the surface of the hard mask layer away from the substrate 100 are coplanar, and finally the hard mask layer is removed to obtain as shown. Figure 3e The components shown in the figure on the left.

[0079] In some embodiments, in a direction parallel to the plane of the substrate 100 , an aperture d2 of the second capacitor hole 262 is smaller than an aperture d1 of the first capacitor hole 261 .

[0080] It is understandable that since the second sub-electrode 62 needs to be bound and connected to the first sub-electrode 61, there is an alignment requirement when performing the etching process to form the second capacitor hole 262. If the second capacitor hole 262 is aligned with the first capacitor hole 261, it is easy for adjacent capacitors to be connected together and cause a short circuit. The embodiment of the present application increases the alignment window by making the aperture d2 of the second capacitor hole 262 smaller than the aperture d1 of the first capacitor hole 261, and the aperture d2 of the second capacitor hole 262 becomes smaller, then the spacing between the capacitors will become larger, making it difficult for adjacent capacitors to connect, avoiding short circuits.

[0081] In some embodiments, the manufacturing method further comprises:

[0082] At least one second through hole 251 is formed on the third supporting layer 25 , and the orthographic projection of the first through hole 231 on the substrate 100 falls within the orthographic projection of the second through hole 251 on the substrate 100 ;

[0083] The second sacrificial layer 24 and the first sacrificial layer 22 are removed.

[0084] Specifically, such as Figure 3g As shown, the third support layer 25 is photolithographically processed using a sixth mask assembly 900 to form at least one second through hole 251 on the third support layer 25; and then Figure 3h As shown, since the second sacrificial layer 24 is connected to the first sacrificial layer 22 through the first through hole 231 , the second sacrificial layer 24 and the first sacrificial layer 22 can be removed together by one etching process.

[0085] In some embodiments, the manufacturing method further comprises:

[0086] A capacitor dielectric layer 63 is formed on the surface of the lower electrode layer 600;

[0087] An upper electrode layer 64 is formed on a surface of the capacitor dielectric layer 63 away from the lower electrode layer 600 .

[0088] Specifically, such as Figure 3i As shown, after forming the lower electrode layer 600, the capacitor dielectric layer 63 and the upper electrode layer 64 are manufactured, thereby forming a complete capacitor structure.

[0089] like Figure 3f As shown in the figure on the right side, the embodiment of the present application provides a semiconductor structure, including a substrate 100, a primary support structure and a lower electrode layer 600, wherein the primary support structure is located on the substrate 100, and the primary support structure includes a first support layer 21, a first sacrificial layer 22, a second support layer 23, a second sacrificial layer 24 and a third support layer 25 arranged in sequence from bottom to top; the primary support structure is further provided with a plurality of capacitor through holes 26 that penetrate the primary support structure; wherein the capacitor through hole 26 includes a first capacitor hole 261 and a second capacitor hole 262 that are connected, and the first capacitor The hole 261 passes through the second supporting layer 23, the first sacrificial layer 22 and the first supporting layer 21, and the second capacitor hole 262 passes through the third supporting layer 25 and the second sacrificial layer 24; and in the direction parallel to the plane of the substrate 100, the aperture of the second capacitor hole 262 is smaller than the aperture of the first capacitor hole 261; the lower electrode layer 600 is located in the capacitor through hole 26; wherein, at least one first through hole 231 is also provided on the second supporting layer 23, and the first sacrificial layer 22 and the second sacrificial layer 24 are connected through the first through hole 231.

[0090] It can be understood that since the second sacrificial layer 24 is connected to the first sacrificial layer 22 through the first through hole 231, when the sacrificial layer is subsequently removed, it is only necessary to etch the third supporting layer 25 on the top to remove the second sacrificial layer 24 and the first sacrificial layer 22 at one time, and there is no need to etch the second supporting layer 23 in the middle, that is, there is no problem of etching the middle supporting layer downward, which not only reduces the process difficulty, but also reduces the process steps and saves costs.

[0091] like Figure 3h As shown, the embodiment of the present application also provides a semiconductor structure, including a substrate 100, a support structure and a lower electrode layer 600, wherein the support structure is located on the substrate 100, and the support structure includes a first support layer 21, a second support layer 23 and a third support layer 25 arranged in sequence from bottom to top; the support structure is further provided with a plurality of capacitor through holes 26 penetrating the support structure; wherein the capacitor through hole 26 includes a first capacitor hole 261 and a second capacitor hole 262 connected to each other, the first capacitor hole 261 penetrating the second support layer 23 and the first support layer 21, and the second capacitor hole 262 is located above the first capacitor hole 261 and passes through the third supporting layer 25. In the direction parallel to the plane of the substrate 100, the aperture of the second capacitor hole 262 is smaller than the aperture of the first capacitor hole 261; the lower electrode layer 600 is located in the capacitor through hole 26; wherein, at least one first through hole 231 is further provided on the second supporting layer 23, and at least one second through hole 251 is further provided on the third supporting layer 25, and the orthographic projection of the first through hole 231 on the substrate 100 falls into the orthographic projection of the second through hole 251 on the substrate 100.

[0092] It should be noted that the semiconductor structure provided in this embodiment is manufactured using the above-mentioned method for manufacturing a semiconductor structure, and the specific manufacturing process flow will not be described in detail here.

[0093] In some embodiments, as Figure 3i As shown, the semiconductor structure further includes a capacitor dielectric layer 63 and an upper electrode layer 64. The capacitor dielectric layer 63 is located on the surface of the lower electrode layer 600; the upper electrode layer 64 is located on the surface of the capacitor dielectric layer 63 away from the lower electrode layer 600. In other words, the lower electrode layer 600, the capacitor dielectric layer 63, and the upper electrode layer 64 form a complete capacitor structure.

[0094] In some embodiments, in a direction parallel to the plane where the substrate 100 is located, the aperture of the first through hole 231 is greater than 0 and less than or equal to the distance between two adjacent lower electrode layers 600 .

[0095] It is understandable that in this embodiment, by making the aperture of the first through hole 231 smaller than or equal to the spacing between adjacent lower electrode layers 600 , the lower electrode layer 600 is prevented from being affected during the etching process of forming the first through hole 231 .

[0096] In some embodiments, in a direction parallel to the plane of the substrate 100 , the aperture of the second through hole 251 is larger than the aperture of the first through hole 231 .

[0097] It can be understood that since the aperture of the second capacitor hole 262 is smaller than the aperture of the first capacitor hole 261, the spacing between adjacent second capacitor holes 262 is greater than the spacing between adjacent first capacitor holes 261. Therefore, the aperture of the second through hole 251 can be set to be larger than the aperture of the first through hole 231 to increase the contact area between the etching solution and the second sacrificial layer 24, so that the second sacrificial layer 24 and the first sacrificial layer 22 can be removed more quickly.

[0098] In summary, an embodiment of the present application provides a semiconductor structure and a manufacturing method thereof, the manufacturing method comprising: sequentially forming a first supporting layer, a first sacrificial layer, and a second supporting layer on a substrate; forming a plurality of first capacitor holes on the first supporting layer, the first sacrificial layer, and the second supporting layer; filling a first sub-electrode in the first capacitor hole; forming at least one first through hole on the second supporting layer; sequentially forming a second sacrificial layer and a third supporting layer on the second supporting layer; forming a second capacitor hole on the third supporting layer and the second sacrificial layer, wherein the orthographic projection of the second capacitor hole on the substrate falls within the orthographic projection of the first capacitor hole on the substrate, and the second capacitor hole exposes the first sub-electrode; and The second sub-electrode is filled in the capacitance hole, and the second sub-electrode and the first sub-electrode are combined to form a lower electrode layer. The present application forms at least one first through hole on the second supporting layer before forming the second sacrificial layer and the third supporting layer, so that the second sacrificial layer can be connected to the first sacrificial layer through the first through hole. When the sacrificial layer is subsequently removed, only the top third supporting layer needs to be etched to remove the second sacrificial layer and the first sacrificial layer at one time, without etching the middle second supporting layer. This not only reduces the process difficulty, but also reduces the process steps, saves costs, and solves the technical problems of the difficulty of opening the middle second supporting layer and the easy loss or even damage of the top third supporting layer. Furthermore, it is also beneficial to increase the capacity (Cs) of the formed capacitor and the overall height of the capacitor.

[0099] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: forming a first supporting layer, a first sacrificial layer and a second supporting layer in sequence from bottom to top on the substrate; forming a plurality of first capacitor holes on the first supporting layer, the first sacrificial layer, and the second supporting layer; Filling the first sub-electrode in the first capacitor hole; forming at least one first through hole on the second supporting layer; forming a second sacrificial layer and a third supporting layer in sequence from bottom to top on the second supporting layer, wherein the second sacrificial layer fills the first through hole and is connected to the first sacrificial layer through the first through hole; forming a second capacitor hole on the third supporting layer and the second sacrificial layer, wherein an orthographic projection of the second capacitor hole on the substrate falls within an orthographic projection of the first capacitor hole on the substrate, and the second capacitor hole exposes the first sub-electrode; A second sub-electrode is filled in the second capacitor hole, and the second sub-electrode and the first sub-electrode are combined to form a lower electrode layer.

2. The manufacturing method according to claim 1, characterized in that The step of filling the first sub-electrode in the first capacitor hole and forming at least one first through hole on the second supporting layer comprises: Filling the first capacitor hole with an electrode material layer, wherein the electrode material layer completely fills the first capacitor hole and covers the second supporting layer; forming at least one first hole on the electrode material layer and the second supporting layer; The electrode material layer located on a side of the second supporting layer away from the substrate is removed to obtain a first sub-electrode and at least one first through hole located on the second supporting layer.

3. The manufacturing method according to claim 2, characterized in that The removing of the electrode material layer located on a side of the second supporting layer away from the substrate to obtain a first sub-electrode and at least one first through hole located on the second supporting layer includes: coating a hard mask material on the electrode material layer, wherein the hard mask material covers the electrode material layer and fills the first hole; removing the hard mask material and the electrode material layer located on a side of the second supporting layer away from the substrate to obtain a first sub-electrode, at least one first through hole located on the second supporting layer, and a hard mask layer located within the first through hole, wherein a surface of the first sub-electrode away from the substrate, a surface of the second supporting layer away from the substrate, and a surface of the hard mask layer away from the substrate are coplanar; The hard mask layer is removed.

4. The manufacturing method according to claim 1, characterized in that In a direction parallel to the plane where the substrate is located, the aperture of the second capacitor hole is smaller than the aperture of the first capacitor hole.

5. The manufacturing method according to any one of claims 1 to 4, characterized in that: The manufacturing method further comprises: forming at least one second through hole on the third supporting layer, wherein an orthographic projection of the first through hole on the substrate falls within an orthographic projection of the second through hole on the substrate; The second sacrificial layer and the first sacrificial layer are removed.

6. The manufacturing method according to claim 5, characterized in that The manufacturing method further comprises: forming a capacitor dielectric layer on the surface of the lower electrode layer; An upper electrode layer is formed on a surface of the capacitor dielectric layer away from the lower electrode layer.

7. A semiconductor structure, characterized in that include: substrate; A primary support structure is located on the substrate, the primary support structure comprising a first support layer, a first sacrificial layer, a second support layer, a second sacrificial layer, and a third support layer arranged in sequence from bottom to top; the primary support structure is further provided with a plurality of capacitor through-holes penetrating the primary support structure; wherein the capacitor through-holes include a first capacitor hole and a second capacitor hole that are connected, the first capacitor hole penetrating the second support layer, the first sacrificial layer, and the first support layer, and the second capacitor hole penetrating the third support layer and the second sacrificial layer; and in a direction parallel to the plane of the substrate, the aperture of the second capacitor hole is smaller than the aperture of the first capacitor hole; A lower electrode layer is located in the capacitor through hole; Wherein, at least one first through hole is further provided on the second supporting layer, and the first sacrificial layer and the second sacrificial layer are connected via the first through hole.

8. A semiconductor structure obtained by the method for manufacturing a semiconductor structure according to claim 1, characterized in that: include: substrate; A support structure is located on the substrate, the support structure comprising a first support layer, a second support layer, and a third support layer arranged in sequence from bottom to top; the support structure is further provided with a plurality of capacitor through-holes penetrating the support structure; wherein the capacitor through-holes include a first capacitor hole and a second capacitor hole that are connected, the first capacitor hole penetrating the second support layer and the first support layer, the second capacitor hole is located above the first capacitor hole and penetrating the third support layer, and the aperture of the second capacitor hole is smaller than the aperture of the first capacitor hole in a direction parallel to the plane of the substrate; A lower electrode layer is located in the capacitor through hole; The second supporting layer is further provided with at least one first through hole, the third supporting layer is further provided with at least one second through hole, and the orthographic projection of the first through hole on the substrate falls within the orthographic projection of the second through hole on the substrate.

9. The semiconductor structure according to claim 8, wherein: The semiconductor structure further comprises: a capacitor dielectric layer, located on the surface of the lower electrode layer; The upper electrode layer is located on the surface of the capacitor dielectric layer away from the lower electrode layer.

10. The semiconductor structure according to any one of claims 7 to 9, characterized in that: In a direction parallel to the plane where the substrate is located, the aperture of the first through hole is greater than 0 and less than or equal to the distance between two adjacent lower electrode layers.

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