Topological calculation method and device for power misoperation prevention, medium and program product

Abstract

The application provides a topology calculation method, device, medium and program product for power anti-misoperation, comprising: constructing an electrical topology network of a circuit; performing network topology calculation, setting a network clock parameter to identify a time of performing each round of network topology calculation, wherein in one round of network topology calculation, for each source in the electrical topology network, starting from the source, according to the connectivity of elements in the electrical topology network, traversing pins and / or contacts in the electrical topology network, and transmitting a potential value corresponding to the source and a network clock parameter value corresponding to the current round; the network topology calculation of the current round ends, and a ground island, a power supply island and a floating island of the electrical topology network are obtained; in the same round of network topology calculation, when the ground island and the power supply island have an intersection, the electrical topology network is abnormal. By using the above technical scheme, the electrical conflict detection can be realized by quickly calculating according to the electrical topology network.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of power system misoperation prevention, and in particular to a topology calculation method, device, medium and program product for power misoperation prevention. BACKGROUND

[0002] In a power system, misoperation accidents can cause serious consequences, seriously threatening the safety of the power grid, personnel and equipment, and seriously affecting the safe and stable operation of the power system. At present, the power misoperation prevention system generally uses a logic expression to describe the misoperation prevention rules. The misoperation prevention rules described using the logic expression must cover all the devices of the station, which is a huge amount of work for large stations. Moreover, manual review and verification of the logic expression is prone to errors. In addition, the addition and deletion of misoperation prevention rules require professional personnel to re-write and review, which also brings a huge workload to the engineering personnel. SUMMARY

[0003] To solve the above problems of the prior art, embodiments of the present application provide a topology calculation method for power misoperation prevention, which can realize electrical conflict detection through fast calculation.

[0004] To achieve the above purpose, in one aspect, a topology calculation method for power misoperation prevention is provided, comprising:

[0005] An electrical topology network of a line is constructed in a one-to-one correspondence between elements in the electrical topology network and real devices in the line, the elements in the electrical topology network comprising: a source, a conductor and a switch; the source comprising: a voltage source and a ground source; wherein in the electrical topology network, the elements are connected to each other through pins, a plurality of pins are connected through a contact point, one pin points to one contact point, and one contact point points to a plurality of pins;

[0006] Network topology calculation is performed on the electrical topology network, and a network clock parameter is set to identify the time when each round of network topology calculation is performed, wherein in one round of network topology calculation, for each source in the electrical topology network, the source is taken as a starting point, the pins and / or the contact points in the electrical topology network are traversed according to the connectivity of the elements in the electrical topology network, and the potential value corresponding to the source and the value of the network clock parameter corresponding to the current round are transmitted;

[0007] When the network clock parameter corresponding to the current round is transmitted in all sources of the electrical topology network, the network topology calculation of the current round ends, and the ground island, the power island and the floating island of the electrical topology network are obtained, wherein the ground island is a set of nodes to which the potential value of the ground source is transmitted when the ground source is taken as a starting point; the power island is a set of nodes to which the potential value of the voltage source is transmitted when the voltage source is taken as a starting point; and the floating island is a set of nodes whose network clock parameter value is less than the network clock parameter value corresponding to the current round.

[0008] In the network topology calculation of the same round, when the ground island and the power island have an intersection, the electrical topology network is abnormal.

[0009] Preferably, in the topology calculation method, the initial value of the network clock parameter is 0.

[0010] Preferably, in the topology calculation method, the value of the network clock parameter is increased after the network topology calculation of each round.

[0011] Preferably, in the topology calculation method, before the potential value of the source and the network clock parameter value corresponding to the current round are transmitted to the pin and / or the contact in the electrical topology network, the method further comprises:

[0012] For the current pin and / or contact, it is determined whether the value of the network clock parameter currently corresponding to the current pin and / or contact is less than the network clock parameter value corresponding to the current round; if yes, the network clock parameter value corresponding to the current round is transmitted to the current pin and / or contact; otherwise, the transmission of the network clock parameter value corresponding to the current round to the current pin and / or contact is stopped.

[0013] Preferably, in the topology calculation method, the value of the network clock parameter of the pin or the contact in the electrical topology network identifies the round of the network topology calculation in which the pin or the contact participates.

[0014] Preferably, in the topology calculation method, in the network topology calculation of the same round, when the ground island and the power island have no intersection, the electrical topology network is normal.

[0015] In another aspect, a topology calculation device for power misoperation prevention is provided, which comprises a memory and a processor, the memory stores at least one program, and the at least one program is executed by the processor to implement the steps of the topology calculation method according to any one of the above aspects.

[0016] In yet another aspect, there is provided a computer readable storage medium having stored therein at least one program, the at least one program being executable by a processor to implement the steps of the topology calculation method according to any one of the preceding aspects.

[0017] In yet another aspect, there is provided a computer program product comprising a computer program which, when executed by a processor, implements the steps of the topology calculation method according to any one of the preceding aspects.

[0018] The above technical solutions have the following technical effects:

[0019] The technical solution of the embodiment of the application constructs an electrical topology network of a line by means of one-to-one correspondence between elements in the electrical topology network and real devices in the line, can realize what you see is what you get, and is convenient for judging actual line faults; in addition, the embodiment of the application sets a network clock parameter to identify a time of performing each round of network topology calculation in network topology calculation, can determine a round of topology calculation of a network element by means of passing a value of the network clock parameter in topology calculation, and judges whether a grounding island and a power island intersect, that is, whether there is an intersection, according to a calculation result of the same round, and if yes, judges that the network has an abnormality. The embodiment of the application realizes verification of a misoperation prevention rule by means of an electrical network topology; the embodiment of the application provides a solution for misoperation prevention verification of a general electrical connection scene by means of a cleverly designed device and connection model of an electrical network participating in verification, can perform fast calculation according to an electrical topology network, and realizes electrical conflict detection. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 A flowchart of a topology calculation method for power misoperation prevention according to an embodiment of the application;

[0021] Figure 2 A structural diagram of a wire as a network graph element in an electrical topology network;

[0022] Figure 3 A structural diagram of a switch as a network graph element in an electrical topology network, that is, a corresponding electrical topology network graph;

[0023] Figure 4 A structural diagram of a source as a network graph element in an electrical topology network, that is, a corresponding electrical topology network graph;

[0024] Figure 5 An example of a typical electrical topology network;

[0025] Figure 6 A structural diagram of an exemplary electrical topology network model;

[0026] Figure 7Fig. 1 is a flowchart of a topology calculation method for an electrical topology network according to an embodiment of the present application;

[0027] Figure 8 Fig. 2 is an exemplary electrical topology network. DETAILED DESCRIPTION

[0028] To further illustrate the embodiments, the present application provides drawings. These drawings are part of the disclosure of the present application and mainly serve to illustrate the embodiments, and can be used to explain the operating principles of the embodiments in conjunction with the relevant descriptions. Those of ordinary skill in the art should be able to understand other possible implementations and advantages of the present application in conjunction with these. The components in the drawings are not drawn to scale, and similar component symbols are generally used to represent similar components.

[0029] The present application is further illustrated in conjunction with the drawings and the specific embodiments.

[0030] Embodiment 1:

[0031] Figure 1 Fig. 1 is a flowchart of a topology calculation method for power anti-misoperation according to an embodiment of the present application. As shown in Fig. 1, the topology calculation method for power anti-misoperation according to the embodiment includes the following steps: Figure 1

[0032] An electrical topology network of a line is constructed in a one-to-one correspondence between elements in the electrical topology network and real devices in the line and the elements in the electrical topology network include sources, conductors and switches; the sources include voltage sources and ground sources; wherein in the electrical topology network, the elements are connected to each other through pins, multiple pins are connected through contacts, one pin points to one contact, and one contact points to multiple pins;

[0033] Network topology calculation is performed on the electrical topology network, and a network clock parameter is set to identify the time when each round of network topology calculation is performed; in one round of network topology calculation, for each source in the electrical topology network, the source is taken as a starting point, the pins and / or contacts in the electrical topology network are traversed according to the connectivity of the elements in the electrical topology network, and the potential value corresponding to the source and the value of the network clock parameter corresponding to the current round are transmitted; in one specific implementation, the initial value of the network clock parameter is 0, and when the first round of network topology calculation is started, the value of the network clock parameter is 1; after each round of network topology calculation is completed, the value of the network clock parameter is incremented;

[0034] ​When the network clock parameter value corresponding to the current round is transmitted in all sources of the electrical topology network, the network topology calculation of the current round ends, and the ground island, the power island and the suspended island of the electrical topology network are obtained, wherein the ground island is a set of nodes to which the potential value of the ground source is transmitted when the ground source is taken as a starting point; the power island is a set of nodes to which the potential value of the voltage source is transmitted when the voltage source is taken as a starting point; the suspended island is a set of nodes whose network clock parameter value is less than the network clock parameter value corresponding to the current round; wherein the network clock parameter values corresponding to the ground island and the power island are equal to the network clock parameter value corresponding to the current round; the above nodes include pins and / or joints.

[0035] In the network topology calculation of the same round, when the ground island and the power island have an intersection, the electrical topology network is abnormal.

[0036] Preferably, in the network topology calculation of the same round, when the ground island and the power island have no intersection, the electrical topology network is normal.

[0037] In a specific implementation, further, the potential value of the node belonging to the ground island is 0; and the potential value of the node belonging to the power island is equal to the potential value of the voltage source taken as a starting point.

[0038] Embodiment two:

[0039] The following describes in detail a specific implementation of the composition, construction and network topology calculation of the electrical topology network in a topology calculation method for power anti-misoperation according to an embodiment of the application.

[0040] 1. Concept definition related to the electrical topology network constructed according to the embodiment of the application:

[0041] 1.1 Cell

[0042] A cell is a basic component of an electrical network, and the interconnection of cells constitutes an electrical network. A cell contains a function function, an operation and a pin. The function function determines the operation of the cell in the network, processes the input of the pin and inputs the result to a specific pin; the operation represents additional functions supported, such as opening / closing of a switch; and the pin is a port for input and output of the cell.

[0043] 1.2 Pin

[0044] A pin is a basic component of a cell. The electrical quantity of the cell is input and output through the pin, for driving the function function of the cell to operate.

[0045] 1.3 Joint

[0046] A joint represents the interconnection relationship of pins, and is a set of pins.

[0047] 1.4 Graph

[0048] The collection of elements are connected to each other by pins to form a graph, i.e. the electrical network topology graph corresponding to the electrical topology of the circuit.

[0049] 2. Electrical elements and networks

[0050] 2.1 Wire

[0051] The elements of the electrical topology network constructed by the embodiment of the present application include: wires. Figure 2 The structural diagram of the wire as a network graph element in the electrical topology network. As shown in Figure 2 In the electrical topology network, the wire contains two pins; the function of this element is to pass the input of one pin to the other pin; no other operation.

[0052] 2.2 Switch

[0053] The elements of the electrical topology network constructed by the embodiment of the present application include: switches. Figure 3 The structural diagram of the switch as a network graph element in the electrical topology network, i.e. the corresponding electrical topology network graph. As shown in Figure 3 In the electrical topology network, the switch contains two pins; the function of this element is to pass the input of one pin to the other pin according to the switch state; it has two operations, the on operation and the off operation.

[0054] 2.3 Source

[0055] The elements of the electrical topology network constructed by the embodiment of the present application include: sources. Among them, the source includes: a ground or a voltage source. Figure 4 The structural diagram of the source as a network graph element in the electrical topology network, i.e. the corresponding electrical topology network graph. As shown in Figure 4 The source contains one pin; the function of this element is to generate an output voltage, and no other operation. Among them, the ground source is a source with an output voltage of zero, and the voltage source is a source with an output voltage not equal to zero. The source is the starting point of network topology calculation.

[0056] The topology network of the prior art is obtained by abstracting the circuit, usually, the wire will be regarded as an equipotential point and will not appear as an element in the topology network; and the prior art will also omit the source when performing network calculation, and directly calculate on the network; and the topology calculation method of the embodiment of the present application will calculate with the source.

[0057] 2.4 Electrical topology network

[0058] The electrical network, i.e. the electrical topology network, is a graph composed of electrical elements and their connection points. In the preferred embodiment of the present application, the electrical topology network is composed of only sources, wires and switches. In the first embodiment of the present application, the electrical network is composed of a voltage source as the incoming line, a ground source, and at least one other element, such as a wire or a switch. Figure 5 The following is an example of a typical electrical topology network.

[0059] 3. Construction of the electrical topology network and its calculation

[0060] 3.1 Construction of the electrical topology network

[0061] In the electrical topology network, elements are connected to each other through pins, and multiple pins are connected through connection points, one pin pointing to one connection point, and one connection point pointing to multiple pins. Figure 6 The following is a structural diagram of an exemplary electrical topology network model.

[0062] As Figure 6 , compared with the topology network constructed by the prior art, the pins in the electrical topology network constructed by the embodiment of the present application have different connection modes; the embodiment of the present application directly constructs the topology network on the elements, while the prior art generally constructs the topology network through a linked list, and the topology network is constructed after the electrical line is abstracted; the embodiment of the present application defines the elements in the electrical topology network first, so that the elements correspond to the real devices, the entire electrical topology network is constructed through the connection of the real devices, and the topology calculation is performed on the entire electrical topology network. In the embodiment of the present application, the electrical topology network and the real device have a one-to-one correspondence, and what is seen is what is obtained. The topology network constructed by the prior art is abstracted and then constructed, so that many connection characteristics of the real device are lost, for example, a wire is connected to multiple devices, and the wire is lost in the electrical topology network after being abstracted by the prior art. However, the wire as an element still exists in the electrical topology network constructed by the embodiment of the present application.

[0063] 3.2 Topology calculation using the electrical topology network constructed by the embodiment of the present application

[0064] In order to perform fast network topology calculation, the embodiment of the present application defines a network clock parameter as an auxiliary parameter for the calculation when performing topology calculation of the electrical network. In a specific implementation, a variable tick is used to represent the network clock parameter. The network clock parameter is used to identify the time when the electrical topology network performs the current round of network topology calculation, which is equivalent to the role of network clock. The value of the network clock parameter is assigned during the calculation, and the value corresponds to the time when the current round of calculation is performed, i.e., corresponds to the current round. Preferably, the initial value of tick is zero. The value of tick is incremented by one round of network topology calculation; preferably, tick is taken at the beginning of each round of calculation, and the value of tick is incremented, such as by one, when the electrical topology network completes one round of network topology calculation.

[0065] In one round of topology calculation of the electrical topology network, starting from a source such as a voltage source as a starting point, the electrical quantity such as the potential value at the starting point and the value of the network clock parameter tick corresponding to the current round of calculation are transmitted in the entire electrical topology network according to the connectivity of the elements in the electrical topology network, and are transmitted to each node in the network. After the calculation for all sources is completed, i.e., after the value of the network clock parameter tick corresponding to the current round of calculation is transmitted through all sources, the round of network topology calculation is completed.

[0066] Figure 7 A flowchart of the process of topology calculation for the electrical topology network in an embodiment is shown in FIG. 1. Figure 7 The topology calculation of the embodiment includes the following steps:

[0067] 701, a source is taken as the starting point for the calculation; the source can be any source in the electrical topology network, such as a voltage source;

[0068] 702, the value of tick is obtained, which corresponds to the time when the current round of calculation is performed, i.e., the value of tick corresponding to the current round of calculation, which is taken as the tick value of the source; for example, the initial value of tick is 0, and the calculation is the first round of calculation, tick = 1;

[0069] 703, according to the connectivity of the elements in the network, the value of the source, i.e., the potential value or voltage value, and the tick value are transmitted, specifically, output through the pin;

[0070] 704, it is determined whether there is a junction; if there is, step 705 is entered; otherwise, step 708 is executed to end the calculation of the current source, and step 709 is executed to determine whether there is another source; if there is another source, step 701 is entered; otherwise, the flow of the current round of calculation is ended;

[0071] 705, the potential value and tick value are inputted to the corresponding element through the pin joint for processing;

[0072] As there can be a loop in the electrical topology network, such as the input and output of an element being connected, which can cause the topology calculation to enter a dead loop. To avoid the topology calculation entering a dead loop, when the corresponding potential value and tick value are transmitted to the corresponding pin or joint, step 706 is performed first to determine whether the current existing tick value of the corresponding pin or joint is valid, for example, by determining whether the current existing tick value of the corresponding pin or joint is less than the tick value to be transmitted currently to determine whether it is valid; if it is less, it is determined that the current existing tick value of the corresponding pin or joint is valid, and the path corresponding to the corresponding pin or joint has not been calculated, step 707 is performed to continue the current topology calculation, the inputted potential value and tick value are processed by the element corresponding to the corresponding pin or joint, and are outputted to the connected other pins, and then step 703 is entered; otherwise, it means that there is a problem in the current network, and the current topology calculation process is ended; wherein, if the current existing tick value of the corresponding pin or joint is equal to the tick value to be transmitted currently, it means that the tick value to be transmitted currently has passed through the path corresponding to the corresponding pin or joint, i.e. it means that the node corresponding to the corresponding pin or joint has been calculated in the current round of topology calculation. In a specific implementation, for each joint in the network, a corresponding variable is used to store the tick value corresponding to each node such as the pin or joint; the value is updated to the tick value transmitted in the current round of calculation with each round of calculation.

[0073] When the network topology calculation of one round is completed, the electrical topology network is divided into at most 3 parts which are complementary intersections: the ground island, the power island and / or the suspended island. Among them, the suspended island can be empty, i.e. there is no node belonging to the suspended island. Among them, the ground island is a set composed of all the nodes transmitted by the network topology calculation starting from the ground source; the potential value of all the nodes in the ground island is 0, and the tick value is equal to the tick value corresponding to the current round of calculation. The power island is a set composed of all the nodes transmitted by the network topology calculation starting from the voltage source; the potential value of all the nodes in the voltage island is equal to the voltage value of the starting voltage source, and the tick value is equal to the tick value corresponding to the current round of calculation. The suspended island contains all the nodes whose tick values are less than the tick values of the nodes in the power island or the ground island.

[0074] In a specific implementation, according to the nodes contained in the suspended island, it can be determined which elements are currently not in the working state.

[0075] Figure 8 An exemplary electrical topology network is shown in FIG. 1. As shown in FIG. 1, the electrical topology network includes a ground source 101, a voltage source 102, a resistor 103, a capacitor 104, a diode 105, a transistor 106, a pin 107, a pin 108, a pin 109, a pin 110, a pin 111, a pin 112, a pin 113, a pin 114, a pin 115, a pin 116, a pin 117, a pin 118, a pin 119, a pin 120, a pin 121, a pin 122, a pin 123, a pin 124, a pin 125, a pin 126, a pin 127, a pin 128, a pin 129, a pin 130, a pin 131, a pin 132, a pin 133, a pin 134, a pin 135, a pin 136, a pin 137, a pin 138, a pin 139, a pin 140, a pin 141, a pin 142, a pin 143, a pin 144, a pin 145, a pin 146, a pin 147, a pin 148, a pin 149, a pin 150, a pin 151, a pin 152, a pin 153, a pin 154, a pin 155, a pin 156, a pin 157, a pin 158, a pin 159, a pin 160, a pin 161, a pin 162, a pin 163, a pin 164, a pin 165, a pin 166, a pin 167, a pin 168, a pin 169, a pin 170, a pin 171, a pin 172, a pin 173, a pin 174, a pin 175, a pin 176, a pin 177, a pin 178, a pin 179, a pin 180, a pin 181, a pin 182, a pin 183, a pin 184, a pin 185, a pin 186, a pin 187, a pin 188, a pin 189, a pin 190, a pin 191, a pin 192, a pin 193, a pin 194, a pin 195, a pin 196, a pin 197, a pin 198, a pin 199, a pin 200, a pin 201, a pin 202, a pin 203, a pin 204, a pin 205, a pin 206, a pin 207, a pin 208, a pin 209, a pin 210, a pin 211, a pin 212, a pin 213, a pin 214, a pin 215, a pin 216, a pin 217, a pin 218, a pin 219, a pin 220, a pin 221, a pin 222, a pin 223, a pin 224, a pin 225, a pin 226, a pin 227, a pin 228, a pin 229, a pin 230, a pin 231, a pin 232, a pin 233, a pin 234, a pin 235, a pin 236, a pin 237, a pin 238, a pin 239, a pin 240, a pin 241, a pin 242, a pin 243, a pin 244, a pin 245, a pin 246, a pin 247, a pin 248, a pin 249, a pin 250, a pin 251, a pin 252, a pin 253, a pin 254, a pin 255, a pin 256, a pin 257, a pin 258, a pin 259, a pin 260, a pin 261, a pin 262, a pin 263, a pin 264, a pin 265, a pin 266, a pin 267, a pin 268, a pin 269, a pin 270, a pin 271, a pin 272, a pin 273, a pin 274, a pin 275, a pin 276, a pin 277, a pin 278, a pin 279, a pin 280, a pin 281, a pin 282, a pin 283, a pin 284, a pin 285, a pin 286, a pin 287, a pin 288, a pin 289, a pin 290, a pin 291, a pin 292, a pin 293, a pin 294, a pin 295, a pin 296, a pin 297, a pin 298, a pin 299, a pin 300, a pin 301, a pin 302, a pin 303, a pin 304, a pin 305, a pin 306, a pin 307, a pin 308, a pin 309, a pin 310, a pin 311, a pin 312, a pin 313, a pin 314, a pin 315, a pin 316, a pin 317, a pin 318, a pin 319, a pin 320, a pin 321, a pin 322, a pin 323, a pin 324, a pin 325, a pin 326, a pin 327, a pin 328, a pin 329, a pin 330, a pin 331, a pin 332, a pin 333, a pin 334, a pin 335, a pin 336, a pin 337, a pin 338, a pin 339, a pin 340, a pin 341, a pin 342, a pin 343, a pin 344, a pin 345, a pin 346, a pin 347, a pin 348, a pin 349, a pin 350, a pin 351, a pin 352, a pin 353, a pin 354, a pin 355, a pin 356, a pin 357, a pin 358, a pin 359, a pin 360, a pin 361, a pin 362, a pin 363, a pin 364, a pin 365, a pin 366, a pin 367, a pin 368, a pin 369, a pinFigure 8 The exemplary electrical topology network includes a 220V voltage source, two switches and a ground source. Figure 8 When both switches in the above network are open, the topology calculation method using the embodiment of the present application is used to calculate the topology of the electrical topology network shown in the above network. Figure 8 The calculation of the electrical topology network shown in the above network using the topology calculation method of the embodiment of the present application includes:

[0076] When the calculation of the first round is started from the 220V voltage source, the tick value of the voltage source is 1, the voltage value of 220V and the tick value of 1 of the voltage source are transmitted to the first pin of the first switch, that is, the first pin of the first switch obtains the result corresponding to (value: 220, tick: 1) in the above network through the calculation; since both the first switch and the second switch are in the open state, the potential value of 220V and the tick value of 1 of the voltage source are only transmitted to the first pin 801 of the first switch, and the calculation of the voltage source ends; then the topology calculation of this round is performed from the ground source, and the tick value corresponding to this round of calculation is 1, so the potential value of 0V and the tick value of 1 are transmitted from the ground source; since both the first switch and the second switch are in the open state, the potential value of 0V and the tick value of 1 of the ground source are only transmitted to the first pin 802 of the second switch, and the calculation of the ground source ends; since the network only includes two sources, at this point, the tick value of 1 has been transmitted in all sources, and the calculation of this round ends. As a result, the power source island only includes the first pin of the first switch; the ground island only includes the second pin of the second switch, and the other pins and nodes have a tick value of 0, less than 1, and belong to the floating island. Since the power source island and the ground island have no intersection, the electrical topology network meets the anti-misoperation rule, and the network is normal.

[0077] For the electrical topology network, at most one of the two switches can be closed, and if both are closed, it is a short circuit and a fault. Using the topology calculation method of the embodiment of the present application, if both switches are closed, the ground island and the voltage island have an intersection, and it can be judged that the network is abnormal.

[0078] Embodiment three:

[0079] The present application also provides a topology calculation device for power anti-misoperation, which includes a processor, a memory, and a computer program stored in the memory and executable on the processor, the processor includes one or more processing cores, the memory is connected to the processor through a bus, the memory is used to store program instructions, and the processor executes the computer program to implement the steps in the above method embodiments of the first embodiment of the present application.

[0080] Further, as an executable solution, the topology calculation device for power misoperation prevention can be a computer unit, which can be a desktop computer, a notebook computer, a palm computer, a cloud server, and the like. The computer unit can include, but is not limited to, a processor and a memory. Those skilled in the art can understand that the above-mentioned constituent structure of the computer unit is only an example of the computer unit, and does not constitute a limitation on the computer unit, and can include more or fewer components than the above, or combine certain components, or different components. For example, the computer unit can also include an input / output device, a network access device, a bus, and the like, and the embodiments of the present application do not limit this.

[0081] Further, as an executable solution, the processor can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, and the like. The general-purpose processor can be a microprocessor or any conventional processor, and the like. The processor is the control center of the computer unit, and connects various parts of the computer unit through various interfaces and lines.

[0082] The memory can be used to store the computer program and / or modules, and the processor realizes various functions of the computer unit by running or executing the computer program and / or modules stored in the memory, and calling the data stored in the memory. The memory can mainly include a program storage area and a data storage area, wherein the program storage area can store an operating system and at least one application required by a function; the data storage area can store data created according to the use of the mobile phone, and the like. In addition, the memory can include a high-speed random access memory, and can also include a non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, at least one disk storage device, a flash memory device, or other volatile solid-state memory devices.

[0083] Embodiment Four

[0084] The application further provides a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement the steps of the method of the above-mentioned embodiments of the application.

[0085] The modules / cells integrated with the computer unit, if realized in the form of software functional units and sold or used as independent products, can be stored in a computer readable storage medium. Based on such understanding, the application can also be implemented by a computer program to instruct related hardware to complete all or part of the processes of the above-mentioned embodiments, and the computer program can be stored in a computer readable storage medium. The computer program includes computer program code, which can be in the form of source code, object code, executable files or some intermediate forms, etc. The computer readable medium can include any entity or device capable of carrying the computer program code, recording medium, U disk, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM) and software distribution medium, etc. It should be noted that the content included in the computer readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction.

[0086] Embodiment five:

[0087] The application further provides a computer program product, which includes a computer program, and the computer program is executed by a processor to implement the steps of the method as described above.

[0088] Although the application is specifically shown and described in connection with preferred embodiments, those skilled in the art should understand that various changes in form and details can be made to the application without departing from the spirit and scope of the application as defined in the appended claims.

Claims

1. A topology calculation method for preventing power errors, characterized in that: include: An electrical topology network of the circuit is constructed by a one-to-one correspondence between elements in the electrical topology network and actual devices in the circuit, wherein the elements in the electrical topology network include: sources, wires, and switches; the sources include: voltage sources and ground sources; wherein, in the electrical topology network, the elements are interconnected through pins, and multiple pins are connected through contacts, wherein one pin points to one contact, and one contact points to multiple pins; Performing a network topology calculation on the electrical topology network, setting a network clock parameter to identify the time of executing each round of network topology calculation, wherein in a round of network topology calculation, for each source in the electrical topology network, starting from the source, traversing the pins and / or contacts in the electrical topology network according to the connectivity of the elements in the electrical topology network, transferring the potential value corresponding to the source and the network clock parameter value corresponding to the current round; When the network clock parameter values ​​corresponding to the current round are transmitted once in all sources of the electrical topology network, the network topology calculation of the current round is completed, and the ground island, power island and floating island of the electrical topology network are obtained, wherein the ground island is a set of nodes to which the potential value of the ground source is transmitted when the ground source is used as the starting point; the power island is a set of nodes to which the potential value of the voltage source is transmitted when the voltage source is used as the starting point; and the floating island is a set of nodes whose network clock parameter values ​​are less than the network clock parameter values ​​corresponding to the current round; In the same round of network topology calculation, when the ground island and the power island intersect, the electrical topology network is abnormal; Before traversing the pins and / or contacts in the electrical topology network and transferring the potential value corresponding to the source and the network clock parameter value corresponding to the current round, the method further includes: For the currently traversed pin and / or contact, determine whether the value of the network clock parameter currently corresponding to the currently traversed pin and / or contact is less than the value of the network clock parameter corresponding to the current round; if so, transfer the value of the network clock parameter corresponding to the current round to the currently traversed pin and / or contact; otherwise, stop transferring the value of the network clock parameter corresponding to the current round to the currently traversed pin and / or contact.

2. The topology calculation method according to claim 1, characterized in that: The initial value of the network clock parameter is 0.

3. The topology calculation method according to claim 1, characterized in that: After each round of network topology calculation, the value of the network clock parameter is automatically incremented.

4. The topology calculation method according to claim 1, characterized in that: The network clock parameter value of a pin or a contact in the electrical topology network identifies the round of network topology calculation in which the pin or the contact participates.

5. The topology calculation method according to claim 1, characterized in that: In the same round of network topology calculation, when there is no intersection between the ground island and the power island, the electrical topology network is normal.

6. A topology calculation device for preventing power errors, characterized in that: The method comprises a memory and a processor, wherein the memory stores at least one program, and the at least one program is executed by the processor to implement the steps of the topology calculation method according to any one of claims 1 to 5.

7. A computer-readable storage medium, characterized in that The storage medium stores at least one program, and the at least one program is executed by a processor to implement the steps of the topology calculation method according to any one of claims 1 to 5.

8. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the topology calculation method according to any one of claims 1 to 5 are implemented.

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