Frequency conversion circuit of power supply

Abstract

The invention discloses a frequency conversion circuit of a power supply. The frequency conversion circuit comprises a frequency adjusting circuit; and a switch control signal generating circuit coupled to the frequency adjusting circuit. The switch control signal generating circuit generates a plurality of switch control signals to the frequency adjusting circuit according to a peak load request so as to control a plurality of switches of the frequency adjusting circuit. In response to the switching control signals, an internal equivalent resistance and an internal equivalent capacitance of the frequency adjustment circuit are changed. In response to the internal equivalent resistance and the internal equivalent capacitance of the frequency adjustment circuit being changed, the frequency adjustment circuit controls a switching frequency of a power factor correction circuit power stage of the power supply to meet the peak load request.

Description

Technical Field

[0001] The invention relates to a power supply, and in particular to a frequency conversion circuit of the power supply. Background Art

[0002] A power supply provides power to multiple units in an electronic system. An electronic system may include one or more high power consuming units, such as a central processing unit (CPU) or a graphics processing unit (GPU). When the central processing unit (CPU) or the graphics processing unit (GPU) requires a lot of power, a peak load demand will occur. In order to meet the peak load demand and avoid saturation of the internal inductor of the power factor correction (PFC) circuit of the power supply during the peak load period, there are currently several approaches. One approach is to increase the number of winding turns of the PFC inductor, but this will increase the size of the choke. The second approach is to increase the cross-sectional area of ​​the choke, but this will also increase the size of the choke. The third approach is to increase the air gap of the choke to reduce the inductance value, but this will reduce the efficiency of the PFC and is not conducive to low power consumption. The fourth approach is to change the material of the choke from ferroelectric material to soft saturation material, but this will reduce the efficiency of the PFC and have an acoustic impact.

[0003] Therefore, the industry is working hard to develop a frequency conversion circuit for a power supply that can reduce the shortcomings of the prior art and provide many advantages. Summary of the invention

[0004] In view of the shortcomings of the prior art, the present invention provides a frequency conversion circuit for a power supply, which can avoid affecting the power supply efficiency of the power supply without increasing the number of turns or the cross-sectional area of ​​the middle column of the PFC inductor.

[0005] The present invention provides a frequency conversion circuit of a power supply, comprising: a frequency adjustment circuit; and a switch control signal generating circuit coupled to the frequency adjustment circuit. The switch control signal generating circuit generates a plurality of switch control signals to the frequency adjustment circuit according to a peak load request to control a plurality of switches of the frequency adjustment circuit. In response to the switch control signals, an internal equivalent resistance and an internal equivalent capacitance of the frequency adjustment circuit are changed. In response to the internal equivalent resistance and the internal equivalent capacitance of the frequency adjustment circuit being changed, the frequency adjustment circuit controls a switching frequency of a power stage of a power factor correction circuit of the power supply to meet the peak load request.

[0006] It can be seen from the above scheme that the advantages of the present invention are:

[0007] When there is a peak load request at the system end or the load end, the present invention increases the switching frequency of the power factor correction circuit of the power supply to reduce the peak current of the internal inductor of the power stage of the power factor correction circuit of the power supply, thereby making the internal inductor less likely to enter inductor saturation. Therefore, the present invention can avoid affecting the power supply efficiency of the power supply without increasing the number of turns or the cross-sectional area of ​​the middle column of the PFC inductor. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a functional block diagram of a power supply according to an embodiment of the present invention;

[0009] Figure 2 It is a circuit structure diagram of a frequency adjustment circuit and a switch control signal generating circuit according to a first embodiment of the present invention;

[0010] Figure 3 is a circuit structure diagram of a frequency adjustment circuit and a switch control signal generating circuit according to a second embodiment of the present invention;

[0011] Figure 4A and Figure 4B is a circuit structure diagram of a frequency adjustment circuit and a switch control signal generating circuit according to a third embodiment of the present invention;

[0012] Figure 5 is a waveform diagram of inductance value and switching frequency according to an embodiment of the present invention;

[0013] Fig. 6A The waveform diagram of the inductor current IL, the output voltage Vout and the output current Iout in the prior art;

[0014] Figure 6B 1 is a waveform diagram of the inductor current IL, the output voltage Vout and the output current Iout according to an embodiment of the present invention;

[0015] Among them, the reference numerals

[0016] 100-power supply;

[0017] 110-Power factor correction circuit power stage;

[0018] 120-control circuit;

[0019] 130- frequency conversion circuit;

[0020] 140, IC103-controller;

[0021] 150-frequency adjustment circuit;

[0022] 151-Resistor-Capacitor (RC) Circuit;

[0023] 152- switch circuit;

[0024] 160, 160A, 160B-switch control signal generating circuit;

[0025] RT, RT2, R142~R143, R145~R150, R133~R139, R141, Rshunt, R158~R162 - resistors;

[0026] CT, CT2, C123-C125, Cout-capacitor;

[0027] SW1, SW2, Q115, Q108, Q118-Q120- switches;

[0028] Q117-transistor;

[0029] PC101-optically coupled diode;

[0030] Fsw - switching frequency. DETAILED DESCRIPTION

[0031] The technical terms in this specification refer to the customary terms in the technical field. If some terms are explained or defined in this specification, the interpretation of these terms shall be based on the explanation or definition in this specification. Each embodiment of the present invention has one or more technical features. Under the premise of possible implementation, a person with ordinary knowledge in the technical field can selectively implement some or all of the technical features in any embodiment, or selectively combine some or all of the technical features in these embodiments.

[0032] In order to better understand the above technical solutions and other aspects of the present invention, embodiments are given below and described in detail with reference to the accompanying drawings as follows:

[0033] Figure 1 FIG. 1 is a functional block diagram of a power supply according to an embodiment of the present invention. Figure 1 As shown, a power supply 100 according to an embodiment of the present invention includes a power factor correction (PFC) circuit power stage 110 and a control circuit 120. The power factor correction circuit power stage 110 is coupled to the control circuit 120. The architecture of the power factor correction circuit power stage 110 is not particularly limited herein. In addition, the power factor correction circuit power stage 110 includes an internal inductor (not shown).

[0034] The control circuit 120 includes a frequency conversion circuit 130 and other components (not shown). The frequency conversion circuit 130 includes: a frequency adjustment circuit 150 and a switch control signal generating circuit 160. The frequency adjustment circuit 150 includes a controller 140 and other components (not shown). The frequency adjustment circuit 150 is coupled to the switch control signal generating circuit 160.

[0035] The switch control signal generating circuit 160 can generate a switch control signal according to the peak load request to control the internal switch (not shown) of the frequency adjustment circuit 150. When the internal switch of the frequency adjustment circuit 150 is controlled, the internal equivalent resistance and the internal equivalent capacitance of the frequency adjustment circuit 150 will be changed. In response to the change of the internal equivalent resistance and the internal equivalent capacitance of the frequency adjustment circuit 150, the controller 140 can control the switching frequency of the power factor correction circuit power stage 110 to meet the peak load request. Here, the peak load request at least includes: a sudden increase in load signal sent by the system end or the load end, or an output current exceeding a threshold value (such as Figures 2 to 4A and Figure 4B Iout).

[0036] The switch control signal generating circuit 160 may have multiple implementations, which will be described below.

[0037] First embodiment:

[0038] Figure 2 FIG. 1 is a circuit diagram of the frequency adjustment circuit 150 and the switch control signal generating circuit 160 according to the first embodiment of the present invention. Figure 2 As shown, the controller 140 is implemented as a control integrated circuit (IC).

[0039] The frequency adjustment circuit 150 includes a controller 140, a resistor-capacitor (RC) circuit 151, and a switch circuit 152. The RC circuit 151 includes resistors RT and RT2, capacitors CT and CT2; the switch circuit 152 includes switches SW1 and SW2. The controller 140 is coupled to the RC circuit 151 and the switch circuit 152.

[0040] The switch SW1 includes: a first terminal (for example but not limited to a source terminal) coupled to the resistor RT, the capacitors CT and CT2; a second terminal (for example but not limited to a drain terminal) coupled to the resistor RT2; and a control terminal (for example but not limited to a gate terminal) receiving the first switch control signal VGS_SW1 generated by the switch control signal generating circuit 160.

[0041] The switch SW2 includes: a first terminal (for example but not limited to a source terminal) coupled to the ground terminal; a second terminal (for example but not limited to a drain terminal) coupled to the capacitor CT2; and a control terminal (for example but not limited to a gate terminal) receiving the second switch control signal VGS_SW2 generated by the switch control signal generating circuit 160.

[0042] The resistor RT is coupled between the reference voltage VREF provided by the controller 140 and the first terminal of the switch SW1. The resistor RT2 is coupled between the reference voltage VREF provided by the controller 140 and the second terminal of the switch SW1.

[0043] The capacitor CT is coupled between the first terminal of the switch SW1 and the ground terminal. The capacitor CT2 is coupled between the first terminal of the switch SW1 and the second terminal of the switch SW2.

[0044] The switch control signal generating circuit 160 includes a switch Q115, a switch Q108, a transistor Q117, an optically coupled diode PC101, resistors R142-R143 and R145-R150. The resistors R145 and R150 form a voltage divider circuit, and the resistors R148 and R149 form a voltage divider circuit.

[0045] The switch Q115 includes: a first terminal (for example but not limited to a source terminal) coupled to the ground terminal; a second terminal (for example but not limited to a drain terminal) coupled to the resistor R146 and outputting a second switch control signal VGS_SW2; and a control terminal (for example but not limited to a gate terminal) coupled to the optically coupled diode PC101.

[0046] The switch Q108 includes: a first terminal (for example but not limited to a source terminal) coupled to the ground terminal; a second terminal (for example but not limited to a drain terminal) coupled to the optically coupled diode PC101; and a control terminal (for example but not limited to a gate terminal) receiving a surge load signal SL. The surge load signal SL is sent by the system terminal or the load terminal. When the system terminal or the load terminal requires high power, the surge load signal SL is, for example but not limited to, a low level (0-0.1V); and when the system terminal or the load terminal requires normal power, the surge load signal SL is, for example but not limited to, a high level (3-5V).

[0047] The transistor Q117 includes: a first terminal coupled to the voltage source PFC_VCC; a second terminal coupled to the resistors R146 and R147; and a third terminal outputting the first switch control signal VGS_SW1 through the resistor R149.

[0048] The optically coupled diode PC101 includes: a first terminal receiving a voltage Vout; a first terminal coupled to a switch Q108 through a resistor R143; a third terminal coupled to resistors R145 and R150; and a fourth terminal coupled to the ground terminal.

[0049] Resistor R142 is coupled between the surge load signal SL and the ground terminal. Resistor R143 is coupled between the optical coupling diode PC101 and the switch Q108. Resistors R145 and R150 form a voltage divider circuit, which is coupled in series between the voltage source PFC_VCC and the ground terminal. Resistor R146 is coupled between the transistor Q117 and the switch Q115. Resistor R147 is coupled between the voltage source PFC_VCC and resistor R146. Resistor R148 and R149 form a voltage divider circuit, which is coupled in series between the transistor Q117 and the ground terminal.

[0050] The operation of the first embodiment of the present invention will now be described.

[0051] The controller 140 and the frequency adjustment circuit 150 are used to switch the switching frequency of the power supply 100 , and the switch control signal generating circuit 160 can detect the sudden increase load signal SL provided by the system end or the load end.

[0052] The operating principles of the controller 140 and the frequency adjustment circuit 150 are divided into two states: state 1 (surge load is present, the switching frequency is increased) and state 2 (surge load is not present, the original switching frequency is maintained). They will be described below.

[0053] When the system or the load side makes a sudden load request, the sudden load signal SL is at a low level; and when the system or the load side does not make a sudden load request (that is, when the power requirement of the system or the load side is normal power), the sudden load signal SL is at a high level.

[0054] In state 1 (surge load is established, the switching frequency is increased), in response to the surge load signal SL at a low level, the switch control signal generating circuit 160 generates a high-level first switch control signal VGS_SW1 and a low-level second switch control signal VGS_SW2. When the first switch control signal VGS_SW1 is at a high level, the first switch SW1 is turned on, so that the resistors RT and RT2 are connected in parallel, and the equivalent resistance is RT in parallel with RT2 (RT / / RT2). When the second switch control signal VGS_SW2 is at a low level, the second switch SW2 is turned off, and the equivalent capacitance is CT.

[0055] An example is given below, but these data are only used for illustration and are not used to limit the present invention. RT = 27KΩ; RT2 = 15.8KΩ; CT = 470pF; CT2 = 560pF. VREF = 7.52V.

[0056] In state 1: equivalent resistance Req=RT / / RT2=9.97KΩ, and equivalent capacitance Ceq=CT=470pF.

[0057] tRAMP=9.97K*470p*0.5678=2.66μs.

[0058] tDEADTIME=292*500p=0.137μs.

[0059] The switching frequency Fsw_high in state 1 can be expressed as:

[0060] Fsw_high=1 / tRAMP=1 / (0.5678*(RT / / RT2)*CT)

[0061] =1 / (2.66μs+0.137μs)=357.4kHz.

[0062] Wherein, tRAMP represents the charging time tRAMP when the reference voltage VREF charges the capacitor CT through the resistor RT until the cross voltage of the capacitor CT reaches the set value (for example, but not limited to about 4V). When the cross voltage of the capacitor CT reaches the set value, the capacitor CT is discharged, and the discharge time tDEADTIME is passed when the cross voltage of the capacitor CT is discharged to another set value (for example, but not limited to about 1.5V). The frequency setting is achieved by charging and discharging the capacitor CT within a fixed voltage range. Usually, the discharge time tDEADTIME is very short, so the frequency can be approximated to 1 / tRAMP.

[0063] The operating frequency can be changed by adjusting the values ​​of the resistor RT and the capacitor CT. This means that the charging and discharging time of the capacitor CT can be adjusted by changing the resistance value and / or capacitance value of the resistor RT and the capacitor CT, thereby achieving frequency adjustment.

[0064] In state 2 (surge load is not established, original switching frequency is maintained), in response to the surge load signal SL at a high level, the switch control signal generating circuit 160 generates a low-level first switch control signal VGS_SW1 and a high-level second switch control signal VGS_SW2 .

[0065] When the first switch control signal VGS_SW1 is at a low level, the first switch SW1 is turned off, and the equivalent resistance is equal to the resistance RT. When the second switch control signal VGS_SW2 is at a high level, the second switch SW2 is turned on, and the equivalent capacitance is (CT+CT2).

[0066] tRAMP=27K*1000p*0.5678=15.33μs.

[0067] tDEADTIME=292*1000p=0.292μs.

[0068] The switching frequency Fsw_normal in state 2 can be expressed as:

[0069] Fsw_normal=1 / tRAMP=1 / (0.5678*RT*(CT+CT2))

[0070] =1 / (15.33μs+0.292μs)=64kHz.

[0071] Similarly, the operation principle of the switch control signal generating circuit 160 is divided into two states: state 1 (surge load is established, the switching frequency is increased), and state 2 (surge load is not established, the original switching frequency is maintained). They will be described below.

[0072] In state 1 (surge load is established, the switching frequency is increased), in response to the surge load signal SL at a low level, the switch Q108 is turned off, and the optically coupled diode PC101 is also turned off. After the voltage source PFC_VCC is divided by the resistors R145 and R150, the divided voltage is input to the control end of the switch Q115 to turn on the switch Q115, so that the second switch control signal VGS_SW2 is low. Since the switch Q115 is turned on, the transistor Q117 is turned on due to the bias of the resistors R146 and R147. Through the turned-on transistor Q117, the voltage source PFC_VCC is divided by the resistors R148 and R149 to generate a high-level first switch control signal VGS_SW1.

[0073] In state 2 (surge load is not established, the original switching frequency is maintained), in response to the surge load signal SL at a high level, the switch Q108 is turned on and the optical coupling diode PC101 is also turned on. Since the optical coupling diode PC101 is turned on, the switch Q115 is turned off, so the second switch control signal VGS_SW2 is at a high level. Since the switch Q115 is turned off, no bias is generated, so that the transistor Q117 is turned off, and the first switch control signal VGS_SW1 is at a low level.

[0074] Through the above operations, in the first embodiment of the present invention, when a sudden increase in load occurs, the switching frequency can be increased (for example, but not limited to, increased by at least 5 times) so that the power supply can provide higher power to the system end or the load end; and, when there is no sudden increase in load request, the switching frequency can be maintained.

[0075] Second embodiment:

[0076] Figure 3 FIG. 1 is a circuit structure diagram of a frequency adjustment circuit 150 and a switch control signal generating circuit 160A according to a second embodiment of the present invention. Figure 3The frequency adjustment circuit 150 is substantially the same as Figure 2 The frequency adjustment circuit 150 is described above, so its circuit structure and operation details are omitted here.

[0077] Different from Figure 3 ,exist Figure 3 In the embodiment, the switch control signal generating circuit 160A detects the current to determine whether a sudden load increase request is issued from the system end or the load end, and further determines whether to increase the switching frequency.

[0078] The switch control signal generating circuit 160A includes: a switch Q115, a switch Q108, a transistor Q117, an optically coupled diode PC101, resistors R142-R143 and R145-R150; and a controller IC103, resistors R133-R139, R141, Rshunt, capacitors C123-C125, and Cout.

[0079] The controller IC 103 has 8 pins.

[0080] Resistor R133 is coupled between controller IC103 and resistor Rshunt. Resistor R134 is coupled between controller IC103 and resistor Rshunt. Resistor R135 is coupled between controller IC103 and ground. Resistor R136 is coupled between controller IC103 and resistor R134. Resistors R137 and R138 are coupled in series between controller IC103 and ground. Resistor R139 is coupled between controller IC103 and output voltage Vout. Resistors R141 and R142 are coupled in series between controller IC103 and ground. Capacitor C123 is coupled between controller IC103 and ground. Capacitor C124 is coupled between controller IC103 and ground. Capacitor C125 is coupled between two pins of controller IC103.

[0081] Figure 3 The operating principles of the controller 140 and the frequency adjustment circuit 150 are basically the same as Figure 2 The operating principles of the controller 140 and the frequency adjustment circuit 150 are described above, and thus the details are omitted here.

[0082] The operation principle of the switch control signal generating circuit 160A is divided into two states: state 1 (sudden load increase occurs, the switching frequency is increased) and state 2 (sudden load increase does not occur, the original switching frequency is maintained). They will be described below.

[0083] In state 1 (sudden load increase, increasing switching frequency), the output current Iout flows through the resistor Rshunt to generate a voltage difference ΔV, so the resistor Rshunt can also be called a sampling resistor. In the second embodiment of the present invention, the pins 5, 6, and 7 of the controller IC103 form an operational amplifier, and the resistors R133, R134, R135, and R136 and the operational amplifier (composed of the pins 5, 6, and 7 of the controller IC103) form a differential signal amplifier circuit. After the voltage difference ΔV generated by the resistor Rshunt is amplified by the differential signal amplifier circuit (amplification factor = (R136 / R134)), an amplified voltage "ΔV*(R136 / R134)" is generated at the pin 7 of the controller IC103. After this amplified voltage "ΔV*(R136 / R134)" is divided by the resistors R137 and R138, the divided voltage is input to the pin 2 of the controller IC103. The divided voltage is compared with the reference voltage (for example but not limited to 2.5V) of pin 3 of controller IC103. When the divided voltage of pin 2 of controller IC103 is greater than the reference voltage of pin 3 of controller IC103, pin 1 of controller IC103 outputs a low-level signal, so that switch Q108 is turned off and optically coupled diode PC101 is also turned off. After the voltage source PFC_VCC is divided by resistors R145 and R150, the divided voltage is input to the control end of switch Q115 to turn on switch Q115, so that the second switch control signal VGS_SW2 is low. Since switch Q115 is turned on, transistor Q114 is turned on due to the bias of resistors R146 and R147, and the voltage source PFC_VCC is divided by resistors R148 and R149 to generate a high-level first switch control signal VGS_SW1.

[0084] In state 2 (sudden load increase does not exist, and the original switching frequency is maintained), since the output current Iout is small, the divided voltage of pin 2 of the controller IC103 will be smaller than the reference voltage of pin 3 of the controller IC103, and the pin 1 of the controller IC103 outputs a high-level signal. The switch Q108 is turned on and the optical coupling diode PC101 is also turned on. Since the optical coupling diode PC101 is turned on, the switch Q115 is turned off, so the second switch control signal VGS_SW2 is high. Since the switch Q115 is turned off, no bias is generated, so that the transistor Q117 is turned off, and the first switch control signal VGS_SW1 is low.

[0085] Through the above operations, in the second embodiment of the present invention, when a sudden increase in load occurs, the switching frequency can be increased (for example, but not limited to, increased by at least 5 times) so that the power supply can provide higher power to the system end or the load end; and, when there is no sudden increase in load request, the switching frequency can be maintained.

[0086] Third embodiment:

[0087] Figure 4A and Figure 4B FIG. 1 is a circuit diagram of the frequency adjustment circuit 150 and the switch control signal generating circuit 160B of the third embodiment of the present invention. The switch control signal generating circuit 160B of the third embodiment can be regarded as a combination of the switch control signal generating circuit 160 of the first embodiment and the switch control signal generating circuit 160A of the second embodiment. Figure 3 The frequency adjustment circuit 150 is substantially the same as Figure 2 The frequency adjustment circuit 150 is described above, so its circuit structure and operation details are omitted here.

[0088] Different from Figure 2 and Figure 3 ,exist Figure 4A and Figure 4B In the embodiment, the switch control signal generating circuit 160B detects the output current Iout to determine whether to increase the switching frequency, and / or the switch control signal generating circuit 160B detects a sudden load increase request from the system end or the load end to determine whether to increase the switching frequency.

[0089] like Figure 4A and Figure 4B As shown, the switch control signal generating circuit 160B includes: switch Q115, switch Q108, transistor Q117, optically coupled diode PC101, resistors R142~R143 and R145~R150, controller IC103, resistors R133~R139, R141, Rshunt, capacitors C123-C125, Cout; and switches Q118-Q120, resistors R158~R162.

[0090] The switch Q118 includes: a first terminal (for example but not limited to a source terminal) coupled to the switch Q119; a second terminal (for example but not limited to a drain terminal) coupled to the resistor R160; and a control terminal (for example but not limited to a gate terminal) receiving a divided voltage divided by the resistors R141 and R142.

[0091] The switch Q119 includes: a first terminal (for example but not limited to a source terminal) coupled to the ground terminal; a second terminal (for example but not limited to a drain terminal) coupled to the first terminal of the switch Q119; and a control terminal (for example but not limited to a gate terminal) receiving the surge load signal SL.

[0092] The switch Q120 includes: a first terminal (for example but not limited to a source terminal) coupled to the ground terminal; a second terminal (for example but not limited to a drain terminal) coupled to the control terminal of the switch Q108; and a control terminal (for example but not limited to a gate terminal) receiving a divided voltage divided by the resistors R159 and R160.

[0093] Resistors R158 and R162 are coupled in series between the output voltage Vout and the ground terminal to divide the output voltage Vout, and the divided voltage is received by the control terminal of the switch Q108. Resistors R159 and R160 are coupled in series between the output voltage Vout and the ground terminal to divide the output voltage Vout, and the divided voltage is received by the control terminal of the switch Q120. Resistor R161 is coupled between the control terminal of the switch Q119 and the ground terminal.

[0094] The operating principle of the controller 140 and the frequency adjustment circuit 150 is divided into two states: state 1 (surge load exists, increase the switching frequency), and state 2 (surge load does not exist, maintain the original switching frequency). The details are omitted here.

[0095] The operation of the switch control signal generating circuit 160B in state 1 (surge load is established, the switching frequency is increased) and state 2 (surge load is not established, the original switching frequency is maintained) will now be described.

[0096] In state 1 (sudden load is established, the switching frequency is increased), in response to the sudden load signal SL of a low level, the switch Q119 is turned off; and in state 2 (sudden load is not established, the original switching frequency is maintained), in response to the sudden load signal SL of a high level, the switch Q119 is turned on.

[0097] The details of detecting the output current Iout so as to make the pin 1 of the controller IC103 output a high level signal or a low level signal may be referred to the second embodiment and will not be repeated here.

[0098] In the third embodiment of the present invention, the switches Q118 and Q119 are designed as NAND logic. When the system or the load sends a low-level surge load signal SL to the switch Q119, the gate-source voltage of the switch Q119 is low to turn off the switch Q119; and, when the system or the load sends a high-level surge load signal SL to the switch Q119, the gate-source voltage of the switch Q119 is high to turn on the switch Q119. When the output current Iout causes the pin 1 of the controller IC103 to output a low-level signal, the gate-source voltage of the switch Q118 is low to turn off the switch Q118; and, when the output current Iout causes the pin 1 of the controller IC103 to output a high-level signal, the gate-source voltage of the switch Q118 is high to turn on the switch Q118. When one of the gate-source voltages of the switches Q118 and Q119 is at a low level or both are at a low level (i.e., the system end or the load end sends a low-level surge load signal SL, or / and, the output current Iout causes the pin 1 of the controller IC103 to output a low-level signal), it is considered that the surge load condition is met. Conversely, when the gate-source voltages of the switches Q118 and Q119 are at a high level at the same time, the surge load condition is not met.

[0099] State 1 (surge load is established, increasing switching frequency):

[0100] The condition is that one of the gate-source voltages of switches Q118 and Q119 is at a low level or both are at a low level, then switches Q118 and / or Q119 are turned off. Therefore, the voltage divided by resistors R160 and R159 on the output voltage Vout turns on switch Q120. Since the switch Q120 is turned on, the gate-source voltage of the switch Q108 is at a low level, and the switch Q108 is turned off (cut off), so that the optically coupled diode PC101 is also cut off. The divided voltage after the voltage source PFC_VCC is divided by the resistors R145 and R150 turns on the switch Q115, so that the second switch control signal VGS_SW2 is at a low level. When the switch Q115 is turned on, the transistor Q114 is turned on due to the bias voltage of the resistors R146 and R147. The resistors R149 and R148 generate a high-level first switch control signal VGS_SW1 for the divided voltage of the voltage source PFC_VCC.

[0101] State 2 (surge load does not apply, original switching frequency is maintained):

[0102] The establishment condition is that the gate-source voltage of switches Q118 and Q119 is high at the same time, switches Q118 and Q119 are turned on at the same time, so that the gate-source voltage of switch Q120 is low, switch Q120 is turned off, resistors R162 and R158 divide the output voltage Vout, so that switch Q108 is turned on, and the optical coupling diode PC101 is also turned on. The conduction of the optical coupling diode PC101 makes the gate-source voltage of switch Q115 low, switch Q115 is turned off, and the second switch control signal VGS_SW2 is high. Since switch Q115 is turned off, no bias is generated, and the switch transistor Q114 is turned off, so that the first switch control signal VGS_SW1 is low.

[0103] Through the above operations, in the third embodiment of the present invention, when a sudden increase in load occurs, the switching frequency can be increased (for example but not limited to, increased by at least 5 times) so that the power supply can provide higher power to the system end or the load end; and, when there is no sudden increase in load request, the switching frequency can be maintained.

[0104] Figure 5 FIG. 1 is a waveform diagram of the inductance value and the switching frequency according to an embodiment of the present invention. Figure 5 As shown in FIG. 1 , when entering the peak load stage, if the switching frequency Fsw is only slightly increased, the internal inductance value of the PFC circuit of the power supply is only slightly reduced. However, if the switching frequency Fsw is increased by 2 times or more, the internal inductance value of the PFC circuit of the power supply can be greatly reduced to avoid inductor saturation.

[0105] Fig. 6A and Figure 6B The waveforms of the inductor current IL, the output voltage Vout and the output current Iout of the prior art and an embodiment of the present invention are shown respectively. Fig. 6A As shown in FIG. 1 , in the prior art, when entering the peak load stage, since the switching frequency Fsw is not increased, the inductor has a high peak current value, and then the inductor enters a saturation state. Figure 6B As shown, in one embodiment of the present invention, when entering the peak load stage, since the switching frequency Fsw is increased (from 65kHz to 325kHz), the peak current value of the inductor is lower, and thus the inductor is less likely to enter the saturation state.

[0106] As described above, in the above embodiment of the present invention, when there is a peak load request at the system end or the load end, the switching frequency of the power factor correction circuit of the power supply is increased to reduce the peak current of the internal inductor of the power stage of the power factor correction circuit of the power supply, thereby making the internal inductor less likely to enter inductor saturation. Therefore, an embodiment of the present invention can avoid affecting the power supply efficiency of the power supply without increasing the number of turns or the cross-sectional area of ​​the middle column of the PFC inductor.

[0107] In summary, although the present invention has been disclosed as above by the embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application.

Claims

1. A frequency conversion circuit of a power supply, characterized in that: include: a frequency adjustment circuit; as well as a switch control signal generating circuit, coupled to the frequency adjusting circuit, The switch control signal generating circuit generates a plurality of switch control signals to the frequency adjustment circuit according to a peak load request, so as to control a plurality of switches of the frequency adjustment circuit. In response to the switch control signals, an internal equivalent resistance and an internal equivalent capacitance of the frequency adjustment circuit are changed; In response to the internal equivalent resistance and the internal equivalent capacitance of the frequency adjustment circuit being changed, the frequency adjustment circuit controls a switching frequency of a power stage of a power factor correction circuit of the power supply to meet the peak load request.

2. The frequency conversion circuit according to claim 1, characterized in that: The peak load request at least includes: a sudden load increase signal sent by a system end or a load end, and / or an output current exceeding a threshold value.

3. The frequency conversion circuit according to claim 1, characterized in that: When a system end or a load end makes the peak load request, a surge load signal is at a first level; and When the system end or the load end does not make the peak load request, the surge load signal is at a second level.

4. The frequency conversion circuit according to claim 1, characterized in that: The frequency adjustment circuit comprises: a first controller; a resistor-capacitor circuit coupled to the first controller, the resistor-capacitor circuit comprising a plurality of resistors and a plurality of capacitors; and A switch circuit is coupled to the first controller, and the switch circuit includes the plurality of switches.

5. The frequency conversion circuit according to claim 4, characterized in that: When a sudden load increase occurs: In response to a sudden increase load signal of a first level, the switch control signal generating circuit generates a first switch control signal of a second level and a second switch control signal of a first level; When the first switch control signal is at the second level and the second switch control signal is at the first level, the switch circuit controls the internal equivalent resistance of the plurality of resistors of the resistor-capacitor circuit to be a first equivalent resistance value, and the switch circuit controls the internal equivalent capacitance of the plurality of capacitors of the resistor-capacitor circuit to be a first equivalent capacitance value; and The first controller controls the switching frequency of the power stage of the power factor correction circuit of the power supply to be a first switching frequency; and In the case where a sudden load increase does not exist: In response to the surge load signal at a second level, the switch control signal generating circuit generates a first switch control signal at a first level and a second switch control signal at a second level; as well as When the first switch control signal is at the first level and the second switch control signal is at the second level, the switch circuit controls the internal equivalent resistance of the plurality of resistors of the resistor-capacitor circuit to be a second equivalent resistance value, and the switch circuit controls the internal equivalent capacitance of the plurality of capacitors of the resistor-capacitor circuit to be a second equivalent capacitance value; and The first controller controls the switching frequency of the power stage of the power factor correction circuit of the power supply to be a second switching frequency, The first equivalent resistance value is lower than the second equivalent resistance value, the first equivalent capacitance value is lower than the second equivalent capacitance value, and the first switching frequency is higher than the second switching frequency.

6. The frequency conversion circuit according to claim 5, characterized in that: The switch control signal generating circuit comprises: a first switch, receiving the sudden load increase signal; an optically coupled diode, coupled to the first switch; a second switch, coupled to the optically coupled diode, to generate the second switch control signal; and A transistor is coupled to the second switch and generates the first switch control signal.

7. The frequency conversion circuit according to claim 6, characterized in that: When the surge load is established: In response to the surge load signal at the first level, the first switch is turned off, the optically coupled diode is also turned off, the second switch is turned on to generate the second switch control signal at the first level, and the transistor is turned on to generate the first switch control signal at the second level.

8. The frequency conversion circuit according to claim 6, characterized in that: When the surge load does not exist: In response to the surge load signal at the second level, the first switch is turned on, the optically coupled diode is also turned on, the second switch is turned off to generate the second switch control signal at the second level, and the transistor is turned off to generate the first switch control signal at the first level.

9. The frequency conversion circuit according to claim 5, characterized in that: The switch control signal generating circuit comprises: a first switch; an optically coupled diode, coupled to the first switch; a second switch, coupled to the optically coupled diode, generating the second switch control signal; a transistor, coupled to the second switch, generating the first switch control signal; a sampling resistor, used for sampling an output current; and A second controller is coupled to the sampling resistor and the first switch.

10. The frequency conversion circuit according to claim 9, characterized in that: When the surge load is established: The output current flows through the sampling resistor to generate a voltage difference. According to the voltage difference and a reference voltage, the second controller outputs a first level An output signal, In response to the output signal of the second controller being at the first level, the first switch is turned off, the optically coupled diode is also turned off, the second switch is turned on to generate the second switch control signal at the first level, and the transistor is turned on to generate the first switch control signal at the second level.

11. The frequency conversion circuit according to claim 9, characterized in that: When the surge load does not exist: The output current flows through the sampling resistor to generate a voltage difference. According to the voltage difference and a reference voltage, the second controller outputs the output signal of a second level. In response to the output signal of the second controller being the second level, the first switch is turned on, the optically coupled diode is also turned on, the second switch is turned off to generate the second switch control signal being the second level, and the transistor is turned off to generate the first switch control signal being the first level.

12. The frequency conversion circuit according to claim 5, characterized in that: The switch control signal generating circuit comprises: a first switch; an optically coupled diode, coupled to the first switch; a second switch, coupled to the optically coupled diode, generating the second switch control signal; a transistor, coupled to the second switch, generating the first switch control signal; a sampling resistor, used for sampling an output current; a second controller coupled to the sampling resistor and the first switch; a third switch coupled to the second controller; a fourth switch, receiving the sudden load increase signal; and A fifth switch is coupled to the first switch, the third switch and the fourth switch.

13. The frequency conversion circuit according to claim 12, characterized in that: When the surge load is established: When the surge load signal is at the first level, the fourth switch is turned off, and / or when the output current flows through the sampling resistor to generate a voltage difference, and according to the voltage difference and a reference voltage, the second controller outputs an output signal at a first level, the third switch is turned off; In response to the third switch and / or the fourth switch being turned off, the fifth switch is turned on, so that the first switch is turned off, the optically coupled diode is also turned off, the second switch is turned on to generate the second switch control signal of the first level, and the transistor is turned on to generate the first switch control signal of the second level.

14. The frequency conversion circuit according to claim 12, characterized in that: When the surge load does not exist: When the surge load signal is at the second level, the fourth switch is turned on; When the second controller outputs the output signal of a second level, the third switch is turned on; In response to the third switch and the fourth switch being turned on, the fifth switch being turned off, so that the first switch is turned on, the optically coupled diode is also turned on, the second switch is turned off to generate the second switch control signal of the second level, and the transistor is turned off to generate the first switch control signal of the first level.

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