A High-Efficiency Incremental Analog-to-Digital Converter Based on a High-Order Filter

Abstract

The present invention discloses a high-energy-efficiency incremental analog-to-digital converter based on a high-order filter, which includes an analog loop filter with a CIFF architecture and a high-order CoI decimation filter. The analog loop filter includes a partially turn-offable first-stage integrator, a second-stage integrator, a passive summing circuit, and a multi-bit quantizer; the high-order CoI decimation filter is implemented by a multi-stage digital integrator composed of full adders and registers. The present invention performs a higher-order integration on the digital output of the analog loop filter based on the high-order decimation filter. The first-stage integrator is divided into four parallel integrators, and two of them are turned off in the latter 50% cycle of each conversion process, and another one is turned off in the last 25% cycle. The present invention reduces the quantization error of the incremental analog-to-digital converter through the high-order decimation filter, and at the same time uses the partially turn-offable integrator to reduce power consumption, thereby overall improving the energy efficiency of the analog-to-digital converter.

Description

Technical Field

[0001] The present invention belongs to the technical field of analog-to-digital conversion, and in particular relates to a high-efficiency incremental analog-to-digital converter based on a high-order filter. Background Art

[0002] In recent years, with the continuous development of the concept of the Internet of Everything, smart sensors used in the field of the Internet of Things have become a topic of focus for researchers; Incremental Analog-to-Digital Converters (IADCs) are widely used in high-performance sensor systems due to their simple filter design, high precision, and low latency. However, for low-order and low-bit incremental analog-to-digital converters, achieving a high signal-to-quantization-noise ratio (SQNR) requires a long conversion cycle, which increases the number of times power-consuming circuit modules such as integrators work, making it difficult to reduce system power consumption.

[0003] Researchers have taken a series of measures to improve the energy efficiency of IADC. For example, the Chinese patent application with publication number CN114285414A proposed a scaling incremental analog-to-digital conversion method and converter, which adopts a scaling architecture to move the quantizer outside the loop, which is beneficial to the optimization and improvement of the system linearity and energy efficiency of IADC. However, the scaling operation introduces additional quantization errors, which requires more conversion cycles to quantize the signal. Extended counting technology is another effective means to reduce the quantization noise of IADC. For example, the Chinese patent application with publication number CN115549683A proposed a high-precision incremental zoom ADC architecture, the principle of which is to further quantize the quantization noise, but a high-gain amplifier is required in the circuit to prevent the leakage of quantization noise, which increases the difficulty of circuit design.

[0004] It can be seen that the improvement ideas of the existing work are all to improve the analog loop filter of the IADC, which increases the cost or design difficulty of the analog circuit. Summary of the invention

[0005] In view of the above, the present invention provides a high-efficiency incremental analog-to-digital converter based on a high-order filter, which utilizes the random distribution characteristics of quantization noise to improve the SQNR, and at the same time utilizes the nonlinear weight brought by the high-order filter to perform slice-by-slice shutdown of the integrator to optimize the power consumption of the IADC and improve the energy efficiency of the entire IADC.

[0006] A high-efficiency incremental analog-to-digital converter based on a high-order filter, comprising:

[0007] The analog loop filter of the CIFF (Cascaded Integrators with Feedforward) architecture is used as a Δ-Σ modulator to implement analog-to-digital conversion of differential input signals and shaping of quantization noise;

[0008] A high-order CoI (Cascade-of-Integrator) decimation filter is used to perform a higher-order decimation filtering on the digital output of the Δ-Σ modulator to obtain the final digital output result of the IADC and reduce the quantization error of the IADC.

[0009] Furthermore, the analog loop filter includes a clock generation module, a first-stage integrator with shardable shutdown, a second-stage integrator, a passive summing circuit, and a multi-bit quantizer, where:

[0010] The clock generation module is used to provide necessary switching clocks for the first-stage integrator, the second-stage integrator, the passive summing circuit, and the multi-bit quantizer;

[0011] The first-stage integrator is used to calculate the difference between the differential input signal and the output of the multi-bit quantizer, and then accumulate the difference with the output signal of the first-stage integrator in the previous cycle to obtain the output signal of the first-stage integrator in the current cycle;

[0012] The second-stage integrator is used to accumulate the output signal of the first-stage integrator in the current cycle with the output signal of the second-stage integrator in the previous cycle to obtain the output signal of the second-stage integrator in the current cycle;

[0013] The passive summing circuit is used to perform passive summation on the differential input signal, the output signal of the first-stage integrator in the current cycle, and the output signal of the second-stage integrator in the current cycle through charge redistribution of capacitors;

[0014] The multi-bit quantizer is used to quantize the summation result of the passive summing circuit to obtain the digital output of the Δ-Σ modulator.

[0015] Furthermore, the first-stage integrator includes four parallel integrators and a control logic module. The working states of these four integrators are enabled by the control logic module. Each integrator includes sampling feedback capacitors C S1P and C S1N , integrating capacitors C INT1P and C INT1N , an amplifier AMP1 applying chopping technology, and switches S 1 ~S 12 , where one end of S 1 is connected to the positive input signal V IP and serves as the positive input terminal of the first-stage integrator, and S 1The other end is connected to S 3 One end of, S 5 One end of and C S1P One end of are connected, S 2 One end of receives the inverting input signal V IN And serves as the inverting input terminal of the first-stage integrator, S 2 The other end is connected to S 4 One end of, S 6 One end of and C S1N One end of are connected, S 3 The other end and S 4 The other end receives the inverting voltage reference source V refn , S 5 The other end and S 6 The other end receives the non-inverting voltage reference source V refp , C S1P The other end is connected to S 7 One end of, S 9 One end of and the non-inverting input terminal of AMP1 are connected, C S1N The other end is connected to S 8 One end of, S 10 One end of and the inverting input terminal of AMP1 are connected, S 7 The other end and S 8 The other end receives the common-mode voltage V CM , S 9 The other end is connected to C INT1P One end of, S 10 The other end is connected to C INT1N One end of, C INT1P The other end is connected to the inverting output terminal of AMP1 and S 11 One end of, C INT1N The other end is connected to the non-inverting output terminal of AMP1 and S 12 One end of, S 11 The other end serves as the non-inverting output terminal of the first-stage integrator, S 12 The other end serves as the inverting output terminal of the first-stage integrator.

[0016] Furthermore, within the switch clock φ 1 , the first-stage integrator performs a sampling operation, S 1 , S 2 , S 7 , S 8 Close, V IP And V IN Are respectively sampled onto C S1P And C S1N ; Within the switch clock φ 2Inside, the first-stage integrator performs an integration operation. The output of the multi-bit quantizer is controlled by DWA (Data Weighted Averaging) digital logic operation to control S 3 、S 4 、S 5 、S 6 's on and off, so that C S1P and C S1N are connected to V refp or V refn , feeding back the quantization result of the previous cycle; and then closing S 9 and S 10 , so that the residual of the input and the feedback is integrated onto C INT1P and C INT1N .

[0017] Furthermore, the control logic module outputs an enable signal EN of a 4-bit digital code. The 4-bit digital code correspondingly controls the working states of four integrators. For each Nyquist conversion of the IADC, within the first 50% cycle, the enable signal EN output by the control logic module is 1111; within the 50% - 75% cycle, the enable signal EN output by the control logic module is 1100; within the last 25% cycle, the enable signal EN output by the control logic module is 1000; when the digital code is 1, the corresponding integrator performs relevant operations according to the switch clocks φ 1 and φ 2 ; when the digital code is 0, S 1 ~S 12 in the corresponding integrator are all turned off.

[0018] Furthermore, the second-stage integrator includes sampling capacitors C S2P and C S2N , integration capacitors C INT2P and C INT2N , an amplifier AMP2, and switches S 13 ~S 18 , where one end of C S2P is connected to one end of S 13 and the positive-phase output end of the first-stage integrator and serves as the positive-phase input end of the second-stage integrator. One end of C S2N is connected to one end of S 14 and the negative-phase output end of the first-stage integrator and serves as the negative-phase input end of the second-stage integrator. The other end of C S2P is connected to one end of S 15 , one end of S 17 , and the positive-phase input end of AMP2. The other end of C S2N is connected to one end of S 16 , one end of S 18 , and the negative-phase input end of AMP2. S13 The other end of, S 14 The other end of, S 15 The other end of and S 16 The other end of is connected to the common-mode voltage V CM , S 17 The other end of is connected to C INT2P The other end of, S 18 The other end of is connected to C INT2N The other end of C INT2P The other end of is connected to the inverting output terminal of AMP2 and serves as the non-inverting output terminal of the second-stage integrator, C INT2N The other end of is connected to the non-inverting output terminal of AMP2 and serves as the inverting output terminal of the second-stage integrator.

[0019] Furthermore, within the switch clock φ 1 , the second-stage integrator performs an integration operation, S 13 , S 14 , S 17 , S 18 are closed, and the integration from C S2P and C S2N to C INT2P and C INT2N is completed; within the switch clock φ 2 , the second-stage integrator performs a sampling operation, S 11 , S 12 , S 15 , S 16 are closed, and the integration result of the first-stage integrator is sampled onto C S2P and C S2N .

[0020] Furthermore, the passive summing circuit includes summing capacitors C F1P ~ C F3P and C F1N ~ C F3N , summing control switches S 19 ~ S 34 , where one end of S 19 is connected to the non-inverting output terminal of the second-stage integrator, one end of S 20 is connected to the inverting output terminal of the second-stage integrator, the other end of S 19 is connected to one end of S 31 and one end of C F3P , one end of S 20 is connected to one end of S 32 and one end of C F3N , the other end of S 31 is connected to one end of S 27 and is connected to the common-mode voltage V CM , S 32The other end is connected to S 28 One end of which is connected and receives the common-mode voltage V CM , S 27 The other end of which is connected to one end of C F2P And the positive-phase input terminal of the second-stage integrator. The other end of S 28 Is connected to one end of C F2N And the inverting input terminal of the second-stage integrator. One end of C F2P The other end is connected to one end of S 29 , one end of S 33 , one end of S 25 , one end of C F3P The other end of which and one end of C F1P Are connected and used as the positive-phase output terminal of the passive summing circuit. One end of C F2N The other end is connected to one end of S 30 , one end of S 34 , one end of S 26 , one end of C F3N The other end of which and one end of C F1N Are connected and used as the inverting output terminal of the passive summing circuit. One end of S 29 The other end is connected to the other end of S 33 And receives the common-mode voltage V CM , S 30 The other end is connected to the other end of S 34 And receives the common-mode voltage V CM , S 25 The other end and the other end of S 26 Receive the common-mode voltage V CM , C F1P The other end is connected to one end of S 23 And one end of S 21 . One end of C F1N The other end is connected to one end of S 24 And one end of S 22 . One end of S 23 The other end and the other end of S 24 Receive the common-mode voltage V CM , S 21 The other end receives the positive-phase input signal V IP , S 22 The other end receives the inverting input signal V IN .

[0021] Furthermore, within the switch clock φ 1 , S 19 , S 20 , S 21 , S 22 , S 25 , S 26 , S 33 , S34 When closed, the passive summing circuit samples the differential input signal onto C F1P and C F1N and samples the output signal of the second-stage integrator onto C F3P and C F3N ; within the switch clock φ ADD_2 , S 29 and S 30 are closed, and the passive summing circuit integrates the output signal of the first-stage integrator onto C F2P and C F2N ; within the switch clock φ ADD phase, S 23 , S 24 , S 27 , S 28 , S 31 , S 32 are closed, and the passive summing circuit performs charge redistribution to complete the summation of the differential input signal, the output signal of the first-stage integrator, and the output signal of the second-stage integrator.

[0022] Furthermore, the high-order CoI decimation filter is composed of three-stage digital integrators D INT1 ~D INT3 connected in sequence. Each stage of the digital integrator is composed of an adder and a register connected. The adder in D INT1 adds the digital output of the Δ-Σ modulator and the output result of D INT1 in the previous cycle as the output result of D INT1 in the current cycle, and stores this output result in the register; the adder in D INT2 adds the output result of D INT1 in the previous cycle and the output result of D INT2 in the previous cycle as the output result of D INT2 in the current cycle, and stores this output result in the register; the adder in D INT3 adds the output result of D INT2 in the previous cycle and the output result of D INT3 in the previous cycle as the output result of D INT3 in the current cycle (i.e., the final digital output result of the current cycle IADC), and stores this output result in the register.

[0023] Due to the periodic reset working mode of the IADC, the design of its decimation filter can be implemented by a CoI digital integrator. The present invention proposes an incremental analog-to-digital converter architecture based on a high-order filter, which effectively utilizes the characteristic of the random distribution of quantization errors. Starting from the idea of filter design, the quantization error of the system is reduced and the SQNR is improved. At the same time, the present invention shards and turns off the first-stage integrator, and combines dynamic power reduction technology to optimize the power consumption of the IADC while ensuring the noise performance, and improves the energy efficiency of the entire IADC. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 FIG. is a system block diagram of a high-energy-efficiency incremental analog-to-digital converter based on a high-order filter according to the present invention.

[0025] Figure 2 FIG. is a schematic circuit diagram of an analog loop filter of a CIFF architecture in an embodiment of the present invention.

[0026] Figure 3 FIG. is a schematic timing diagram of the operation of an analog loop filter in an embodiment of the present invention.

[0027] Figure 4 FIG. is a schematic diagram of the circuit structure and control logic of a shardable and turn-offable first-stage integrator in an embodiment of the present invention.

[0028] Figure 5 FIG. is a schematic circuit diagram of a high-order CoI decimation filter in an embodiment of the present invention.

[0029] Figure 6 FIG. is a schematic diagram of the IADC output spectrum before and after applying a high-order decimation filter under an AC input in an embodiment of the present invention.

[0030] Figure 7 FIG. is an IADC output spectrum diagram before and after applying a partially turn-offable technology under an AC input in an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0031] In order to describe the present invention more specifically, the technical solutions of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0032] As Figure 1 shown, the incremental analog-to-digital converter based on a high-order decimation filter of the present invention includes two parts: an analog loop filter of a CIFF architecture and a high-order CoI decimation filter. The analog loop filter uses two-stage integrators (transfer function is , z represents the Z-transform operator) to perform Δ-Σ modulation on the input signal U to obtain a digital output V. The quantization error in the analog loop filter is E 1 ; the high-order CoI decimation filter performs third-order digital integration on V to obtain the final output D of the IADCOUT ; The reset of the analog loop filter and the high-order CoI decimation filter is controlled by the RST (reset) signal.

[0033] The analog loop filter of the CIFF architecture consists of a partially turn-off first-stage integrator INT1, a second-stage integrator INT2, a passive summing circuit, and a 3-bit (BIT) quantizer. The circuit implementation is as Figure 2 shown, where:

[0034] The first-stage integrator INT1 includes four shard integrators 1-4 in parallel and a control logic module. The operating states of these four shard integrators 1-4 are enabled by the control logic module. Each integrator includes sampling feedback capacitors C S1P and C S1N , integration capacitors C INT1P and C INT1N , an amplifier AMP1 applying chopping technology, and switches S 1 ~S 12 , where one end of S 1 is connected to the non-inverting input signal V IP and serves as the non-inverting input terminal of the first-stage integrator. One end of S 1 is connected to one end of S 3 , one end of S 5 , and one end of C S1P . One end of S 2 is connected to the inverting input signal V IN and serves as the inverting input terminal of the first-stage integrator. One end of S 2 is connected to one end of S 4 , one end of S 6 , and one end of C S1N . The other end of S 3 and the other end of S 4 are connected to the inverting voltage reference source V refn . The other end of S 5 and the other end of S 6 are connected to the non-inverting voltage reference source V refp . The other end of C S1P is connected to one end of S 7 , one end of S 9 , and the non-inverting input terminal of AMP1. The other end of C S1N is connected to one end of S 8 , one end of S 10 , and the inverting input terminal of AMP1. The other end of S 7 and the other end of S 8 are connected to the common-mode voltage V CM . The other end of S 9 is connected to one end of C INT1P . One end of S10 The other end is connected to C INT1N One end of is connected, and C INT1P The other end is connected to the inverting output terminal of AMP1 and S 11 One end of is connected, and C INT1N The other end is connected to the non-inverting output terminal of AMP1 and S 12 One end of is connected, and S 11 The other end is used as the non-inverting output terminal of the first-stage integrator, and S 12 The other end is used as the inverting output terminal of the first-stage integrator.

[0035] The second-stage integrator INT2 includes sampling capacitors C S2P and C S2N , integration capacitors C INT2P and C INT2N , amplifier AMP2, and switches S 13 ~S 18 , where one end of C S2P is connected to one end of S 13 and the non-inverting output terminal of the first-stage integrator and serves as the non-inverting input terminal of the second-stage integrator. One end of C S2N is connected to one end of S 14 and the inverting output terminal of the first-stage integrator and serves as the inverting input terminal of the second-stage integrator. One end of C S2P is connected to one end of S 15 , one end of S 17 , and the non-inverting input terminal of AMP2. One end of C S2N is connected to one end of S 16 , one end of S 18 , and the inverting input terminal of AMP2. One end of S 13 , one end of S 14 , one end of S 15 , and one end of S 16 are connected to the common-mode voltage V CM . One end of S 17 is connected to one end of C INT2P . One end of S 18 is connected to one end of C INT2N . One end of C INT2P is connected to the inverting output terminal of AMP2 and serves as the non-inverting output terminal of the second-stage integrator. One end of C INT2N is connected to the non-inverting output terminal of AMP2 and serves as the inverting output terminal of the second-stage integrator.

[0036] The passive summing circuit includes summing capacitors C F1P ~C F3P and C F1N ~C F3N , summing control switch S19 ~S 34 , where S 19 One end of is connected to the positive-phase output terminal of the second-stage integrator, S 20 One end of is connected to the inverting-phase output terminal of the second-stage integrator, S 19 The other end of is connected to S 31 One end of and C F3P One end of is connected, S 20 The other end of is connected to S 32 One end of and C F3N One end of is connected, S 31 The other end of is connected to S 27 One end of is connected and connected to the common-mode voltage V CM , S 32 The other end of is connected to S 28 One end of is connected and connected to the common-mode voltage V CM , S 27 The other end of is connected to C F2P One end of and the positive-phase input terminal of the second-stage integrator are connected, S 28 The other end of is connected to C F2N One end of and the inverting-phase input terminal of the second-stage integrator are connected, C F2P The other end of is connected to S 29 One end of, S 33 One end of, S 25 One end of, C F3P The other end of and C F1P One end of are connected and used as the positive-phase output terminal of the passive summing circuit, C F2N The other end of is connected to S 30 One end of, S 34 One end of, S 26 One end of, C F3N The other end of and C F1N One end of are connected and used as the inverting-phase output terminal of the passive summing circuit, S 29 The other end of is connected to S 33 The other end of is connected and connected to the common-mode voltage V CM , S 30 The other end of is connected to S 34 The other end of is connected and connected to the common-mode voltage V CM , S 25 The other end of and S 26 The other end of are connected to the common-mode voltage V CM , C F1P The other end of is connected to S 23 One end of and S 21 One end of are connected, C F1N The other end of is connected to S 24 One end of and S 22 One end of are connected, S 23The other end and S 24 The other end is connected to the common-mode voltage V CM , S 21 The other end is connected to the positive-phase input signal V IP , S 22 The other end is connected to the negative-phase input signal V IN .

[0037] As Figure 3 shown is the working timing of the analog loop filter, including φ 1 , φ 2 , φ ADD , φ ADD_2 four clocks. During the φ 1 phase, the first-stage integrator performs a sampling operation, and S 1 , S 2 , S 7 , S 8 are closed, and the input signals V IP , V IN are sampled onto C S1P and C S1N ; the second-stage integrator performs an integration operation, and S 13 , S 14 , S 17 , S 18 are closed, and the integration from C S2P , C S2N to C INT2P , C INT2N is completed; in the passive summing circuit, S 21 , S 22 , S 25 , S 26 are closed, and the input signals are sampled onto C F1P and C F1N ; S 19 , S 20 , S 33 , S 34 are closed, and the output of the second-stage integrator is sampled onto C F3P and C F3N . During the φ 2 phase, the first-stage integrator performs an integration operation, and S 3 , S 4 , S 5 , S 6 are controlled by the quantizer output after DWA digital logic operation. For the lower plates of C S1P and C S1N , they are connected to the reference sources V refn , V refp to feedback the quantization result of the previous cycle; S 9 , S 10Closed, the residual of the input and feedback is integrated to C INT1P , C INT1N ; The second-stage integrator performs a sampling operation, S 11 , S 12 , S 15 , S 16 Closed, the integration result of the first stage is sampled to C S2P , C S2N . φ ADD_2 During the φ stage, in the passive summing circuit, S 29 , S 30 Closed, the output of the first stage is integrated to C F2P and C F2N . φ ADD During the φ stage, S 23 , S 24 , S 27 , S 28 , S 31 , S 32 Closed, the passive summing circuit performs charge redistribution to complete the summation of the input signal, the first-stage integrator, and the second-stage integrator.

[0038] As Figure 4 shown is the partial turn-off circuit implementation and timing of the first-stage integrator. The switches S 1 ~S 12 in four identical integrators and the operation of the amplifier AMP1 are controlled not only by the φ 1 , φ 2 clocks but also by the enable signal EN<1:4>. When EN(i) = 1 (i = 1, 2, 3, 4), each part in the integrator is controlled by the φ 1 , φ 2 clocks to implement the predetermined circuit functions, and the output signals V OP1 and V ON1 are output. When EN(i) = 0, S 1 , S 2 , S 7 , S 8 are disconnected and no sampling operation is performed; S 3 , S 4 , S 5 , S 6 are disconnected and no feedback from the reference sources V refn , V refp is performed; S 9 , S 10 , S 11 , S 12Disconnected, the power supply to AMP1 is disconnected. For each Nyquist conversion of the incremental analog-to-digital converter, within the first 50% of the cycle, all four integrators are turned on, EN<1:4>=1111; from 50% to 75% of the cycle, EN<1:4>=1100; in the last 25% of the cycle, EN<1:4>=1000.

[0039] As Figure 5 shown is the circuit implementation of the third-order CoI decimation filter in this embodiment, which includes three stages of digital integrators D INT1 ~D INT3 , and each stage of digital integrator includes a full adder and a register. The inputs of the first-stage full adder are respectively the output V of the analog loop filter and the accumulated result of the previous cycle stored in the register; the two inputs of the second-stage integrator are respectively the accumulated results of the first and second stages of the previous cycle; the two inputs of the third-stage integrator are respectively the accumulated results of the second and third stages of the previous cycle, and the output of the third-stage integrator is the final output D of the IADC OUT . The reset signal RST is set high at the start of each Nyquist conversion to reset all registers; at the end of the quantization operation in each conversion cycle, when the clock signal CLK arrives, the register stores and refreshes the accumulated result of the current cycle.

[0040] This embodiment of the incremental analog-to-digital converter based on a high-order filter effectively improves the signal-to-noise ratio of the IADC. As Figure 6 shown, the IADC after applying the high-order decimation filter has a signal-to-noise and distortion ratio of 106.5 dB, while without applying the high-order decimation filter, it is only 100.5 dB, and the effective number of bits is increased by 1 bit. As Figure 7 shown, on the basis of applying the high-order decimation filter, partial turn-off is performed on the first-stage integrator. After applying the partial turn-off technology, the SNDR only decreases by 0.3 dB, and the power consumption of the IADC is reduced to 75% of that without using the partial turn-off technology, effectively improving the energy efficiency of the IADC.

[0041] The above description of the embodiments is to enable those of ordinary skill in the art to understand and apply the present invention. It is obvious that those skilled in the art can easily make various modifications to the above embodiments and apply the general principles described herein to other embodiments without creative labor. Therefore, the present invention is not limited to the above embodiments, and all improvements and modifications made by those skilled in the art based on the disclosure of the present invention should be within the protection scope of the present invention.

Claims

1. A high-efficiency incremental analog-to-digital converter based on a high-order filter, characterized in that: include: The analog loop filter of the CIFF architecture acts as a delta-sigma modulator to achieve analog-to-digital conversion of the differential input signal and shaping of the quantization noise; A high-order CoI decimation filter is used to perform a higher-order decimation filter on the digital output of the delta-sigma modulator to obtain the final digital output result of the IADC and reduce the quantization error of the IADC; The analog loop filter comprises a clock generation module, a first-stage integrator with slice-turnoff capability, a second-stage integrator, a passive summing circuit and a multi-bit quantizer, wherein: The clock generation module is used to provide necessary switching clocks for the first-stage integrator, the second-stage integrator, the passive summing circuit and the multi-bit quantizer; The first-stage integrator is used to calculate the difference between the differential input signal and the output of the multi-bit quantizer, and then accumulate the difference with the output signal of the first-stage integrator in the previous cycle to obtain the output signal of the first-stage integrator in the current cycle; The second-stage integrator is used to accumulate the output signal of the first-stage integrator in the current cycle and the output signal of the second-stage integrator in the previous cycle to obtain the output signal of the second-stage integrator in the current cycle; The passive summing circuit is used to perform passive summing of the differential input signal, the output signal of the first-stage integrator in the current cycle, and the output signal of the second-stage integrator in the current cycle through charge redistribution of the capacitor; The multi-bit quantizer is used to quantize the summation result of the passive summation circuit to obtain the digital output of the delta-sigma modulator; The first-stage integrator includes four parallel integrators and a control logic module. The working state of the four integrators is enabled by the control logic module. Each integrator includes a sampling feedback capacitor C S1P and C S1N , Integral capacitor C INT1P and C INT1N , Amplifier AMP1 and switches S1 to S1 using chopping technology 12 , where one end of S1 is connected to the positive phase input signal V IP And as the positive phase input terminal of the first stage integrator, the other end of S1 is connected to one end of S3, one end of S5 and C S1P One end of S2 is connected to the inverting input signal V IN And as the inverting input end of the first stage integrator, the other end of S2 is connected to one end of S4, one end of S6 and C S1N The other end of S3 and the other end of S4 are connected to the inverting voltage reference source V refn , the other end of S5 and the other end of S6 are connected to the positive phase voltage reference source V refp , C S1P The other end is connected to one end of S7, one end of S9 and the positive input end of AMP1. S1N The other end of S8 and S 10 One end of S7 and the inverting input of AMP1 are connected, and the other end of S7 and the other end of S8 are connected to the common mode voltage V CM , the other end of S9 is connected to C INT1P One end is connected to S 10 The other end of the INT1N One end of C INT1P The other end is connected to the inverting output of AMP1 and S 11 One end of C INT1N The other end is connected to the positive phase output terminal of AMP1 and S 12 One end is connected to S 11 The other end of the first stage integrator is used as the positive phase output end, S 12 The other end serves as the inverting output end of the first-stage integrator.

2. The high-efficiency incremental analog-to-digital converter based on a high-order filter according to claim 1, characterized in that: In the switching clock φ1, the first-stage integrator performs sampling operation, S1, S2, S7, S8 are closed, and V IP and V IN are sampled to C S1P and C S1N In the switching clock φ2, the first-stage integrator performs integration operation, and the output of the multi-bit quantizer controls the on / off of S3, S4, S5, and S6 after the DWA digital logic operation, so that C S1P and C S1N Connect to V refp or V refn , feedback the quantization result of the previous cycle; then S9 and S 10 Closed, so that the residual of input and feedback is integrated to C INT1P and C INT1N superior.

3. The high-efficiency incremental analog-to-digital converter based on a high-order filter according to claim 2, characterized in that: The control logic module outputs an enable signal EN of a 4-bit digital code, and the 4-bit digital code corresponds to the working state of the four integrators. For each Nyquist conversion of the IADC, within the first 50% cycle, the enable signal EN output by the control logic module is 1111; within 50% to 75% of the cycle, the enable signal EN output by the control logic module is 1100; within the last 25% of the cycle, the enable signal EN output by the control logic module is 1000; when the digital code is 1, the corresponding integrator performs related operations according to the switch clocks φ1 and φ2; When the digital code is 0, the corresponding integrator S1~S 12 All off.

4. The high-efficiency incremental analog-to-digital converter based on a high-order filter according to claim 1, characterized in that: The second stage integrator includes a sampling capacitor C S2P and C S2N , Integral capacitor C INT2P and C INT2N , amplifier AMP2 and switch S 13 ~S 18 , where C S2P One end of S 13 One end of the integrator is connected to the positive phase output of the first stage integrator and serves as the positive phase input of the second stage integrator. S2N One end of S 14 One end of the inverting output end of the first stage integrator is connected to the inverting input end of the second stage integrator. S2P The other end of S 15 One end, S 17 One end of the AMP2 is connected to the positive input terminal, C S2N The other end of S 16 One end, S 18 One end is connected to the inverting input of AMP2, S 13 The other end, S 14 The other end, S 15 The other end and S 16 The other end is connected to the common mode voltage V CM , S 17 The other end of the INT2P One end is connected to S 18 The other end of the INT2N One end of C INT2P The other end is connected to the inverting output of AMP2 and serves as the non-inverting output of the second-stage integrator. INT2N The other end is connected to the non-inverting output end of AMP2 and serves as the inverting output end of the second-stage integrator.

5. The high-efficiency incremental analog-to-digital converter based on a high-order filter according to claim 4, characterized in that: Within the switching clock φ1, the second-stage integrator performs integration operation, S 13 , S 14 , S 17 , S 18 Closed, completed from C S2P and C S2N to C INT2P and C INT2N The second-stage integrator performs sampling operation within the switching clock φ2, S 11 , S 12 , S 15 , S 16 Close, and sample the integration result of the first-stage integrator to C S2P and C S2N superior.

6. The high-efficiency incremental analog-to-digital converter based on a high-order filter according to claim 1, characterized in that: The passive summing circuit includes a summing capacitor C F1P ~C F3P and C F1N ~C F3N , summing control switch S 19 ~S 34 , where S 19 One end of S is connected to the positive phase output end of the second stage integrator. 20 One end of S is connected to the inverting output end of the second stage integrator. 19 The other end of S 31 One end and C F3P One end is connected to S 20 The other end of S 32 One end and C F3N One end is connected to S 31 The other end of S 27 One end is connected to the common mode voltage V CM , S 32 The other end of S 28 One end is connected to the common mode voltage V CM , S 27 The other end of the F2P One end of the second stage integrator is connected to the non-inverting input end, S 28 The other end of the F2N One end of the inverting input terminal of the second stage integrator is connected to C F2P The other end of S 29 One end, S 33 One end, S 25 One end of C F3P The other end and C F1P One end of the passive summing circuit is connected to the positive phase output terminal, C F2N The other end of S 30 One end, S 34 One end, S 26 One end of C F3N The other end and C F1N One end of the passive summing circuit is connected to the inverting output terminal, S 29 The other end of S 33 The other end is connected to the common mode voltage V CM , S 30 The other end of S 34 The other end is connected to the common mode voltage V CM , S 25 The other end and S 26 The other end is connected to the common mode voltage V CM , C F1P The other end of S 23 One end and S 21 One end of C F1N The other end of S 24 One end and S 22 One end is connected to S 23 The other end and S 24 The other end is connected to the common mode voltage V CM , S 21 The other end is connected to the positive phase input signal V IP , S 22 The other end is connected to the inverting input signal V IN .

7. The high-efficiency incremental analog-to-digital converter based on a high-order filter according to claim 6, characterized in that: Within the switching clock φ1, S 19 , S 20 , S 21 , S 22 , S 25 , S 26 , S 33 , S 34 Closed, the passive summing circuit samples the differential input signal to C F1P and C F1N The output signal of the second stage integrator is sampled to C F3P and C F3N On; at the switching clock φ ADD_2 Inside, S 29 and S 30 Closed, the passive summing circuit integrates the output signal of the first stage integrator to C F2P and C F2N On; at the switching clock φ ADD During the stage, S 23 , S 24 , S 27 , S 28 , S 31 , S 32 When closed, the passive summing circuit performs charge redistribution to complete the summation of the differential input signal, the first-stage integrator output signal, and the second-stage integrator output signal.

8. The high-efficiency incremental analog-to-digital converter based on a high-order filter according to claim 1, characterized in that: The high-order CoI extraction filter consists of a three-stage digital integrator D INT1 ~D INT3 Each level of digital integrator is composed of a full adder and a register. INT1 The full adder adds the digital output of the delta-sigma modulator to the previous cycle D INT1 The output result is added as the current cycle D INT1 The output result is stored in the register; D INT2 The full adder in the previous cycle D INT1 The output result of the previous cycle D INT2 The output result is added as the current cycle D INT2 The output result is stored in the register; D INT3 The full adder in the previous cycle D INT2 The output result of the previous cycle D INT3 The output result is added as the current cycle D INT3 The output result is stored in the register.

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