Channel decoding acceleration system and method and SoC chip

Abstract

The invention provides a channel decoding acceleration system, a channel decoding acceleration method and an SoC chip, and the channel decoding acceleration system comprises a task configuration register, a task scheduling module, a data memory and a hardware decoding core resource pool. According to the scheme, the task scheduling module polls each subtask register in the task configuration register, and after the decoding task configuration information stored in the subtask register is analyzed, the next subtask register continues to be polled; and the task scheduling module performs hardware decoding kernel scheduling and data decoding according to the analyzed task information, so that parallel execution of a plurality of decoding tasks is realized, and compared with a task serial processing mode in the related technology, the parallel processing mode of the scheme greatly reduces the probability of decoding congestion, and is beneficial to improving the decoding efficiency.

Description

Technical Field

[0001] The present application relates to the field of chip design technology, and in particular to a channel decoding acceleration system, method and SoC chip. Background Art

[0002] In signal processing technology, channel data is mostly coded data, so it is necessary to decode the coded data to obtain the message information. The decoding technology in the related technology is generally divided into software decoding and hardware decoding. Among them, software decoding has a large overhead, so hardware decoding is generally selected.

[0003] The hardware decoding solution in the related art adopts a serial processing method, that is, the next decoding task is carried out after one decoding task is completed. This solution has low decoding efficiency in signal processing scenarios with a large number of decoding tasks. Summary of the invention

[0004] The purpose of the embodiments of the present application is to provide a channel decoding acceleration system, method and SoC chip to improve the efficiency of hardware decoding.

[0005] In a first aspect, an embodiment of the present application provides a channel decoding acceleration system, the system comprising: a task configuration register, a task scheduling module, a data storage device, and a hardware decoding core resource pool, wherein:

[0006] The task configuration register is used to receive decoding task configuration information and store the decoding task configuration information in the subtask register; wherein the decoding task configuration information includes the task decoding type and the address of the data to be decoded;

[0007] The data storage device is used to store the data to be decoded and the decoded data;

[0008] The hardware decoding core resource pool includes hardware decoding cores for scheduling by the task scheduling module;

[0009] The task scheduling module is used to poll each of the subtask registers and schedule the hardware decoding core to decode the data to be decoded according to the decoding task configuration information stored in the subtask register; the task scheduling module continues to poll the next subtask register after parsing the decoding task configuration information stored in the current subtask register.

[0010] During the implementation of the above scheme, the task scheduling module polls each subtask register in the task configuration register, and continues to poll the next subtask register after parsing the decoding task configuration information stored in the subtask register. The task scheduling module performs hardware decoding core scheduling and data decoding according to the parsed task information, thereby realizing the parallel execution of multiple decoding tasks. Compared with the task serial processing method in the related technology, the parallel processing method of the above scheme greatly reduces the probability of decoding congestion, which is conducive to improving decoding efficiency.

[0011] In an implementation manner of the first aspect, the data storage device is an SRAM; the SRAM provides idle address segments for all the subtask registers in the task configuration register to store the data to be decoded.

[0012] During the implementation of the above scheme, all subtask registers can use the free address segments in the SRAM to store the data to be decoded, thereby realizing SRAM sharing among multiple decoding types, which is conducive to the simplified design of the channel decoding acceleration system, reducing the used area of ​​SRAM, and reducing the deployment cost and difficulty.

[0013] In an implementation manner of the first aspect, the hardware decoding core resource pool includes one or more types of the hardware decoding cores.

[0014] During the implementation of the above scheme, one or more types of hardware decoding cores can be set in the hardware decoding core resource pool so that the above channel decoding acceleration system can support multiple types of decoding, thereby enabling the above channel decoding acceleration system to be applied to more application scenarios, which is conducive to improving the adaptability of the above channel decoding acceleration system.

[0015] In an implementation manner of the first aspect, the number of each type of hardware decoding cores is one or more.

[0016] During the implementation of the above scheme, the number of each hardware decoding core can be set to one or more, so as to realize parallel decoding of hardware decoding cores of multiple decoding types and multiple hardware decoding cores of the same decoding type. On the one hand, it is beneficial to improve the decoding efficiency of the above-mentioned channel decoding acceleration system; on the other hand, it enables the above-mentioned channel decoding acceleration system to be applicable to more scenarios, which is beneficial to improving the adaptability of the above-mentioned channel decoding acceleration system.

[0017] In an implementation of the first aspect, when the subtask register stores the decoding task configuration information, the task scheduling module performs the following steps: reading and parsing the decoding task configuration information stored in the subtask register; scheduling the hardware decoding core of the corresponding type in the hardware decoding core resource pool according to the task decoding type; reading the data to be decoded in the data storage device according to the address of the data to be decoded; decoding the data to be decoded using the hardware decoding core to obtain the decoded data; and storing the decoded data in the data storage device.

[0018] In the implementation process of the above scheme, the task scheduling module executes the decoding task through the decoding task configuration information in conjunction with the data storage device and the hardware decoding core, thereby realizing efficient scheduling of the hardware decoding core, which is beneficial to improving the decoding efficiency in scenarios with a large number of decoding tasks.

[0019] In an implementation of the first aspect, the task scheduling module schedules the hardware decoding core of a corresponding type in the hardware decoding core resource pool according to the task decoding type, including:

[0020] Applying for the hardware decoding core of the corresponding type from the hardware decoding core resource pool;

[0021] If there are idle hardware decoding cores of the corresponding type in the hardware decoding core resource pool, the steps of reading data to be decoded, decoding, and storing the decoded data are executed;

[0022] If there is no idle hardware decoding core of the corresponding type in the hardware decoding core resource pool, a queue is performed until an idle hardware decoding core of the corresponding type appears in the hardware decoding core resource pool.

[0023] During the implementation of the above scheme, when there is no idle hardware decoding core of the corresponding type in the hardware decoding core resource pool, the system waits for the appearance of an idle hardware decoding core of the corresponding type in the hardware decoding core resource pool. Compared with the queuing method for a single hardware decoding core in the related art, the above scheme queues all hardware decoding cores of the corresponding type in the hardware decoding core resource pool, which reduces the probability of decoding congestion in scenarios with a large number of decoding tasks, and is conducive to improving the decoding efficiency of the above channel decoding acceleration system.

[0024] In a second aspect, an embodiment of the present application provides a channel decoding acceleration method, which is applied to a task scheduling module, and the method includes:

[0025] Poll each subtask register in the task configuration register;

[0026] If the decoding task configuration information is not stored in the subtask register, continue to poll the next subtask register;

[0027] If the subtask register stores decoding task configuration information, then reading and parsing the decoding task configuration information stored in the subtask register to obtain the task decoding type and the address of the data to be decoded;

[0028] After reading and parsing the decoding task configuration information, continue to poll the next subtask register;

[0029] For each decoding task configuration information that has been parsed, the hardware decoding core of the corresponding type is scheduled in the hardware decoding core resource pool according to the task decoding type; the data to be decoded is read in the data memory according to the address of the data to be decoded; the data to be decoded is decoded by using the hardware decoding core to obtain the decoded data; and the decoded data is stored in the data memory.

[0030] In a third aspect, an embodiment of the present application provides a SoC chip, the SoC chip comprising: a channel decoding acceleration system and a SoC bus as provided in the first aspect or any possible implementation of the first aspect; the channel decoding acceleration system is mounted on the SoC bus through an interface.

[0031] In an implementation manner of the third aspect, the SoC chip is a GNSS chip.

[0032] In an implementation of the third aspect, the hardware decoding core resource pool in the channel decoding acceleration system includes: at least one type of decoding core among: Hamming code decoding core, CRC decoding core, LDPC decoding core, convolution decoding core, CRC convolution decoding core, BCH code decoding core and Viterbi decoding core. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0034] Figure 1 A schematic diagram of the structure of a channel decoding acceleration system provided in an embodiment of the present application;

[0035] Figure 2 A schematic diagram of the interaction flow of various components in a channel decoding acceleration system in a certain scenario provided by an embodiment of the present application;

[0036] Figure 3 A schematic diagram of the processing timing of decoding task 1 and decoding task 2 in a certain scenario provided in an embodiment of the present application;

[0037] Figure 4 A flow chart of a channel decoding acceleration method applied to a task scheduling module provided in an embodiment of the present application;

[0038] Figure 5 A schematic diagram of the architecture of the SoC chip provided in an embodiment of the present application. DETAILED DESCRIPTION

[0039] The following will describe the technical solutions in the embodiments of the present application in conjunction with the accompanying drawings in the embodiments of the present application. The following embodiments are only used to more clearly illustrate the technical solutions of the present application, and are therefore only used as examples, and cannot be used to limit the scope of protection of the present application.

[0040] Most hardware decoding solutions in related technologies use serial processing. For example, for decoding task A and decoding task B, the decoding solution in related technologies first executes decoding task A, and then executes decoding task B after decoding task A completes decoding. This decoding method has low decoding efficiency in signal processing scenarios with a large number of decoding tasks.

[0041] Based on this, an embodiment of the present application provides a channel decoding acceleration system, in which a task scheduling module polls each subtask register in a task configuration register, and continues to poll the next subtask register after parsing the decoding task configuration information stored in the subtask register. The task scheduling module performs hardware decoding core scheduling and data decoding according to the parsed task information, thereby realizing the parallel execution of multiple decoding tasks. Compared with the serial processing method of tasks in the related technology, the parallel processing method of the above scheme greatly reduces the probability of decoding congestion, which is conducive to improving decoding efficiency.

[0042] The following is a detailed description of the above channel decoding acceleration system. Figure 1 , the embodiment of the present application provides a channel decoding acceleration system 100, the system comprising:

[0043] The task configuration register 110 is used to receive the decoding task configuration information and store the decoding task configuration information in the subtask register; wherein the decoding task configuration information includes the task decoding type and the address of the data to be decoded;

[0044] A data memory 120, used for storing data to be decoded and decoded data;

[0045] The hardware decoding core resource pool 130 includes hardware decoding cores for scheduling by the task scheduling module;

[0046] The task scheduling module 140 is used to poll each subtask register and schedule the hardware decoding core to decode the data to be decoded according to the decoding task configuration information stored in the subtask register.

[0047] After parsing the decoding task configuration information stored in the current subtask register, the task scheduling module 140 continues to poll the next subtask register.

[0048] The following is an introduction to the relevant contents of the task configuration register 110:

[0049] It can be understood that the task configuration register 110 is a register group including multiple subtask registers, and each subtask register can be configured by software in a read-write configuration manner to configure the decoding task configuration information stored in each subtask register. The configurable contents include:

[0050] (1) Task decoding type, which is used to indicate what type of decoding the decoding task needs to perform;

[0051] When performing data decoding scheduling, the task scheduling module 140 schedules a hardware decoding core of a corresponding type in the hardware decoding core resource pool 130 according to the task decoding type.

[0052] (2) an address of data to be decoded, which is used to indicate the storage address of the data to be decoded in the data memory 120;

[0053] When performing data decoding scheduling, the task scheduling module 140 reads the data to be decoded from the data memory 120 according to the address of the data to be decoded.

[0054] It can be understood that, by controlling the two parameters of the task decoding type and the address of the data to be decoded, the subtask register can be configured as any required decoding task, thereby achieving hardware acceleration of the decoding task.

[0055] The following is an introduction to the relevant contents of the data storage 120:

[0056] The hardware decoding solution in the related art has a large amount of decoding data, and each decoding method requires an independent decoding system, which makes the area overhead of SRAM (Static Random-Access Memory) large, increasing the layout cost and layout difficulty of the channel decoding acceleration system. Based on this, the embodiment of the present application provides the following solution:

[0057] As an optional implementation of the channel decoding acceleration system, the data storage device is an SRAM, and the SRAM provides idle address segments for all subtask registers in the task configuration register 110 to store data to be decoded.

[0058] It is understandable that the SRAM can be used for data reading and writing operations by software, for example: writing the data to be decoded into the SRAM by software and reading the decoded data stored in the SRAM by software.

[0059] In addition, it can be understood that the SRAM is open to all subtask registers, and each subtask register can store the data to be decoded in the free address segment of the SRAM as needed, without overlapping with the data to be decoded of other tasks, thereby achieving flexible use of the SRAM space.

[0060] In the above scheme, all subtask registers can use the free address segments in the SRAM to store the data to be decoded, thereby realizing SRAM sharing among multiple decoding types, which is conducive to simplifying the design of the channel decoding acceleration system, reducing the used area of ​​SRAM, and reducing the deployment cost and difficulty.

[0061] It is understandable that the size of the SRAM in the channel decoding acceleration system 100 can be configured according to the required maximum amount of data to be decoded and the decoding performance.

[0062] The following is an introduction to the relevant contents of the hardware decoding core resource pool 130:

[0063] The hardware decoding core resource pool 130 may include one or more hardware decoding cores that can be scheduled by the task scheduling module 140. It is understandable that the hardware decoding core may be a decoding circuit.

[0064] As an optional implementation of the channel decoding acceleration system, the hardware decoding core resource pool 130 includes one or more types of hardware decoding cores. This implementation is, for example:

[0065] In the GNSS scenario, the hardware decoding core resource pool 130 may be provided with various decoding cores such as a Hamming code decoding core, a CRC decoding core, an LDPC decoding core, and a Viterbi decoding core to implement decoding operations for various codes.

[0066] During the implementation of the above scheme, one or more types of hardware decoding cores can be set in the hardware decoding core resource pool 130, so that the above channel decoding acceleration system 100 can support multiple types of decoding, thereby making the above channel decoding acceleration system applicable to more application scenarios, which is conducive to improving the adaptability of the above channel decoding acceleration system 100.

[0067] As an optional implementation of the above channel decoding acceleration system, the number of each type of hardware decoding core is one or more. This implementation is, for example:

[0068] In a certain scenario, the channel decoding acceleration system 100 needs to support three decoding methods: Hamming code decoding, CRC decoding and LDPC decoding, and the amount of decoding data for CRC decoding is large. At this time, multiple CRC decoding cores can be set, and multiple CRC decoding cores as well as Hamming code decoding cores and LDPC decoding cores can perform parallel decoding on the data to be decoded.

[0069] It is understandable that when there are multiple types of hardware decoding cores, the number of hardware decoding cores of each type may be one or more. When there is one type of hardware decoding core, the number of hardware decoding cores of this type may be more than one.

[0070] In the above scheme, the number of each hardware decoding core can be set to one or more, so as to realize parallel decoding of hardware decoding cores of multiple decoding types and multiple hardware decoding cores of the same decoding type. On the one hand, it is beneficial to improve the decoding efficiency of the above-mentioned channel decoding acceleration system 100; on the other hand, it enables the above-mentioned channel decoding acceleration system 100 to be applicable to more scenarios, which is beneficial to improving the adaptability of the above-mentioned channel decoding acceleration system 100.

[0071] It is understandable that the type and quantity of the hardware decoding cores in the hardware decoding core resource pool 130 can be set by comprehensively considering the required decoding service scenarios, decoding performance and system area, so as to further enhance the adaptability of the above-mentioned channel decoding acceleration system 100.

[0072] The following is an introduction to the relevant contents of the task scheduling module 140:

[0073] As an optional implementation of the above-mentioned channel decoding acceleration system, when the subtask register stores decoding task configuration information, the task scheduling module 140 performs the following steps: read and parse the decoding task configuration information stored in the subtask register, obtain the task decoding type and the address of the data to be decoded; schedule the corresponding type of hardware decoding core in the hardware decoding core resource pool according to the task decoding type; read the data to be decoded in the data storage device according to the address of the data to be decoded; use the hardware decoding core to decode the data to be decoded and obtain the decoding data; store the decoding data in the data storage device.

[0074] In the implementation process of the above solution, the task scheduling module 140 executes the decoding task through the decoding task configuration information in conjunction with the data storage and the hardware decoding core, thereby realizing efficient scheduling of the hardware decoding core, which is beneficial to improving the decoding efficiency in scenarios with a large number of decoding tasks.

[0075] As an optional implementation of the above-mentioned channel decoding acceleration system, the task scheduling module 140 schedules the corresponding type of hardware decoding core in the hardware decoding core resource pool according to the task decoding type, including: the hardware decoding core resource pool applies for the corresponding type of hardware decoding core; if there is an idle hardware decoding core of the corresponding type in the hardware decoding core resource pool, then execute the step of reading the data to be decoded, the decoding step and the step of storing the decoded data; if there is no idle hardware decoding core of the corresponding type in the hardware decoding core resource pool, then queue and wait until an idle hardware decoding core of the corresponding type appears in the hardware decoding core resource pool.

[0076] It is understandable that a counter can be used to indicate the number of idle hardware decoding cores. When the counter value of a certain type of hardware decoding core is non-zero, it indicates that there are idle hardware decoding cores available for invocation, and when the counter value of a certain type of hardware decoding core is 0, it indicates that there are no idle hardware decoding cores available for invocation. Whenever the task scheduling module 140 successfully schedules a hardware decoding core, the counter value corresponding to the decoding core is reduced by 1, and the counter value is increased by 1 after the decoding task is completed.

[0077] When there is no idle hardware decoding core of the corresponding type in the hardware decoding core resource pool, the above scheme waits for the appearance of an idle hardware decoding core of the corresponding type in the hardware decoding core resource pool. Compared with the queuing method for a single hardware decoding core in the related art, the above scheme queues all hardware decoding cores of the corresponding type in the hardware decoding core resource pool, which reduces the probability of decoding congestion in scenarios with a large number of decoding tasks, and is conducive to improving the decoding efficiency of the above-mentioned channel decoding acceleration system 100.

[0078] The following describes the working principle of the channel decoding acceleration system 100 by taking the interaction process between the task configuration register 110, the data storage 120, the hardware decoding core resource pool 130 and the task scheduling module 140 in a certain scenario. In this scenario, the multiple subtask registers in the task configuration register 110 respectively store the decoding task configuration information configured by the user through software, and the hardware decoding core resource pool 130 is also provided with the corresponding type of hardware decoding core. Figure 2 , the interaction process is as follows:

[0079] Step 1: The task scheduling module 140 polls the nth subtask register in the task configuration register 110; in the initial state, the value of n is 1;

[0080] Step 2: determine whether the current subtask register stores decoding task configuration information. If yes, execute step 3; otherwise, calculate n=n+1 and return to step 1.

[0081] Step 3: read and parse the task configuration information, obtain the task decoding type and the data to be decoded and the address of the data to be decoded, and after completing the configuration information parsing, execute steps 4 and 5 in parallel;

[0082] Step 4: Calculate n=n+1 and then return to step 1;

[0083] Step 5: According to the task decoding type, request the hardware decoding core resource pool 130 for the corresponding type of hardware decoding core, obtain the counter value corresponding to each type of hardware decoding core, and then execute step 6;

[0084] It can be understood that the counter value corresponding to each type of hardware decoding core represents the number of idle hardware decoding cores of this type in the hardware decoding core resource pool 130. Taking the hardware decoding core of type A as an example, if the counter value corresponding to the hardware decoding core of type A is a non-zero value, it means that there are idle hardware decoding cores of type A available for call in the hardware decoding core resource pool 130. If the counter value corresponding to the hardware decoding core of type A is zero, it means that there are no idle hardware decoding cores of type A available for call in the hardware decoding core resource pool 130.

[0085] Step 6: determine whether there is an idle hardware decoding core of the corresponding type available for calling. If not, wait in a queue until there is an idle hardware decoding core of the corresponding type available for calling by the current decoding task in the hardware decoding core resource pool 130; if so, read the data to be decoded in the data memory 120 according to the address of the data to be decoded and call the idle hardware decoding core to process the data to be decoded and obtain the decoded data returned by the hardware decoding core, and then execute step 7;

[0086] Step 7, storing the decoded data into the data memory 120;

[0087] It is understandable that the task scheduling module 140 does not perform the next polling after the decoding task is completed, but performs the next polling when the decoding task configuration information is parsed or when the decoding task configuration information does not exist in the subtask register.

[0088] Taking the above scenario as an example, it is assumed that the first subtask register corresponding to task 1 and the second subtask register corresponding to task 2 both store decoding task configuration information, decoding task 1 and decoding task 2 perform the same type of decoding processing on the to-be-decoded data at different addresses, and the hardware decoding core resource pool 130 includes multiple hardware decoding cores of the same type for processing the above to-be-decoded data. The processing timing of decoding task 1 and decoding task 2 is as follows: Figure 3 As shown by Figure 3It can be seen that by properly configuring the types and quantities of hardware decoding cores included in the decoding hardware decoding core resource pool 130, it is possible to implement parallel processing of decoding tasks of the same type or different types, thereby greatly improving decoding efficiency.

[0089] See also Figure 4 Based on the same inventive concept, the embodiment of the present application further provides a channel decoding acceleration method, which is applied to the above-mentioned task scheduling module 140, including:

[0090] Step S210: polling each subtask register in the task configuration register 110;

[0091] Step S220: If the subtask register does not store the decoding task configuration information, continue to poll the next subtask register;

[0092] Step S230: if the subtask register stores decoding task configuration information, read and parse the decoding task configuration information stored in the subtask register, obtain the task decoding type and the address of the data to be decoded, and then execute steps S240 and S250 in parallel;

[0093] Step S240: after reading and parsing the decoding task configuration information, continue to poll the next subtask register;

[0094] Step S250: for each decoding task configuration information that has been parsed, schedule the hardware decoding core of the corresponding type in the hardware decoding core resource pool 130 according to the task decoding type; read the data to be decoded in the data storage 120 according to the address of the data to be decoded; use the hardware decoding core to decode the data to be decoded to obtain the decoded data; and store the decoded data in the data storage 120.

[0095] See also Figure 5 Based on the same inventive concept, an embodiment of the present application further provides a SoC chip 300, which includes any one of the above-mentioned channel decoding acceleration systems 100 and a SoC bus 310, and the channel decoding acceleration system 100 is mounted on the SoC bus 310 through an interface.

[0096] It is understandable that the channel decoding acceleration system 100 can be mounted on the SoC bus 310 using an AXI / AHB interface.

[0097] As an optional implementation of the SoC chip, the SoC chip 300 is a GNSS chip.

[0098] GNSS (Global Navigation Satellite System) is an airborne radio navigation and positioning system that can provide users with all-weather three-dimensional coordinates, speed and time information at any location on the earth's surface or near-earth space. GNSS includes channel coding methods such as Hamming code, CRC+convolution, BCH code, LDPC code Viterbi, etc. If the solution of setting multiple decoding accelerators in the related technology is adopted, the integration of SoC chips will be increased, and the hardware implementation cost will also be high. The above-mentioned channel decoding acceleration system 100 solves these defects.

[0099] As an optional implementation of the above-mentioned SoC chip, the hardware decoding core resource pool 130 in the channel decoding acceleration system 100 includes: at least one type of decoding core among: Hamming code decoding core, CRC decoding core, LDPC decoding core, convolution decoding core, CRC convolution decoding core, BCH code decoding core and Viterbi decoding core.

[0100] An embodiment of the present application further provides a computer-readable storage medium having computer program instructions stored thereon. When the computer program instructions are read and executed by a processor of a computer, the channel decoding acceleration method provided in the embodiment of the present application is executed.

[0101] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by technicians in the technical field to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" in the specification and claims of this application and the above-mentioned figure descriptions and any variations thereof are intended to cover non-exclusive inclusions.

[0102] In the description of the embodiments of the present application, the technical terms "first", "second", etc. are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features. In the description of the embodiments of the present application, the meaning of "multiple" is more than two, unless otherwise clearly and specifically defined.

[0103] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0104] In the description of the embodiments of the present application, the term "and / or" is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0105] The above description is only an embodiment of the present application and is not intended to limit the protection scope of the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A channel decoding acceleration system, characterized in that: The system includes: a task configuration register, a task scheduling module, a data memory and a hardware decoding core resource pool, wherein: The task configuration register is used to receive decoding task configuration information and store the decoding task configuration information in the subtask register; wherein the decoding task configuration information includes the task decoding type and the address of the data to be decoded; The data memory is used to store data to be decoded and decoded data; The hardware decoding core resource pool includes hardware decoding cores for scheduling by the task scheduling module; The task scheduling module is used to poll each of the subtask registers and schedule the hardware decoding core to decode the data to be decoded according to the decoding task configuration information stored in the subtask register; the task scheduling module continues to poll the next subtask register after parsing the decoding task configuration information stored in the current subtask register.

2. The channel decoding acceleration system according to claim 1, characterized in that: The data memory is an SRAM; the SRAM provides idle address segments for all the subtask registers in the task configuration register to store the data to be decoded.

3. The channel decoding acceleration system according to claim 1, wherein: The hardware decoding core resource pool includes one or more types of hardware decoding cores.

4. The channel decoding acceleration system according to claim 3, wherein: The number of each type of hardware decoding core is one or more.

5. The channel decoding acceleration system according to claim 1, wherein: When the decoding task configuration information is stored in the subtask register, the task scheduling module performs the following steps: Reading and parsing the decoding task configuration information stored in the subtask register; Scheduling the hardware decoding core of a corresponding type in the hardware decoding core resource pool according to the task decoding type; Reading the data to be decoded from the data memory according to the address of the data to be decoded; Decoding the data to be decoded using the hardware decoding core to obtain the decoded data; The decoded data is stored in the data memory.

6. The channel decoding acceleration system according to claim 1, wherein: The task scheduling module schedules the hardware decoding core of a corresponding type in the hardware decoding core resource pool according to the task decoding type, including: Applying for the hardware decoding core of the corresponding type from the hardware decoding core resource pool; If there is an idle hardware decoding core of the corresponding type in the hardware decoding core resource pool, executing the steps of reading data to be decoded, decoding, and storing the decoded data; If there is no idle hardware decoding core of the corresponding type in the hardware decoding core resource pool, a queue is set to wait until an idle hardware decoding core of the corresponding type appears in the hardware decoding core resource pool.

7. A channel decoding acceleration method, characterized in that: Applied to the task scheduling module, the method includes: Poll each subtask register in the task configuration register; If the decoding task configuration information is not stored in the subtask register, continue to poll the next subtask register; If the subtask register stores decoding task configuration information, then reading and parsing the decoding task configuration information stored in the subtask register to obtain the task decoding type and the address of the data to be decoded; After reading and parsing the decoding task configuration information, continue to poll the next subtask register; For each decoding task configuration information that has completed parsing, the hardware decoding core of the corresponding type is scheduled in the hardware decoding core resource pool according to the task decoding type; the data to be decoded is read from the data memory according to the address of the data to be decoded; the data to be decoded is decoded using the hardware decoding core to obtain decoded data; and the decoded data is stored in the data memory.

8. A SoC chip, characterized in that: The SoC chip comprises: the channel decoding acceleration system according to any one of claims 1 to 6 and a SoC bus; the channel decoding acceleration system is mounted on the SoC bus through an interface.

9. The SoC chip according to claim 8, characterized in that: The SoC chip is a GNSS chip.

10. The SoC chip according to claim 9, characterized in that: The hardware decoding core resource pool in the channel decoding acceleration system includes at least one type of decoding cores selected from the group consisting of Hamming code decoding core, CRC decoding core, LDPC decoding core, convolutional decoding core, CRC convolutional decoding core, BCH code decoding core and Viterbi decoding core.

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