Common mode gain rejection active balun architecture, receiver, and communication system

Abstract

The application discloses a common-mode gain suppression active balun architecture, a receiver and a communication system, and the common-mode gain suppression active balun architecture comprises a first amplifier unit, a second amplifier unit and a transimpedance amplifier unit. The first amplifier unit is connected with a first input voltage and a second bias voltage, and outputs a first current path and a second current path; the second amplifier unit is connected with a second input voltage and the second bias voltage, and outputs the first current path and the second current path; and the transimpedance amplifier unit amplifies the first current path and the second current path and then outputs a first differential signal and a second differential signal. In the application, the first current path and the second current path generated by the two amplifier units are cross-added at an input node of the transimpedance amplifier unit, and when the differential signals are subtracted, the common-mode component can be suppressed, so that the gain and phase mismatch of the output signal can be reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and particularly relates to a common-mode gain suppression active balun architecture, a receiver and a communication system. BACKGROUND

[0002] In high-speed optical communication or wired communication, there is a scenario of using single-ended signal to transmit high-speed serial data. In this scenario, the single-ended signal has weak anti-interference performance, and is generally converted into a differential signal through a balun and then processed by a subsequent module.

[0003] A balun is a structure used for converting a single-ended signal into a differential signal in a communication system, which can improve the transmission efficiency and anti-interference performance of the signal, reduce the distortion and noise of the signal, and improve the eye diagram quality. The balun is a core device of the receiving end of a single-ended communication system. A traditional passive balun realizes the function of converting a single-ended signal into a differential signal through capacitors, inductors, transmission lines or coaxial cables and other passive devices. An active balun has the following advantages compared with the traditional passive balun: 1. It can provide gain to enhance the strength of the signal and improve the signal-to-noise ratio; 2. It can provide buffering to isolate the signal source and the load and reduce interference; and 3. The device size is small, which is convenient for integration in a chip.

[0004] However, due to the characteristics of the transistors or triodes of the active balun itself, the circuit common-mode gain of the traditional active balun is high, so that there is obvious gain and phase mismatch between the output signals.

[0005] Therefore, the prior art still needs to be improved and developed. SUMMARY

[0006] In view of the deficiencies of the prior art, the purpose of the present application is to provide a common-mode gain suppression active balun architecture, a receiver and a communication system to solve the problem of obvious gain and phase mismatch between the output signals of the traditional active balun.

[0007] The technical scheme of the present application is as follows:

[0008] In a first aspect, the present application provides a common-mode gain suppression active balun architecture, which comprises a first amplifier unit, a second amplifier unit and a transimpedance amplifier unit, wherein

[0009] The first amplifier unit is connected to a first input voltage and a second bias voltage, and outputs a first current path and a second current path;

[0010] The second amplifier unit is connected to a second input voltage and a second bias voltage, and outputs a first current path and a second current path;

[0011] The output end of the first amplifier unit, the output end of the second amplifier unit and the input end of the transimpedance amplifier unit are cross-connected, and the first current path and the second current path are cross-added at the input end of the transimpedance amplifier unit;

[0012] The transimpedance amplifier unit amplifies the first current path and the second current path and outputs a first differential signal and a second differential signal; wherein the first differential signal and the second differential signal each include a sum signal of the first current path and the second current path.

[0013] Further provided in the application, the transimpedance amplifier unit includes a first transimpedance amplifier and a second transimpedance amplifier; wherein,

[0014] The first transimpedance amplifier is connected with the first amplifier unit and is used for amplifying the first current path and the second current path and outputting a first differential signal;

[0015] The second transimpedance amplifier is connected with the second amplifier unit and is used for amplifying the first current path and the second current path and outputting a second differential signal.

[0016] Further provided in the application, the first amplifier unit includes a first MOS tube, a second MOS tube and a third MOS tube;

[0017] The gate of the first MOS tube is connected with a first input voltage, the drain of the first MOS tube is connected with the gate of the third MOS tube, and the source of the first MOS tube is grounded through a current source;

[0018] The gate of the second MOS tube is connected with a first bias voltage, the drain of the second MOS tube is connected with the drain of the third MOS tube, and the source of the second MOS tube is grounded through a current source;

[0019] The source of the third MOS tube is connected with a power supply voltage;

[0020] The common terminal of the drain of the second MOS tube and the drain of the third MOS tube is connected with the input end of the first transimpedance amplifier.

[0021] Further provided in the application, the second amplifier unit includes a fourth MOS tube, a fifth MOS tube and a sixth MOS tube; wherein,

[0022] The gate of the fourth MOS tube is connected with a second input voltage, the drain of the fourth MOS tube is connected with the drain of the sixth MOS tube, and the source of the fourth MOS tube is grounded through a current source;

[0023] The gate of the fifth MOS tube is connected to a second bias voltage, the drain of the fifth MOS tube is connected to the gate of the sixth MOS tube, and the source of the fifth MOS tube is grounded through a current source;

[0024] The source of the sixth MOS tube is connected to a power supply voltage;

[0025] The drain of the fourth MOS tube and the common terminal of the drain of the sixth MOS tube are connected to the input terminal of the second transimpedance amplifier.

[0026] Further provided by the application, the common-mode rejection active balun architecture further comprises a seventh MOS tube, an eighth MOS tube, a first resistor and a second resistor, wherein,

[0027] One end of the first resistor is connected to the drain of the first MOS tube, and the other end of the first resistor is connected to the gate of the seventh MOS tube;

[0028] The drain of the seventh MOS tube is connected to the drain of the first MOS tube, and the source of the seventh MOS tube is connected to a power supply voltage;

[0029] One end of the second resistor is connected to the drain of the fifth MOS tube, and the other end of the second resistor is connected to the gate of the eighth MOS tube;

[0030] The drain of the eighth MOS tube is connected to the drain of the fifth MOS tube, and the source of the eighth MOS tube is connected to a power supply voltage.

[0031] Further provided by the application, the common-mode rejection active balun architecture further comprises a low-frequency filter connected to the input terminal of the transimpedance amplifier unit for filtering out low-frequency component signals.

[0032] Further provided by the application, the first transimpedance amplifier comprises a ninth MOS tube, a tenth MOS tube and a first feedback resistor, wherein,

[0033] The gate of the ninth MOS tube is connected to the gate of the tenth MOS tube, the drain of the ninth MOS tube is connected to the drain of the tenth MOS tube, the source of the ninth MOS tube is connected to a power supply voltage, and the source of the tenth MOS tube is grounded through a current source;

[0034] The first feedback resistor is connected between the input terminal and the output terminal of the first transimpedance amplifier.

[0035] Further provided by the application, the second transimpedance amplifier comprises an eleventh MOS tube, a twelfth MOS tube and a second feedback resistor, wherein,

[0036] The gate of the eleventh MOS transistor is connected with the gate of the twelfth MOS transistor, the drain of the eleventh MOS transistor is connected with the drain of the twelfth MOS transistor, the source of the eleventh MOS transistor is connected with a power supply voltage, and the source of the twelfth MOS transistor is connected with a ground through a current source.

[0037] The second feedback resistor is connected between the input terminal and the output terminal of the second transimpedance amplifier.

[0038] In a second aspect, the present application provides a receiver comprising the common-mode rejection active balun architecture as described above.

[0039] In a third aspect, the present application provides a communication system comprising the receiver as described above.

[0040] The common-mode gain rejection active balun architecture, the receiver and the communication system provided by the present application comprise a first amplifier unit, a second amplifier unit and a transimpedance amplifier unit. The first amplifier unit is connected with a first input voltage and a second bias voltage, and outputs a first current path and a second current path; the second amplifier unit is connected with a second input voltage and the second bias voltage, and outputs the first current path and the second current path; the output terminal of the first amplifier unit, the output terminal of the second amplifier unit and the input terminal of the transimpedance amplifier unit are cross-connected, and the first current path and the second current path are cross-added at the input terminal of the transimpedance amplifier unit; the transimpedance amplifier unit amplifies the first current path and the second current path, and outputs a first differential signal and a second differential signal; wherein the first differential signal and the second differential signal both comprise the sum signal of the first current path and the second current path. In the present application, each of the two amplifier units can generate a first current path and a second current path, and the first current path and the second current path generated by the two amplifier units are cross-added at the input node of the transimpedance amplifier unit. Since the first differential signal and the second differential signal output by the transimpedance amplifier unit both comprise the sum signal of the first current path and the second current path, when the differential signals are subtracted, the common-mode component can be suppressed, so that the gain and phase mismatch of the output signal can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from the structures shown in the drawings without creative labor.

[0042] Figure 1is a schematic diagram of a conventional active balun architecture and its small signal model.

[0043] Figure 2 is a schematic diagram of a common mode gain suppression active balun architecture in the present application.

[0044] Figure 3 is a schematic diagram of a common mode gain suppression active balun architecture in the present application and its common mode small signal model.

[0045] Figure 4 is a comparison diagram of the common mode gain between the new active balun provided by the present application and the conventional active balun in one embodiment of the present application.

[0046] Figure 5 is a comparison diagram of the gain mismatch and phase mismatch between the new active balun provided by the present application and the conventional active balun in one embodiment of the present application.

[0047] In the drawings: 100, first amplifier unit; 200, second amplifier unit; 300, transimpedance amplifier unit. DETAILED DESCRIPTION

[0048] The present application provides a common mode gain suppression active balun architecture, a receiver and a communication system, in order to make the purpose, technical scheme and effect of the present application more clear and explicit, the present application is further described in detail below with reference to the drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0049] In the embodiments and the scope of the application, unless the article has a special limitation in the text, "a", "an", "said" and "the" can also include plural forms. If the description of "first", "second" and the like is involved in the embodiments of the present application, the description of "first", "second" and the like is only for the purpose of description, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the features limited by "first", "second" can explicitly or implicitly include at least one of the features.

[0050] It should be further understood that the phrase "comprising" used in the specification of the present application means that the features, integers, steps, operations, elements and / or components exist, but does not exclude the existence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It should be understood that when an element is said to be "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there can be intermediate elements. In addition, "connection" or "coupling" used herein can include wireless connection or wireless coupling. The phrase "and / or" used herein includes all or any unit and all combinations of the associated listed items.

[0051] Those skilled in the art can understand that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art in the field of the present application. It should also be understood that the terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0052] In addition, the technical solutions among various embodiments can be combined with each other, but it must be based on the fact that a person skilled in the art can realize it. When the combination of technical solutions appears contradictory or unachievable, it should be considered that the combination of technical solutions does not exist and is not within the protection scope required by the present application.

[0053] The inventor found that, for an active balun circuit, the differential input of the circuit has one end of the input signal and one end of the bias signal. The single-ended input signal V in can be written as (V in +V in ) / 2, and the bias voltage V B can be represented as (V in -V in ) / 2. Each of them contains a common-mode signal V in / 2 and a differential signal (V in / 2, -V in / 2).

[0054] As Figure 1 shown, for the differential output signals V outp and V outn of the conventional current-mode logic active balun circuit, they can be represented as:

[0055]

[0056] where A CM and A CM represent the common-mode gain and the differential-mode gain, respectively. The mismatch between the differential signals can be represented as ΔV OUT :

[0057]

[0058] Enhanced common-mode rejection will result in smaller differential signal mismatch, so that the output signal is closer to the ideal differential-mode signal. The small-signal common-mode gain of the conventional current-mode logic active balun circuit can be represented as:

[0059]

[0060] wherein r O is the equivalent output impedance of the tail current source, g m1 is the transconductance of the transistor M1, g m2 is the transconductance of the transistor M2. Due to the finite output impedance and parasitic capacitance, the common mode gain cannot be completely cancelled. Therefore, the conventional current-mode logic type active balun circuit has amplitude and phase mismatch between the outputs of its differential outputs P / N nodes.

[0061] To solve the above technical problems, the application provides a common mode gain suppression active balun architecture, a receiver and a communication system. Two amplifier units in the common mode gain suppression active balun architecture can generate a first current path and a second current path, and the first current path and the second current path generated by the two amplifier units are cross-added at the input node of the transimpedance amplifier unit. Since the first differential signal and the second differential signal output by the transimpedance amplifier unit both include the sum signal of the first current path and the second current path, when the differential signals are subtracted, the common mode component can be suppressed, so that the gain and phase mismatch of the output signal can be reduced, and the common mode gain suppression active balun architecture has higher competitiveness compared with the conventional passive balun.

[0062] Please refer to Figures 2 to 5 , the application provides a preferred embodiment of the common mode gain suppression active balun architecture.

[0063] In some embodiments, as shown in Figure 2 , the application provides a common mode gain suppression active balun architecture, which comprises a first amplifier unit 100, a second amplifier unit 200 and a transimpedance amplifier unit 300. The first amplifier unit 100 is connected to a first input voltage and a second bias voltage, and outputs a first current path Path1 and a second current path Path2. The second amplifier unit 200 is connected to a second input voltage V in2 and a second bias voltage V b2 , and outputs the first current path Path1 and the second current path Path2. The output end of the first amplifier unit 100, the output end of the second amplifier unit 200 and the input end of the transimpedance amplifier unit 300 are cross-connected, and the first current path Path1 and the second current path Path2 are cross-added at the input end of the transimpedance amplifier unit 300. The transimpedance amplifier unit 300 amplifies and outputs a first differential signal V outp and a second differential signal V outn after the first current path Path1 and the second current path Path2. The first differential signal V outp and the second differential signal V outn both include the sum signal of the first current path and the second current path.

[0064] In the embodiment, the active balun architecture is composed of two amplifier units and a trans-impedance amplifier unit, wherein each of the two amplifier units can generate the first current path Path1 and the second current path Path2, i.e., the first amplifier unit 100 and the second amplifier unit 200 can generate the first current path Path1 and the second current path Path2, respectively. The first current path Path1 and the second current path Path2 generated by the two amplifier units are cross-added at the input node of the trans-impedance amplifier unit, so that the sum can be obtained at the input end of the trans-impedance amplifier unit. The first differential signal V outp and the second differential signal V outn each include the sum of the first current path Path1 and the second current path Path2. When the differential signals are subtracted, the common mode component is suppressed, and only the differential mode signal is amplified, so that the gain and phase mismatch of the output signal can be reduced, and the active balun has higher competitiveness compared with the traditional passive balun.

[0065] In some embodiments, as shown in Figure 2 and Figure 3 , the trans-impedance amplifier unit 300 includes a first trans-impedance amplifier and a second trans-impedance amplifier. The first trans-impedance amplifier is connected with the first amplifier unit, and is configured to amplify and output the first differential signal V outp after amplifying the first current path Path1 and the second current path Path2. The second trans-impedance amplifier is connected with the second amplifier unit, and is configured to amplify and output the second differential signal V outn after amplifying the first current path Path1 and the second current path Path2.

[0066] In the embodiment, the trans-impedance amplifier unit 300 is composed of the first trans-impedance amplifier and the second trans-impedance amplifier. The output signal V op output by adding the first current path Path1 and the second current path Path2 output by the first amplifier unit 100 is amplified by the first trans-impedance amplifier to output the first differential signal V outp , and the output signal V on output by adding the first current path Path1 and the second current path Path2 output by the second amplifier unit is amplified by the second trans-impedance amplifier to output the second differential signal V outn . Therefore, the signals output at the two output ends of the trans-impedance amplifier unit both include the sum of the first current path Path1 and the second current path Path2, and when the two differential signals are subtracted, the common mode component is suppressed.

[0067] In some embodiments, as Figure 2 With Figure 3 the first amplifier unit 100 includes: a first MOS transistor M1, a second MOS transistor M2 and a third MOS transistor M3; the gate of the first MOS transistor M1 is connected to a first input voltage V in1 , the drain of the first MOS transistor M1 is connected to the gate of the third MOS transistor M3, and the source of the first MOS transistor M1 is grounded through a current source; the gate of the second MOS transistor M2 is connected to a first bias voltage V b1 , the drain of the second MOS transistor M2 is connected to the drain of the third MOS transistor M3, and the source of the second MOS transistor M2 is grounded through a current source; the source of the third MOS transistor M3 is connected to a power supply voltage VDD; and the common terminal of the drain of the second MOS transistor M2 and the drain of the third MOS transistor M3 is connected to the input terminal of the first transimpedance amplifier.

[0068] Further, the second amplifier unit 200 includes: a fourth MOS transistor M4, a fifth MOS transistor M5 and a sixth MOS transistor M6; wherein the gate of the fourth MOS transistor M4 is connected to a second input voltage V in2 , the drain of the fourth MOS transistor M4 is connected to the drain of the sixth MOS transistor M6, and the source of the fourth MOS transistor M4 is grounded through a current source; the gate of the fifth MOS transistor M5 is connected to a second bias voltage V b2 , the drain of the fifth MOS transistor M5 is connected to the gate of the sixth MOS transistor M6, and the source of the fifth MOS transistor M5 is grounded through a current source; the source of the sixth MOS transistor M6 is connected to a power supply voltage VDD; and the common terminal of the drain of the fourth MOS transistor M4 and the drain of the sixth MOS transistor M6 is connected to the input terminal of the second transimpedance amplifier.

[0069] Specifically, the first input voltage V in1 is applied to the input terminal of the first MOS transistor, the second input voltage V in2 is applied to the input terminal of the fourth MOS transistor M4, the first bias voltage V b1 is applied to the input terminal of the second MOS transistor M2, the second bias voltage V b2 is applied to the input terminal of the fifth MOS transistor M5, so that two paths of signals, i.e. a first current path Path1 and a second current path Path2, are formed.

[0070] wherein V cmM1+M5 represents the common mode component of the first MOS transistor and the fifth MOS transistor, M2+M4 represents the common mode component of the second MOS transistor and the fourth MOS transistor, M3+M6 represents the common mode component of the third MOS transistor and the sixth MOS transistor, and M7+M8 represents the common mode component of the seventh MOS transistor and the eighth MOS transistor. The gate of the first MOS transistor M1 is connected to the first input voltage V in1 , the first input signal is amplified by the first MOS transistor M1 and is common source amplified by the third MOS transistor M3, and is common drain amplified (source follower) with the second input voltage V in2 of the fourth MOS transistor M4, and is subsequently common gate amplified by the second MOS transistor M2, the first input voltage V in1 and the second input voltage V in2 are added at the common connection of the drain of the second MOS transistor M2 and the drain of the third MOS transistor M3 to form the output signal V op . The gate of the fourth MOS transistor M4 is connected to the second input voltage V in2 , the second input voltage V in2 is common source amplified by the fourth MOS transistor M4, and the first input voltage V in1 of the first MOS transistor M1 is common drain amplified (source follower), and is subsequently common gate amplified by the fifth MOS transistor M5, the second input voltage V in2 and the first input voltage V in1 are added at the common connection of the drain of the fourth MOS transistor M4 and the drain of the sixth MOS transistor to form the output signal. In this way, by cross-coupling the single-ended input voltage and the bias voltage to the input terminals of the two amplifier units, the signals on the two output paths (the first current path Path1 and the second current path Path2) of different strengths are added at one output terminal, so that each output signal contains the signals of the first current path Path1 and the second current path Path2, and when the differential signals are subtracted, the common mode component can be suppressed.

[0071] In some embodiments, as Figure 3As shown, the common-mode rejection active balun architecture further comprises a seventh MOS transistor M7, an eighth MOS transistor M8, a first resistor R1 and a second resistor R2. The one end of the first resistor R1 is connected with the drain of the first MOS transistor M1, and the other end of the first resistor R1 is connected with the gate of the seventh MOS transistor M7. The drain of the seventh MOS transistor M7 is connected with the drain of the first MOS transistor M1, and the source of the seventh MOS transistor M7 is connected with a power supply voltage VDD. The one end of the second resistor R2 is connected with the drain of the fifth MOS transistor M5, and the other end of the second resistor R2 is connected with the gate of the eighth MOS transistor M8. The drain of the eighth MOS transistor M8 is connected with the drain of the fifth MOS transistor M5, and the source of the eighth MOS transistor M8 is connected with the power supply voltage VDD.

[0072] In the embodiment, the seventh MOS transistor M7 and the first resistor R1 constitute an active inductor, the eighth MOS transistor M8 and the second resistor R2 constitute an active inductor, and the first resistor R1 and the second resistor R2 are active peak resistors, which can improve the bandwidth without occupying a large area.

[0073] In some embodiments, as shown in Figure 2 As shown, the common-mode rejection active balun architecture further comprises a low-frequency filter LPF connected with the input end of the transimpedance amplifier unit 300, for filtering out low-frequency component signals, so that the first input voltage and the second input voltage are signals with high-frequency components.

[0074] In some embodiments, as shown in Figure 2 and Figure 3 As shown, the first transimpedance amplifier comprises a ninth MOS transistor M9, a tenth MOS transistor M10 and a first feedback resistor R F1 . The gate of the ninth MOS transistor M9 is connected with the gate of the tenth MOS transistor M10, the drain of the ninth MOS transistor M9 is connected with the drain of the tenth MOS transistor M10, the source of the ninth MOS transistor M9 is connected with a power supply voltage VDD, and the source of the tenth MOS transistor M10 is connected with a ground through a current source. The first feedback resistor R F1 is connected between the input end and the output end of the first transimpedance amplifier.

[0075] Further, the second transimpedance amplifier comprises an eleventh MOS transistor M11, a twelfth MOS transistor M12 and a second feedback resistor R F2The gate of the eleventh MOS transistor M11 is connected with the gate of the twelfth MOS transistor M12, the drain of the eleventh MOS transistor M11 is connected with the drain of the twelfth MOS transistor M12, the source of the eleventh MOS transistor M11 is connected with a power voltage VDD, and the source of the twelfth MOS transistor M12 is connected with a ground through a current source; the second feedback resistor R F2 is connected between the input end and the output end of the second transimpedance amplifier.

[0076] Specifically, the first transimpedance amplifier and the second transimpedance amplifier are both composed of an inverter and a feedback resistor. The common connection end of the gates of the ninth MOS transistor M9 and the tenth MOS transistor M10 is the input end of the first transimpedance amplifier, the common connection end of the drains of the ninth MOS transistor M9 and the tenth MOS transistor M10 is the output end of the first transimpedance amplifier, and the output signal V op of the first amplifier unit 100 is input from the input end of the first transimpedance amplifier and output from the output end of the first transimpedance amplifier after amplification. outp The common connection end of the gates of the eleventh MOS transistor M11 and the twelfth MOS transistor M12 is the input end of the second transimpedance amplifier, the common connection end of the drains of the eleventh MOS transistor M11 and the twelfth MOS transistor M12 is the output end of the second transimpedance amplifier, and the output signal V on of the second amplifier unit 200 is input from the input end of the second transimpedance amplifier and output from the output end of the second transimpedance amplifier after amplification. outn .

[0077] In the embodiment, the small signal common mode gain of the active balun can be represented as:

[0078] A CM =(G m1 -G m2 )·CM_Gain TIA .

[0079] Wherein, G m1 and G m2 represent the common mode gains of the first current path Path1 and the second current path Path2, CM_Gain TIA represents the common mode gain of the transimpedance amplifier, and G m1 and G m2 are respectively represented as:

[0080]

[0081]

[0082] wherein g m1 represents the transconductance of the first MOS transistor, g m2 represents the transconductance of the second MOS transistor, g m3 represents the transconductance of the third MOS transistor, g m4 represents the transconductance of the fourth MOS transistor, S refers to the independent variable of Laplace transform, ω T is the zero point of the input impedance of the transimpedance amplifier, r O is the equivalent output impedance of the tail current source, R represents the resistance values of the first resistor R1 and the second resistor R2.

[0083] As shown in Figure 4 , the active balun structure of the present application has higher common-mode gain suppression capability compared with the active balun structure of the conventional inverter structure. As shown in Figure 5 , the active balun structure of the present application has lower differential output mismatch compared with the active balun structure of the conventional current mode logic structure.

[0084] In some embodiments, the present application also provides a receiver comprising the common-mode suppression active balun architecture as described above. Details are described in the embodiment of the common-mode suppression active balun structure, which will not be repeated here.

[0085] In some embodiments, the present application also provides a communication system comprising the receiver as described above, which comprises the common-mode suppression active balun structure. Details are described in the embodiment of the common-mode suppression active balun structure, which will not be repeated here.

[0086] In summary, the common-mode gain suppression active balun architecture, the receiver and the communication system provided by the present application have the following beneficial effects:

[0087] The two amplifier units employed can generate a first current path and a second current path, and the first current path and the second current path generated by the two amplifier units are cross-added at the input node of the transimpedance amplifier unit. Since the first differential signal and the second differential signal output by the transimpedance amplifier unit both include the sum signal of the first current path and the second current path, when the differential signals are subtracted, the common-mode component can be suppressed, thereby reducing the gain and phase mismatch of the output signal. Compared with the active balun structure of the conventional inverter structure, the present application has higher common-mode gain suppression capability, and compared with the active balun structure of the conventional current mode logic structure, the present application has lower differential output mismatch.

[0088] It should be understood that the application of the present application is not limited to the above examples, and those of ordinary skill in the art can make improvements or changes according to the above description, and all these improvements and changes shall fall within the protection scope of the claims of the present application.

Claims

1. A common-mode gain suppression active balun architecture, characterized in that: include: A first amplifier unit, a second amplifier unit and a transimpedance amplifier unit; wherein, The first amplifier unit receives a first input voltage and a second bias voltage, and outputs a first current path and a second current path; The second amplifier unit receives a second input voltage and a second bias voltage, and outputs a first current path and a second current path; The output end of the first amplifier unit and the output end of the second amplifier unit are cross-connected with the input end of the transimpedance amplifier unit, and the first current path and the second current path are cross-added at the input end of the transimpedance amplifier unit; The transimpedance amplifier unit amplifies the first current path and the second current path and outputs a first differential signal and a second differential signal; wherein the first differential signal and the second differential signal both include summed signals of the first current path and the second current path.

2. The common-mode gain suppression active balun architecture according to claim 1, characterized in that: The transimpedance amplifier unit includes a first transimpedance amplifier and a second transimpedance amplifier; wherein, The first transimpedance amplifier is connected to the first amplifier unit and is configured to amplify the first current path and the second current path and output a first differential signal; The second transimpedance amplifier is connected to the second amplifier unit, and is configured to amplify the first current path and the second current path and then output a second differential signal.

3. The common-mode gain suppression active balun architecture according to claim 2, characterized in that: The first amplifier unit includes: a first MOS transistor, a second MOS transistor and a third MOS transistor; The gate of the first MOS transistor is connected to a first input voltage, the drain of the first MOS transistor is connected to the gate of the third MOS transistor, and the source of the first MOS transistor is grounded via a current source; The gate of the second MOS transistor is connected to the first bias voltage, the drain of the second MOS transistor is connected to the drain of the third MOS transistor, and the source of the second MOS transistor is grounded via a current source; The source of the third MOS tube is connected to the power supply voltage; A common terminal of the drain of the second MOS transistor and the drain of the third MOS transistor is connected to the input terminal of the first transimpedance amplifier.

4. The common-mode gain suppression active balun architecture according to claim 3, characterized in that: The second amplifier unit includes: a fourth MOS tube, a fifth MOS tube and a sixth MOS tube; wherein, The gate of the fourth MOS transistor is connected to the second input voltage, the drain of the fourth MOS transistor is connected to the drain of the sixth MOS transistor, and the source of the fourth MOS transistor is grounded via a current source; The gate of the fifth MOS transistor is connected to the second bias voltage, the drain of the fifth MOS transistor is connected to the gate of the sixth MOS transistor, and the source of the fifth MOS transistor is grounded via a current source; The source of the sixth MOS transistor is connected to the power supply voltage; A common terminal of the drain of the fourth MOS transistor and the drain of the sixth MOS transistor is connected to the input terminal of the second transimpedance amplifier.

5. The common-mode gain suppression active balun architecture according to claim 4, characterized in that: Also includes: a seventh MOS transistor, an eighth MOS transistor, a first resistor, and a second resistor; wherein, One end of the first resistor is connected to the drain of the first MOS transistor, and the other end of the first resistor is connected to the gate of the seventh MOS transistor; The drain of the seventh MOS transistor is connected to the drain of the first MOS transistor, and the source of the seventh MOS transistor is connected to the power supply voltage; One end of the second resistor is connected to the drain of the fifth MOS transistor, and the other end of the second resistor is connected to the gate of the eighth MOS transistor; The drain of the eighth MOS transistor is connected to the drain of the fifth MOS transistor, and the source of the eighth MOS transistor is connected to the power supply voltage.

6. The common-mode gain suppression active balun architecture according to claim 1, wherein: It also includes a low-frequency filter, which is connected to the input end of the transimpedance amplifier unit and is used to filter out low-frequency component signals.

7. The common-mode gain suppression active balun architecture according to claim 2, wherein: The first transimpedance amplifier includes: a ninth MOS transistor, a tenth MOS transistor and a first feedback resistor; wherein, The gate of the ninth MOS transistor is connected to the gate of the tenth MOS transistor, the drain of the ninth MOS transistor is connected to the drain of the tenth MOS transistor, the source of the ninth MOS transistor is connected to the power supply voltage, and the source of the tenth MOS transistor is grounded via a current source; The first feedback resistor is connected between the input terminal and the output terminal of the first transimpedance amplifier.

8. The common-mode gain suppression active balun architecture according to claim 2, wherein: The second transimpedance amplifier includes: an eleventh MOS transistor, a twelfth MOS transistor and a second feedback resistor; wherein, The gate of the eleventh MOS transistor is connected to the gate of the twelfth MOS transistor, the drain of the eleventh MOS transistor is connected to the drain of the twelfth MOS transistor, the source of the eleventh MOS transistor is connected to the power supply voltage, and the source of the twelfth MOS transistor is grounded via a current source; The second feedback resistor is connected between the input terminal and the output terminal of the second transimpedance amplifier.

9. A receiver, characterized in that: It comprises the common-mode rejection active balun architecture as described in any one of claims 1 to 8.

10. A communication system, characterized in that: Comprising a receiver as claimed in claim 9.

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