Security chip and password service processing method

Abstract

The disclosed embodiment of the present invention discloses a security chip and a cryptographic service processing method, wherein the security chip includes: a controller and cryptographic service execution hardware; the controller is connected to the cryptographic service execution hardware; the controller is used to send scheduling instructions and data to be processed about the cryptographic service to be processed to the cryptographic service execution hardware; the cryptographic service execution hardware is used to respond to the scheduling instructions and determine whether the scheduling instructions are abnormal based on a service lookup table; when the scheduling instructions are not abnormal, the data to be processed is processed based on an operation operator corresponding to the cryptographic service to be processed to obtain a final operation result, and the final operation result is output.

Description

Technical Field

[0001] The present disclosure relates to but is not limited to the field of computer technology, and in particular to a security chip and a cryptographic service processing method. Background Art

[0002] Cryptographic services are used in data usage, transmission, and storage, and may include encryption, decryption, and signature verification. In related technologies, the processing of cryptographic services is as follows: the user sends a cryptographic service request to the central processing unit (CPU) of the cryptographic chip; the CPU of the cryptographic chip calls the processing logic of the cryptographic service to implement the processing of the cryptographic service. However, during the processing of a complete cryptographic service, there will be multiple intermediate calculation results, which will be stored in the memory of the cryptographic chip. Users can easily read these multiple intermediate calculation results by issuing CPU instructions, and derive the key based on the intermediate calculation results, turning the ciphertext into plaintext, which has low security. Summary of the invention

[0003] In view of this, the embodiments of the present disclosure at least provide a security chip and a cryptographic service processing method.

[0004] The technical solution of the embodiment of the present disclosure is implemented as follows:

[0005] On the one hand, an embodiment of the present disclosure provides a security chip including: a controller and cryptographic service execution hardware; the controller is connected to the cryptographic service execution hardware; the controller is used to send scheduling instructions and data to be processed regarding a cryptographic service to be processed to the cryptographic service execution hardware; the cryptographic service execution hardware is used to respond to the scheduling instructions and determine whether the scheduling instructions are abnormal based on a service lookup table; when the scheduling instructions are not abnormal, the data to be processed is processed based on an operation operator corresponding to the cryptographic service to be processed to obtain a final operation result, and the final operation result is output.

[0006] In some embodiments, the cryptographic service execution hardware includes: an operation sequence detection module; an operation sequence detection module, used to determine whether a scheduling instruction is abnormal based on a service lookup table; the service lookup table includes: at least one operation sequence list of a cryptographic service; an operation sequence detection module, used to determine, based on an identifier of the cryptographic service to be processed, a target operation sequence list corresponding to the cryptographic service to be processed from at least one operation sequence list; based on the target operation sequence list, determine whether an operation operator corresponding to the cryptographic service to be processed is abnormal.

[0007] In some embodiments, the operation sequence list includes: the operation operators involved in the processing of the corresponding cryptographic service and the calling order of each operation operator; an operation sequence detection module, which is used to detect the currently called operation operator and the calling order of the currently called operation operator based on the operation operators and the calling order of each operation operator in the target operation sequence list to determine whether the currently called operation operator is abnormal.

[0008] In some embodiments, the operation sequence table includes: the total number of operator calls; an operation sequence detection module, which is used to determine that the current operation result is an intermediate operation result when the number of calls to the operation operator does not reach the total number of operator calls; when the number of calls to the operation operator reaches the total number of operator calls, determine that the current operation result is the final operation result.

[0009] In some embodiments, the operation sequence table includes: operation operators that need to be detected when the corresponding cryptographic service is processed; the operation operators that need to be detected are operation operators that carry keys, and / or operation operators whose keys can be reversely deduced.

[0010] In some embodiments, the operation sequence table includes: the total number of times the operation results involved in the processing of the corresponding cryptographic service are transferred; an operation sequence detection module, which is used to determine that the current operation result is an intermediate operation result when the number of times the operation result is transferred does not reach the total number of times; when the number of times the operation result is transferred reaches the total number of times, determine that the current operation result is the final operation result.

[0011] In some embodiments, the cryptographic service execution hardware includes: an operator operation counter; an operator operation counter for counting the number of times the operation operator is called; when the operation result of the operation operator needs to be moved, counting the number of times the operation result is moved.

[0012] In some embodiments, the cryptographic service execution hardware includes: a data storage area; the data storage area includes: an input data area, an operation result area and an output data area; a controller, used to write the data to be processed into the input data area; the cryptographic service execution hardware is used to write the operation result of the data to be processed processed by the operation operator corresponding to the scheduling instruction into the operation result area; an operation sequence detection module is used to determine that the intermediate operation result stored in the operation result area is the final operation result when the number of times the operation result is transferred reaches the total number of times, or the number of times the operation operator is called reaches the total number of times; the operation sequence detection module is used to clear the data in the data storage area when the operation operator is abnormal, or the number of times the operation result is transferred does not reach the total number of times, or the number of times the operation operator is called does not reach the total number of times.

[0013] In some embodiments, when the scheduling instruction is a cryptographic service selection instruction, the cryptographic service execution hardware is used to respond to the cryptographic service selection instruction, and determine the target operation sequence list corresponding to the cryptographic service to be processed based on the cryptographic service to be processed selected by the cryptographic service selection instruction; when the scheduling instruction is an enable instruction, the cryptographic service execution hardware is used to respond to the enable instruction and enter a ready state; when the scheduling instruction is a first data transfer instruction, the cryptographic service execution hardware is used to respond to the first data transfer instruction and transfer the data in the operation result area to the input data area; when the scheduling instruction is a second data transfer instruction, the cryptographic service execution hardware is used to respond to the second data transfer instruction and transfer the data in the operation result area to the output result area.

[0014] On the other hand, an embodiment of the present disclosure provides a cryptographic service processing method including: a controller sends a scheduling instruction and data to be processed regarding a cryptographic service to be processed to the cryptographic service execution hardware; the cryptographic service execution hardware responds to the scheduling instruction and determines whether the scheduling instruction is abnormal based on a service lookup table; when the scheduling instruction is not abnormal, the data to be processed is processed based on an operation operator corresponding to the cryptographic service to be processed to obtain a final operation result, and outputs the operation result of the data to be processed.

[0015] In some embodiments, determining whether a scheduling instruction is abnormal based on a service lookup table includes: determining whether the scheduling instruction meets preset conditions based on the service lookup table; the preset conditions include: the scheduling instruction needs to access the final calculation result, and the operation operator corresponding to the scheduling instruction has no abnormalities; if the scheduling instruction meets the preset conditions, determining that the scheduling instruction has no abnormalities; if the scheduling instruction does not meet the preset conditions, determining that the scheduling instruction is abnormal.

[0016] In some embodiments, the data to be processed is processed based on the operation operator corresponding to the cryptographic service to be processed to obtain the final operation result, and the operation result of the data to be processed is output, including: based on the first operation operator in the operation operator sequence, the data to be processed in the input data area is processed to obtain the first intermediate operation result, and the first intermediate operation result is written into the operation result area; in response to the first data transfer instruction, the first intermediate operation result in the operation result area is transferred to the input data area; based on the second operation operator in the operation operator sequence, the first intermediate operation result in the input data area is processed to obtain the second intermediate operation result, and the second intermediate operation result is written into the operation result area; in response to the next first data transfer instruction, the second intermediate operation result in the operation result area is transferred to the input data area, and the operator operation of the next operation operator in the operation operator sequence is continued until the operation operator sequence is processed and the final operation result is obtained; in response to the second data transfer instruction, the final operation result in the operation result area is transferred to the output result area to output the final operation result; the scheduling instruction includes the operation operator sequence, the first data transfer instruction, and the second data transfer instruction.

[0017] In some embodiments, the service lookup table includes: an operation sequence list of at least one cryptographic service; the cryptographic service processing method also includes: the cryptographic service execution hardware determines, based on the identification of the cryptographic service to be processed, a target operation sequence list corresponding to the cryptographic service to be processed from multiple operation sequence lists; based on the operation operators in the target operation sequence list and the calling order of each operation operator, the currently called operation operator and the calling order of the currently called operation operator are detected to determine whether the currently called operation operator is abnormal.

[0018] In some embodiments, the cryptographic service processing method also includes: when a scheduling instruction wants to access an intermediate calculation result, or an operation operator corresponding to the cryptographic service to be processed is abnormal, clearing the data in the data storage area and reporting the exception; the data storage area includes: an input data area, a calculation result area, and an output data area.

[0019] In the disclosed embodiment, the controller schedules the cryptographic service, and the cryptographic service execution hardware performs the cryptographic service calculation, which fully considers the design requirements and implementation costs of the security chip. This combination of software and hardware design reduces the chip area while maximizing the high security and high performance of the cryptographic service calculation. In addition, the cryptographic service execution hardware will output the calculation result only after the cryptographic service processing is completed, and the intermediate calculation result will not be output during the entire process, which further improves the security and performance of the cryptographic service calculation.

[0020] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and are not intended to limit the technical solutions of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and are used to illustrate the technical solutions of the present disclosure together with the specification.

[0022] Figure 1 A schematic diagram of the structure of a security chip provided in an embodiment of the present disclosure Figure 1 ;

[0023] Figure 2 A schematic diagram of implementing an operation sequence table in a security chip provided by an embodiment of the present disclosure;

[0024] Figure 3 A schematic diagram of the implementation process of a cryptographic service processing method provided in the embodiment of the present disclosure Figure 1 ;

[0025] Figure 4 A schematic diagram of the structure of a security chip provided in an embodiment of the present disclosure Figure 2 ;

[0026] Figure 5 A schematic diagram of implementing operation sequence detection in a security chip provided by an embodiment of the present disclosure;

[0027] Figure 6 A schematic diagram of the implementation process of a cryptographic service processing method provided in the embodiment of the present disclosure Figure 2 . DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated in detail below in conjunction with the drawings and embodiments. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.

[0029] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the present disclosure and are not intended to limit the present disclosure.

[0031] Before describing the security chip provided by the embodiments of the present disclosure, the technical terms involved in the embodiments of the present disclosure are explained first:

[0032] Register Transfer Level (RTL) code is a hardware description language (HDL) used to describe the data flow and logic operations between registers in digital circuits.

[0033] Cryptographic algorithms are mathematical functions used for encryption and decryption. Cryptographic algorithms are the basis of cryptographic protocols. Current cryptographic algorithms mainly include stream ciphers, block ciphers, public key ciphers, hash functions, etc., which are used to ensure data security and can provide authentication, integrity, and non-repudiation services.

[0034] A hardware acceleration engine, also known as a hardware accelerator, is a dedicated acceleration chip / module that can replace the CPU to complete complex, time-consuming, and high-computing operations. The process requires no or only a small amount of CPU participation.

[0035] A key is the corresponding substitution relationship between ciphertext and plaintext, and is divided into symmetric keys and asymmetric keys.

[0036] The operator module is a hardware implementation module that includes but is not limited to the following mathematical operations.

[0037] Modular addition is a binary operation, equivalent to the "XOR" operation.

[0038] Modular subtraction is a special binary operation. When performing modular subtraction, the minuend and subtrahend are first taken modulo, then the subtraction operation is performed, and finally the modulo is taken again.

[0039] Modular exponentiation is a mathematical operation used to calculate the value of (a^b)%p, where a and b are integers and p is a positive integer. The result of modular exponentiation is the remainder of a raised to the power of b divided by p.

[0040] Modular inverse operation means that in modular operation, the modular inverse of a number is defined as the modular inverse of the number multiplied by the product of the modular inverse of the number is 1.

[0041] The dot product operation refers to the dot product. In mathematics, the dot product, also known as the scalar product, is a binary operation that operates on two vectors on the real number R and returns a real-valued scalar.

[0042] PKE stands for public key encryption. Public-key cryptography, also known as asymmetric cryptography, is a type of cryptographic algorithm that uses two different keys: an encryption key and a decryption key.

[0043] DMA, Direct Memory Access (DMA) is a function provided by some computer bus architectures that can directly transfer memory data.

[0044] Sensitive data, key information or original plaintext information, or the intermediate results of cryptographic operations that can be used to derive key information or original plaintext information.

[0045] The present disclosure provides a security chip. Figure 1 As shown, the security chip 10 includes: a controller 11 and a cryptographic service execution hardware 12; the controller 11 is connected to the cryptographic service execution hardware 12; the controller 11 is used to send scheduling instructions and data to be processed about the cryptographic service to be processed to the cryptographic service execution hardware 12; the cryptographic service execution hardware 12 is used to respond to the scheduling instruction and determine whether the scheduling instruction is abnormal based on a service lookup table; if the scheduling instruction is not abnormal, the data to be processed is processed based on the operation operator corresponding to the cryptographic service to be processed to obtain a final operation result, and output the final operation result.

[0046] The cryptographic service to be processed refers to the computational requirements of the data to be processed. Cryptographic services may include, but are not limited to, encryption services, decryption services, signature services, and signature verification services. The processing of cryptographic services refers to the use of the operation operators corresponding to the cryptographic services to perform operations on the data to be processed. Different cryptographic services have different corresponding operation operators.

[0047] An operator refers to one or more operators involved in the processing of a corresponding cryptographic service. The calling order of these multiple operators is preset, so it can be called an operator sequence, or a cryptographic operation sequence. For example, an operator can include but is not limited to a modular subtraction operator, a modular exponentiation operator, a point multiplication operator, and a dot product operator. The scheduling instruction is used to control the cryptographic service execution hardware 12 to perform the corresponding operation. For example, the scheduling instruction can include but is not limited to a cryptographic service selection instruction, an enable instruction, and a data handling instruction.

[0048] The service lookup table is the basis for judging whether the scheduling instructions and operation operators are abnormal. The service lookup table includes at least one operation sequence table of a cryptographic service. There is a one-to-one correspondence between the cryptographic service and the operation sequence table, and the operation sequence tables corresponding to different cryptographic services are different.

[0049] The controller 11 is used to control the operations that can be executed in the security chip 10. Specifically, the controller 11 is used to schedule the cryptographic service execution hardware 12 to execute the operator operation corresponding to the cryptographic service. More specifically, the controller 11 is used to send a scheduling instruction about the cryptographic service to the cryptographic service execution hardware 12. For example, the controller 11 can be a CPU.

[0050] The cryptographic service execution hardware 12 refers to a hardware circuit based on the Register Transfer Level code. This circuit is integrated on the security chip 10 and can store keys and provide cryptographic operation services. The cryptographic service execution hardware 12 is used to execute operator operations corresponding to the cryptographic service. Specifically, the cryptographic service execution hardware 12 is used to determine whether the scheduling instruction is abnormal based on the service lookup table; and to process the data to be processed based on the operation operator corresponding to the cryptographic service. For example: if the cryptographic service is an encryption service, the cryptographic service execution hardware 12 is used to encrypt the data to be processed based on the operation operator of the encryption service.

[0051] like Figure 1 As shown, the cryptographic service execution hardware 12 and the controller 11 can be connected via a bus system. Specifically, the cryptographic service execution hardware 12 can be connected to the bus system of the security chip 10 via a bus interface, so as to be connected to the controller 11 via the bus system.

[0052] In some implementations, the operation operators involved in the cryptographic service may be pre-placed in the operator module 131 of the cryptographic service execution hardware 12. Figure 1 As shown, the operator module 131 may include a modular subtraction operator, a modular power operator, a point multiplication operator, and the like.

[0053] In some implementations, the chip bus can be prohibited from accessing the calculation results through hardware memory management, and the calculation results are output only after the cryptographic service processing is completed. In this way, the intermediate calculation results will not be output, further improving the security of the cryptographic service calculation.

[0054] It should be noted that hardware security is higher than software security. Therefore, the disclosed embodiment places the scheduling of cryptographic services at the software level (scheduling of the controller 11) and the operation of cryptographic services at the hardware level (execution of the cryptographic service execution hardware 12). In this way, the design requirements and implementation costs of the security chip are fully considered. This combination of software and hardware design maximizes the high security and high performance of cryptographic service operations while reducing the chip area. In addition, the cryptographic service execution hardware 12 will only output the operation results after the cryptographic service processing is completed. The intermediate operation results will not be output during the entire process, which further improves the security of the cryptographic service operation.

[0055] In the disclosed embodiment, the controller schedules the cryptographic service, and the cryptographic service execution hardware performs the cryptographic service calculation, which fully considers the design requirements and implementation costs of the security chip. This combination of software and hardware design reduces the chip area while maximizing the high security and high performance of the cryptographic service calculation. In addition, the cryptographic service execution hardware will output the calculation result only after the cryptographic service processing is completed, and the intermediate calculation result will not be output during the entire process, which further improves the security and performance of the cryptographic service calculation.

[0056] In some embodiments, the cryptographic service execution hardware 12 includes: an operation sequence detection module 121; the operation sequence detection module 121 is used to determine whether the scheduling instruction is abnormal based on a service lookup table; the service lookup table includes: an operation sequence list of at least one cryptographic service; the operation sequence detection module 121 is used to determine, based on the identifier of the cryptographic service to be processed, a target operation sequence list corresponding to the cryptographic service to be processed from at least one of the operation sequence lists; based on the target operation sequence list, determine whether the operation operator corresponding to the cryptographic service to be processed is abnormal.

[0057] The operation sequence detection module 121 is used to detect illegal operations of the CPU and whether there are abnormalities in the processing of the cryptographic service. The operation sequence detection module 121 pre-stores a plurality of operation sequence tables corresponding to the cryptographic services. The operation sequence table is used to reflect the operation operators involved in the processing of the corresponding cryptographic service and the calling order of each operation operator. The target operation sequence table refers to the target operation sequence table corresponding to the cryptographic service to be processed. For example: if the cryptographic service to be processed is an encryption service, the target operation sequence table is the operation sequence table corresponding to the encryption service.

[0058] In some implementations, the operation sequence detection module 121 is implemented by integrating the circuit designed with RTL code into hardware. Specifically, the operation sequence detection module 121 is used to determine whether the operation operator of the cryptographic service to be processed is abnormal based on the target operation sequence table; if the operation operator of the cryptographic service to be processed is abnormal, the operator operation of the cryptographic service to be processed is determined to be illegal; if the operator operation of the cryptographic service to be processed is not abnormal, the operation operator of the cryptographic service to be processed is determined to be legal. The detection of the operation operator includes the detection of the operation operator itself and the detection of the operation operator operation process.

[0059] In some embodiments, the operation sequence list includes: the operation operators involved in the processing of the corresponding cryptographic service and the calling order of each operation operator; the operation sequence detection module 121 is used to detect the currently called operation operator and the calling order of the currently called operation operator based on the operation operators and the calling order of each operation operator in the target operation sequence list to determine whether the currently called operation operator is abnormal.

[0060] like Figure 2 As shown, the operation sequence table may include: the total number of operator calls, the operator identifier of the first call, the operator identifier of the second call, ... The operator identifier of the ith call not only reflects the operation operator corresponding to the cryptographic service, but also reflects the calling order of each operation operator.

[0061] In some embodiments, when any operation operator is executed, the operation sequence detection module 121 can first determine whether the identifier of this operation operator matches the identifier of the operation operator in the target operation sequence table, and then determine whether the calling order of this operation operator matches the calling order of the operation operator in the target operation sequence table; if both the identifier and the calling order match, it is determined that there is no abnormality in this operation operator; if at least one of the identifier and the calling order does not match, it is determined that there is an abnormality in this operation operator. In this way, by means of a lookup table (target operation sequence table), it is detected whether the operator called each time is legal. In addition, the basis for hardware detection is solidified into a lookup table, which cannot be changed in the hardware circuit of the chip and has extremely high security.

[0062] In some implementations, the number of times the operation operator of the cryptographic service is called can be determined by an operator operation counter. When the number of times the operation operator of the cryptographic service is called does not reach the total number of operator calls in the target operation sequence table, it is prohibited to move the data in the operation result area to the output data area; if the number of times the operation operator of the cryptographic service is called does not reach the total number of operator calls in the target operation sequence table, a data moving instruction to move the data in the operation result area to the output data area is received, it is determined that someone is trying to steal the intermediate operation result at this time, an exception is reported, and all data in the security chip memory is cleared.

[0063] In some embodiments, the operation sequence table includes: the total number of operator calls; the operation sequence detection module 121 is used to determine that the current operation result is an intermediate operation result when the number of calls to the operation operator does not reach the total number of operator calls; when the number of calls to the operation operator reaches the total number of operator calls, determine that the current operation result is the final operation result.

[0064] To prevent others from reading the intermediate operation results, the number of times the operator is called can be counted, and the total number of operator calls can be preset. In this way, it is possible to determine whether the current operation result is an intermediate operation result or a final operation result based on the matching relationship between the number of operator calls and the total number of operator calls.

[0065] In some embodiments, the operation sequence table includes: operation operators that need to be detected when the corresponding cryptographic service is processed; the operation operators that need to be detected are operation operators that carry keys and / or operation operators whose keys can be reversely deduced.

[0066] In some implementations, the operation operators can be divided into operation operators that need to be detected and operation operators that do not need to be detected according to whether the operation operators carry keys and / or the keys can be reversed. In this way, the amount of data in the operation sequence table can be reduced, saving the hardware area of ​​the chip.

[0067] In some embodiments, the operation sequence table includes: the total number of times the operation results involved in the processing of the corresponding cryptographic service are transferred; the operation sequence detection module 121 is used to determine that the current operation result is an intermediate operation result when the number of times the operation result is transferred does not reach the total number of times; when the number of times the operation result is transferred reaches the total number of times, determine that the current operation result is the final operation result.

[0068] When the operation result of the operator needs to be transferred, in order to prevent others from reading the intermediate operation result, the number of transfers can also be counted. When the number of transfers reaches the total number of transfers in the operation sequence table, the current operation result is determined as the final operation result. That is, the total number of transfers of the corresponding cryptographic service is stored in the operation sequence table. When the number of transfers of the operation result of the cryptographic service reaches the total number of transfers, the current operation result is determined as the final operation result to allow the operation result to be output.

[0069] In some embodiments, Figure 4 As shown, the cryptographic service execution hardware 12 includes: an operator operation counter; the operator operation counter is used to count the number of times the operation operator is called; when the operation result of the operation operator needs to be transported, the number of times the operation result is transported is counted.

[0070] In some embodiments, the cryptographic service execution hardware 12 includes: a data storage area 141; the data storage area 141 includes: an input data area, a calculation result area and an output data area; the controller 11 is used to write the data to be processed into the input data area; the cryptographic service execution hardware 12 is used to write the calculation result of the data to be processed based on the operation operator corresponding to the scheduling instruction into the calculation result area; the calculation sequence detection module 121 is used to determine that the intermediate calculation result stored in the calculation result area is the final calculation result when the number of times the calculation result is transferred reaches the total number of times, or the number of times the operation operator is called reaches the total number of times; the calculation sequence detection module 121 is used to clear the data in the data storage area 141 when the operation operator is abnormal, or the number of times the calculation result is transferred does not reach the total number of times, or the number of times the operation operator is called does not reach the total number of times.

[0071] The data storage area 141 may be a memory of the security chip 10. For example, the data storage area 141 may be a direct memory access (DMA). The input data area is used to store data to be operated by an operator. The operation result area is used to store the operation result after the operator operation. The output result area is used to store the final operation result of the cryptographic service.

[0072] It should be noted that the calculation result area is not readable by the security chip 10, and the output data area is readable by the security chip 10. In this way, the intermediate calculation results cannot be read by the outside world, preventing the key from being leaked.

[0073] In some implementations, the operation operators can be divided into two categories based on their functions: one is the operation operator that calls various operation operators to perform operations, and the other is the transport operator that performs data transport. The operation result after each round of operator operation is stored in the operation result area. If it is transported to the input data area, then the operation result is the intermediate operation result; if it is transported to the output data area, then the operation result is the final operation result, that is, the operation of the cryptographic service is completed. For example, the operation result of the cryptographic service can be a completed encryption result, decryption result, signature result, signature verification result, etc., or it can be a collection of encryption results, decryption results, signature results, and signature verification results.

[0074] For example, the operation operators involved in a normal cryptographic service may be: calling the modular subtraction operator → calling the modular exponentiation operator → calling the point multiplication operator, or calling the modular exponentiation operator → calling the modular subtraction operator → calling the point multiplication operator, etc. The operation result after each operator operation is completed is stored in the operation result area. If the operator operation is required later, the operation result is moved to the input data area for the next operator operation. If the operator operation is not required later, and the number of times the operation result is moved reaches the total number of times, and the number of times the operation operator is called reaches the total number of times, the operation result is moved to the output data area. If at least one of the following three situations exists: in the first situation, the operator operation is abnormal; in the second situation, the number of times the operation result is moved does not reach the total number of times; in the third situation, the number of calls does not reach the total number of calls; then it is determined that the cryptographic service is abnormal, and the data in the data storage area is cleared at this time, and an abnormal interrupt is sent to the interrupt system of the security chip. The security chip must restart the cryptographic service execution hardware to start a new cryptographic service. If the security chip is attacked and attempts are made to steal the key in the cryptographic service execution hardware through an illegal operator sequence, it will be identified by the operation sequence detection module and the operation results will be automatically cleared, making the attacker's efforts futile.

[0075] In some embodiments, when the scheduling instruction is a cryptographic service selection instruction, the cryptographic service execution hardware 12 is used to respond to the cryptographic service selection instruction and determine a target operation sequence table corresponding to the cryptographic service to be processed based on the cryptographic service to be processed selected by the cryptographic service selection instruction;

[0076] In the case where the scheduling instruction is an enable instruction, the cryptographic service execution hardware 12 is used to respond to the enable instruction and enter a ready state;

[0077] In the case where the scheduling instruction is a first data transfer instruction, the cryptographic service execution hardware 12 is used to respond to the first data transfer instruction and transfer the data in the operation result area to the input data area;

[0078] In the case where the scheduling instruction is a second data transfer instruction, the cryptographic service execution hardware 12 is used to respond to the second data transfer instruction and transfer the data in the calculation result area to the output result area.

[0079] The scheduling instructions may include, but are not limited to: a cryptographic service selection instruction, an enable instruction, a first data transfer instruction, and a second data transfer instruction. Among them, the enable instruction is used to make the cryptographic service execution hardware 12 enter a ready state. The first data transfer instruction is used to transfer the data in the operation result area to the input data area. The second data transfer instruction is used to transfer the data in the operation result area to the output data area.

[0080] The present disclosure provides a method for processing a cryptographic service, which can be executed by a processor of a security chip 10. Figure 3 As shown, the method includes the following steps 301 to 302:

[0081] Step 301: The controller sends a scheduling instruction and data to be processed about a cryptographic service to be processed to the cryptographic service execution hardware.

[0082] Step 302: The cryptographic service execution hardware responds to the scheduling instruction and determines whether the scheduling instruction is abnormal based on a service lookup table; if the scheduling instruction is not abnormal, the data to be processed is processed based on the operation operator corresponding to the cryptographic service to be processed to obtain a final operation result, and outputs the final operation result.

[0083] For example, if the cryptographic service to be processed is an encryption service and the data to be processed is text data, the key of the encryption service is obtained; the text data is encrypted based on the operator sequence and key corresponding to the encryption service; after obtaining the final encryption result, the final encryption result is output.

[0084] In some embodiments, the specific implementation method of "determining whether the scheduling instruction is abnormal based on the service lookup table" in step 302 can be: based on the service lookup table, determining whether the scheduling instruction meets the preset conditions; the preset conditions include: the scheduling instruction needs to access the final calculation result and the operation operator corresponding to the scheduling instruction has no abnormalities; if the scheduling instruction meets the preset conditions, determining that the scheduling instruction has no abnormalities; if the scheduling instruction does not meet the preset conditions, determining that the scheduling instruction is abnormal.

[0085] During implementation, if a scheduling instruction is received, first determine whether the scheduling instruction is legal (abnormal) based on the service lookup table. Specifically, if the scheduling instruction is a read instruction for the calculation result, determine whether the calculation result to be read is the final calculation result based on the service lookup table. If the calculation result to be read is the final calculation result, the final calculation result is read from the output result area and returned to the controller. If the calculation result to be read is an intermediate calculation result, the scheduling instruction is determined to be an abnormal instruction, and it is believed that someone else wants to steal the data. The data in the cryptographic service instruction hardware needs to be cleared and the abnormality is reported.

[0086] In some implementations, the "processing the data to be processed based on the operation operator corresponding to the cryptographic service to be processed to obtain a final operation result, and outputting the operation result of the data to be processed" in step 302 can be performed through the following steps 3021 to 3025:

[0087] Step 3021: Process the data to be processed in the input data area based on the first operator in the operator sequence to obtain a first intermediate operation result, and write the first intermediate operation result into the operation result area.

[0088] In step 3022, in response to the first data transfer instruction, the first intermediate operation result in the operation result area is transferred to the input data area.

[0089] Step 3023: Process the first intermediate operation result in the input data area based on the second operation operator in the operation operator sequence to obtain a second intermediate operation result, and write the second intermediate operation result into the operation result area.

[0090] Step 3024, in response to the next first data transfer instruction, transfer the second intermediate operation result of the operation result area to the input data area, and continue the operator operation of the next operator in the operator sequence until the operator sequence is processed and the final operation result is obtained.

[0091] Step 3025, in response to the second data transfer instruction, transfer the final operation result of the operation result area to the output result area to output the final operation result; the scheduling instruction includes the operation operator sequence, the first data transfer instruction, and the second data transfer instruction.

[0092] In some embodiments, the cryptographic service processing method provided by the embodiments of the present disclosure further includes the following steps 303 to 304:

[0093] Step 303: The cryptographic service execution hardware determines a target operation sequence list corresponding to the cryptographic service to be processed from the plurality of operation sequence lists based on the identifier of the cryptographic service to be processed.

[0094] Step 304: The cryptographic service execution hardware detects the currently called operation operator and the calling order of the currently called operation operator based on the operation operators in the target operation sequence table and the calling order of each operation operator to determine whether the currently called operation operator is abnormal.

[0095] In addition, the cryptographic service processing method provided in the embodiment of the present disclosure further includes the following step 305:

[0096] Step 305: When the scheduling instruction needs to access the intermediate operation result, or the operation operator corresponding to the cryptographic service to be processed is abnormal, clear the data in the data storage area and report the abnormality; the data storage area includes: an input data area, a calculation result area, and an output data area.

[0097] It should be noted that when the scheduling instruction is abnormal and the operation operator is abnormal, the data in the data storage area is cleared to prevent the data from being stolen by the outside world and to improve the security of the data.

[0098] In the disclosed embodiment, the controller schedules the cryptographic service, and the cryptographic service execution hardware performs the cryptographic service calculation, which fully considers the design requirements and implementation costs of the security chip. This combination of software and hardware design reduces the chip area while maximizing the high security and high performance of the cryptographic service calculation. In addition, the cryptographic service execution hardware will output the calculation result only after the cryptographic service processing is completed, and the intermediate calculation result will not be output during the entire process, which further improves the security of the cryptographic service calculation.

[0099] The following describes the application of the security chip provided by the embodiments of the present disclosure in actual scenarios.

[0100] The software in the disclosed embodiment refers to the non-secure area in the security chip, and the non-secure area refers to the user program area that has no authority to obtain the key but can use the password service. The non-secure area is connected to the chip bus (corresponding to Figure 1 bus system in the cryptographic service execution hardware 12 (hardware security area, corresponding to Figure 1 In other words, the user sends a cryptographic service request to the security chip. The disclosed embodiment enables the user to safely use the cryptographic service provided by the security chip when the user cannot obtain the key of the security chip.

[0101] The hardware in the embodiments of the present disclosure refers to a hardware circuit implemented by RTL code programming, which is integrated on a security chip and can store keys and provide cryptographic operation services.

[0102] The disclosed embodiments fully consider the design requirements and implementation costs of cryptographic chips, and combine software and hardware in a design that reduces the chip area while ensuring high security and high performance of cryptographic operations.

[0103] 1. Hardware implements the top-level operator modules required by the PKE algorithm for modular exponentiation and point multiplication operations, which are dispatched by software to improve the performance and security of operations;

[0104] 2. The hardware provides private DMA function to realize the MOVE action, which can directly read and write operation data from the memory;

[0105] 3. The hardware uses a lookup table to solidify the operation sequence of various cryptographic algorithms, and monitors the behavior of the CPU bus accordingly to ensure that the cryptographic algorithm operates in the correct sequence to ensure security. At the same time, the lookup table can also be compressed to only monitor the operation sequence that may leak sensitive data; this has achieved the goal of further reducing chip area and wafer investment costs while ensuring security.

[0106] The technical solution of the embodiment of the present disclosure is as follows:

[0107] 1. Add an operation sequence detection module (use RTL code to design the circuit and integrate it into hardware implementation); the operation sequence detection module is used to monitor illegal CPU operations (for example, reading intermediate operation results).

[0108] 2. By adding a lookup table ( Figure 2 The operation sequence table shown in the figure is used to determine whether the operator operation (corresponding to the operator itself and the operation process of the operator) is legal. The lookup table is used to implement cryptographic services, and is a sequence of operation operators that call various cryptographic operators (corresponding to the above-mentioned operation operators) for the first category to perform operations; a normal cryptographic operation request may be to call the modular subtraction operator → modular exponentiation operator → point multiplication operator, or to call the modular exponentiation operator → modular subtraction operator → point multiplication operator, etc. For the set of operation sequences of the data transfer process in the memory of the second category of cryptographic algorithms, this set is a legal set; the operation result after each round of operator operation is stored in the operation result area, and then it is decided whether to transfer to the input data area or the output data area. If it is transferred to the input data area, then the operation result is an intermediate operation result; if it is transferred to the output data area, then the operation result is the final operation result, that is, the result of the completed cryptographic service operation. For example, it can be a completed encryption result, decryption result, signature result, signature verification structure, etc.

[0109] 3. The lookup table can be compressed to save chip area.

[0110] Compression principle 1: Cryptographic operators are divided into operator sequences that need to be monitored and operator sequences that do not need to be monitored, according to whether they carry keys or whether they can be reversed to deduce keys. In other words, operator sequences that do not need to be monitored are not edited into the lookup table.

[0111] Compression principle 2: When the operation result of the operator needs to be moved, the number of times the operation is moved is counted. When the count reaches the point where the operation result can be fully output, the operation result is allowed to be moved to the output data area. That is, the total number of times the corresponding cryptographic algorithm is moved is stored in the lookup table, and the operation result is allowed to be moved to the output data area only when the total number of times is reached.

[0112] The disclosed embodiments are applied to security chips, which can help the security chips realize high-security and low-cost cryptographic service execution hardware 12. As a slave, the cryptographic service execution hardware 12 is connected to the bus system of the security chip through a bus interface, and is scheduled and used by the security chip to provide cryptographic operation services for the security chip.

[0113] The operation sequence monitoring module is used to monitor whether the scheduling sequence of the chip bus system for the cryptographic service execution hardware 12 is legal. As long as it is a legal scheduling, it can ensure that the sensitive information of the cryptographic service execution hardware 12 is not leaked. Illegal scheduling sequences will be identified by the monitoring module. The monitoring module will automatically clear the sensitive data in the cryptographic algorithm memory to ensure that sensitive data is not leaked, and report error interrupts to the chip.

[0114] like Figure 1 and Figure 4 As shown, the password service process is as follows:

[0115] ①, when the security chip 10 needs the cryptographic service execution hardware 12 to provide cryptographic services, it sends the required services to the operation sequence detection module 121, and the operation sequence detection module 121 selects the corresponding lookup table (such as Figure 5 ① and ② in the figure are used to monitor the operation sequence. Then, an enable instruction is sent to the cryptographic service execution hardware 12, and the cryptographic service execution hardware 12 is ready to respond to the security chip 10 calling the operator to perform cryptographic operations (corresponding to the above-mentioned operator operations). At the same time, the operation sequence detection module 121 will also automatically start to monitor the cryptographic operation sequence sent from the chip bus interface to see if it meets the sequence requirements of the selected lookup table (such as Figure 5 : Operation sequence comparison).

[0116] ② The security chip 10 writes the data that needs to be cryptographically calculated into the input data area of ​​the data storage area 141 through the bus interface.

[0117] ③. The security chip 10 calls the required operator through the bus interface to perform cryptographic operations (corresponding to the above-mentioned operator operations).

[0118] ④. The operator will call the password and perform operations on the data in the input data area. After the operation is completed, the operation result will be automatically written into the operation result area. The chip bus system cannot read the data in the operation result area (through hardware memory management, the chip bus is prohibited from accessing the operation result area) to ensure that the password called by the operator will not be transmitted to the outside of the cryptographic service execution hardware 12 through the bus interface. Because only one operator operation is performed, it is easy to deduce the password called by the operator through the known input data and operation results, and then crack the cryptographic service execution hardware 12.

[0119] ⑤. The security chip 10 sends a data transfer DMA command through the bus interface, and the cryptographic service execution hardware 12 automatically transfers the data in the calculation result area to the input data area for the next operator calculation to perform iterative calculations. In addition, at this time, the security chip can also write the chip's input data to the input data area according to the cryptographic service requirements, so that the next operator calculation can calculate the new data and the last calculation data.

[0120] ⑥. The security chip 10 repeats ②③④⑤ according to the selected cryptographic service operation sequence until all sequences are executed, and then sends a data transfer DMA command to transfer the operation result to the output data area.

[0121] ⑦. The output data area is readable by the security chip 10. The result of the cryptographic service operation can be transmitted from the output data area to the outside of the cryptographic service execution hardware 12 through the chip bus. A complete cryptographic operation is completed. The chip bus can send a command to shut down the cryptographic service execution hardware 12.

[0122] ⑧⑨, the operation sequence detection module 121 will monitor whether the operation sequence of ②③④⑤⑥⑦ conforms to the established operation sequence according to the cryptographic service lookup table selected by ①. If it conforms, the cryptographic service can be completed normally; if an illegal operation that does not conform is found, a memory clearing operation is issued to clear the data in the cryptographic algorithm memory (such as ⑨), and an abnormal interrupt is sent to the interrupt system of the security chip (such as ⑧). The security chip 10 must restart the cryptographic service execution hardware 12 to start a new cryptographic service. If the security chip 10 is attacked and attempts to steal the password in the cryptographic service execution hardware 12 through an illegal operation sequence, it will be identified by the operation sequence detection module 121, and the operation result will be automatically cleared, making the attacker's efforts in vain.

[0123] ⑩、The operator operation counter is based on the total number of operator calls in the lookup table (the structure of the lookup table is shown in Figure 2 ), the cumulative count of the number of calls to the operator by the bus interface. When the number of calls does not reach the total number of operator calls in the lookup table, the data in the operation result area is moved to the output data area through the bus interface. When an attempt is made to steal the intermediate operation result, the operator operation counter reports an error interrupt⑧ and automatically clears the operation result in the cryptographic algorithm memory⑨.

[0124] like Figure 5 As shown, the specific scheme for determining whether the operation sequence is legal is as follows:

[0125] ①. The chip bus sends a cryptographic service selection instruction and an enable command to the operation sequence detection module 121.

[0126] ②③. The operation sequence detection module 121 selects the corresponding lookup table according to the cryptographic service selected by the chip and performs operation sequence comparison monitoring.

[0127] ④. If an illegal sequence is found, a memory clearing operation is sent to clear the password algorithm memory.

[0128] ⑤. If an illegal sequence is found, an abnormal interrupt signal is sent to the chip interrupt system.

[0129] like Figure 2 As shown in Figure 1, the sequence monitoring lookup table consists of the total number of operator calls required to implement a complete cryptographic service and the operator ID of each call. The hardware monitoring module will monitor whether each operator call is legal according to the call sequence specified by the lookup table.

[0130] like Figure 6 As shown, the password service processing flow includes the following steps:

[0131] Step 601: When the security chip requests a cryptographic service, it sends a scheduling instruction and data to the cryptographic service execution hardware through the chip bus.

[0132] Step 602: The security chip sends the cryptographic service to be executed to the operation sequence detection module, and enables the cryptographic service execution hardware (monitoring is also started).

[0133] Step 603: The security chip writes the data to be calculated into the input data area through the chip bus interface.

[0134] Step 604: The security chip sends a command to call the cryptographic operator to perform cryptographic operations.

[0135] Step 605: The cryptographic operator uses the input data and the key to perform an operation, and the operation result is automatically written into the operation result area.

[0136] Step 606: The chip bus sends a command, and the cryptographic service execution hardware moves the data in the calculation result area to the input data area and inputs new data.

[0137] Step 607: The chip bus calls the next operator to perform operations on the new input data and the result of the previous operation, and the result is automatically written into the operation result area.

[0138] Step 608: Repeat steps 603 to 607 until the operator scheduling required for the cryptographic service is completed. The chip bus sends a command to move the operation result to the output data area and then read it out.

[0139] The protection point of the disclosed embodiment is to provide a design method and circuit architecture for a complex cryptographic algorithm chip with software and hardware collaboration, high security and low cost. In terms of hardware, it is sufficient to implement the operator module and the data handling module, and the software schedules the operation operator combination to achieve the goal of implementing the complex cryptographic algorithm. During this period, the hardware monitors the software operation sequence by looking up the table to achieve high security.

[0140] The disclosed embodiments can achieve at least the following technical effects: First, the chip system design is carried out by software and hardware in coordination, which can ensure area optimization, high security and other effects. Second, the basis of hardware monitoring is solidified into a lookup table and implemented in the hardware circuit during chip manufacturing, which cannot be modified and has very high security.

[0141] It should be noted that the following methods for improving the solution provided by the embodiments of the present disclosure all fall within the scope of protection of the embodiments of the present disclosure:

[0142] 1. Increase the types and number of cryptographic operators to implement other symmetric or asymmetric cryptographic algorithms.

[0143] 2. Increase the number of cryptographic algorithm memories and modify the partitions and space of the cryptographic algorithm memories.

[0144] 3. Modify the lookup table to achieve more or less secure monitoring.

[0145] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned steps / processes does not mean the order of execution. The execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0146] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0147] In the several embodiments provided in the present disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored, or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0148] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0149] In addition, all functional units in the embodiments of the present disclosure may be integrated into one processing unit, or each unit may be separately configured as a unit, or two or more units may be integrated into one unit; the above-mentioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0150] A person skilled in the art can understand that: all or part of the steps of implementing the above method embodiment can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps of the above method embodiment; and the aforementioned storage medium includes: various media that can store program codes, such as mobile storage devices, read-only memories (ROM), magnetic disks or optical disks.

[0151] Alternatively, if the above-mentioned integrated unit of the present disclosure is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present disclosure can essentially or in other words, the part that contributes to the relevant technology can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in each embodiment of the present disclosure. The aforementioned storage medium includes: various media that can store program codes, such as mobile storage devices, ROMs, magnetic disks, or optical disks.

[0152] The above description is only an implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Claims

1. A security chip, characterized in that: The security chip includes: a controller and cryptographic service execution hardware; The controller is connected to the cryptographic service execution hardware via a bus system; The controller is used to directly send scheduling instructions and data to be processed about the cryptographic service to be processed to the cryptographic service execution hardware; The cryptographic service execution hardware is used to respond to the scheduling instruction and determine whether the scheduling instruction is abnormal based on the service lookup table; if the scheduling instruction is not abnormal, the to-be-processed data is processed based on the operation operator corresponding to the to-be-processed cryptographic service to obtain a final operation result, and output the final operation result; the intermediate operation result of processing the to-be-processed data is unreadable by the security chip; The service lookup table includes: the total number of times the operation results involved in the processing of the corresponding cryptographic service are transferred; The cryptographic service execution hardware is further used to determine that the current operation result is an intermediate operation result when the number of times the operation result of the data to be processed is transferred does not reach the total number of times; and determine that the current operation result is a final operation result when the number of times the operation result of the data to be processed is transferred reaches the total number of times; The cryptographic service execution hardware includes: an operator operation counter; the operator operation counter is used to count the number of times the operation result is moved when the operation result of the operation operator needs to be moved.

2. The security chip according to claim 1, characterized in that: The cryptographic service execution hardware includes: an operation sequence detection module; The operation sequence detection module is used to determine whether the scheduling instruction is abnormal based on a service lookup table; the service lookup table includes: an operation sequence table of at least one cryptographic service; The operation sequence detection module is used to determine, based on the identifier of the cryptographic service to be processed, a target operation sequence list corresponding to the cryptographic service to be processed from at least one of the operation sequence lists; based on the target operation sequence list, determine whether the operation operator corresponding to the cryptographic service to be processed is abnormal.

3. The security chip according to claim 2, characterized in that: The operation sequence table includes: the operation operators involved in the processing of the corresponding cryptographic service and the calling order of each operation operator; The operation sequence detection module is used to detect the currently called operation operator and the calling order of the currently called operation operator based on the operation operators in the target operation sequence table and the calling order of each operation operator, so as to determine whether the currently called operation operator is abnormal.

4. The security chip according to claim 3, characterized in that: The operation sequence table includes: the total number of operator calls; The operation sequence detection module is used to determine that the current operation result is an intermediate operation result when the number of calls to the operation operator does not reach the total number of calls to the operator; and to determine that the current operation result is a final operation result when the number of calls to the operation operator reaches the total number of calls to the operator.

5. The security chip according to claim 2, characterized in that: The operation sequence table includes: operation operators that need to be detected when the corresponding cryptographic service is processed; the operation operators that need to be detected are operation operators that carry keys and / or operation operators whose keys can be reversely deduced.

6. The security chip according to claim 4, characterized in that: The operator operation counter is used to count the number of times the operation operator is called.

7. The security chip according to any one of claims 2 to 5, characterized in that: The cryptographic service execution hardware includes: a data storage area; the data storage area includes: an input data area, a calculation result area and an output data area; The controller is used to write the data to be processed into the input data area; The cryptographic service execution hardware is used to write the operation result of processing the to-be-processed data based on the operation operator corresponding to the scheduling instruction into the operation result area; The operation sequence detection module is used to determine that the intermediate operation result stored in the operation result area is the final operation result and allow it to be transferred to the output data area when the number of transfers of the operation result reaches the total number of transfers or the number of calls of the operation operator reaches the total number of calls; The operation sequence detection module is used to clear the data in the data storage area when the operation operator is abnormal, the number of times the operation result is transferred does not reach the total number of times, or the number of times the operation operator is called does not reach the total number of times.

8. The security chip according to any one of claims 1 to 5, characterized in that: In the case where the scheduling instruction is a cryptographic service selection instruction, the cryptographic service execution hardware is used to respond to the cryptographic service selection instruction and determine a target operation sequence table corresponding to the cryptographic service to be processed based on the cryptographic service to be processed selected by the cryptographic service selection instruction; In the case where the scheduling instruction is an enable instruction, the cryptographic service execution hardware is used to respond to the enable instruction and enter a ready state; In the case where the scheduling instruction is a first data transfer instruction, the cryptographic service execution hardware is used to respond to the first data transfer instruction and transfer the data in the operation result area to the input data area; In the case where the scheduling instruction is a second data transfer instruction, the cryptographic service execution hardware is used to respond to the second data transfer instruction and transfer the data in the calculation result area to the output result area.

9. A cryptographic service processing method, characterized in that: The cryptographic service processing method comprises: The controller directly sends scheduling instructions and data to be processed about the cryptographic service to be processed to the cryptographic service execution hardware through the bus system; The cryptographic service execution hardware responds to the scheduling instruction, and determines whether the scheduling instruction is abnormal based on the service lookup table; if the scheduling instruction is not abnormal, the to-be-processed data is processed based on the operation operator corresponding to the to-be-processed cryptographic service to obtain a final operation result, and outputs the final operation result; the intermediate operation result of processing the to-be-processed data is unreadable by the security chip; The service lookup table includes: the total number of transfers of the operation results involved in the processing of the corresponding cryptographic service; when the number of transfers of the operation results of the data to be processed by the cryptographic service execution hardware does not reach the total number of transfers, the current operation result is determined to be an intermediate operation result; when the number of transfers of the operation results of the data to be processed reaches the total number of transfers, the current operation result is determined to be a final operation result; The cryptographic service execution hardware includes: an operator operation counter; the operator operation counter is used to count the number of times the operation result is moved when the operation result of the operation operator needs to be moved.

10. The cryptographic service processing method according to claim 9, characterized in that: The determining whether the scheduling instruction is abnormal based on the service lookup table includes: Based on the service lookup table, determining whether the scheduling instruction meets preset conditions; the preset conditions include: the scheduling instruction needs to access the final operation result, and the operation operator corresponding to the scheduling instruction has no abnormality; When the scheduling instruction satisfies the preset condition, it is determined that the scheduling instruction has no abnormality.

11. The cryptographic service processing method according to claim 9, characterized in that: The processing of the data to be processed based on the operation operator corresponding to the cryptographic service to be processed to obtain a final operation result, and outputting the final operation result includes: Processing the data to be processed in the input data area based on the first operation operator in the operation operator sequence to obtain a first intermediate operation result, and writing the first intermediate operation result into the operation result area; In response to a first data transfer instruction, transfer the first intermediate operation result of the operation result area to the input data area; Processing the first intermediate operation result in the input data area based on the second operation operator in the operation operator sequence to obtain a second intermediate operation result, and writing the second intermediate operation result into the operation result area; In response to the next first data transfer instruction, the second intermediate operation result of the operation result area is transferred to the input data area, and the operator operation of the next operation operator in the operation operator sequence is continued until the operation operator sequence is processed and the final operation result is obtained; In response to a second data transfer instruction, the final operation result of the operation result area is transferred to the output result area to output the final operation result; the scheduling instruction includes the operator sequence, the first data transfer instruction, and the second data transfer instruction.

12. The cryptographic service processing method according to claim 9, characterized in that: The service lookup table includes: an operation sequence table of at least one cryptographic service; the cryptographic service processing method also includes: The cryptographic service execution hardware determines, based on the identifier of the cryptographic service to be processed, a target operation sequence list corresponding to the cryptographic service to be processed from the plurality of operation sequence lists; Based on the operators in the target operation sequence table and the calling order of each operator, the currently called operator and the calling order of the currently called operator are detected to determine whether the currently called operator is abnormal.

13. The cryptographic service processing method according to claim 10, characterized in that: The cryptographic service processing method further includes: When the scheduling instruction wants to access the intermediate operation result, or the operation operator corresponding to the cryptographic service to be processed is abnormal, the data in the data storage area is cleared and the abnormality is reported; the data storage area includes: an input data area, a calculation result area and an output data area.

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