Ethernet switch chip flow and delay test verification method
Through the routine traffic and delayed monitoring components in the Ethernet exchange chip verification platform, the problem of high resource consumption and efficiency caused by waveform analysis in the existing technology, and achieved more efficient and accurate traffic and delay test verification verification Essence
Patent Information
- Application Number
- CN202411406899.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-10
- Publication Date
- 2025-01-28
AI Technical Summary
During the verification process of Ethernet switch chips, the prior art relies on waveform analysis, resulting in high resource consumption and low efficiency, especially in the regression stage.
During the normalization of traffic and delay monitoring components of the platform environment, the clock cycle and flow calculation interval are configured, the monitoring flow and delay, and dynamically adjust the calculation interval to improve the accuracy.
Through embedded flow and delayed monitoring components, the accuracy and efficiency of flow calculation are improved, artificial intervention is reduced, the abnormal points can be quickly located, and the test results are directly displayed through the chart.
Smart Images
Figure CN119383101A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of Ethernet switching chips, and in particular to a method for testing and verifying the flow and delay of an Ethernet switching chip. Background Art
[0002] During the verification process of Ethernet switching chips, verifiers often calculate the output traffic bandwidth of modules or subsystems through waveform analysis. The waveform analysis method requires simulation to generate waveform files. On the one hand, turning on the waveform control option will consume simulation resources. On the other hand, waveform analysis is heavily dependent on manual participation and is inefficient. The above shortcomings are particularly obvious in the regression stage.
[0003] To improve efficiency, the verifier can write a traffic monitoring module, simulate the above-mentioned waveform analysis method, instantiate the monitoring module to the top level of the platform, and print the traffic calculation results to the simulation log at regular intervals. After the simulation, the verifier checks the simulation log to confirm whether the traffic meets expectations. This method eliminates the need for the verifier to view waveforms and perform manual calculations, but still requires attention to each traffic calculation result. For delay measurement, the verifier often also determines it through waveform analysis, which also has the disadvantage of inefficiency.
[0004] Therefore, it is necessary to provide an Ethernet switch chip traffic and delay test verification method to solve the above technical problems. Summary of the invention
[0005] The present invention provides a method for testing and verifying the flow and delay of an Ethernet switching chip, which solves the problem that in this way, verification personnel no longer need to view waveforms and perform manual calculations, but still need to pay attention to the calculation results of each flow. For delay measurement, verification personnel often also determine it through waveform analysis, which also has the disadvantage of inefficiency.
[0006] In order to solve the above technical problems, the present invention provides an Ethernet switch chip flow and delay test verification method, comprising the following steps: S1: Instantiate traffic and latency monitoring components in the platform environment; S2: Specify parameters based on the flow number of each flow, call the interface in technical solution 2-5 during the configuration phase of the test case, and configure the clock cycle and traffic calculation interval parameters; S3: In the monitoring component of the verification platform, the flow number is calculated by using the port number, physical address, virtual LAN identifier and other information. When valid data is monitored on the input and output interfaces, the interface in technical solution 6-7 is called to accumulate the number of valid data bits and mark the timestamp of the input at the end of the frame and the timestamp of the output frame head; S4: The flow and delay monitoring component calculates the flow and determines whether it is within the allowable fluctuation range. If it exceeds the range, an alarm message is printed to the simulation log; S5: The traffic and delay monitoring component calculates the delay and writes it based on the recorded input-output timestamps.
[0007] Preferably, the flow and delay monitoring component is named flow_traffic_delay_cal, and provides various interfaces to the outside, such as configuring the clock cycle and configuring the flow calculation interval.
[0008] Preferably, the clock cycle provides an external configuration interface, cfg_clk_freq, to transmit the clock frequency in megahertz MHz.
[0009] Preferably, the traffic calculation interval provides an external configuration interface cfg_cal_interval.
[0010] Preferably, the calculation interval provides a dynamic adjustment interface, cfg_cal_interval_dynamic_enable. After the dynamic adjustment of the calculation interval is enabled, if two consecutive flow calculations are both 0, an attempt is made to adjust the calculation interval.
[0011] Preferably, the traffic fluctuation range configuration interface is provided, cfg_traffic_variation_range.
[0012] Preferably, the externally provided data volume accumulation interface, add_valid_data_by_octet, is called when valid data is received at the interface.
[0013] Preferably, the timestamp enabling interface, rec_curr_timestamp, is provided externally, and the component marks the timestamp of the corresponding stream according to the frame start mark frame_sop, the frame end mark frame_eop and the outgoing mark.
[0014] Preferably, the flow rate is calculated for each flow, and each flow rate calculation result is compared with a set fluctuation range, and an alarm message is printed when the flow rate is higher or lower than the expected flow rate.
[0015] Preferably, the data packets of each flow are subjected to input-output order-preserving monitoring, and the packet delay (storage-forwarding delay) is calculated; based on the order-preserving monitoring, the packet loss rate can be counted, an initialization interface can be provided, and the default values of parameters such as the clock cycle, flow calculation interval, and allowed flow fluctuation range can be configured.
[0016] Compared with the related art, the Ethernet switch chip flow and delay test verification method provided by the present invention has the following beneficial effects: The present invention provides an Ethernet switching chip flow and delay test verification method, which embeds flow and delay monitoring components in the monitoring components of the original verification platform, configures clock cycles and flow calculation intervals to monitor flow and delay, and dynamically adjusts the flow calculation interval to improve the accuracy of flow calculation; by setting the expected flow allowable fluctuation range, when the calculated flow is higher or lower than the expected flow, alarm information is printed, so that verification personnel can quickly locate abnormal points in a targeted manner; by extracting flow and delay information through scripts and drawing corresponding charts, the test results are more intuitively displayed. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 A schematic diagram of the use of components of an Ethernet switch chip flow and delay test verification method provided by the present invention; Figure 2 A schematic diagram of dynamically adjusting flow calculation intervals for an Ethernet switch chip flow and delay test verification method provided by the present invention. DETAILED DESCRIPTION
[0018] The present invention will be further described below in conjunction with the accompanying drawings and implementation modes.
[0019] Please refer to Figure 1 and Figure 2 ,in, Figure 1 A schematic diagram of the use of components of an Ethernet switch chip flow and delay test verification method provided by the present invention; Figure 2 A schematic diagram of dynamically adjusting the flow calculation interval of an Ethernet switch chip flow and delay test verification method provided by the present invention. An Ethernet switch chip flow and delay test verification method includes the following steps: S1: Instantiate traffic and latency monitoring components in the platform environment; S2: Specify parameters based on the flow number of each flow, call the interface in technical solution 2-5 during the configuration phase of the test case, and configure the clock cycle and traffic calculation interval parameters; S3: In the monitoring component of the verification platform, the flow number is calculated by using the port number, physical address, virtual LAN identifier and other information. When valid data is monitored on the input and output interfaces, the interface in technical solution 6-7 is called to accumulate the number of valid data bits and mark the timestamp of the input at the end of the frame and the timestamp of the output frame head; S4: The flow and delay monitoring component calculates the flow and determines whether it is within the allowable fluctuation range. If it exceeds the range, an alarm message is printed to the simulation log; S5: The traffic and delay monitoring component calculates the delay and writes it based on the recorded input-output timestamps.
[0020] The flow and delay monitoring component, named flow_traffic_delay_cal, provides various interfaces to the outside, such as configuring the clock cycle and configuring the flow calculation interval.
[0021] The clock cycle provides an external configuration interface, cfg_clk_freq, which transmits the clock frequency in megahertz MHz.
[0022] The traffic calculation interval provides a configuration interface cfg_cal_interval to the outside.
[0023] The calculation interval provides a dynamic adjustment interface, cfg_cal_interval_dynamic_enable. After the dynamic adjustment of the calculation interval is enabled, if two consecutive flow calculations are both 0, the calculation interval is tried to be adjusted.
[0024] The traffic fluctuation range configuration interface is provided, cfg_traffic_variation_range.
[0025] The externally provided data volume accumulation interface, add_valid_data_by_octet, is called when valid data is received at the interface.
[0026] The timestamp enabling interface, rec_curr_timestamp, is provided externally, and the component marks the timestamp of the corresponding stream according to the frame start mark frame_sop, the frame end mark frame_eop and the outgoing mark.
[0027] When calculating the flow rate, each flow is calculated, and each flow calculation result is compared with the set fluctuation range, and an alarm message is printed when the flow rate is higher or lower than the expected flow rate.
[0028] The described method performs input-output order-keeping monitoring on the data packets of each flow, and calculates the packet delay (storage-forwarding delay); based on the order-keeping monitoring, the packet loss rate can be counted, an initialization interface is provided, and the default values of parameters such as the clock cycle, flow calculation interval, and allowed flow fluctuation range are configured.
[0029] Provides a clock cycle configuration interface, cfg_clk_freq (int clk_freq), to transmit the clock frequency in megahertz (MHz).
[0030] Provides a flow calculation interval configuration interface, cfg_cal_interval(int flow_id, int cal_interval).
[0031] import java.util.HashMap; import java.util.Map; public class IntervalConfigurator { Private Map<Integer, Integer> intervalMap = new HashMap<>(); public void cfg_cal_interval(int flow_id, int cal_interval) { intervalMap.put(flow_id, cal_interval); } public int getCalculationIntervalForFlow(int flow_id) { return intervalMap.getOrDefault(flow_id, 0); } public static void main(String[] args) { IntervalConfigurator configurator = new IntervalConfigurator(); configurator.cfg_cal_interval(1, 10); configurator.cfg_cal_interval(2, 20); System.out.println("Flow 1 interval: " + configurator.getCalculationIntervalForFlow(1)); System.out.println("Flow 2 interval: " + configurator.getCalculationIntervalForFlow(2)); } } The dynamic adjustment calculation interval enable interface, cfg_cal_interval_dynamic_enable (intflow_id, bit enable), is provided to the outside. After the dynamic adjustment calculation interval is enabled, if two consecutive flow calculations are both 0, the calculation interval is tried to be adjusted.
[0032] Here is a sample code that implements the interface using Python: class DynamicIntervalConfigurator: def __init__(self): self.flow_config = {} def cfg_cal_interval_dynamic_enable(self, flow_id, enable): self.flow_config[flow_id] = {'enable': bool(enable), 'last_two_calculations': [0, 0]} def check_and_adjust_interval(self, flow_id): config = self.flow_config.get(flow_id) if config and config['enable'] and config['last_two_calculations'] == [0, 0]: # You can add the actual interval adjustment logic here print(f "Adjusting interval for flow {flow_id}") def update_calculation(self, flow_id, value): config = self.flow_config.get(flow_id) if config: config['last_two_calculations'].pop(0) config['last_two_calculations'].append(value) self.check_and_adjust_interval(flow_id) # Create an instance and perform operations configurator = DynamicIntervalConfigurator() configurator.cfg_cal_interval_dynamic_enable(1, 1) configurator.cfg_cal_interval_dynamic_enable(2,0) configurator.update_calculation(1, 5) configurator.update_calculation(1,0) configurator.update_calculation(1,0) Provides an interface for configuring the allowed traffic fluctuation range, cfg_traffic_variation_range (intflow_id, int cfg_range).
[0033] Example code to implement this interface using Python: class FlowRateConfigurer: def __init__(self): self.flow_rate_map = {} def cfg_traffic_variation_range(self, flow_id, cfg_range): self.flow_rate_map[flow_id] = cfg_range def get_flow_rate(self, flow_id): return self.flow_rate_map.get(flow_id, 0) # Create an instance and perform operations configurer = FlowRateConfigurer() configurer.cfg_traffic_variation_range(1, 100) configurer.cfg_traffic_variation_range(2, 200) print("Flow 1 rate:", configurer.get_flow_rate(1)) print("Flow 2 rate:", configurer.get_flow_rate(2)) The following is a sample code for using Java to implement the interface for configuring the allowed traffic fluctuation range: import java.util.HashMap; import java.util.Map; public class FlowRateConfigurator { Private Map<Integer, Integer> flowRateMap = new HashMap<>(); public void cfg_traffic_variation_range(int flow_id, int cfg_range) { flowRateMap.put(flow_id, cfg_range); } public int getFlowRate(int flow_id) { return flowRateMap.getOrDefault(flow_id, 0); } public static void main(String[] args) { FlowRateConfigurator configurator = new FlowRateConfigurator(); configurator.cfg_traffic_variation_range(1, 100); configurator.cfg_traffic_variation_range(2, 200); System.out.println("Flow 1 rate: " + configurator.getFlowRate(1)); System.out.println("Flow 2 rate: " + configurator.getFlowRate(2)); } } In the above code, a class named FlowRateConfigurator is defined, which provides a cfg_traffic_variation_range method for configuring the allowed fluctuation range of traffic. This method accepts two parameters: flow_id represents the ID of the traffic, and cfg_range represents the allowed fluctuation range of the traffic.
[0034] The flowRateMap is used to store the fluctuation ranges corresponding to different flow IDs, and the getFlowRate method is used to obtain the fluctuation range of the specified flow ID.
[0035] In the main method, a FlowRateConfigurator object is created, and the flow fluctuation range is configured and obtained.
[0036] The following is a sample code for using Java to implement the interface for configuring the allowed traffic fluctuation range: import java.util.HashMap; import java.util.Map; public class FlowRateConfigurator { Private Map<Integer, Integer> flowRateMap = new HashMap<>(); public void cfg_traffic_variation_range(int flow_id, int cfg_range) { flowRateMap.put(flow_id, cfg_range); } public int getFlowRate(int flow_id) { return flowRateMap.getOrDefault(flow_id, 0); } public static void main(String[] args) { FlowRateConfigurator configurator = new FlowRateConfigurator(); configurator.cfg_traffic_variation_range(1, 100); configurator.cfg_traffic_variation_range(2, 200); System.out.println(“Flow 1 rate: ” + configurator.getFlowRate(1)); System.out.println("Flow 2 rate: " + configurator.getFlowRate(2)); } } In the above code, a class named FlowRateConfigurator is defined, which provides a cfg_traffic_variation_range method for configuring the allowed fluctuation range of traffic. This method accepts two parameters: flow_id represents the ID of the traffic, and cfg_range represents the allowed fluctuation range of the traffic.
[0037] The flowRateMap is used to store the fluctuation ranges corresponding to different flow IDs. The getFlowRate method is used to obtain the fluctuation range of the specified flow ID.
[0038] In the main method, a FlowRateConfigurator object is created, and the flow fluctuation range is configured and obtained.
[0039] Provides a data accumulation interface, add_valid_data_by_octet(int flow_id, intvalid_octes), which is called when valid data is received on the interface.
[0040] The following is a sample code that implements this interface using Java: public class DataAccumulator { Private Map<Integer,Integer> flowDataMap = new HashMap< >(); public void addValidDataByOctet(int flow_id, int valid_octes) { if (flowDataMap.containsKey(flow_id)) { flowDataMap.put(flow_id, flowDataMap.get(flow_id) + valid_octes); } else { flowDataMap.put(flow_id, valid_octes); } } public int getAccumulatedDataForFlow(int flow_id) { return flowDataMap.getOrDefault(flow_id, 0); } } Provides a timestamp enable interface, rec_curr_timestamp(int flow_id, bit frame_sop, bit frame_eop, bit egress_flag), and the component marks the timestamp of the corresponding flow according to the frame start mark (frame_sop), frame end mark (frame_eop) and egress mark.
[0041] You can use conditional judgment to determine whether to mark the timestamp. When the frame start mark, frame end mark, and outbound mark are all true, use the current_timestamp function to get the current timestamp and return it.
[0042] In MySQL, you can use the following code to provide a timestamp enable interface to the outside world: CREATE FUNCTION rec_curr_timestamp(flow_id INT, frame_sop BIT, frame_eop BIT, egress_flag BIT) RETURNS TIMESTAMP DETERMINISTIC BEGIN IF frame_sop = 1 AND frame_eop = 1 AND egress_flag = 1 THEN RETURN CURRENT_TIMESTAMP; ELSE RETURN NULL; END IF; END; In the above code, a function named rec_curr_timestamp is defined, which accepts four parameters: flow_id (flow ID), frame_sop (frame start mark), frame_eop (frame end mark) and egress_flag (egress flag). The function uses the IF statement to determine whether the frame start mark, frame end mark and egress flag are all true. If so, the CURRENT_TIMESTAMP function is used to obtain the current timestamp and return it, otherwise it returns NULL.
[0043] The flow rate of each flow is calculated internally, and each flow calculation result is compared with the set fluctuation range. When the flow rate is higher or lower than the expected flow rate, an alarm message is printed.
[0044] Internally, the input-output order-keeping monitoring is performed on the data packets of each flow, and the packet delay (store-and-forward delay) is calculated; the packet loss rate can be counted based on the order-keeping monitoring.
[0045] Provides an initialization interface to configure the default values of parameters such as clock cycle, traffic calculation interval, and allowed traffic fluctuation range.
[0046] The working principle of the Ethernet switch chip flow and delay test verification method provided by the present invention is as follows: When working, first instantiate the flow and delay monitoring component in the platform environment; specify parameters based on the flow number (flow_id) of each flow, call the interface in technical solution 2-5 in the configuration stage of the test case, and configure parameters such as clock cycle and flow calculation interval; calculate the flow number (flow_id) through the port number, physical address, virtual LAN identifier and other information in the monitoring component of the verification platform. When valid data is monitored on the input and output interfaces, call the interface in technical solution 6-7 to accumulate the number of valid data bits and mark the timestamp of the input at the end of the frame and the timestamp of the output frame head; the flow and delay monitoring component calculates the flow and determines whether it is within the allowable fluctuation range. If it exceeds the range, print the alarm information to the simulation log.
[0047] The traffic and delay monitoring component calculates and writes the delay based on the recorded input-output timestamps.
[0048] Compared with the related art, the Ethernet switch chip flow and delay test verification method provided by the present invention has the following beneficial effects: The present invention provides an Ethernet switching chip flow and delay test verification method, which embeds flow and delay monitoring components in the monitoring components of the original verification platform, configures clock cycles and flow calculation intervals to monitor flow and delay, and dynamically adjusts the flow calculation interval to improve the accuracy of flow calculation; by setting the expected flow allowable fluctuation range, when the calculated flow is higher or lower than the expected flow, alarm information is printed, so that verification personnel can quickly locate abnormal points in a targeted manner; by extracting flow and delay information through scripts and drawing corresponding charts, the test results are more intuitively displayed.
[0049] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.
Claims
1. A method for verifying the flow and delay test of an Ethernet switching chip, characterized in that: The following steps are involved: S1: Instantiate traffic and latency monitoring components in the platform environment; S2: Specify parameters based on the flow number of each flow, call the interface in technical solution 2-5 during the configuration phase of the test case, and configure the clock cycle and traffic calculation interval parameters; S3: In the monitoring component of the verification platform, the flow number is calculated by using the port number, physical address, virtual LAN identifier and other information. When valid data is monitored on the input and output interfaces, the interface in technical solution 6-7 is called to accumulate the number of valid data bits and mark the timestamp of the input at the end of the frame and the timestamp of the output frame head; S4: The flow and delay monitoring component calculates the flow and determines whether it is within the allowable fluctuation range. If it exceeds the range, an alarm message is printed to the simulation log; S5: The traffic and delay monitoring component calculates the delay and writes it based on the recorded input-output timestamps.
2. The Ethernet switch chip flow and delay test verification method according to claim 1 is characterized in that: The flow and delay monitoring component, named flow_traffic_delay_cal, provides various interfaces to the outside, such as configuring the clock cycle and configuring the flow calculation interval.
3. The Ethernet switch chip flow and delay test verification method according to claim 1 is characterized in that: The clock cycle provides an external configuration interface, cfg_clk_freq, which transmits the clock frequency in megahertz MHz.
4. The Ethernet switch chip flow and delay test verification method according to claim 1 is characterized in that: The traffic calculation interval provides a configuration interface cfg_cal_interval to the outside.
5. The Ethernet switch chip flow and delay test verification method according to claim 1 is characterized in that: The calculation interval provides a dynamic adjustment interface, cfg_cal_interval_dynamic_enable. After the dynamic adjustment of the calculation interval is enabled, if two consecutive flow calculations are both 0, the calculation interval is tried to be adjusted.
6. The Ethernet switch chip flow and delay test verification method according to claim 2 is characterized in that: The traffic fluctuation range configuration interface is provided, cfg_traffic_variation_range.
7. The Ethernet switch chip flow and delay test verification method according to claim 2 is characterized in that: The externally provided data volume accumulation interface, add_valid_data_by_octet, is called when valid data is received at the interface.
8. The Ethernet switch chip flow and delay test verification method according to claim 2 is characterized in that: The timestamp enabling interface, rec_curr_timestamp, is provided externally, and the component marks the timestamp of the corresponding stream according to the frame start mark frame_sop, the frame end mark frame_eop and the outgoing mark.
9. The Ethernet switch chip flow and delay test verification method according to claim 1, characterized in that: When calculating the flow rate, each flow is calculated, and each flow calculation result is compared with the set fluctuation range, and an alarm message is printed when the flow rate is higher or lower than the expected flow rate.
10. The Ethernet switch chip flow and delay test verification method according to claim 9, characterized in that: The input-output order-keeping monitoring is performed on the data packets of each flow, and the packet delay (storage and forwarding delay) is calculated; based on the order-keeping monitoring, the packet loss rate can be counted, an initialization interface is provided, and the default values of parameters such as the clock cycle, flow calculation interval, and allowed flow fluctuation range are configured.