Semiconductor structure and method for manufacturing the same

Abstract

The disclosed embodiments relate to the field of semiconductors and provide a semiconductor structure and a method for manufacturing the same. The method comprises: forming a stacked structure on a substrate; patterning the stacked structure to form a wordline trench; forming a semiconductor layer and a wordline within the wordline trench; forming a wordline isolation trench, the wordline isolation trench separating the wordline into a first wordline and a second wordline, and separating the semiconductor layer into a first semiconductor layer and a second semiconductor layer; patterning the stacked structure to form a capacitor trench; filling the capacitor trench to form a capacitor structure, the capacitor structure comprising an upper electrode plate, an upper electrode layer, a dielectric layer, and a lower electrode layer; forming a capacitor isolation trench, the capacitor isolation trench separating at least the lower electrode layer into a first lower electrode layer and a second lower electrode layer; and forming a bitline, the bitline being located on a side of the wordline trench away from the capacitor trench. The semiconductor structure and the method for manufacturing the same provided by the disclosed embodiments at least contribute to improving the integration density of the semiconductor structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] Memory is a storage component used to store programs and various data. Random Access Memory (RAM) used in general computer systems can be divided into two types: Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM). DRAM is a commonly used semiconductor memory device in computers and is composed of many repeated storage cells.

[0003] A memory cell typically includes a capacitor structure and a transistor, wherein one of the source, drain, or drain of the transistor is connected to a bit line structure, and the other of the source, drain, or drain is connected to the capacitor structure. The capacitor structure includes a capacitor structure contact structure and a capacitor structure. The word line structure of the memory cell can control the opening or closing of the channel region of the transistor, thereby reading the data information stored in the capacitor structure through the bit line structure, or writing the data information into the capacitor structure for storage through the bit line structure. Summary of the Invention

[0004] The embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which are at least beneficial to improving the integration density of the semiconductor structure.

[0005] According to some embodiments of the present disclosure, on one hand, a method for manufacturing a semiconductor structure is provided, comprising: providing a substrate; forming a stacked structure on the substrate, the stacked structure comprising alternately stacked support layers and sacrificial layers; patterning the stacked structure to form a word line groove; forming a semiconductor layer, the semiconductor layer covering the inner wall of the word line groove; forming a word line, the word line filling the remaining word line groove; forming a word line isolation groove, the word line isolation groove extending along a first direction, the word line isolation groove separating the word line into a first word line and a second word line, and separating the semiconductor layer into a first semiconductor layer and a second semiconductor layer; patterning the stacked structure to form a capacitor groove; filling the capacitor groove to form a capacitor. The capacitor structure includes an upper electrode plate, an upper electrode layer, a dielectric layer, and a lower electrode layer, wherein the lower electrode layer covers the inner wall of the capacitor groove, the dielectric layer covers the inner wall of the lower electrode layer, the upper electrode layer covers the inner wall of the dielectric layer, and the upper electrode plate fills the remaining capacitor groove; a capacitor isolation groove is formed, which extends along a first direction and separates the lower electrode layer into at least a first lower electrode layer and a second lower electrode layer, wherein the first lower electrode layer is used to be electrically connected to the first semiconductor layer, and the second lower electrode layer is used to be electrically connected to the second semiconductor layer; a bit line is formed, wherein the bit line is located on a side of the word line groove away from the capacitor groove and extends along a second direction, and the bit line is used to be electrically connected to the first semiconductor layer and the second semiconductor layer.

[0006] In some embodiments, after forming the word line groove and before forming the semiconductor layer, the method further includes: etching a portion of the sacrificial layer along the first direction and the second direction based on the word line groove; after forming the semiconductor layer, the method further includes: removing a portion of the semiconductor layer facing the surface of the word line groove from the support layer along the third direction.

[0007] In some embodiments, filling the capacitor groove to form a capacitor structure and forming a capacitor isolation groove includes: forming a lower electrode layer, the lower electrode layer covers the bottom surface and inner wall of the capacitor groove; forming a capacitor structure isolation groove, the capacitor structure isolation groove separates the lower electrode layer into a first lower electrode layer and a second lower electrode layer; forming a dielectric layer, the dielectric layer covers the inner walls of the first lower electrode layer and the second lower electrode layer; forming an upper electrode layer, the upper electrode layer covers the inner wall of the dielectric layer; forming an upper electrode plate, the upper electrode plate fills the remaining capacitor groove.

[0008] In some embodiments, after forming the capacitor groove and before forming the lower electrode layer, it also includes: etching a portion of the sacrificial layer along the first direction and the second direction based on the capacitor groove; after forming the lower electrode layer, it also includes: removing a portion of the lower electrode layer facing the surface of the capacitor groove along the third direction.

[0009] In some embodiments, after forming the capacitor trench and before forming the lower electrode layer, the method further includes: removing a portion of the sacrificial layer along the first direction to connect the capacitor trench with the word line trench.

[0010] In some embodiments, forming a bit line includes: patterning a stacked structure to form a first trench extending along a second direction; removing a sacrificial layer of a word line trench on a side away from the capacitor trench along the first direction based on the first trench to form a second trench; and forming a bit line in the second trench.

[0011] In some embodiments, the word line isolation trench and the capacitor isolation trench are connected and formed in the same process step.

[0012] According to some embodiments of the present disclosure, another aspect of the embodiments of the present disclosure further provides a semiconductor structure, including: a first word line and a second word line adjacent to each other and insulated from each other along a second direction, the first word line and the second word line both extending along a third direction; a first semiconductor layer and a second semiconductor layer, the first semiconductor layer at least covering a surface of the first word line away from the second word line along the second direction, and the second semiconductor layer at least covering a surface of the second word line away from the first word line along the second direction; a capacitor structure, the capacitor structure being located on one side of the first word line and the second word line along the first direction, the capacitor structure comprising an upper electrode plate, an upper electrode layer, a dielectric layer, a first lower electrode layer and a second lower electrode layer, the upper electrode plate extending along the third direction, the upper electrode layer covering a sidewall of the upper electrode plate, the dielectric layer covering a surface of the upper electrode layer away from the upper electrode plate, the first lower electrode layer at least covering a surface of the dielectric layer on one side along the second direction and being electrically connected to the first semiconductor layer, the second lower electrode layer at least covering a surface of the dielectric layer on the other side along the second direction and being electrically connected to the second semiconductor layer; a bit line, the bit line being located on the other side of the first word line and the second word line along the first direction and extending along the second direction, the bit line being electrically connected to the first semiconductor layer and the second semiconductor layer.

[0013] In some embodiments, the first word line includes a first main portion and a first extension portion, the first main portion extends along a third direction, the first extension portion is located on a surface of the first main portion away from the second word line, and extends along the second direction, and the first semiconductor layer covers the surface of the first extension portion; the second word line includes a second main portion and a second extension portion, the second main portion extends along the third direction, the second extension portion is located on a surface of the second main portion away from the first word line, and extends along the second direction, and the second semiconductor layer covers the surface of the second extension portion.

[0014] In some embodiments, the upper electrode plate includes a main body and a protrusion, the main body extends along a third direction, the protrusion surrounds the main body, the upper electrode layer covers the side walls of the main body and the protrusion, the dielectric layer covers the side walls of the upper electrode layer, the first lower electrode layer at least covers the side surface of the dielectric layer opposite to the protrusion along the second direction, and the second lower electrode layer at least covers the other side surface of the dielectric layer opposite to the protrusion along the second direction.

[0015] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0016] The manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure forms a semiconductor layer covering the sidewalls of the wordline groove and a wordline filling the wordline groove in the wordline groove, so that the wordline formed in this way extends along the third direction, and the semiconductor layer surrounds the sidewalls of the wordline along the first direction, thereby forming a structure in which the channel surrounds the wordline. This can increase the contact area between the wordline and the channel region, thereby facilitating the improvement of the gate control capability. A capacitor groove is formed on one side of the wordline groove along the first direction, the lower electrode layer covers the inner wall of the capacitor groove, the dielectric layer covers the inner wall of the lower electrode layer, the upper electrode layer covers the inner wall of the dielectric layer, the upper electrode plate covers the inner wall of the upper electrode layer and fills the capacitor groove, so that the lower electrode layer, the dielectric layer, the upper electrode layer and the upper electrode plate constitute a capacitor structure. The formed capacitor isolation groove separates the lower electrode layer into at least a first lower electrode layer and a second lower electrode layer, so that the capacitor structure can constitute two independent capacitors. In addition, the wordline isolation trench separates the wordline into a first wordline and a second wordline, and separates the semiconductor layer into a first semiconductor layer and a second semiconductor layer. The first semiconductor layer is electrically connected to the first lower electrode layer, and the second semiconductor layer is electrically connected to the second lower electrode layer. In this way, two independent memory cells can be formed, thereby improving the integration density of the semiconductor structure. The manufacturing method of the semiconductor structure provided in this embodiment can form a larger transistor structure and capacitor structure in the front-end process step, and then separate a memory cell into two independent memory cells through the wordline isolation trench and the capacitor isolation trench, thereby increasing the process window of the front-end process and doubling the number of memory cells. The formed bit line extends along the second direction, so that the transistors corresponding to the multiple first semiconductor layers and the multiple second semiconductor layers along the second direction can share the same bit line control terminal, thereby improving the control capability of the bit line. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figures 1 to 16 A schematic structural diagram corresponding to each step of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0019] Figure 17 for Figure 16 Schematic diagram of the cross-sectional structure along the BB1 ​​direction;

[0020] Figure 18 for Figure 16Schematic diagram of the cross-sectional structure along CC1 direction. DETAILED DESCRIPTION

[0021] According to some embodiments of the present disclosure, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, which can improve the integration density of the semiconductor structure.

[0022] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to facilitate a better understanding of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented.

[0023] Figures 1 to 16 A schematic structural diagram corresponding to each step of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure, wherein: Figures 3 to 7 for Figure 2 Schematic diagram of the cross-sectional structure along the AA1 and BB1 directions, Figures 9 to 14 for Figure 8 The cross-sectional structure diagram along the AA1 direction and the CC1 direction is shown. The manufacturing method of the semiconductor structure provided by this embodiment will be described in detail with reference to the accompanying drawings, as follows:

[0024] refer to Figures 1 to 16 , a method for manufacturing a semiconductor structure, comprising:

[0025] refer to Figure 1 , providing a substrate 100; forming a stacked structure 200 on the substrate 100, the stacked structure 200 including alternately stacked support layers 201 and sacrificial layers 202.

[0026] The material of substrate 100 includes a basic semiconductor, a compound semiconductor, or an alloy semiconductor. For example, a basic semiconductor includes germanium (Ge); a compound semiconductor includes silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or Group III-V semiconductor materials; and an alloy semiconductor includes silicon germanium (SiGe), silicon germanium carbide, germanium tin, silicon germanium tin, gallium arsenic phosphide, gallium indium phosphide, gallium indium arsenide, indium gallium arsenide phosphide, aluminum indium arsenide, and / or aluminum gallium arsenide. In some embodiments, substrate 100 may also be a silicon-on-insulator (SOI) structure, a silicon-germanium-on-insulator (SGI) structure, a germanium-on-insulator (GOI) structure, or a combination thereof.

[0027] The materials of the support layer 201 and the sacrificial layer 202 include silicon oxide, silicon nitride or silicon oxynitride, etc. The support layer 201 and the sacrificial layer 202 are made of different materials, so that under the same etching environment, the support layer 201 and the sacrificial layer 202 can have different etching rates.

[0028] refer to Figure 2 , patterning the stacked structure 200 to form a word line trench 310 .

[0029] In some embodiments, the wordline trenches may be filled with insulating material first, and after the bitlines and capacitors are formed, the insulating material in the wordline trenches may be removed and the semiconductor layer and wordlines may be formed. Alternatively, the semiconductor layer and wordlines may be formed in the wordline trenches first, followed by the bitlines and capacitors. Alternatively, the bitlines may be formed first and then the capacitors, or the capacitors may be formed first and then the bitlines. In other words, the order of forming the semiconductor layer, wordlines, bitlines, and capacitors may be varied, and this embodiment does not limit the order of forming the semiconductor layer, wordlines, bitlines, and capacitors.

[0030] The following description will be made by taking the example of forming the semiconductor layer and word lines first and then forming the capacitors and bit lines.

[0031] refer to Figure 3 Based on the word line groove 310 , a portion of the sacrificial layer 202 is etched along the first direction X and the second direction Y. After the sacrificial layer 202 is partially etched along the first direction X and the second direction Y, the surface of the support layer 201 facing the word line groove 310 protrudes from the surface of the sacrificial layer 202 facing the word line groove 310 .

[0032] refer to Figure 4 , forming a semiconductor layer 700, the semiconductor layer 700 covers the inner wall of the word line groove 310; removing the portion of the semiconductor layer 700 on the surface of the support layer 201 facing the word line groove 310. In this way, a plurality of semiconductor layers 700 spaced apart along the third direction Z can be formed, which can facilitate the subsequent formation of a plurality of transistor structures stacked along the third direction Z. In addition, since the semiconductor layer 700 is located on the inner wall of the groove formed by the support layer 201 and the sacrificial layer 202, after the word line is subsequently filled, the surface of the semiconductor layer 700 in contact with the word line includes the inner wall surface of the semiconductor layer 700 along the first direction X and the second direction Y and the two inner wall surfaces opposite to each other along the third direction Z. The contact area between the semiconductor layer 700 and the word line can be increased, and the gate control capability of the word line can be improved.

[0033] The material of the semiconductor layer 700 includes indium gallium zinc oxide, tungsten-doped indium oxide, or indium tin oxide.

[0034] It should be noted that the stacked structure 200 in the accompanying drawings of this embodiment includes multiple layers of alternating support layers 201 and sacrificial layers 202, which facilitates the formation of multiple stacked transistor structures, thereby increasing the integration density of the semiconductor structure. In some embodiments, there may be only one transistor along the third direction, eliminating the need to etch portions of the sacrificial layer along the first and second directions based on the wordline trenches, thereby improving the manufacturing efficiency of the semiconductor structure.

[0035] refer to Figure 5, forming a word line 300 , which fills the remaining word line groove 310 .

[0036] The material of the word line 300 includes at least one of polysilicon, titanium nitride, titanium aluminide, tantalum nitride, nickel silicide, cobalt silicide, tantalum, aluminum, lanthanum, titanium, or tungsten.

[0037] In some embodiments, before forming the word line, the method further includes: forming a gate dielectric layer, wherein the gate dielectric layer at least covers the inner wall surface of the semiconductor layer.

[0038] The material of the gate dielectric layer includes silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicide, high-K material, ferroelectric material, anti-ferroelectric material or a combination thereof.

[0039] refer to Figure 6 , forming wordline isolation trenches 330. Wordline isolation trenches 330 extend along a first direction X. Wordline isolation trenches 330 separate wordline 300 into first wordline 301 and second wordline 302, and separate semiconductor layer 700 into first semiconductor layer 701 and second semiconductor layer 702. This allows the number of wordlines and semiconductor layers to be tripled, thereby doubling the number of transistor structures to be formed subsequently, thereby increasing the integration density of the semiconductor structure. Furthermore, when wordline 300 and semiconductor layer 700 are formed first, a larger process window is created, reducing the difficulty of the semiconductor structure manufacturing process.

[0040] refer to Figure 7 , forming a word line isolation layer 350 , which fills the word line isolation trench 330 .

[0041] The wordline isolation layer 350 may be made of materials such as fluorinated polymers, low-k glass fibers, microporous high-quality polymers, fluoropolyurethanes, or porous low-k fatty acid methyl esters, such as SiON, SiCN, SiOC, or SiOCN. Low-k materials can prevent parasitic capacitance between the first wordline 301 and the second wordline 302.

[0042] refer to Figure 8 , the stacked structure 200 is patterned to form a capacitor trench 610 , and the capacitor trench 610 is located on one side of the word line trench 310 along the first direction X.

[0043] refer to Figure 9 Based on the capacitor groove 610, a portion of the sacrificial layer 202 is removed along the first direction X and the second direction Y. After the sacrificial layer 202 is partially etched along the first direction X and the second direction Y, the surface of the support layer 201 facing the capacitor groove 610 protrudes from the surface of the sacrificial layer 202 facing the capacitor groove 610.

[0044] refer to Figure 10, forming a lower electrode layer 604, which covers the inner wall of the capacitor groove 610; and removing the portion of the lower electrode layer 604 on the support layer 201 facing the surface of the capacitor groove 610. In this way, multiple lower electrode layers 604 spaced apart along the third direction Z can be formed, and the lower electrode layers 604 can be used to form memory cells with corresponding semiconductor layers 700.

[0045] It will be appreciated that the stacked structure 200 in the accompanying drawings of this embodiment includes alternating layers of support layers 201 and sacrificial layers 202, thereby facilitating the formation of multiple stacked transistor structures, thereby increasing the integration density of the semiconductor structure. In some embodiments, there may be only one transistor along the third direction, eliminating the need to etch portions of the sacrificial layer along the first and second directions based on the capacitor trench, thereby improving the manufacturing efficiency of the semiconductor structure.

[0046] In some embodiments, reference Figure 10 When a portion of the sacrificial layer 202 is removed along the first direction X, the capacitor trench 610 can be connected to the wordline trench 310. The surface of the subsequently formed lower electrode layer 604 facing the wordline trench 310 can directly electrically contact the surface of the semiconductor layer 700, thereby facilitating direct electrical connection between the lower electrode layer 604 and the semiconductor layer 700 for signal transmission.

[0047] In some embodiments, the capacitor trench and the word line trench may be disconnected, and then in other process steps, the sacrificial layer between the lower electrode layer and the semiconductor layer is removed and a contact structure is formed to electrically connect the semiconductor layer and the lower electrode layer.

[0048] The material of the contact structure includes one or more of tungsten, copper, aluminum or cobalt.

[0049] In some embodiments, reference Figure 11 After forming the lower electrode layer 604, the method includes forming a filling layer 620, wherein the filling layer 620 covers the inner wall of the lower electrode layer 604 and fills the capacitor groove 610. Figure 12 , forming a capacitor isolation trench 630, the capacitor structure isolation trench 630 separates the lower electrode layer 604 into a first lower electrode layer 614 and a second lower electrode layer 624. Figure 13, the filling layer 620 is removed, and a dielectric layer 603 is formed, which covers the inner walls of the first lower electrode layer 614 and the second lower electrode layer 624; an upper electrode layer 602 is formed, which covers the inner walls of the dielectric layer 603; and an upper electrode plate 601 is formed, which fills the remaining capacitor groove 610. In this way, the first lower electrode layer 614 and the second lower electrode layer 624 are electrically connected to the first semiconductor layer 701 and the second semiconductor layer 702, respectively, thereby forming two independent memory cells in the second direction Y. The two memory cells share the dielectric layer 603, the upper electrode layer 602, and the upper electrode plate 601.

[0050] In some embodiments, reference Figure 14 After forming the lower electrode layer 604, the process includes: forming a dielectric layer 603, where the dielectric layer 603 covers the inner wall of the lower electrode layer 604; forming an upper electrode layer 602, where the upper electrode layer 602 covers the inner wall of the dielectric layer 603; forming an upper electrode plate 601, where the upper electrode plate 601 fills the remaining capacitor groove 610; forming a capacitor isolation groove 630, where the capacitor isolation groove 630 separates the lower electrode layer 604 into a first lower electrode layer 614 and a second lower electrode layer 624, separates the dielectric layer 603 into a first dielectric layer 613 and a second dielectric layer 623, separates the upper electrode layer 602 into a first upper electrode layer 612 and a second upper electrode layer 622, and separates the upper electrode plate 601 into a first upper electrode plate 611 and a second upper electrode plate 621. That is, after forming the capacitor structure 600, a capacitor isolation trench 630 is formed to separate the capacitor structure 600 into two independent capacitors along the second direction Y. Specifically, the first lower electrode layer 614, the first dielectric layer 613, the first upper electrode layer 612, and the first upper electrode plate 611 constitute one capacitor, and the second lower electrode layer 624, the second dielectric layer 623, the second upper electrode layer 622, and the second upper electrode plate 621 constitute another capacitor. Thus, each first semiconductor layer 701 and each second semiconductor layer 702 corresponds to a capacitor, thereby forming multiple independent storage cells.

[0051] The material of the lower electrode layer 604 and the upper electrode layer 602 includes at least one of platinum nickel, titanium, tantalum, cobalt, silicon germanium, copper, tungsten, tantalum nitride, titanium nitride or ruthenium.

[0052] The material of the dielectric layer 603 includes high dielectric constant materials such as silicon oxide, tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, titanium oxide, barium oxide, strontium oxide, yttrium oxide, lanthanum oxide, praseodymium oxide or barium strontium titanate.

[0053] The material of the upper electrode plate 601 is at least one of platinum nickel, titanium, tantalum, cobalt, silicon germanium, copper, tungsten, tantalum nitride, titanium nitride or ruthenium.

[0054] In some embodiments, the upper electrode plate 601 and the upper electrode layer 602 are made of the same material. Thus, the upper electrode plate 601 and the upper electrode layer 602 can be formed in the same process step to improve the manufacturing efficiency of the semiconductor structure. In some embodiments, the upper electrode plate 601 and the upper electrode layer 602 are made of different materials.

[0055] In some embodiments, the wordline isolation trench 330 and the capacitor isolation trench 630 are interconnected and formed in the same process step. That is, after the semiconductor layer 700 and the wordline 300 are first formed in the wordline trench 310 and the capacitor structure 600 is formed in the capacitor trench 610, the interconnected wordline isolation trench 330 and the capacitor isolation trench 630 are then formed to separate a single transistor structure into two independent transistor structures. This doubles the number of transistor structures in a single process step, thereby increasing the integration density and manufacturing efficiency of the semiconductor structure.

[0056] refer to Figure 15 The stacked structure 200 is patterned to form a first trench 410 extending along the second direction Y. The first trench 410 is located on the other side of the word line trench 310 along the first direction X. Based on the first trench 410, the sacrificial layer 202 on the side of the word line trench 310 away from the capacitor trench 610 along the first direction X is removed to form a second trench 420. Figure 16 A bit line 400 is formed in the second trench 420 . The bit line 400 is located on the other side of the first word line 301 and the second word line 302 along the first direction X and extends along the second direction Y. The bit line 400 is electrically connected to the first semiconductor layer 701 and the second semiconductor layer 702 .

[0057] The material of bit line 400 includes at least one of metal silicide, titanium nitride, or tungsten. In some embodiments, the material of bit line 400 can be a single metal, a metal compound, or an alloy. The single metal can be aluminum, tungsten, gold, or silver; the metal compound can be tungsten nitride, tantalum nitride, or titanium nitride; and the alloy can be an alloy of at least two of aluminum, tungsten, gold, or silver.

[0058] In some embodiments, after forming the bit line 400, the process further includes forming an isolation layer 401, which fills the first trench 410. The isolation layer 401 can insulate the bit line 400 from other structures to prevent leakage between the bit line 400 and other structures.

[0059] The material of the isolation layer 401 includes silicon oxide, silicon nitride or silicon oxynitride.

[0060] The present invention provides a method for manufacturing a semiconductor structure. A semiconductor layer 700 is formed within a wordline trench 310, covering the sidewalls of the wordline trench 310 and a wordline 300 filling the wordline trench 310. The wordline 300 thus formed extends along a third direction Z. The semiconductor layer 700 surrounds the sidewalls of the wordline 300 along a first direction X, thereby forming a channel-surrounding wordline structure. This increases the contact surface between the wordline 300 and the channel region, thereby improving gate control capability. A capacitor trench 610 is formed on one side of the wordline trench 310 along the first direction X. A lower electrode layer 604 covers the inner wall of the capacitor trench 610, a dielectric layer 603 covers the inner wall of the lower electrode layer 604, an upper electrode layer 602 covers the inner wall of the dielectric layer 603, and an upper electrode plate 601 covers the inner wall of the upper electrode layer 602 and fills the capacitor trench 610. The lower electrode layer 604, the dielectric layer 603, the upper electrode layer 602, and the upper electrode plate 601 constitute a capacitor structure 600. The formed capacitor isolation trench 630 at least separates the lower electrode layer 604 into a first lower electrode layer 614 and a second lower electrode layer 624, so that the capacitor structure 600 can constitute two independent capacitors. In addition, the word line isolation trench 330 separates the word line 300 into a first word line 301 and a second word line 302, and separates the semiconductor layer 700 into a first semiconductor layer 701 and a second semiconductor layer 702. The first semiconductor layer 701 is electrically connected to the first lower electrode layer 614, and the second semiconductor layer 702 is electrically connected to the second lower electrode layer 624. In this way, two independent memory cells can be formed, thereby improving the integration density of the semiconductor structure. The manufacturing method of the semiconductor structure provided in this embodiment can form a larger transistor structure and capacitor structure in the front-end process step, and then separate a memory cell into two independent memory cells through the word line isolation trench 330 and the capacitor isolation trench 630, thereby increasing the process window of the front-end process and doubling the number of memory cells. The formed bit line 400 extends along the second direction Y, so that the transistors corresponding to the plurality of first semiconductor layers 701 and the plurality of second semiconductor layers 702 along the second direction Y can share the same bit line control terminal, thereby improving the control capability of the bit line 400 .

[0061] According to some embodiments of the present disclosure, another embodiment of the present disclosure provides a semiconductor structure that can be formed using the above-mentioned semiconductor structure preparation method to improve the integration density of the semiconductor structure. It should be noted that for the parts that are the same or corresponding to the above-mentioned embodiments, reference can be made to the corresponding description of the above-mentioned embodiments and will not be repeated in detail below.

[0062] refer to Figure 16 、 Figure 7 and Figure 14The semiconductor structure includes: a first word line 301 and a second word line 302 adjacent to each other and insulated from each other along a second direction Y, wherein the first word line 301 and the second word line 302 both extend along a third direction Z; a first semiconductor layer 701 and a second semiconductor layer 702, wherein the first semiconductor layer 701 at least covers a surface of the first word line 301 away from the second word line 302 along the second direction Y, and the second semiconductor layer 702 at least covers a surface of the second word line 302 away from the first word line 301 along the second direction Y; a capacitor structure 600, wherein the capacitor structure 600 is located on one side of the first word line 301 and the second word line 302 along the first direction X, and the capacitor structure 600 includes an upper electrode plate 601, an upper electrode layer 602, a dielectric layer 603, a first lower electrode layer 614 and The second lower electrode layer 624, the upper electrode plate 601 extends along the third direction Z, the upper electrode layer 602 covers the side wall of the upper electrode plate 601, the dielectric layer 603 covers the surface of the upper electrode layer 602 away from the upper electrode plate 601, the first lower electrode layer 614 covers at least one side surface of the dielectric layer 603 along the second direction Y and is electrically connected to the first semiconductor layer 701, the second lower electrode layer 624 covers at least the other side surface of the dielectric layer 603 along the second direction Y and is electrically connected to the second semiconductor layer 702; the bit line 400, the bit line 400 is located on the other side of the first word line 301 and the second word line 302 along the first direction X, and extends along the second direction Y, and the bit line 400 is electrically connected to the first semiconductor layer 701 and the second semiconductor layer 702.

[0063] In some embodiments, reference Figure 17 , Figure 17 for Figure 16Schematic diagram of the cross-sectional structure along the BB1 ​​direction, the first word line 301 includes a first main portion 321 and a first extension portion 311, the first main portion 321 extends along the third direction Z, the first extension portion 311 is located on a surface of the first main portion 321 away from the second word line 302 along the second direction Y, and extends along the second direction Y, the first semiconductor layer 701 covers the surface of the first extension portion 311, that is, the first semiconductor layer 701 covers the sidewalls of the first extension portion 311 and two opposite surfaces of the first extension portion 311 along the third direction Z; the second word line 302 includes a second main portion 322 and a second extension portion 312, the second main portion 322 extends along the third direction Z, the second extension portion 312 is located on a surface of the second main portion 322 away from the first word line 301 along the second direction Y, and extends along the second direction Y, the second semiconductor layer 702 covers the surface of the second extension portion 312, that is, the second semiconductor layer 702 covers the sidewalls of the second extension portion 312 and two opposite surfaces of the second extension portion 312 along the third direction Z. In this way, the first extension portion 311 protrudes from the surface of the first main portion 321. The first extension portion 311 can further increase the surface area of ​​the first word line 301. The corresponding first semiconductor layer 701 surrounds the surface of the first extension portion 311, which can further increase the contact area between the first semiconductor layer 701 and the first word line 301, thereby improving the gate control capability of the first word line 301. Similarly, the gate control capability of the second word line 302 can also be improved. In addition, along the third direction Z, the first word line 301 can include a first main portion 321 and multiple first extension portions 311. The number of corresponding first semiconductor layers 701 is multiple, each first semiconductor layer 701 surrounds the surface of a first extension portion 311, and adjacent first semiconductor layers 701 are spaced apart from each other. The multiple first semiconductor layers 701 can respectively form semiconductor channels of multiple transistors. The second word line 302 and the second semiconductor layer 702 are similar. In this way, the integration density of the semiconductor structure can be improved.

[0064] In some embodiments, reference Figure 18 , Figure 18 for Figure 16Schematic diagram of the cross-sectional structure along the CC1 direction, the upper electrode plate 601 includes a main body 631 and a protrusion 641, the main body 631 extends along the third direction Z, the protrusion 641 surrounds the main body 631, the upper electrode layer 602 covers the side walls of the main body 631 and the protrusion 641, the dielectric layer 603 covers the side walls of the upper electrode layer 602, the first lower electrode layer 614 covers at least one side surface of the dielectric layer 603 opposite to the protrusion 641 along the second direction Y, and the second lower electrode layer 624 covers at least the other side surface of the dielectric layer 603 opposite to the protrusion 641 along the second direction Y. It is understandable that when forming a multi-layer stacked transistor structure, the corresponding capacitors also need to be stacked. When the capacitor structure 600 is formed using the above method, the first lower electrode layer 614 and the second lower electrode layer 624 are formed to cover the inner wall of the groove formed by the support layer 201 and the sacrificial layer 202. The subsequently formed dielectric layer 603, the upper electrode layer 602 and the upper electrode plate 601 are stacked in sequence. The upper electrode plate 601 corresponds to the position of the first lower electrode layer 614 and the second lower electrode layer 624, that is, the position of the groove formed by the support layer 201 and the sacrificial layer 202, so that a protrusion 641 may be formed when the capacitor groove 610 is filled. In addition, the protrusion 641 can serve as a supporting structure to facilitate maintaining the morphology of the capacitor structure 600, thereby improving the stability of the semiconductor structure.

[0065] The semiconductor structure provided by the embodiment of the present disclosure is formed using the above-mentioned method for preparing a semiconductor structure. The word line 300 extends along the third direction Z, the semiconductor layer 700 surrounds the sidewall of the word line 300 along the first direction X, and the word line isolation trench 330 separates the word line 300 into a first word line 301 and a second word line 302, and separates the semiconductor layer 700 into a first semiconductor layer 701 and a second semiconductor layer 702. In this way, the number of transistor structures in the same space can be increased by two times, and the integration density of the semiconductor structure is increased. In addition, the upper electrode plate 601 extends along the third direction Z, the upper electrode layer 602 covers the sidewall of the upper electrode plate 601, the dielectric layer 603 covers the surface of the upper electrode layer 602 away from the upper electrode plate 601, the first lower electrode layer 614 covers at least one side surface of the dielectric layer 603 along the second direction Y and is electrically connected to the first semiconductor layer 701, and the second lower electrode layer 624 covers at least the other side surface of the dielectric layer 603 along the second direction Y and is electrically connected to the second semiconductor layer 702. In this way, the first semiconductor layer 701 and the second semiconductor layer 702 respectively correspond to a capacitor, the number of storage units in the same space is doubled, and the integration density of the semiconductor structure is improved.

[0066] Those skilled in the art will appreciate that the above-mentioned embodiments are specific examples for implementing the present disclosure, and that in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: providing a substrate; forming a stacked structure on the substrate, the stacked structure comprising alternately stacked support layers and sacrificial layers; patterning the stacked structure to form word line trenches; Based on the word line groove, etching a portion of the sacrificial layer along a first direction and a second direction; forming a semiconductor layer, wherein the semiconductor layer covers an inner wall of the word line trench; removing a portion of the semiconductor layer of the support layer facing the surface of the word line groove along a third direction; forming a word line, wherein the word line fills the remaining word line groove; forming a word line isolation trench extending along the first direction, the word line isolation trench separating the word line into a first word line and a second word line, and separating the semiconductor layer into a first semiconductor layer and a second semiconductor layer; patterning the stacked structure to form a capacitor trench; Filling the capacitor slot to form a capacitor structure, the capacitor structure comprising an upper electrode plate, an upper electrode layer, a dielectric layer, and a lower electrode layer, wherein the lower electrode layer covers the inner wall of the capacitor slot, the dielectric layer covers the inner wall of the lower electrode layer, the upper electrode layer covers the inner wall of the dielectric layer, and the upper electrode plate fills the remaining capacitor slot; forming a capacitor isolation trench, the capacitor isolation trench extending along the first direction and separating the lower electrode layer into at least a first lower electrode layer and a second lower electrode layer, the first lower electrode layer being used to be electrically connected to the first semiconductor layer, and the second lower electrode layer being used to be electrically connected to the second semiconductor layer; A bit line is formed. The bit line is located on a side of the word line groove away from the capacitor groove and extends along the second direction. The bit line is used to electrically connect the first semiconductor layer and the second semiconductor layer.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein: Filling the capacitor groove to form a capacitor structure and forming a capacitor isolation groove includes: forming the lower electrode layer, wherein the lower electrode layer covers the bottom surface and inner wall of the capacitor groove; forming the capacitor structure isolation trench, wherein the capacitor structure isolation trench separates the lower electrode layer into the first lower electrode layer and the second lower electrode layer; forming the dielectric layer, wherein the dielectric layer covers inner walls of the first lower electrode layer and the second lower electrode layer; forming the upper electrode layer, wherein the upper electrode layer covers the inner wall of the dielectric layer; The upper electrode plate is formed, and the upper electrode plate fills the remaining capacitor groove.

3. The method for manufacturing a semiconductor structure according to claim 2, wherein: After forming the capacitor groove and before forming the lower electrode layer, the method further includes: Based on the capacitor groove, etching a portion of the sacrificial layer along the first direction and the second direction; After forming the lower electrode layer, the method further includes: A portion of the lower electrode layer that is located on the support layer and faces the surface of the capacitor groove is removed along a third direction.

4. The method for manufacturing a semiconductor structure according to claim 2 or 3, wherein: After forming the capacitor groove and before forming the lower electrode layer, the method further includes: A portion of the sacrificial layer is removed along the first direction to connect the capacitor groove with the word line groove.

5. The method for manufacturing a semiconductor structure according to claim 1, wherein: The forming of the bit line comprises: patterning the stacked structure to form a first trench extending along the second direction; Based on the first trench, removing the sacrificial layer on a side of the word line trench away from the capacitor trench along the first direction to form a second trench; The bit line is formed in the second trench.

6. The method for manufacturing a semiconductor structure according to claim 1, wherein: The word line isolation trench and the capacitor isolation trench are connected and formed in the same process step.

7. A semiconductor structure, characterized in that include: A first word line and a second word line adjacent to each other and insulated from each other along the second direction, wherein the first word line and the second word line both extend along the third direction; a first semiconductor layer and a second semiconductor layer, the first semiconductor layer at least covering a surface of the first word line away from the second word line along the second direction, and the second semiconductor layer at least covering a surface of the second word line away from the first word line along the second direction; a capacitor structure, the capacitor structure being located on one side of the first word line and the second word line along the first direction, the capacitor structure comprising an upper electrode plate, an upper electrode layer, a dielectric layer, a first lower electrode layer, and a second lower electrode layer, the upper electrode plate extending along the third direction, the upper electrode layer covering a sidewall of the upper electrode plate, the dielectric layer covering a surface of the upper electrode layer away from the upper electrode plate, the first lower electrode layer covering at least one side surface of the dielectric layer along the second direction and being electrically connected to the first semiconductor layer, and the second lower electrode layer covering at least another side surface of the dielectric layer along the second direction and being electrically connected to the second semiconductor layer; a bit line, the bit line being located on the other side of the first word line and the second word line along the first direction and extending along the second direction, the bit line being electrically connected to the first semiconductor layer and the second semiconductor layer; In which, the first word line includes a first main portion and a first extension portion, the first main portion extends along the third direction, the first extension portion is located on a surface of the first main portion away from the second word line and extends along the second direction, and the first semiconductor layer covers the surface of the first extension portion; the second word line includes a second main portion and a second extension portion, the second main portion extends along the third direction, the second extension portion is located on a surface of the second main portion away from the first word line and extends along the second direction, and the second semiconductor layer covers the surface of the second extension portion.

8. The semiconductor structure according to claim 7, wherein: The upper electrode plate includes a main body and a protrusion, the main body extends along the third direction, the protrusion surrounds the main body, the upper electrode layer covers the side walls of the main body and the protrusion, the dielectric layer covers the side walls of the upper electrode layer, the first lower electrode layer at least covers the side surface of the dielectric layer facing the protrusion along the second direction, and the second lower electrode layer at least covers the other side surface of the dielectric layer facing the protrusion along the second direction.

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