Memory cell, manufacturing method thereof, and semiconductor structure

Abstract

The embodiments of the present disclosure relate to the field of semiconductors and provide a memory cell, a method for manufacturing the same, and a semiconductor structure, wherein the memory cell includes: a first word line extending along a first direction; a first bit line extending along the first direction, the first bit line and the first word line being arranged along a second direction, and the first bit line being spaced apart from the first word line; a first channel layer, the first channel layer being located between the first bit line and the first word line, and being electrically connected to the first bit line and the first word line, respectively; a second word line extending along a third direction; a second channel layer extending along the third direction, the second channel layer surrounding the second word line, the second channel layer controlling the conduction and disconnection of a transmission path between the first word line and the first bit line; a second bit line, the second bit line being located at least on one side of the second word line along the second direction, and being electrically connected to the second channel layer, and being spaced apart from the first word line and the first bit line in the third direction, thereby providing a new memory cell structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to a memory cell, a manufacturing method thereof, and a semiconductor structure. Background Art

[0002] Common dynamic random access memory (DRAM) is of the 1T1C (1Transistor-1Capacitor) type, where a transistor source or drain is electrically connected to a capacitor to form a storage unit. This structure uses capacitors to store data, but because reading consumes the capacitor's power and the capacitor itself leaks electricity, the charge in the capacitor needs to be constantly refreshed, resulting in high power consumption and unstable electrical performance. Furthermore, the large area occupied by the capacitor manufacturing process makes it difficult to scale down the size of the capacitor.

[0003] To overcome the problem caused by capacitance, a 2T0C type memory cell structure is used, that is, the source or drain of a transistor is electrically connected to the gate of another transistor to form a memory cell structure. Summary of the Invention

[0004] The embodiments of the present disclosure provide a memory cell, which at least proposes a new 2T0C structure.

[0005] According to some embodiments of the present disclosure, on one hand, an embodiment of the present disclosure provides a storage unit, comprising: a first word line extending along a first direction; a first bit line extending along the first direction, the first bit line and the first word line being arranged along a second direction, and the first bit line and the first word line being spaced apart; a first channel layer, the first channel layer being located between the first bit line and the first word line, and being electrically connected to the first bit line and the first word line, respectively; a first transistor comprising: the first word line, the first bit line and the first channel layer; a second word line extending along a third direction; a second channel layer extending along the third direction, the second channel layer being arranged opposite to the second word line, the second channel layer controlling the conduction and disconnection of a transmission path between the first word line and the first bit line; a second bit line, the second bit line being located at least on one side of the second word line along the second direction, and being electrically connected to the second channel layer, and being spaced apart from the first word line and the first bit line in the third direction; and a second transistor comprising: the second word line, the second channel layer and the second bit line.

[0006] In some embodiments, the first transistor further includes: a first metal oxide layer, the first metal oxide layer is in contact with and connected to the second channel layer, and is arranged opposite to the first channel layer; the second transistor further includes: a second metal oxide layer, the second metal oxide layer is in contact with and connected to the second channel layer and the second bit line, and the second metal oxide layer is spaced apart from the first metal oxide layer.

[0007] In some embodiments, the first metal oxide layer surrounds the second channel layer, and the first transistor further includes: a first dielectric layer, the first dielectric layer surrounds the first metal oxide layer, and the first channel layer surrounds the first dielectric layer.

[0008] In some embodiments, the second metal oxide layer surrounds the second channel layer, and the second bit line surrounds the second metal oxide layer.

[0009] In some embodiments, the second transistor further includes: a second dielectric layer, wherein the second dielectric layer is located between the second word line and the second channel layer.

[0010] According to some embodiments of the present disclosure, on the other hand, embodiments of the present disclosure further provide a semiconductor structure, comprising a plurality of memory cells as described above, wherein the plurality of memory cells are arranged at intervals along the first direction and the third direction, and the first word lines of the plurality of memory cells are located on the same side of the second word line along the second direction.

[0011] In some embodiments, the system further includes: a first conductive pillar, the first conductive pillar is in contact with and connected to the first word line, and the first word lines of the plurality of memory cells are in contact with and connected to the same first conductive pillar.

[0012] In some embodiments, it also includes: a second conductive pillar, which is in contact with and connected to the first bit line; a third conductive pillar, which is in contact with and connected to the second bit line, the second conductive pillars connected to different first bit lines are adjacent along the first direction, and the third conductive pillars connected to different second bit lines are adjacent along the first direction.

[0013] In some embodiments, the system further includes: a second conductive pillar, the second conductive pillar being in contact with and connected to the first bit line; a third conductive pillar, the third conductive pillar being in contact with and connected to the second bit line, and the second conductive pillar and the third conductive pillar being arranged alternately along the first direction.

[0014] According to some embodiments of the present disclosure, on the other hand, the embodiments of the present disclosure further provide a method for manufacturing a memory cell, including: forming a first transistor, the first transistor including: a first word line extending along a first direction, a first bit line extending along the first direction, the first bit line and the first word line are arranged along a second direction, and the first bit line is spaced apart from the first word line, a first channel layer, the first channel layer is located between the first bit line and the first word line, and is respectively in contact with and connected to the first bit line and the first word line; forming a second transistor, the second transistor including: a second word line extending along a third direction, a second channel layer extending along the third direction, the second channel layer is arranged opposite to the second word line, the second channel layer controls the conduction and disconnection of a transmission path between the first word line and the first bit line, a second bit line, the second bit line is located at least on one side of the second word line along the second direction, and is electrically connected to the second channel layer, and is spaced apart from the first word line and the first bit line in the third direction.

[0015] In some embodiments, the method of forming the second transistor includes: providing a stack structure, the stack structure including a first sacrificial layer, a second sacrificial layer, a first insulating layer and a third sacrificial layer stacked in sequence; etching the stack structure to form a first groove passing through the stack structure; forming a second channel layer, the second channel layer covering the inner wall of the first groove; forming a second word line, the second word line is located in the first groove and fills the first groove; removing the third sacrificial layer, and forming the second bit line, the second bit line is located on the top surface of the first insulating layer, and the second bit line is electrically connected to the second channel layer.

[0016] In some embodiments, the method of forming the first transistor includes: removing the second sacrificial layer to form a second groove; forming the first channel layer, the first channel layer being located in the second groove; forming the first word line and the first bit line, the first word line and the first bit line being located in the second groove, the first word line and the first bit line being arranged at intervals along the second direction, and the first word line and the first bit line being in contact with the first channel layer.

[0017] In some embodiments, before forming the first word line and the first bit line, the method further includes: forming a second insulating layer, where the second insulating layer covers sidewalls of the first channel layer arranged along the first direction.

[0018] In some embodiments, the method of forming the second insulating layer includes: forming a second initial insulating layer, wherein the second initial insulating layer fills the second groove; and etching the second initial insulating layer to expose the sidewalls of the first channel layer arranged along the second direction.

[0019] In some embodiments, before forming the first channel layer, the process also includes: etching the exposed second sacrificial layer and the third sacrificial layer along the first groove to form a third groove, wherein the third groove exposes part of the top surface of the first insulating layer and the first sacrificial layer; forming a first metal oxide layer, wherein the first metal oxide layer is located in the third groove between the second sacrificial layer and the second channel layer; and forming a second metal oxide layer, wherein the second metal oxide layer is located in the third groove on the top surface of the first insulating layer.

[0020] The technical solution provided by the embodiments of the present disclosure has at least the following advantages: the second transistor can be used as a write transistor, the first transistor can be used as a read transistor, wherein the second word line can be used as the gate of the second transistor; when an electrical signal is input to the second word line, the second word line is turned on, and the signal on the second bit line can be transmitted to the second channel layer, so that the second channel layer can control the first channel layer of the first transistor to transmit signals, thereby transmitting signals between the first bit line and the first word line; when the signal can be read from between the first bit line and the first word line, it indicates that data information is stored in the storage unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] Figure 1 A schematic structural diagram of a storage unit provided in one embodiment of the present disclosure;

[0023] Figure 2 A cross-sectional view of a memory cell provided in one embodiment of the present disclosure;

[0024] Figure 3 A schematic structural diagram of a second storage unit provided in one embodiment of the present disclosure;

[0025] Figure 4 A schematic structural diagram of a semiconductor structure provided in one embodiment of the present disclosure;

[0026] Figure 5 A cross-sectional view of a semiconductor structure provided in one embodiment of the present disclosure;

[0027] Figures 6 to 32A schematic structural diagram corresponding to each step of a method for manufacturing a storage unit provided in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] As can be seen from the background technology, it is necessary to propose a new 2TOC structure.

[0029] The present disclosure provides a storage unit, in which a second transistor can be used as a write transistor and a first transistor can be used as a read transistor, wherein a second word line can be used as a gate of the second transistor. When an electrical signal is input to the second word line, the second word line is turned on, and the signal on the second bit line can be transmitted to the second channel layer, so that the second channel layer can control the first channel layer of the first transistor to transmit signals, thereby transmitting signals between the first bit line and the first word line. When a signal can be read between the first bit line and the first word line, it indicates that data information is stored in the storage unit.

[0030] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to facilitate a better understanding of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented.

[0031] refer to Figures 1 to 3 , Figure 1 A schematic structural diagram of a storage unit provided in one embodiment of the present disclosure is shown. Figure 2 An embodiment of the present disclosure provides Figure 1 Cross-section in BB direction; Figure 3 A cross-sectional view of a second memory cell provided in accordance with an embodiment of the present disclosure.

[0032] In some embodiments, the memory cell may include a first word line 100 extending along a first direction X.

[0033] The memory cell may include a first bit line 110 extending along a first direction X, the first bit line 110 and the first word line 100 being arranged along a second direction Y, and the first bit line 110 and the first word line 100 being spaced apart.

[0034] The memory cell may include: a first channel layer 120 , which is located between the first bit line 110 and the first word line 100 and electrically connected to the first bit line 110 and the first word line 100 respectively; the first transistor 130 includes: the first word line 100 , the first bit line 110 and the first channel layer 120 .

[0035] The memory cell may include a second word line 200 extending along a third direction Z.

[0036] The memory cell may include a second channel layer 220 extending along a third direction Z, the second channel layer 220 being disposed opposite to the second word line 200 , and controlling the on / off switching of a transmission path between the first word line 100 and the first bit line 110 .

[0037] The memory cell may include: a second bit line 210, the second bit line 210 is located at least on one side of the second word line 200 along the second direction Y, and is electrically connected to the second channel layer 220, and is spaced apart from the first word line 100 and the first bit line 110 in the third direction Z, and the second transistor 230 includes: a second word line 200, a second channel layer 220 and a second bit line 210.

[0038] The second transistor 230 can be used as a write transistor, and the first transistor 130 can be used as a read transistor, wherein the second word line 200 can be used as the gate of the second transistor 230. When an electrical signal is input to the second word line 200, the second word line 200 is turned on, and the signal on the second bit line 210 can be transmitted to the second channel layer 220, so that the second channel layer 220 can control the first channel layer 120 of the first transistor 130 to transmit signals, so that signals can be transmitted between the first bit line 110 and the first word line 100. When a signal can be read from between the first bit line 110 and the first word line 100, it indicates that data information is stored in the storage unit.

[0039] In some embodiments, the second bit line 210 can be in direct contact with the second channel layer 220. In this way, when a high-level signal is received on the second word line 200, the second channel layer 220 can be turned on under the influence of the second word line 200, so that the signal on the second bit line 210 can be transmitted to the second channel layer 220. At this time, the second channel layer 220 can also serve as the gate of the first transistor 130, that is, it receives a high-level signal and controls the first channel layer 120 of the first transistor 130 to be turned on, and the first bit line 110 and the first word line 100 respectively connected to the first channel layer 120 can also transmit signals to each other, thereby forming a 2T0C structure.

[0040] In some embodiments, taking the second word line 200 as a rectangular parallelepiped as an example, the second channel layer 220 can be arranged opposite to only three of the three side surfaces of the rectangular parallelepiped, that is, signal transmission can be achieved. The second channel layer 220 can also surround the entire side surface of the second word line 200, and surrounding the entire side surface of the second word line 200 can relatively increase the length of the second channel layer 220, thereby reducing the short channel effect of the second transistor 230.

[0041] It should be noted that the above description is only based on a rectangular parallelepiped as an example. The second word line 200 may also be cylindrical, and the second channel layer 220 may only surround a portion of the sidewall of the cylinder, or may surround the entire sidewall of the cylinder.

[0042] In some embodiments, the material of the second word line 200 can be a metal material, such as tungsten or cobalt. By setting the material of the second word line 200 to a metal material, the data transmission rate on the second word line 200 can be increased and the resistance of the semiconductor structure can be reduced.

[0043] In some embodiments, the second bit line 210 may be located only on one side of the second word line 200 along the second direction Y. The second bit line 210 only needs to be electrically connected to the second channel layer 220 to transmit the signal to the first transistor 130 through the second channel layer 220, thereby controlling the conduction of the transmission path between the first word line 100 and the first bit line 110 in the first transistor 130. In some embodiments, the second bit line 210 may also surround the second channel layer 220, thereby increasing the contact area between the second bit line 210 and the second channel layer 220 and reducing the contact resistance between the second bit line 210 and the second channel layer 220.

[0044] In some embodiments, the material of the second bit line 210 can be a metal material, such as tungsten or cobalt. By setting the material of the second bit line 210 to be a metal material, the data transmission rate on the second bit line 210 can be increased and the resistance of the semiconductor structure can be reduced. In some embodiments, the material of the second bit line 210 can be the same as the material of the second word line 200.

[0045] In some embodiments, the second channel layer 220 surrounds the entire side of the second word line 200 , and the second bit line 210 may surround the entire side of the second channel layer 220 .

[0046] In some embodiments, the material of the second channel layer 220 may be a metal oxide semiconductor material, such as IGZO (Indium Gallium Zinc Oxide).

[0047] In some embodiments, the first channel layer 120 can surround part of the side wall of the second channel layer 220, and the first channel layer 120 only needs to ensure electrical connection with the first word line 100 and the first bit line 110 respectively to realize the transmission signal between the first word line 100 and the first bit line 110; in some embodiments, the first channel layer can also surround the entire side wall of the second channel layer 220, thereby increasing the channel length of the first transistor 130, and further reducing the short channel effect in the first transistor 130.

[0048] In some embodiments, the material of the first channel layer 120 may also be a metal oxide material, such as IGZO (Indium Gallium Zinc Oxide).

[0049] In some embodiments, the material of the first word line 100 can be a metal material, such as tungsten or cobalt. By setting the material of the first word line 100 to a metal material, the data transmission rate on the first word line 100 can be increased and the resistance of the storage unit can be reduced.

[0050] In some embodiments, the material of the first bit line 110 can be a metal material, such as tungsten or cobalt. By setting the material of the first bit line 110 to be a metal material, the data transmission rate on the first bit line 110 can be increased and the resistance of the semiconductor structure can be reduced. In some embodiments, the material of the first bit line 110 can be the same as the material of the first word line 100.

[0051] In some embodiments, the material of the first bit line 110 may be different from the material of the second bit line 210, and the material of the first word line 100 may be different from the material of the second word line 200. By setting the material of the first bit line 110 to be different from the material of the second bit line 210, and the material of the first word line 100 to be different from the material of the second word line 200, the production of the storage unit can be facilitated.

[0052] In some embodiments, the first transistor 130 further includes: a first metal oxide layer 140, the first metal oxide layer 140 is in contact with the second channel layer 220 and is arranged opposite to the first channel layer 120; the second transistor 230 further includes: a second metal oxide layer 240, the second metal oxide layer 240 is in contact with the second channel layer 220 and the second bit line 210, and the second metal oxide layer 240 is separated from the first metal oxide layer 140. By providing the first metal oxide layer 140, when the signal of the second bit line 210 is transmitted through the second channel layer 220, it is first transmitted into the first metal oxide layer 140. At this time, the first metal oxide layer 140 serves as the gate of the first transistor 130, and then controls the first channel layer 120 of the first transistor 130 to be turned on, thereby turning on the transmission path between the first bit line 110 and the first word line 100. By providing the second metal oxide layer 240, and connecting the second metal oxide layer to the second bit line 210 and the second channel layer 220 respectively, a direct connection between the second bit line 210 and the second channel layer 220 can be avoided, and an excessive difference in material properties between the second bit line 210 and the second channel layer 220 can be avoided, thereby avoiding abnormal signal transmission.

[0053] In some embodiments, the material of the first metal oxide layer 140 may include metal oxides such as indium tin oxide, indium zinc oxide, zinc tin oxide, indium gallium oxide, or indium gallium zinc oxide. In some embodiments, the material of the second metal oxide layer 240 may include metal oxides such as indium tin oxide, indium zinc oxide, zinc tin oxide, indium gallium oxide, or indium gallium zinc oxide. In some embodiments, the material of the first metal oxide layer 140 may be the same as the material of the second metal oxide layer 240.

[0054] In some embodiments, the first metal oxide layer 140 surrounds the second channel layer 220, and the first transistor 130 further includes a first dielectric layer 150, wherein the first dielectric layer 150 surrounds the first metal oxide layer 140, and the first channel layer 120 surrounds the first dielectric layer 150. By providing the first metal oxide layer 140 surrounding the second channel layer 220, the contact area between the first metal oxide layer 140 and the second channel layer 220 can be increased, thereby reducing the contact resistance between the first metal oxide layer 140 and the second channel layer 220. The provision of the first dielectric layer 150 can prevent the first metal oxide layer 140 from directly contacting the first word line 100 and the first bit line 110, thereby preventing abnormal memory cell performance. By providing the first channel layer 120 surrounding the first dielectric layer 150, the relative channel length of the first channel layer 120 can be increased, thereby reducing the short channel effect of the first transistor 130.

[0055] In some embodiments, the first metal oxide layer may be absent, and the first dielectric layer 150 is located between the first channel layer 120 and the second channel layer 220 , thereby preventing carrier transmission between the first channel layer 120 and the second channel layer 220 and preventing abnormal performance of the first transistor 130 .

[0056] In some embodiments, the material of the first dielectric layer 150 may be a material with a high dielectric constant such as hafnium oxide. By setting the material of the first dielectric layer 150 to be a material with a high dielectric constant such as hafnium oxide, the leakage current between the first metal oxide layer 140 and the first channel layer 120 can be reduced.

[0057] In some embodiments, the second metal oxide layer 240 surrounds the second channel layer 220, and the second bit line 210 surrounds the second metal oxide layer 240. Providing the second metal oxide layer 240 surrounding the second channel layer 220 can increase the contact area between the second metal oxide layer 240 and the second channel layer 220. By having the second bit line 210 surround the second metal oxide layer 240, the contact area between the second bit line 210 and the second metal oxide layer 240 can be increased, thereby reducing the contact resistance between the second metal oxide layer 240 and the second channel layer 220. This can also reduce the contact resistance between the second bit line 210 and the second metal oxide layer 240, thereby improving the performance of the memory cell.

[0058] In some embodiments, the second transistor 230 further includes a second dielectric layer 250, which is located between the second word line 200 and the second channel layer 220. The second dielectric layer 250 can prevent direct contact between the second word line 200 and the second channel layer 220, thereby preventing carriers on the second channel layer 220 from flowing directly to the second word line 200.

[0059] In some embodiments, the second dielectric layer 250 may be made of a material with a high dielectric constant, such as hafnium oxide. By setting the second dielectric layer to be made of a material with a high dielectric constant, such as hafnium oxide, leakage current between the second word line 200 and the second channel layer 220 can be reduced.

[0060] It should be noted that the dielectric constant here refers to: relative dielectric constant, with the value of the absolute dielectric constant of free space or vacuum being considered as the standard. The relative dielectric constant refers to the ratio of the absolute dielectric constant of any material to the absolute dielectric constant of free space or vacuum.

[0061] In some embodiments, it may also include: a first insulating layer 160, the first insulating layer 160 is located between the second word line 200 and the first word line 100, for isolating the second word line 200 from the first word line 100, and the first insulating layer 160 is also located between the second word line 200 and the first bit line 110, for isolating the second word line 200 from the first bit line 110, and the first insulating layer 160 is also located between the first metal oxide layer 140 and the second metal oxide layer 240, for isolating the first metal oxide layer 140 from the second metal oxide layer 240.

[0062] In some embodiments, the memory cell may further include: a second insulating layer 170, the second insulating layer 170 covering the sidewalls of the first channel layer 120 arranged along the first direction X, and the second insulating layer 170 is used to separate the first word line 100 from the first bit line 110, thereby avoiding electrical connection between the first word line 100 and the first bit line 110.

[0063] In some embodiments, the memory cell may further include: a third insulating layer 180, the third insulating layer 180 covering the bottom surface of the first word line 100, the first bit line 110 and the first channel layer 120 arranged along the third direction Z. By forming the third insulating layer 180, the first word line 100, the first bit line 110 and the first channel layer 120 can be supported.

[0064] In some embodiments, the memory cell further includes a first metal oxide layer 140 , and the third insulating layer 180 further covers the bottom surface of the first metal oxide layer 140 arranged along the third direction Z to support the first metal oxide layer 140 .

[0065] In some embodiments, the storage unit further includes: a first conductive pillar 190, the first conductive pillar 190 is in contact with the first word line 100; a second conductive pillar 260, the second conductive pillar 260 is in contact with the first bit line 110; a third conductive pillar 270, the third conductive pillar 270 is in contact with the second bit line 210, and data information is provided to the first word line 100, the first bit line 110 and the second bit line 210 respectively through the first conductive pillar 190, the second conductive pillar 260 and the third conductive pillar 270, or the data information in the first word line 100, the first bit line 110 and the second bit line 210 is led out.

[0066] In some embodiments, the second conductive pillar 260 also passes through the second bit line 210 and is connected to the first bit line 110. A fourth insulating layer 280 is also included between the second conductive pillar 260 and the second bit line 210. The fourth insulating layer 280 can prevent the second conductive pillar 260 from being electrically connected to the second bit line 210.

[0067] In the embodiment of the present disclosure, the second transistor 230 is used as a write transistor and the first transistor 130 is used as a read transistor, wherein the second word line 200 can serve as the gate of the second transistor 230. When an electrical signal is input to the second word line 200, the second word line 200 is turned on, and the signal on the second bit line 210 can be transmitted to the second channel layer 220, so that the second channel layer 220 can control the first channel layer 120 of the first transistor 130 to transmit signals, thereby enabling signals to be transmitted between the first bit line 110 and the first word line 100. When a signal can be read from between the first bit line 110 and the first word line 100, it indicates that data information is stored in the storage unit.

[0068] Another embodiment of the present disclosure further provides a semiconductor structure, which includes multiple storage units such as some or all of the above-mentioned embodiments. The semiconductor structure provided by another embodiment of the present disclosure will be described below with reference to the accompanying drawings. It should be noted that the parts that are the same or corresponding to the above-mentioned embodiments can refer to the corresponding description of the above-mentioned embodiments and will not be repeated below.

[0069] refer to Figure 4 and Figure 5 , Figure 5 for Figure 4 Cross-section along CC direction.

[0070] In some embodiments, the semiconductor structure includes: a plurality of memory cells as described in some or all of the above embodiments, and the plurality of memory cells are arranged at intervals along the first direction X and the third direction Z, and the first word lines 100 of the plurality of memory cells are located on the same side of the second word lines 200 along the second direction Y.

[0071] By providing multiple memory cells, with the first word lines 100 of the multiple memory cells located on the same side of the second word line 200 along the second direction Y, the manufacturing process of the entire semiconductor structure can be facilitated and the morphology of the entire semiconductor structure can be improved.

[0072] In some embodiments, the semiconductor structure further includes a first conductive pillar 190, the first conductive pillar 190 being in contact with and connected to the first word line 100. The first word lines 100 of multiple memory cells are in contact with and connected to the same first conductive pillar 190. For example, in the case where the first word lines 100 of multiple memory cells are arranged at intervals along the third direction Z, the multiple first word lines 100 arranged at intervals along the third direction Z are connected via one first conductive pillar 190. For example, if a ground signal is required to be supplied to the first word line 100, the ground signal can be supplied to the first conductive pillar 190. Thus, the signals on multiple first word lines 100 can be controlled by one first conductive pillar 190.

[0073] In some embodiments, multiple memory cells are arranged at intervals along a first direction X, and the first word lines 100 of the memory cells arranged at intervals along the first direction are electrically connected to each other. In other words, applying an electrical signal to one first word line 100 effectively applies the electrical signal to all of the memory cells arranged at intervals along the first direction. In some embodiments, multiple first word lines 100 arranged at intervals along a third direction Z are connected via a first conductive pillar 190. Thus, one first conductive pillar 190 effectively communicates with the first word lines 100 of multiple memory cells arranged along both the first direction X and the third direction Z.

[0074] In some embodiments, the first word lines 100 of the memory cells arranged at intervals along the first direction may be an integrated structure, and the first bit lines 110 of the memory cells arranged at intervals along the first direction may be an integrated structure.

[0075] In some embodiments, the semiconductor device may further include: a second conductive pillar 260, wherein the second conductive pillar 260 is in contact with and connected to a first bit line 110; and a third conductive pillar 270, wherein the third conductive pillar 270 is in contact with and connected to a second bit line 210. The second conductive pillars 260 connected to different first bit lines 110 are adjacent to each other along the first direction X, and the third conductive pillars 270 connected to different second bit lines 210 are adjacent to each other along the first direction X. An electrical signal is fed to the first bit line 110 or an electrical signal from the first bit line 110 is led out through the second conductive pillar 260, and an electrical signal is fed to the second bit line 210 or an electrical signal from the second bit line 210 is led out through the third conductive pillar 270. Arranging the second conductive pillars 260 connected to different first bit lines 110 and the third conductive pillars 270 connected to different second bit lines 210 adjacent to each other along the first direction X facilitates the processing steps of the entire semiconductor structure.

[0076] In some embodiments, the second conductive pillars 260 connected to different memory cells are spaced apart from each other, and the third conductive pillars 270 connected to different memory cells are spaced apart from each other.

[0077] In some embodiments, the memory device may further include: a second conductive pillar 260 , which is in contact with and connected to a first bit line 110 ; and a third conductive pillar 270 , which is in contact with and connected to a second bit line 210 . The second conductive pillar 260 and the third conductive pillar 270 are arranged alternately along the first direction X. An electrical signal is fed into the first bit line 110 or an electrical signal from the first bit line 110 is extracted through the second conductive pillar 260 . An electrical signal is fed into the second bit line 210 or an electrical signal from the second bit line 210 is extracted through the third conductive pillar 270 . By arranging the second conductive pillar 260 and the third conductive pillar 270 alternately along the first direction X, the second conductive pillar 260 can be formed per memory cell, facilitating inspection of each memory cell.

[0078] In some embodiments, the first word lines 100 of the memory cells arranged at intervals along the first direction X are an integrated structure, and the first bit lines 110 of the memory cells arranged at intervals along the first direction X are an integrated structure. Part of the second conductive pillars 260 also penetrate the first bit lines 110 and the second bit lines 210 of part of other memory cells, and a fourth insulating layer 280 is further present between the part of the second conductive pillars 260 and the first bit lines 110 and the second bit lines 210 of the other memory cells, thereby preventing electrical connection between the second conductive pillars 260 and the first bit lines 110 and the second bit lines 210 of the other memory cells; part of the third conductive pillars 270 also penetrate the first bit lines 110 and the second bit lines 210 of part of other memory cells, and a fourth insulating layer 280 is further present between the part of the third conductive pillars 270 and the first bit lines 110 and the second bit lines 210 of the other memory cells, thereby preventing electrical connection between the third conductive pillars 270 and the first bit lines 110 and the second bit lines 210 of the other memory cells.

[0079] For example, the semiconductor structure includes two memory cells arranged along a third direction, namely a first memory cell and a second memory cell. The first memory cell is located above the second memory cell. Therefore, the second conductive column 260 connected to the second memory cell also passes through the first bit line 110 and the second bit line 210 of the first memory cell. Therefore, there is a fourth insulating layer 280 between the second conductive column 260 connected to the second memory cell and the first bit line 110 and the second bit line 210 of the first memory cell, thereby avoiding electrical connection between the first bit line 110 and the second bit line 210 of the first memory cell and the second memory cell.

[0080] In some embodiments, the second word lines 200 of the memory cells arranged along the third direction Z are connected to each other; in some embodiments, the second word lines 200 of the memory cells arranged along the third direction Z can be an integrated structure; in some embodiments, the second dielectric layer 250 of the memory cells arranged along the third direction Z can be an integrated structure.

[0081] Another embodiment of the present disclosure further provides a method for manufacturing a storage unit, which can be used to manufacture the above-mentioned storage unit. The method for manufacturing a storage unit provided by another embodiment of the present disclosure will be described below in conjunction with the accompanying drawings. It should be noted that for the same or corresponding parts as the above-mentioned embodiments, reference can be made to the corresponding descriptions of the above-mentioned embodiments, and will not be repeated below.

[0082] refer to Figures 6 to 32 , Figures 6 to 32 A schematic structural diagram corresponding to each step of a method for manufacturing a storage unit provided in one embodiment of the present disclosure.

[0083] In some embodiments, a method for manufacturing a memory cell may include: forming a first transistor 130, the first transistor 130 including: a first word line 100 extending along a first direction X, a first bit line 110 extending along the first direction X, the first bit line 110 and the first word line 100 being arranged along a second direction Y, and the first bit line 110 being spaced apart from the first word line 100, a first channel layer 120, the first channel layer 120 being located between the first bit line 110 and the first word line 100, and being in contact with the first bit line 110 and the first word line 100, respectively; forming a second Transistor 230, the second transistor 230 includes: a second word line 200 extending along the third direction Z, a second channel layer 220 extending along the third direction Z, the second channel layer 220 is arranged opposite to the second word line 200, the second channel layer 220 controls the conduction and disconnection of the transmission path between the first word line 100 and the first bit line 110, and a second bit line 210, the second bit line 210 is located on at least one side of the second word line 200 along the second direction Y, and is electrically connected to the second channel layer 220, and is spaced apart from the first word line 100 and the first bit line 110 in the third direction Z.

[0084] By forming a first transistor 130, it can be used as a read transistor, and by forming a second transistor 230, it can be used as a write transistor, wherein the second word line 200 can be used as the gate of the second transistor 230. When an electrical signal is input to the second word line 200, the second word line 200 is turned on, and the signal on the second bit line 210 can be transmitted to the second channel layer 220, so that the second channel layer 220 can control the first channel layer 120 of the first transistor 130 to transmit signals, so that signals can be transmitted between the first bit line 110 and the first word line 100. When a signal can be read from between the first bit line 110 and the first word line 100, it indicates that data information is stored in the storage unit.

[0085] refer to Figures 6 to 16 In some embodiments, a method for forming the second transistor 230 may include: providing a stacked structure 290, the stacked structure 290 including a first sacrificial layer 291, a second sacrificial layer 292, a first insulating layer 160, and a third sacrificial layer 293 stacked in sequence; etching the stacked structure 290 to form a first recess 300 penetrating the stacked structure 290; forming a second channel layer 220, the second channel layer 220 covering an inner wall of the first recess 300; forming a second word line 200, the second word line 200 being located within the first recess 300 and completely filling the first recess 300; removing the third sacrificial layer 293, and forming a second bit line 210, the second bit line 210 being located on a top surface of the first insulating layer 160 and electrically connected to the second channel layer 220. By forming the stacked structure first, film deformation can be avoided when forming the second channel layer 220, the second word line 200, and the second bit line 210, thereby improving the quality of the formed second transistor 230.

[0086] refer to Figure 6 , providing a stacked structure 290. In some embodiments, the materials of the first sacrificial layer 291, the second sacrificial layer 292, the first insulating layer 160 and the third sacrificial layer 293 can be different from each other, so that they will not affect each other when the various film layers are subsequently etched, thereby improving the reliability of the formed semiconductor structure.

[0087] In some embodiments, the material of the first sacrificial layer 291 may include silicon oxyfluoride, the material of the second sacrificial layer 292 may include polysilicon, and the material of the third sacrificial layer 293 may include silicon nitride.

[0088] refer to Figures 7 to 10 ,in, Figure 8 for Figure 7 Cross-section along DD direction, Figure 10 for Figure 9Cross-sectional view along the DD direction. Before forming the first channel layer, the process further includes: etching the exposed second sacrificial layer 292 and third sacrificial layer 293 along the first groove 300 to form a third groove 310, wherein the third groove 310 exposes a portion of the top surface of the first insulating layer 160 and the first sacrificial layer 291; forming a first metal oxide layer 140, wherein the first metal oxide layer 140 is located in the third groove 310 between the second sacrificial layer 292 and the second channel layer 220; and forming a second metal oxide layer 240, wherein the second metal oxide layer 240 is located in the third groove 310 on the top surface of the first insulating layer 160. The formation of the third groove 310 provides a process basis for forming the first metal oxide layer 140 and the second metal oxide layer 240. By forming the first metal oxide layer 140, when the signal of the second bit line 210 is transmitted through the second channel layer 220, it is first transmitted into the first metal oxide layer 140. At this time, the first metal oxide layer 140 serves as the gate of the first transistor 130, and then controls the first channel layer 120 of the first transistor 130 to be turned on, thereby turning on the transmission path between the first bit line 110 and the first word line 100. By forming the second metal oxide layer 240, and the second metal oxide layer is connected to the second bit line 210 and the second channel layer 220 respectively, a direct connection between the second bit line 210 and the second channel layer 220 can be avoided, and a large difference in material properties between the second bit line 210 and the second channel layer 220 can be avoided, thereby avoiding abnormal signal transmission.

[0089] In some embodiments, before forming the second channel layer 220, the process may further include: etching the first sacrificial layer 291 exposed along the first groove, so that when the second word line 200 is subsequently formed, the width of the second word line 200 on the same layer as the first sacrificial layer 291 is greater than the width of the second word line 200 on the same layer as the first insulating layer 160, thereby increasing the contact area of ​​the second word line of the storage unit arranged along the third direction.

[0090] refer to Figure 11 and Figure 12 , Figure 12 for Figure 11 A cross-sectional view along the DD direction; after forming the second channel layer 220 and before forming the second word line 200, it also includes: forming a second dielectric layer 250, by forming the second dielectric layer 250 can avoid the carriers in the second channel layer 220 flowing directly to the second word line 200, avoiding the abnormality of the second transistor 230.

[0091] refer to Figure 13 and Figure 14 , Figure 14 for Figure 13 A cross-sectional view along the DD direction; removing the third sacrificial layer 293 , which provides a process basis for the subsequent formation of the second bit line 210 .

[0092] refer to Figure 15 and Figure 16 , Figure 16 for Figure 15 A cross-sectional view along the DD direction; a second bit line 210 is formed.

[0093] refer to Figures 17 to 26 The method for forming the first transistor 130 includes: removing the second sacrificial layer 292 to form a second groove 320; forming a first channel layer 120, wherein the first channel layer 120 is located in the second groove 320; forming a first word line 100 and a first bit line 110, wherein the first word line 100 and the first bit line 110 are located in the second groove 320, and the first word line 100 and the first bit line 110 are arranged at intervals along the second direction Y, and the first word line 100 and the first bit line 110 are both in contact with and connected to the first channel layer 120.

[0094] refer to Figure 17 and Figure 18 , Figure 18 for Figure 17 The second sacrificial layer 292 is removed to form a second groove 320 .

[0095] refer to Figure 19 and Figure 20 , Figure 20 for Figure 19 Cross-sectional view along the DD direction; in some embodiments, before forming the first channel layer 120, the process further includes: forming a first dielectric layer 150. By forming the first dielectric layer 150, the carriers of the first channel layer 120 can be prevented from flowing directly to the second channel layer.

[0096] In some embodiments, a first metal oxide layer 140 is further formed, and the first dielectric layer 150 further covers the sidewalls of the first metal oxide layer.

[0097] After forming the first dielectric layer 150 , the first channel layer 120 is formed.

[0098] refer to Figures 21 to 24 ,in Figure 22 for Figure 20 Cross-section along DD direction, Figure 24 for Figure 23 Cross-sectional view along the DD direction; in some embodiments, before forming the first word line 100 and the first bit line 110, the process further includes forming a second insulating layer 170, where the second insulating layer 170 covers the sidewalls of the first channel layer 120 arranged along the first direction X. Forming the second insulating layer 170 can prevent electrical contact between the subsequently formed first word line 100 and the first bit line 110, thereby improving the reliability of the formed semiconductor structure.

[0099] In some embodiments, a method of forming the second insulating layer 170 includes: forming a second preliminary insulating layer 171, wherein the second preliminary insulating layer 171 completely fills the second groove 320, and etching the second preliminary insulating layer 171 to expose sidewalls of the first channel layer 120 arranged along the second direction Y. By first forming the second preliminary insulating layer 171 to completely fill the second groove 320 and then etching, the reliability of the formed second insulating layer 170 can be improved.

[0100] refer to Figure 25 and Figure 26 ,in Figure 26 for Figure 25 A cross-sectional view along the DD direction; a first word line 100 and a first bit line 110 are formed.

[0101] refer to Figures 27 to 30 ,in Figure 28 for Figure 27 Cross-section along DD direction, Figure 30 for Figure 29 Cross-sectional view along direction DD; in some embodiments, after forming the second transistor 230, the process may further include forming a third insulating layer 180, where the third insulating layer 180 covers the bottom surface of the first word line 100, the first bit line 110, and the first channel layer 120 arranged along the third direction Z. Forming the third insulating layer 180 allows for spacing between different memory cells when forming multiple memory cells.

[0102] refer to Figure 31 and Figure 32 ,in Figure 32 for Figure 31 Cross-sectional view along direction DD; in some embodiments, the second bit line 210 is also etched.

[0103] refer to Figure 1 and Figure 2 After etching the second bit lines 210 , a fifth insulating layer 330 will be formed. The fifth insulating layer 330 can also support other second transistors 230 arranged along the third direction Z.

[0104] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present disclosure, and in actual applications, various changes may be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the scope of protection of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A storage unit, characterized in that: include: a first word line extending along a first direction; a first bit line extending along the first direction, the first bit line and the first word line being arranged along the second direction, and the first bit line and the first word line being spaced apart; a first channel layer, the first channel layer being located between the first bit line and the first word line and being electrically connected to the first bit line and the first word line, respectively; and a first transistor comprising: the first word line, the first bit line, and the first channel layer; a second word line extending along a third direction; a second channel layer extending along the third direction, the second channel layer being arranged opposite to the second word line, and controlling the conduction and disconnection of a transmission path between the first word line and the first bit line; A second bit line, the second bit line is located at least on one side of the second word line along the second direction and is electrically connected to the second channel layer, the second bit line is spaced apart from the first word line and the first bit line in the third direction, and the second transistor includes: the second word line, the second channel layer and the second bit line.

2. The storage unit according to claim 1, wherein The first transistor further includes: a first metal oxide layer, the first metal oxide layer being in contact with and connected to the second channel layer and disposed opposite to the first channel layer; The second transistor further includes a second metal oxide layer, the second metal oxide layer is contact-connected to the second channel layer and the second bit line, and the second metal oxide layer is spaced apart from the first metal oxide layer.

3. The storage unit according to claim 2, wherein: The first metal oxide layer surrounds the second channel layer. The first transistor further includes a first dielectric layer, wherein the first dielectric layer surrounds the first metal oxide layer, and the first channel layer surrounds the first dielectric layer.

4. The storage unit according to claim 2, wherein: The second metal oxide layer surrounds the second channel layer, and the second bit line surrounds the second metal oxide layer. The storage unit according to claim 1 , wherein: The second transistor further includes: A second dielectric layer is located between the second word line and the second channel layer.

6. A semiconductor structure, characterized in that The memory cell comprises a plurality of memory cells as claimed in any one of claims 1 to 5, wherein the plurality of memory cells are arranged at intervals along the first direction and the third direction, and the first word lines of the plurality of memory cells are located on the same side of the second word lines along the second direction.

7. The semiconductor structure according to claim 6, wherein: Also includes: A first conductive pillar is in contact with and connected to the first word line, and the first word lines of a plurality of the memory cells are in contact with and connected to the same first conductive pillar.

8. The semiconductor structure according to claim 6, wherein: Also includes: a second conductive pillar, wherein the second conductive pillar is in contact with and connected to the first bit line; A third conductive pillar is in contact with and connected to a second bit line, the second conductive pillars connected to different first bit lines are adjacent to each other along the first direction, and the third conductive pillars connected to different second bit lines are adjacent to each other along the first direction.

9. The semiconductor structure according to claim 6, wherein: Also includes: a second conductive pillar, wherein the second conductive pillar is in contact with and connected to the first bit line; A third conductive pillar is connected to the second bit line, and the second conductive pillar and the third conductive pillar are arranged alternately along the first direction.

10. A method for manufacturing a storage unit, characterized in that: include: forming a first transistor, the first transistor comprising: a first word line extending along a first direction, a first bit line extending along the first direction, the first bit line and the first word line being arranged along a second direction and spaced apart from each other, and a first channel layer, the first channel layer being located between the first bit line and the first word line and being in contact with and connected to the first bit line and the first word line, respectively; A second transistor is formed, the second transistor comprising: a second word line extending along a third direction, a second channel layer extending along the third direction, the second channel layer being arranged opposite to the second word line, the second channel layer controlling the conduction and disconnection of a transmission path between the first word line and the first bit line, a second bit line, the second bit line being located at least on one side of the second word line along the second direction and being electrically connected to the second channel layer, the second bit line being spaced apart from the first word line and the first bit line in the third direction.

11. The method for manufacturing a memory cell according to claim 10, wherein: The method of forming the second transistor includes: Providing a stack structure, the stack structure comprising a first sacrificial layer, a second sacrificial layer, a first insulating layer, and a third sacrificial layer stacked in sequence; Etching the stack structure to form a first groove penetrating the stack structure; forming a second channel layer, wherein the second channel layer covers an inner wall of the first groove; forming a second word line, wherein the second word line is located in the first groove and completely fills the first groove; The third sacrificial layer is removed, and the second bit line is formed. The second bit line is located on a top surface of the first insulating layer, and the second bit line is electrically connected to the second channel layer.

12. The method for manufacturing a memory cell according to claim 11, wherein: The method of forming the first transistor includes: removing the second sacrificial layer to form a second groove; forming the first channel layer, wherein the first channel layer is located in the second groove; The first word line and the first bit line are formed, the first word line and the first bit line are located in the second groove, the first word line and the first bit line are arranged at intervals along the second direction, and the first word line and the first bit line are both in contact with the first channel layer.

13. The method for manufacturing a memory cell according to claim 12, wherein: Before forming the first word line and the first bit line, the method further includes: A second insulating layer is formed, where the second insulating layer covers sidewalls of the first channel layer arranged along the first direction.

14. The method for manufacturing a memory cell according to claim 13, wherein: The method of forming the second insulating layer includes: forming a second initial insulating layer, wherein the second initial insulating layer completely fills the second groove; The second initial insulating layer is etched to expose sidewalls of the first channel layer arranged along the second direction.

15. The method for manufacturing a memory cell according to claim 11, wherein: Before forming the first channel layer, the method further includes: Etching the exposed second sacrificial layer and the third sacrificial layer along the first groove to form a third groove, wherein the third groove exposes a portion of the top surface of the first insulating layer and the first sacrificial layer; forming a first metal oxide layer, wherein the first metal oxide layer is located in the third groove between the second sacrificial layer and the second channel layer; A second metal oxide layer is formed, where the second metal oxide layer is located in the third groove on the top surface of the first insulating layer.

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