Semiconductor device and manufacturing method thereof

Abstract

The present disclosure provides a semiconductor device and a method for manufacturing the same. The method comprises: providing a first substrate and a first conductive line disposed on the first substrate; sequentially forming a first dielectric layer and a second dielectric layer on the first substrate; wherein the dielectric constant of the first dielectric layer is smaller than the dielectric constant of the second dielectric layer, and the strength of the second dielectric layer is greater than the strength of the first dielectric layer; forming a first trench that sequentially penetrates the second dielectric layer and the first dielectric layer and exposes the first conductive line; forming a second trench in the second dielectric layer at a position corresponding to the first trench; wherein the dimension of the second trench in a direction parallel to the first substrate is larger than the dimension of the first trench in a direction parallel to the first substrate.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly, to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Under the premise of certain process capabilities, in order to improve the integration density per unit area within the chip, the chip's memory array (array) and peripheral circuit (CMOS) can be processed separately on two wafers, and then wafer-to-wafer bonding is performed to form a three-dimensional chip, such as 3D Dynamic Random Access Memory (3D DRAM).

[0003] However, there are still many problems to be solved in the three-dimensional chips formed by bonding. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same.

[0005] To achieve the above objectives, the technical solution of the present disclosure is implemented as follows:

[0006] In a first aspect, an embodiment of the present disclosure provides a method for manufacturing a semiconductor device, the method comprising:

[0007] Providing a first substrate and a first conductive line disposed on the first substrate;

[0008] forming a first dielectric layer and a second dielectric layer in sequence on the first substrate; wherein the dielectric constant of the first dielectric layer is smaller than the dielectric constant of the second dielectric layer, and the strength of the second dielectric layer is greater than the strength of the first dielectric layer;

[0009] forming a first trench that sequentially penetrates the second dielectric layer and the first dielectric layer and exposes the first conductive line;

[0010] A second trench is formed in the second dielectric layer at a position corresponding to the first trench; wherein a dimension of the second trench in a direction parallel to the first substrate is larger than a dimension of the first trench in a direction parallel to the first substrate.

[0011] In some embodiments, forming a second trench in the second dielectric layer at a position corresponding to the first trench includes:

[0012] Corresponding to the position of the first trench, a portion of the second dielectric layer is etched to form a second trench; wherein the height of the second trench in a direction perpendicular to the first substrate is smaller than the height of the second dielectric layer in a direction perpendicular to the first substrate.

[0013] In some embodiments, the second dielectric layer includes a first dielectric sublayer and a second dielectric sublayer, and the strength of the first dielectric sublayer and the second dielectric sublayer is greater than that of the first dielectric layer. The sequentially forming the first dielectric layer and the second dielectric layer on the first substrate includes:

[0014] A first dielectric layer, a first dielectric sublayer and a second dielectric sublayer are sequentially formed on the first substrate.

[0015] In some embodiments, forming a first trench that sequentially penetrates the second dielectric layer and the first dielectric layer and exposes the first conductive line includes:

[0016] A first trench is formed, which sequentially penetrates the second dielectric sub-layer, the first dielectric sub-layer, and the first dielectric layer and exposes the first conductive line.

[0017] In some embodiments, forming a second trench in the second dielectric layer at a position corresponding to the first trench includes:

[0018] Corresponding to the position of the first groove, a second groove is etched to penetrate the second dielectric sublayer and expose the surface of the first dielectric sublayer; wherein the first dielectric sublayer serves as an etching stop layer; and the height of the second groove in a direction perpendicular to the first substrate is the same as the height of the second dielectric sublayer in a direction perpendicular to the first substrate.

[0019] In some embodiments, after forming the second trench in the second dielectric layer at a position corresponding to the first trench, the manufacturing method further includes:

[0020] A conductive material is filled in the first trench and the second trench to form a first conductive pillar; wherein the first conductive pillar includes a first sub-conductive pillar located in the first trench and a second sub-conductive pillar located in the second trench; the first substrate, the first conductive line, the first dielectric layer, the second dielectric layer and the first conductive pillar together form a first semiconductor structure.

[0021] In some embodiments, the manufacturing method further comprises:

[0022] forming a second semiconductor structure, the second semiconductor structure comprising a second substrate, a second conductive line disposed on the second substrate, a third dielectric layer and a fourth dielectric layer sequentially disposed on the second substrate and covering the second conductive line, and a second conductive pillar penetrating the fourth dielectric layer and the third dielectric layer; wherein the dielectric constant of the third dielectric layer is smaller than the dielectric constant of the fourth dielectric layer, and the strength of the fourth dielectric layer is greater than the strength of the third dielectric layer;

[0023] The first semiconductor structure and the second semiconductor structure are bonded; wherein the first conductive pillars and the second conductive pillars are connected in a one-to-one correspondence.

[0024] In a second aspect, an embodiment of the present disclosure provides a semiconductor device, comprising: a first semiconductor structure; the first semiconductor structure comprising:

[0025] a first substrate and a first conductive line provided on the first substrate;

[0026] a first dielectric layer and a second dielectric layer sequentially located on the first substrate and covering the first conductive line; the dielectric constant of the first dielectric layer is smaller than the dielectric constant of the second dielectric layer, and the strength of the second dielectric layer is greater than the strength of the first dielectric layer;

[0027] A first conductive column extends through the second dielectric layer and the first dielectric layer, wherein the first conductive column includes a first sub-conductive column located in the first dielectric layer and a second sub-conductive column located in the second dielectric layer; a size of the second sub-conductive column in a direction parallel to the first substrate is larger than a size of the first sub-conductive column in a direction parallel to the first substrate.

[0028] In some embodiments, the semiconductor device further includes: a second semiconductor structure bonded to the first semiconductor structure; the second semiconductor structure includes:

[0029] a second substrate and a second conductive line provided on the second substrate;

[0030] a third dielectric layer and a fourth dielectric layer sequentially located on the second substrate and covering the second conductive line; the dielectric constant of the third dielectric layer is smaller than the dielectric constant of the fourth dielectric layer, and the strength of the fourth dielectric layer is greater than the strength of the third dielectric layer;

[0031] A second conductive pillar extends through the fourth dielectric layer and the third dielectric layer, wherein the second conductive pillar includes a third sub-conductive pillar located in the third dielectric layer and a fourth sub-conductive pillar located in the fourth dielectric layer; a dimension of the fourth sub-conductive pillar in a direction parallel to the second substrate is greater than a dimension of the third sub-conductive pillar in a direction parallel to the second substrate.

[0032] In some embodiments, the second dielectric layer includes a first dielectric sublayer and a second dielectric sublayer, the first dielectric sublayer is located between the first dielectric layer and the second dielectric sublayer; the strength of the first dielectric sublayer and the second dielectric sublayer is greater than the strength of the first dielectric layer; the height of the second sub-conductive pillar in a direction perpendicular to the first substrate is the same as the height of the second dielectric sublayer in a direction perpendicular to the first substrate;

[0033] The fourth dielectric layer includes a third dielectric sublayer and a fourth dielectric sublayer, the third dielectric sublayer is located between the third dielectric layer and the fourth dielectric sublayer; the strength of the third dielectric sublayer and the fourth dielectric sublayer is greater than the strength of the third dielectric layer; the height of the fourth sub-conductive column in a direction perpendicular to the second substrate is the same as the height of the fourth dielectric sublayer in a direction perpendicular to the second substrate.

[0034] The present disclosure provides a semiconductor device and a method for manufacturing the same. In the present disclosure, a first trench is formed in a first dielectric layer, and a second trench is formed in a second dielectric layer. The dielectric constant of the first dielectric layer is smaller than that of the second dielectric layer, and the strength of the second dielectric layer is greater than that of the first dielectric layer. Because the size of the first trench is smaller than that of the second trench, after the first and second trenches are subsequently filled, the dielectric constant of the first dielectric layer surrounding the first trench is even smaller, thereby effectively reducing signal transmission loss. Furthermore, the strength of the second dielectric layer surrounding the second trench is even greater, thereby effectively improving high-temperature reliability during subsequent bonding processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 A schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0036] Figures 2A to 2F A schematic diagram of a cross-sectional structure of a semiconductor device during a manufacturing process provided by an embodiment of the present disclosure;

[0037] Figures 3A to 3F A schematic cross-sectional view of another semiconductor device during the manufacturing process provided by an embodiment of the present disclosure;

[0038] Figure 4A A schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure;

[0039] Figure 4B A schematic cross-sectional structure diagram of another semiconductor device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0040] The following will clearly and completely describe the technical solutions in the embodiments of the present disclosure in conjunction with the embodiments of the present disclosure and the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0041] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0042] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0043] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part exists in the present disclosure.

[0044] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0045] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0046] In order to fully understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may also have other implementation methods.

[0047] In order to ensure the bonding strength between the memory array wafer and the peripheral circuit wafer in the stacked structure formed by bonding, a higher-strength material is needed to manufacture the insulating layer at the bonding interface. However, a large number of high-speed communication signals need to be transmitted through the bonding interface, and the dielectric constant of the insulating layer at the bonding interface will directly affect the transmission loss of the signal within the entire chip. Therefore, it is necessary to use a material with a lower dielectric constant to manufacture the insulating layer at the bonding interface. Therefore, in the stacked structure formed by bonding the memory array wafer and the peripheral circuit wafer, there are still many problems to be solved.

[0048] In view of this, embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same.

[0049] refer to Figure 1 , Figure 1 Schematic diagram of the process of manufacturing a semiconductor device according to an embodiment of the present disclosure. Figure 1As shown, an embodiment of the present disclosure provides a method for manufacturing a semiconductor device, the manufacturing method comprising:

[0050] Step S101: providing a first substrate and a first conductive line disposed on the first substrate;

[0051] Step S102: forming a first dielectric layer and a second dielectric layer in sequence on a first substrate; wherein the dielectric constant of the first dielectric layer is smaller than the dielectric constant of the second dielectric layer, and the strength of the second dielectric layer is greater than the strength of the first dielectric layer;

[0052] Step S103: forming a first trench that sequentially penetrates the second dielectric layer and the first dielectric layer and exposes the first conductive line;

[0053] Step S104: forming a second trench in the second dielectric layer at a position corresponding to the first trench; wherein a dimension of the second trench in a direction parallel to the first substrate is larger than a dimension of the first trench in the direction parallel to the first substrate.

[0054] refer to Figures 2A to 2F , Figures 2A to 2F A schematic diagram of the cross-sectional structure of a semiconductor device during the manufacturing process provided by the embodiment of the present disclosure. Figure 1 and Figures 2A to 2F , describing in detail the manufacturing process of the semiconductor device provided by the embodiment of the present disclosure.

[0055] like Figure 2A As shown, in step S101 , a first substrate 200 and a first conductive line 202 provided on the first substrate 200 are provided.

[0056] Here, a memory array may be formed on the first substrate 200; alternatively, peripheral circuits may also be formed on the first substrate 200. For example, the memory cell array may be a DRAM memory cell array. First conductive lines 202 disposed on the first substrate 200 may be used to extract electrical signals from the memory array or peripheral circuits on the first substrate 200. Figure 2A Multiple first conductive lines 202 are shown, and the multiple first conductive lines 202 are located in the same layer. In fact, the embodiment of the present disclosure has no special limitation on the number of first conductive lines 202 and the number of layers of first conductive lines 202, and can be flexibly selected according to actual conditions.

[0057] Here, the first substrate 200 can be a semiconductor substrate; specifically, it includes at least one elemental semiconductor material (for example, a silicon (Si) substrate, a germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (for example, a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material or other semiconductor materials known in the art, and may also include other substrates containing semiconductor materials, such as a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, a polycrystalline semiconductor layer on an insulating layer, a silicon-germanium substrate, etc.

[0058] Here, the material of the first conductive line 202 can be any conductive material. The embodiment of the present disclosure has no special limitation on the material of the first conductive line 202.

[0059] like Figure 2A As shown, in step S102, a first dielectric layer 204 and a second dielectric layer 206 are sequentially formed on the first substrate 200, wherein the first dielectric layer 204 covers the first substrate 200 and the first conductive line 202, and the second dielectric layer 206 covers the first dielectric layer 204; wherein the dielectric constant of the first dielectric layer 204 is smaller than the dielectric constant of the second dielectric layer 206, and the strength of the second dielectric layer 206 is greater than the strength of the first dielectric layer 204.

[0060] Here, the process of forming the first dielectric layer 204 and the second dielectric layer 206 may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0061] Here, the material of the first dielectric layer 204 may include a low dielectric constant material, and the material of the second dielectric layer 206 may include a high-strength material. It should be noted that strength refers to the compressive strength or fracture strength of the material, that is, the compressive strength (or fracture strength) of the second dielectric layer is greater than the compressive strength (or fracture strength) of the first dielectric layer.

[0062] In one embodiment, the material of the first dielectric layer 204 may include low-k silicon oxide, and the material of the second dielectric layer 206 may include silicon oxide prepared from tetraethyl orthosilicate (TEOS). Thus, the chemical composition of the first dielectric layer 204 and the second dielectric layer 206 are both silicon oxide, and the contact interface between the first dielectric layer 204 and the second dielectric layer 206 is good.

[0063] like Figure 2B As shown, in step S103 , a first trench 208 is formed that sequentially penetrates the second dielectric layer 206 and the first dielectric layer 204 and exposes the first conductive line 202 .

[0064] For example, a mask layer can be formed on the second dielectric layer, and the second dielectric layer and the first dielectric layer can be sequentially etched using the opening in the mask layer to form the first trench. The mask layer can be used to achieve etching alignment and control etching depth, thereby ensuring uniform etching depth in the first trench.

[0065] Here, the width of the bottom of the first trench 208 may be smaller than the width of the first conductive line 202 . The width of the bottom of the first trench 208 refers to the width of one end of the first trench 208 close to the first substrate 200 .

[0066] Here, the process of forming the first trench 208 may include, but is not limited to, wet etching, dry etching, or a combination thereof.

[0067] like Figure 2C As shown, in step S104, a second trench 210 is formed in the second dielectric layer 206 at a position corresponding to the first trench 208; more specifically, a portion of the second dielectric layer 206 is etched corresponding to the position of the first trench 208 to form the second trench 210; wherein the dimension of the second trench 210 in a direction parallel to the first substrate 200 is larger than the dimension of the first trench 208 in a direction parallel to the first substrate 200, and the height of the second trench 210 in a direction perpendicular to the first substrate 200 is smaller than the height of the second dielectric layer 206 in a direction perpendicular to the first substrate 200.

[0068] Here, corresponding to the position of the first trench 208 , the etching time can be controlled so that the etching depth of the second dielectric layer 206 is smaller than the height of the second dielectric layer 206 . Therefore, the bottom of the second trench 210 formed by etching is located in the second dielectric layer 206 , that is, the transition position between the first trench 208 and the second trench 210 is located in the second dielectric layer 206 .

[0069] In a specific embodiment, the height of the second trench 210 in a direction perpendicular to the first substrate 200 is H1, the height of the second dielectric layer 206 in a direction perpendicular to the first substrate 200 is H2, and the ratio between the difference between the heights of the second dielectric layer 206 and the second trench 210 (i.e., H2-H1) and the height of the second trench 210 (i.e., H1) ranges from 0.2 to 0.3.

[0070] Here, the second trench 210 is located in the second dielectric layer 206, wherein the width of the bottom of the second trench 210 is greater than the width of the first trench 208 at the bottom of the second trench 210, that is, the width of the bottom of the second trench 210 is greater than the width of the top of the first trench 208. In other words, there is a sudden change in width at the transition position between the first trench 208 and the second trench 210.

[0071] In the disclosed embodiment, because the first trench is smaller than the second trench, after the first and second trenches are subsequently filled, the dielectric material surrounding the first trench contributes more to the overall path transmission impedance than the dielectric material surrounding the second trench. Therefore, selecting a material with a lower dielectric constant to form the first dielectric layer surrounding the first trench can effectively reduce signal transmission loss.

[0072] In addition, in the embodiment of the present disclosure, a high temperature annealing process may be encountered in the subsequent bonding process. When the conductive material filled in the first trench and the second trench is heated, the thermal expansion coefficient (CTE) of the dielectric material is smaller than the thermal expansion coefficient of the conductive material. The transition position between the first trench and the second trench (such as Figure 2C The second dielectric layer (shown in the dashed circle) is prone to stress concentration. Therefore, selecting a stronger material to form the second dielectric layer surrounding the second trench, and more specifically, selecting a stronger second dielectric layer surrounding the transition between the first trench and the second trench, can effectively improve the reliability of the bonding structure during high-temperature annealing.

[0073] like Figure 2D As shown, after step S104, the manufacturing method further includes: filling the first trench 208 and the second trench 210 with a conductive material to form a first conductive pillar 212; wherein the first conductive pillar 212 includes a first sub-conductive pillar 214 located in the first trench 208 and a second sub-conductive pillar 216 located in the second trench 210; the first substrate 200, the first conductive line 202, the first dielectric layer 204, the second dielectric layer 206 and the first conductive pillar 212 together form a first semiconductor structure 218.

[0074] For example, a copper seed layer may be deposited into the first trench and the second trench; a copper material may be filled on the surface of the copper seed layer by electrochemical deposition (ECP), so that the copper material layer completely fills the first trench and the second trench and covers the surface of the second dielectric layer; and the copper material layer may be planarized to expose the surface of the second dielectric layer. The planarization process may include, but is not limited to, chemical mechanical polishing (CMP).

[0075] Here, the first sub-conductive pillar 214 is located between the first conductive line 202 and the second sub-conductive pillar 216, and the first sub-conductive pillar 214 is connected to the first conductive line 202. The width of the bottom of the second sub-conductive pillar 216 is greater than the width of the top of the first sub-conductive pillar 214. In other words, there is a sudden change in width at the transition position between the first sub-conductive pillar 214 and the second sub-conductive pillar 216.

[0076] Here, the height of the second sub-conductive pillar 216 in a direction perpendicular to the first substrate 200 is less than the height of the second dielectric layer 206 in a direction perpendicular to the first substrate 200. In one specific embodiment, the height of the second sub-conductive pillar 216 in a direction perpendicular to the first substrate 200 is H1, the height of the second dielectric layer 206 in a direction perpendicular to the first substrate 200 is H2, and the ratio between the difference in height between the second dielectric layer 206 and the second sub-conductive pillar 216 (i.e., H2-H1) and the height of the second sub-conductive pillar 216 (i.e., H1) ranges from 0.2 to 0.3.

[0077] Here, the embodiment of the present disclosure has no particular limitation on the conductive material filled in the first trench 208 and the second trench 210. For example, the conductive material may be copper.

[0078] In the disclosed embodiment, because the first sub-conductive pillar is smaller than the second sub-conductive pillar, the dielectric material surrounding the first sub-conductive pillar contributes more to the overall path transmission impedance than the dielectric material surrounding the second sub-conductive pillar. Therefore, selecting a material with a lower dielectric constant to form the first dielectric layer surrounding the first sub-conductive pillar can effectively reduce signal transmission loss.

[0079] In addition, in the embodiment of the present disclosure, a high temperature annealing process may be encountered during the subsequent bonding process. During the heating process of the first sub-conductive pillar and the second sub-conductive pillar, the thermal expansion coefficient of the dielectric material is smaller than the thermal expansion coefficient of the material of the first sub-conductive pillar and the second sub-conductive pillar. The transition position between the first sub-conductive pillar and the second sub-conductive pillar (such as Figure 2D The second dielectric layer (shown in the dashed circle) is prone to stress concentration. Therefore, a stronger material is selected to form the second dielectric layer surrounding the second sub-conductive pillar. More specifically, the stronger second dielectric layer is selected to surround the transition between the first and second sub-conductive pillars. This prevents the second dielectric layer from cracking due to expansion of the first or second sub-conductive pillars, thereby effectively improving the reliability of the bonding structure during high-temperature annealing.

[0080] like Figure 2EAs shown, the manufacturing method also includes: forming a second semiconductor structure 220, the second semiconductor structure 220 includes a second substrate 222, a second conductive line 224 provided on the second substrate 222, a third dielectric layer 226 and a fourth dielectric layer 228 sequentially located on the second substrate 222 and covering the second conductive line 224, and a second conductive column 234 penetrating the fourth dielectric layer 228 and the third dielectric layer 226; wherein the dielectric constant of the third dielectric layer 226 is smaller than the dielectric constant of the fourth dielectric layer 228, and the strength of the fourth dielectric layer 228 is greater than the strength of the third dielectric layer 226.

[0081] For example, a third dielectric layer 226 and a fourth dielectric layer 228 may be formed on the second substrate 222; a third trench 230 may be formed that sequentially penetrates the fourth dielectric layer 228 and the third dielectric layer 226 and exposes the second conductive line 224; a fourth trench 232 may be formed in the fourth dielectric layer 228 at a position corresponding to the third trench 230; wherein the dimension of the fourth trench 232 in a direction parallel to the second substrate 222 is greater than the dimension of the third trench 230 in a direction parallel to the second substrate 222; and the height of the fourth trench 232 in a direction perpendicular to the second substrate 222 is less than the height of the fourth dielectric layer 228 in a direction perpendicular to the second substrate 222; and a conductive material may be filled in the third trench 230 and the fourth trench 232 to form a second conductive pillar 234; wherein the second conductive pillar 234 includes a third sub-conductive pillar 236 located in the third trench 230 and a fourth sub-conductive pillar 238 located in the fourth trench 232.

[0082] Here, the process of forming the first semiconductor structure 218 and the process of forming the second semiconductor structure 220 may be the same. The detailed process of forming the second semiconductor structure can refer to the process of forming the first semiconductor structure mentioned above, and will not be repeated here.

[0083] Here, a memory array may be formed on the first substrate 200 , and a peripheral circuit may be formed on the second substrate 222 ; or, a peripheral circuit may be formed on the first substrate 200 , and a memory array may be formed on the second substrate 222 .

[0084] like Figure 2F As shown, the manufacturing method further includes: bonding the first semiconductor structure 218 and the second semiconductor structure 220; wherein the first conductive pillar 212 and the second conductive pillar 234 are connected in a one-to-one correspondence; more specifically, the second sub-conductive pillar 216 and the fourth sub-conductive pillar 238 are in direct contact.

[0085] In the embodiment of the present disclosure, the dielectric constant of the first dielectric layer (or the third dielectric layer) surrounding the first sub-conductive pillar (or the third sub-conductive pillar) is smaller, thereby effectively reducing the transmission loss of the signal. In addition, during the hybrid bonding (HB) process between the first semiconductor structure and the second semiconductor structure, a high-temperature annealing process (for example, an annealing temperature of 350°C and an annealing time of 1 hour) is required. During the heating process, the volume expansion of the first sub-conductive pillar and the second sub-conductive pillar (or the third sub-conductive pillar and the fourth sub-conductive pillar) is limited (that is, the thermal expansion coefficient of the dielectric material is smaller than the thermal expansion coefficient of the conductive material), and the transition position (such as the transition position) between the first sub-conductive pillar and the second sub-conductive pillar (or the third sub-conductive pillar and the fourth sub-conductive pillar) is limited. Figure 2F The second sub-conductive pillar (or the fourth sub-conductive pillar) is prone to stress concentration. Using a stronger second dielectric layer around the second sub-conductive pillar (or the fourth sub-conductive pillar) can effectively prevent the second dielectric layer (or the fourth dielectric layer) from being cracked by the first and second sub-conductive pillars (or the third and fourth sub-conductive pillars) during high-temperature annealing, thereby effectively improving the high-temperature reliability of the bonding structure.

[0086] In the embodiment of the present disclosure, the material of the first dielectric layer 204 is the same as the material of the third dielectric layer 226 ; the material of the second dielectric layer 206 is the same as the material of the fourth dielectric layer 228 .

[0087] For example, the materials of the first dielectric layer 204 and the third dielectric layer 226 may both include low-k silicon oxide; and the materials of the second dielectric layer 206 and the fourth dielectric layer 228 may both include silicon oxide prepared from tetraethyl orthosilicate. Here, the dielectric constant of the low-k silicon oxide is lower than the dielectric constant of the silicon oxide prepared from tetraethyl orthosilicate, and the strength of the silicon oxide prepared from tetraethyl orthosilicate is higher than that of the low-k silicon oxide.

[0088] refer to Figures 3A to 3F , Figures 3A to 3F This is a schematic diagram of the cross-sectional structure of another semiconductor device during the manufacturing process provided by the embodiment of the present disclosure. Figure 1 and Figures 3A to 3F , describing in detail the manufacturing process of the semiconductor device provided by the embodiment of the present disclosure.

[0089] like Figure 3A As shown, in step S101 , a first substrate 300 and a first conductive line 302 provided on the first substrate 300 are provided.

[0090] Here, the detailed description of the first substrate 300 and the first conductive line 302 can be referred to Figures 2A to 2FThe first substrate 300 and the first conductive line 302 in the semiconductor device are shown and are not described in detail here.

[0091] like Figure 3A As shown, the second dielectric layer 306 includes a first dielectric sublayer 340 and a second dielectric sublayer 342. Step S102 includes: sequentially forming a first dielectric layer 304, a first dielectric sublayer 340, and a second dielectric sublayer 342 on the first substrate 300, wherein the first dielectric layer 304 covers the first substrate 300 and the first conductive line 302, the first dielectric sublayer 340 covers the first dielectric layer 304, and the second dielectric sublayer 342 covers the first dielectric sublayer 340. The dielectric constant of the first dielectric layer 304 is smaller than the dielectric constants of the first dielectric sublayer 340 and the second dielectric sublayer 342, and the strength of the first dielectric sublayer 340 and the second dielectric sublayer 342 is greater than the strength of the first dielectric layer 304.

[0092] Here, the process of forming the first dielectric layer 304 , the first dielectric sub-layer 340 , and the second dielectric sub-layer 342 may include, but is not limited to, CVD, PVD, ALD, or any combination thereof.

[0093] Here, the material of the first dielectric layer 304 may include a low dielectric constant material, and the materials of the first dielectric sublayer 340 and the second dielectric sublayer 342 may include a high-strength material. The strength of the first dielectric sublayer 340 and the second dielectric sublayer 342 may both be greater than the strength of the first dielectric layer 304. It should be noted that the term "strength" refers to the compressive strength or fracture strength of the material. That is, the compressive strength (or fracture strength) of the first dielectric sublayer and the second dielectric sublayer is greater than the compressive strength (or fracture strength) of the first dielectric layer.

[0094] In a specific embodiment, the material of the first dielectric layer 304 may include silicon oxide with a low dielectric constant; the material of the first dielectric sub-layer 340 may include silicon nitride; and the material of the second dielectric sub-layer 342 may include silicon oxide prepared from tetraethyl orthosilicate.

[0095] like Figure 3B As shown, step S103 includes: forming a first trench 308 that sequentially penetrates the second dielectric sub-layer 342 , the first dielectric sub-layer 340 and the first dielectric layer 304 and exposes the first conductive line 302 .

[0096] Here, the width of the bottom of the first trench 308 is smaller than the width of the first conductive line 302. The width of the bottom of the first trench 308 refers to the width of the end of the first trench 308 close to the first substrate 300.

[0097] Here, the process of forming the first trench 308 may include, but is not limited to, wet etching, dry etching, or a combination thereof.

[0098] like Figure 3C As shown, step S104 includes: etching to form a second groove 310 corresponding to the position of the first groove 308, penetrating the second dielectric sublayer 342 and exposing the surface of the first dielectric sublayer 340; wherein the size of the second groove 310 in a direction parallel to the first substrate 300 is larger than the size of the first groove 308 in a direction parallel to the first substrate 300, and the height of the second groove 310 in a direction perpendicular to the first substrate 300 is the same as the height of the second dielectric sublayer 342 in a direction perpendicular to the first substrate 300.

[0099] Here, corresponding to the location of first trench 308, the etching process parameters can be controlled so that the etching depth of second dielectric sub-layer 342 is equal to the height of second dielectric sub-layer 342, and the etching stops at the surface of first dielectric sub-layer 340. First dielectric sub-layer 340 serves as an etch stop layer. In other words, the transition between first trench 308 and second trench 310 is located on the surface of first dielectric sub-layer 340.

[0100] In a specific embodiment, the heights of the second trench 310 and the second dielectric sublayer 342 along a direction perpendicular to the first substrate 300 are both H1, the height of the first dielectric sublayer 340 along a direction perpendicular to the first substrate 300 is H3, and the ratio between the height of the first dielectric sublayer 340 (i.e., H3) and the height of the second trench 310 (i.e., H1) ranges from 0.2 to 0.3.

[0101] Here, the second trench 310 is located in the second dielectric sub-layer 342, wherein the width of the bottom of the second trench 310 is greater than the width of the first trench 308 at the bottom of the second trench 310, that is, the width of the bottom of the second trench 310 is greater than the width of the top of the first trench 308. In other words, there is a sudden change in width at the transition position between the first trench 308 and the second trench 310.

[0102] In the disclosed embodiment, because the first trench is smaller than the second trench, after the first and second trenches are subsequently filled, the dielectric material surrounding the first trench contributes more to the overall path transmission impedance than the dielectric material surrounding the second trench. Therefore, selecting a material with a lower dielectric constant to form the first dielectric layer surrounding the first trench can effectively reduce signal transmission loss.

[0103] In addition, in the embodiment of the present disclosure, a high temperature annealing process may be encountered in the subsequent bonding process. When the conductive material filled in the first trench and the second trench is heated, the thermal expansion coefficient of the dielectric material is smaller than the thermal expansion coefficient of the conductive material. The transition position between the first trench and the second trench (such as Figure 3CThe dotted circle (shown in the middle) is prone to stress concentration. Therefore, selecting a stronger material to form the second dielectric layer surrounding the second trench, and more specifically, selecting a stronger first dielectric sub-layer and a stronger second dielectric sub-layer to surround the transition between the first trench and the second trench, can effectively improve the reliability of the bonding structure during high-temperature annealing.

[0104] like Figure 3D As shown, after step S104, the manufacturing method further includes: filling the first trench 308 and the second trench 310 with a conductive material to form a first conductive pillar 312; wherein the first conductive pillar 312 includes a first sub-conductive pillar 314 located in the first trench 308 and a second sub-conductive pillar 316 located in the second trench 310; the first substrate 300, the first conductive line 302, the first dielectric layer 304, the second dielectric layer 306 and the first conductive pillar 312 together form a first semiconductor structure 318.

[0105] Here, first sub-conductive pillar 314 is located between first conductive line 302 and second sub-conductive pillar 316, and first sub-conductive pillar 314 is connected to first conductive line 302. The width of the bottom of second sub-conductive pillar 316 is greater than the width of the top of first sub-conductive pillar 314. In other words, there is a sudden change in width at the transition position between first sub-conductive pillar 314 and second sub-conductive pillar 316.

[0106] Here, the height of the second sub-conductive pillar 316 in the direction perpendicular to the first substrate 300 is the same as the height of the second dielectric sub-layer 342 in the direction perpendicular to the first substrate 300. In a specific embodiment, the height of the second sub-conductive pillar 316 and the second dielectric sub-layer 342 in the direction perpendicular to the first substrate 300 is H1, the height of the first dielectric sub-layer 340 in the direction perpendicular to the first substrate 300 is H3, and the ratio between the height of the first dielectric sub-layer 340 (i.e., H3) and the height of the second sub-conductive pillar 316 (i.e., H1) ranges from 0.2 to 0.3.

[0107] In the disclosed embodiment, because the first sub-conductive pillar is smaller than the second sub-conductive pillar, the dielectric material surrounding the first sub-conductive pillar contributes more to the overall path transmission impedance than the dielectric material surrounding the second sub-conductive pillar. Therefore, selecting a material with a lower dielectric constant to form the first dielectric layer surrounding the first sub-conductive pillar can effectively reduce signal transmission loss.

[0108] In addition, in the embodiment of the present disclosure, a high temperature annealing process may be encountered during the subsequent bonding process. During the heating process of the first sub-conductive pillar and the second sub-conductive pillar, the thermal expansion coefficient of the dielectric material is smaller than the thermal expansion coefficient of the material of the first sub-conductive pillar and the second sub-conductive pillar. The transition position between the first sub-conductive pillar and the second sub-conductive pillar (such as Figure 3DThe dotted circle (shown in the middle) is prone to stress concentration. Therefore, a stronger material is selected to form the second dielectric layer surrounding the second sub-conductive pillar. More specifically, a stronger first and second dielectric sub-layers are selected to surround the transition between the first and second sub-conductive pillars. This can prevent the first and second dielectric sub-layers from cracking due to expansion of the first or second sub-conductive pillars, thereby effectively improving the reliability of the bonding structure during high-temperature annealing.

[0109] like Figure 3E As shown, the manufacturing method further includes: forming a second semiconductor structure 320, the second semiconductor structure 320 including a second substrate 322, a second conductive line 324 provided on the second substrate 322, a third dielectric layer 326 and a fourth dielectric layer 328 sequentially located on the second substrate 322 and covering the second conductive line 324, and a second conductive column 334 penetrating the fourth dielectric layer 328 and the third dielectric layer 326; wherein the dielectric constant of the third dielectric layer 326 is smaller than the dielectric constant of the fourth dielectric layer 328, and the strength of the fourth dielectric layer 328 is greater than the strength of the third dielectric layer 326.

[0110] For example, the fourth dielectric layer 328 includes a third dielectric sublayer 344 and a fourth dielectric sublayer 346; the third dielectric layer 326, the third dielectric sublayer 344, and the fourth dielectric sublayer 346 can be formed on the second substrate 322; a third trench 330 is formed that sequentially penetrates the fourth dielectric sublayer 346, the third dielectric sublayer 344, and the third dielectric layer 326 and exposes the second conductive line 324; a fourth trench 332 can be formed in the fourth dielectric sublayer 346 at a position corresponding to the third trench 330; wherein the fourth trench 332 is parallel to the second substrate 322. The dimension in the direction of the bottom 322 is greater than the dimension of the third trench 330 in the direction parallel to the second substrate 322; the height of the fourth trench 332 in the direction perpendicular to the second substrate 322 is the same as the height of the fourth dielectric sublayer 346 in the direction perpendicular to the second substrate 322; conductive material is filled in the third trench 330 and the fourth trench 332 to form a second conductive pillar 334; wherein the second conductive pillar 334 includes a third sub-conductive pillar 336 located in the third trench 330 and a fourth sub-conductive pillar 338 located in the fourth trench 332.

[0111] Here, the process of forming the first semiconductor structure 318 and the process of forming the second semiconductor structure 320 may be the same. The detailed process of forming the second semiconductor structure can refer to the process of forming the first semiconductor structure mentioned above, and will not be repeated here.

[0112] Here, a memory array may be formed on the first substrate 300 , and a peripheral circuit may be formed on the second substrate 322 ; or, a peripheral circuit may be formed on the first substrate 300 , and a memory array may be formed on the second substrate 322 .

[0113] like Figure 3F As shown, the manufacturing method further includes: bonding the first semiconductor structure 318 and the second semiconductor structure 320; wherein the first conductive pillar 312 and the second conductive pillar 334 are connected in a one-to-one correspondence; more specifically, the second sub-conductive pillar 316 and the fourth sub-conductive pillar 338 are in direct contact.

[0114] In the embodiment of the present disclosure, the dielectric constant of the first dielectric layer (or the third dielectric layer) surrounding the first sub-conductive pillar (or the third sub-conductive pillar) is smaller, thereby effectively reducing the transmission loss of the signal. In addition, during the hybrid bonding process of the first semiconductor structure and the second semiconductor structure, a high-temperature annealing process (for example, an annealing temperature of 350°C and an annealing time of 1 hour) is required. During the heating process, the volume expansion of the first sub-conductive pillar and the second sub-conductive pillar (or the third sub-conductive pillar and the fourth sub-conductive pillar) is limited (that is, the thermal expansion coefficient of the dielectric material is smaller than the thermal expansion coefficient of the conductive material), and the transition position (such as the transition position) between the first sub-conductive pillar and the second sub-conductive pillar (or the third sub-conductive pillar and the fourth sub-conductive pillar) is limited. Figure 3F The use of a stronger first and second dielectric sub-layers (or third and fourth dielectric sub-layers) around the second sub-conductive pillar (or fourth sub-conductive pillar) can effectively prevent the first and second dielectric sub-layers (or third and fourth dielectric sub-layers) from being cracked by the first and second sub-conductive pillars (or third and fourth sub-conductive pillars) during high-temperature annealing, thereby effectively improving the high-temperature reliability of the bonding structure.

[0115] In the embodiment of the present disclosure, the material of the first dielectric layer 304 is the same as the material of the third dielectric layer 326; the second dielectric layer 306 includes a first dielectric sublayer 340 and a second dielectric sublayer 342, and the fourth dielectric layer 328 includes a third dielectric sublayer 344 and a fourth dielectric sublayer 346; the material of the first dielectric sublayer 340 is the same as the material of the third dielectric sublayer 344, and the material of the second dielectric sublayer 342 is the same as the material of the fourth dielectric sublayer 346.

[0116] For example, the materials of the first dielectric layer 304 and the third dielectric layer 326 may both include low-k silicon oxide; the materials of the first dielectric sub-layer 340 and the third dielectric sub-layer 344 may both include silicon nitride; and the materials of the second dielectric sub-layer 342 and the fourth dielectric sub-layer 346 may include silicon oxide prepared from tetraethyl orthosilicate. Silicon nitride has a greater strength than low-k silicon oxide.

[0117] refer to Figure 4A , Figure 4ASchematic diagram of the cross-sectional structure of a semiconductor device provided by an embodiment of the present disclosure. Figure 4A As shown, an embodiment of the present disclosure provides a semiconductor device, which includes: a first semiconductor structure 218; the first semiconductor structure 218 includes:

[0118] A first substrate 200 and a first conductive line 202 provided on the first substrate 200;

[0119] A first dielectric layer 204 and a second dielectric layer 206 are sequentially located on the first substrate 200 and covering the first conductive line 202; the dielectric constant of the first dielectric layer 204 is smaller than the dielectric constant of the second dielectric layer 206, and the strength of the second dielectric layer 206 is greater than the strength of the first dielectric layer 204;

[0120] A first conductive pillar 212 extends through the second dielectric layer 206 and the first dielectric layer 204. The first conductive pillar 212 includes a first sub-conductive pillar 214 located in the first dielectric layer 204 and a second sub-conductive pillar 216 located in the second dielectric layer 206. The size of the second sub-conductive pillar 216 along a direction parallel to the first substrate 200 is larger than the size of the first sub-conductive pillar 214 along the direction parallel to the first substrate 200.

[0121] In the embodiment of the present disclosure, the semiconductor device further includes: a second semiconductor structure 220 bonded to the first semiconductor structure 218; the second semiconductor structure 220 includes:

[0122] A second substrate 222 and a second conductive line 224 provided on the second substrate 222;

[0123] A third dielectric layer 226 and a fourth dielectric layer 228 are sequentially located on the second substrate 222 and cover the second conductive line 224; the dielectric constant of the third dielectric layer 226 is smaller than the dielectric constant of the fourth dielectric layer 228, and the strength of the fourth dielectric layer 228 is greater than the strength of the third dielectric layer 226;

[0124] The second conductive pillar 234 penetrates the fourth dielectric layer 228 and the third dielectric layer 226. The second conductive pillar 234 includes a third sub-conductive pillar 236 located in the third dielectric layer 226 and a fourth sub-conductive pillar 238 located in the fourth dielectric layer 228. The size of the fourth sub-conductive pillar 238 along the direction parallel to the second substrate 222 is larger than the size of the third sub-conductive pillar 236 along the direction parallel to the second substrate 222.

[0125] In the embodiment of the present disclosure, the height of the second sub-conductive pillar 216 in the direction perpendicular to the first substrate 200 is smaller than the height of the second dielectric layer 206 in the direction perpendicular to the first substrate 200;

[0126] The height of the fourth sub-conductive pillar 238 in the direction perpendicular to the second substrate 222 is smaller than the height of the fourth dielectric layer 228 in the direction perpendicular to the second substrate 222 .

[0127] In the embodiment of the present disclosure, the material of the first dielectric layer 204 is the same as the material of the third dielectric layer 226 ; the material of the second dielectric layer 206 is the same as the material of the fourth dielectric layer 228 .

[0128] refer to Figure 4B , Figure 4B FIG1 is a schematic diagram of a cross-sectional structure of another semiconductor device provided by an embodiment of the present disclosure. Figure 4B As shown, an embodiment of the present disclosure provides a semiconductor device, which includes: a first semiconductor structure 318; the first semiconductor structure 318 includes:

[0129] A first substrate 300 and a first conductive line 302 provided on the first substrate 300;

[0130] A first dielectric layer 304 and a second dielectric layer 306 are sequentially located on the first substrate 300 and covering the first conductive line 302; the second dielectric layer 306 includes a first dielectric sublayer 340 and a second dielectric sublayer 342, and the first dielectric sublayer 340 is located between the first dielectric layer 304 and the second dielectric sublayer 342; the dielectric constant of the first dielectric layer 304 is smaller than the dielectric constants of the first dielectric sublayer 340 and the second dielectric sublayer 342, and the strength of the first dielectric sublayer 340 and the second dielectric sublayer 342 is greater than the strength of the first dielectric layer 304;

[0131] A first conductive pillar 312 passes through the second dielectric sublayer 342, the first dielectric sublayer 340 and the first dielectric layer 304. The first conductive pillar 312 includes a first sub-conductive pillar 314 located in the first dielectric layer 304 and the first dielectric sublayer 340, and a second sub-conductive pillar 316 located in the second dielectric sublayer 342. The size of the second sub-conductive pillar 316 along the direction parallel to the first substrate 300 is larger than the size of the first sub-conductive pillar 314 along the direction parallel to the first substrate 300.

[0132] In the embodiment of the present disclosure, the semiconductor device further includes: a second semiconductor structure 320 bonded to the first semiconductor structure 318; the second semiconductor structure 320 includes:

[0133] A second substrate 322 and a second conductive line 324 provided on the second substrate 322;

[0134] A third dielectric layer 326 and a fourth dielectric layer 328 are sequentially located on the second substrate 322 and covering the second conductive line 324. The fourth dielectric layer 328 includes a third dielectric sublayer 344 and a fourth dielectric sublayer 346, with the third dielectric sublayer 344 located between the third dielectric layer 326 and the fourth dielectric sublayer 346. The dielectric constant of the third dielectric layer 326 is smaller than the dielectric constants of the third dielectric sublayer 344 and the fourth dielectric sublayer 346, and the strength of the third dielectric sublayer 344 and the fourth dielectric sublayer 346 is greater than the strength of the third dielectric layer 326.

[0135] The second conductive pillar 334 passes through the fourth dielectric sublayer 346, the third dielectric sublayer 344 and the third dielectric layer 326. The second conductive pillar 334 includes a third sub-conductive pillar 336 located in the third dielectric layer 326 and the third dielectric sublayer 344, and a fourth sub-conductive pillar 338 located in the fourth dielectric sublayer 346. The size of the fourth sub-conductive pillar 338 along the direction parallel to the second substrate 322 is larger than the size of the third sub-conductive pillar 336 along the direction parallel to the second substrate 322.

[0136] In the embodiment of the present disclosure, the height of the second sub-conductive pillar 316 in the direction perpendicular to the first substrate 300 is the same as the height of the second dielectric sub-layer 342 in the direction perpendicular to the first substrate 300;

[0137] The height of the fourth sub-conductive pillar 338 in the direction perpendicular to the second substrate 322 is the same as the height of the fourth dielectric sub-layer 346 in the direction perpendicular to the second substrate 322 .

[0138] In the embodiment of the present disclosure, the material of the first dielectric layer 304 is the same as that of the third dielectric layer 326 ; the material of the first dielectric sublayer 340 is the same as that of the third dielectric sublayer 344 ; the material of the second dielectric sublayer 342 is the same as that of the fourth dielectric sublayer 346 .

[0139] In the embodiment of the present disclosure, the materials of the first dielectric layer 304 and the third dielectric layer 326 both include silicon oxide with a low dielectric constant; the materials of the first dielectric sublayer 340 and the third dielectric sublayer 344 both include silicon nitride; and the materials of the second dielectric sublayer 342 and the fourth dielectric sublayer 346 include silicon oxide prepared from ethyl orthosilicate.

[0140] The present disclosure provides a semiconductor device and a method for manufacturing the same. The method comprises: providing a first substrate and a first conductive line disposed on the first substrate; sequentially forming a first dielectric layer and a second dielectric layer on the first substrate; wherein the dielectric constant of the first dielectric layer is smaller than the dielectric constant of the second dielectric layer, and the strength of the second dielectric layer is greater than the strength of the first dielectric layer; forming a first trench that sequentially penetrates the second dielectric layer and the first dielectric layer and exposes the first conductive line; forming a second trench in the second dielectric layer at a position corresponding to the first trench; wherein the dimension of the second trench in a direction parallel to the first substrate is greater than the dimension of the first trench in a direction parallel to the first substrate. In the present disclosure, a first trench is formed in the first dielectric layer and a second trench is formed in the second dielectric layer; wherein the dielectric constant of the first dielectric layer is smaller than the dielectric constant of the second dielectric layer, and the strength of the second dielectric layer is greater than the strength of the first dielectric layer; because the dimension of the first trench is smaller than the dimension of the second trench, after the first and second trenches are subsequently filled, the dielectric constant of the first dielectric layer surrounding the first trench is smaller, thereby effectively reducing signal transmission loss; and the strength of the second dielectric layer surrounding the second trench is greater, thereby effectively improving high-temperature reliability during the subsequent bonding process.

[0141] It should be understood that “one embodiment” or “an embodiment” mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, “in one embodiment” or “in an embodiment” appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0142] The above description is only a preferred embodiment of the present disclosure and does not limit the patent scope of the present disclosure. All equivalent structural transformations made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or direct / indirect application in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The manufacturing method comprises: Providing a first substrate and a first conductive line disposed on the first substrate; forming a first dielectric layer and a second dielectric layer in sequence on the first substrate; wherein the dielectric constant of the first dielectric layer is smaller than the dielectric constant of the second dielectric layer, and the strength of the second dielectric layer is greater than the strength of the first dielectric layer; forming a first trench that sequentially penetrates the second dielectric layer and the first dielectric layer and exposes the first conductive line; forming a second trench in the second dielectric layer at a position corresponding to the first trench; wherein a dimension of the second trench in a direction parallel to the first substrate is greater than a dimension of the first trench in a direction parallel to the first substrate; Wherein, the second dielectric layer includes a first dielectric sublayer and a second dielectric sublayer, and the strength of the first dielectric sublayer and the second dielectric sublayer are both greater than the strength of the first dielectric layer; The step of sequentially forming a first dielectric layer and a second dielectric layer on the first substrate includes: A first dielectric layer, a first dielectric sublayer and a second dielectric sublayer are sequentially formed on the first substrate.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The forming of a second trench in the second dielectric layer at a position corresponding to the first trench comprises: Corresponding to the position of the first trench, a portion of the second dielectric layer is etched to form a second trench; wherein the height of the second trench in a direction perpendicular to the first substrate is smaller than the height of the second dielectric layer in a direction perpendicular to the first substrate.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: The forming of a first trench that sequentially penetrates the second dielectric layer and the first dielectric layer and exposes the first conductive line includes: A first trench is formed, which sequentially penetrates the second dielectric sub-layer, the first dielectric sub-layer, and the first dielectric layer and exposes the first conductive line.

4. The method for manufacturing a semiconductor device according to claim 3, wherein: The forming of a second trench in the second dielectric layer at a position corresponding to the first trench comprises: Corresponding to the position of the first groove, a second groove is etched to penetrate the second dielectric sublayer and expose the surface of the first dielectric sublayer; wherein the first dielectric sublayer serves as an etching stop layer; and the height of the second groove in a direction perpendicular to the first substrate is the same as the height of the second dielectric sublayer in a direction perpendicular to the first substrate.

5. The method for manufacturing a semiconductor device according to claim 2 or 4, wherein: After forming the second trench in the second dielectric layer at a position corresponding to the first trench, the manufacturing method further includes: A conductive material is filled in the first trench and the second trench to form a first conductive pillar; wherein the first conductive pillar includes a first sub-conductive pillar located in the first trench and a second sub-conductive pillar located in the second trench; the first substrate, the first conductive line, the first dielectric layer, the second dielectric layer and the first conductive pillar together form a first semiconductor structure.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: The manufacturing method further comprises: forming a second semiconductor structure, the second semiconductor structure comprising a second substrate, a second conductive line disposed on the second substrate, a third dielectric layer and a fourth dielectric layer sequentially disposed on the second substrate and covering the second conductive line, and a second conductive pillar penetrating the fourth dielectric layer and the third dielectric layer; wherein the dielectric constant of the third dielectric layer is smaller than the dielectric constant of the fourth dielectric layer, and the strength of the fourth dielectric layer is greater than the strength of the third dielectric layer; The first semiconductor structure and the second semiconductor structure are bonded; wherein the first conductive pillars and the second conductive pillars are connected in a one-to-one correspondence.

7. A semiconductor device, characterized in that: The semiconductor device comprises: a first semiconductor structure; the first semiconductor structure comprises: a first substrate and a first conductive line provided on the first substrate; a first dielectric layer and a second dielectric layer sequentially located on the first substrate and covering the first conductive line; the dielectric constant of the first dielectric layer is smaller than the dielectric constant of the second dielectric layer, and the strength of the second dielectric layer is greater than the strength of the first dielectric layer; a first conductive pillar extending through the second dielectric layer and the first dielectric layer, the first conductive pillar comprising a first sub-conductive pillar located in the first dielectric layer and a second sub-conductive pillar located in the second dielectric layer; the second sub-conductive pillar having a dimension parallel to the first substrate that is greater than the dimension of the first sub-conductive pillar in the direction parallel to the first substrate; Wherein, the second dielectric layer includes a first dielectric sublayer and a second dielectric sublayer, and the first dielectric sublayer is located between the first dielectric layer and the second dielectric sublayer; The strength of the first dielectric sublayer and the second dielectric sublayer are both greater than the strength of the first dielectric layer.

8. The semiconductor device according to claim 7, wherein: The semiconductor device further includes: a second semiconductor structure bonded to the first semiconductor structure; the second semiconductor structure includes: a second substrate and a second conductive line provided on the second substrate; a third dielectric layer and a fourth dielectric layer sequentially located on the second substrate and covering the second conductive line; the dielectric constant of the third dielectric layer is smaller than the dielectric constant of the fourth dielectric layer, and the strength of the fourth dielectric layer is greater than the strength of the third dielectric layer; A second conductive pillar extends through the fourth dielectric layer and the third dielectric layer, wherein the second conductive pillar includes a third sub-conductive pillar located in the third dielectric layer and a fourth sub-conductive pillar located in the fourth dielectric layer; a dimension of the fourth sub-conductive pillar in a direction parallel to the second substrate is greater than a dimension of the third sub-conductive pillar in a direction parallel to the second substrate.

9. The semiconductor device according to claim 8, wherein The height of the second sub-conductive pillar in a direction perpendicular to the first substrate is the same as the height of the second dielectric sub-layer in a direction perpendicular to the first substrate; The fourth dielectric layer includes a third dielectric sublayer and a fourth dielectric sublayer, and the third dielectric sublayer is located between the third dielectric layer and the fourth dielectric sublayer; The strength of the third dielectric sublayer and the fourth dielectric sublayer is greater than the strength of the third dielectric layer; the height of the fourth sub-conductive column in a direction perpendicular to the second substrate is the same as the height of the fourth dielectric sublayer in a direction perpendicular to the second substrate.

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