Three-dimensional memory and preparation method thereof

Abstract

The invention discloses a three-dimensional memory and a preparation method thereof, and relates to the field of memorizers, the memory comprises a substrate, a first metal electrode layer, a dielectric layer, a second metal electrode layer, a functional layer and a capacitor dielectric layer; the first metal electrode layers and the dielectric layers are arranged in a staggered and stacked manner; the second metal electrode layer is of a T-shaped structure; the vertical section of the second metal electrode layer penetrates through the substrate from the dielectric layer on the topmost layer and extends into the substrate; the horizontal section of the second metal electrode layer is arranged on the upper surface of the dielectric layer on the topmost layer; and the outer surface of the vertical section of the second metal electrode layer is coated with a capacitor dielectric layer. The functional layer is of a hollow columnar structure with the corresponding second metal electrode layer as the center; and the functional layer penetrates from the dielectric layer at the topmost layer to the direction of the substrate and extends into the substrate. According to the invention, the thickness of the capacitor dielectric medium in the three-dimensional memory is not limited by the ring width of the annular groove any more, and the data retention time of the three-dimensional memory is prolonged.

Description

Technical Field

[0001] The present application relates to the field of memory, and in particular to a three-dimensional memory and a preparation method thereof. Background Art

[0002] 3D 1S1C is considered to be a powerful alternative to DRAM in the face of the three-dimensional stacking dilemma because of its easy three-dimensional stacking, high density and performance close to DRAM (Dynamic Random Access Memory). However, in its current structure, the film thickness of the capacitor dielectric mainly depends on the ring width of the etched annular groove, which will cause the capacitor dielectric in 3D 1S1C to be too thick. Compared with DRAM, where the film thickness of the capacitor dielectric can be controlled independently, the capacitor capacitance in 3D 1S1C will be low due to the excessive thickness of the capacitor dielectric, affecting the data retention time of the storage unit, thereby limiting the further development of 3D 1S1C. Summary of the invention

[0003] The purpose of the present application is to provide a three-dimensional memory and a preparation method thereof, which can solve the problem that the three-dimensional memory has a low capacitance value due to the excessive thickness of the capacitor dielectric, which affects the data retention time of the storage unit.

[0004] To achieve the above objectives, this application provides the following solutions:

[0005] In a first aspect, the present application provides a three-dimensional memory, comprising: a substrate, a plurality of first metal electrode layers, a plurality of dielectric layers, at least one second metal electrode layer, at least one functional layer and at least one capacitor dielectric layer;

[0006] A plurality of the first metal electrode layers and a plurality of the dielectric layers are arranged in a staggered stacking manner; in the staggered stacking structure, the topmost layer is the dielectric layer, and the bottommost layer is the first metal electrode layer; the bottommost first metal electrode layer is arranged on the upper surface of the substrate;

[0007] Each of the second metal electrode layers is a T-shaped structure; the vertical section of each of the second metal electrode layers penetrates from the upper surface of the top dielectric layer toward the substrate and extends to the inside of the substrate; the horizontal section of each of the second metal electrode layers is arranged on the upper surface of the top dielectric layer;

[0008] The outer surface of each vertical segment of the second metal electrode layer is covered with the capacitor dielectric layer.

[0009] The functional layers and the second metal electrode layers are the same in number and correspond one to one;

[0010] Each of the functional layers is a hollow columnar structure with the corresponding second metal electrode layer as the center; each of the functional layers penetrates from the upper surface of the topmost dielectric layer toward the direction where the substrate is located and extends to the inside of the substrate.

[0011] In a second aspect, the present application provides a method for preparing a three-dimensional memory, comprising:

[0012] Alternately stacking and growing a first metal electrode layer and a dielectric layer on a substrate to form a base sheet; in the staggered stacked structure, the topmost layer is the dielectric layer, and the bottommost layer is the first metal electrode layer; the bottommost first metal electrode layer is disposed on the upper surface of the substrate;

[0013] At least one hole is formed on the substrate; the hole penetrates from the upper surface of the topmost dielectric layer toward the substrate and extends to the interior of the substrate;

[0014] Uniformly depositing a capacitor dielectric layer on the inner wall of each hole;

[0015] After depositing the capacitor dielectric layer, the remaining space of the hole is filled with a second metal electrode layer; the third metal electrode layer extends from the area of ​​the hole to a preset area on the upper surface of the topmost dielectric layer;

[0016] After filling the second metal electrode layer, an annular groove is formed on the substrate with each of the second metal electrode layers as the center; the annular groove penetrates from the upper surface of the topmost dielectric layer toward the substrate and extends to the inside of the substrate;

[0017] For each of the annular grooves, a functional layer is uniformly deposited in the annular groove.

[0018] In a second aspect, the present application provides a method for preparing a three-dimensional memory, comprising:

[0019] Alternately stacking and growing a first metal electrode layer and a dielectric layer on a substrate to form a base sheet; in the staggered stacked structure, the topmost layer is the dielectric layer, and the bottommost layer is the first metal electrode layer; the bottommost first metal electrode layer is disposed on the upper surface of the substrate;

[0020] At least one annular groove is formed on the substrate; each of the annular grooves penetrates from the upper surface of the topmost dielectric layer toward the substrate and extends to the interior of the substrate;

[0021] For each of the annular grooves, uniformly depositing a functional layer in the annular groove;

[0022] After filling the functional layers, a hole is formed at the center of each functional layer; each hole penetrates from the upper surface of the topmost dielectric layer toward the substrate and extends to the inside of the substrate;

[0023] For each of the holes, a capacitor dielectric layer is uniformly deposited on the inner wall of the hole;

[0024] After depositing the capacitor dielectric layer, the remaining space in the hole is filled with a second metal electrode layer; the second metal electrode layer extends from the area of ​​the hole to a preset area on the upper surface of the topmost dielectric layer.

[0025] According to the specific embodiments provided in this application, this application discloses the following technical effects:

[0026] The present application provides a three-dimensional memory and a preparation method thereof. A gating device (functional layer) is made in an annular groove, and a capacitor dielectric layer is made on the side wall of a hole, so that the thickness of the capacitor dielectric in the three-dimensional memory is no longer limited by the width of the annular groove, thereby improving the data retention time of the three-dimensional memory and solving the thickness limitation of the annular groove on the capacitor dielectric. The most advanced capacitor dielectric technology can be applied to the development of the three-dimensional memory. At the same time, the width of the annular groove can be about 30nm under the existing semiconductor process. This thickness is within the appropriate functional layer thickness range of the gating device and will not affect the performance of the gating device. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0028] Figure 1 A schematic diagram of the structure of a three-dimensional memory provided in Example 1 of the present application;

[0029] Figure 2 A schematic diagram of a process for preparing a three-dimensional memory provided in Example 2 of the present application;

[0030] Figure 3 A schematic diagram of a process flow of a gating device manufacturing process provided in Example 2 of the present application;

[0031] Figure 4 A schematic diagram of the process flow of the capacitor preparation process provided in Example 2 of the present application.

[0032] Reference numerals:

[0033] 1-substrate; 2-first metal electrode layer; 3-dielectric layer; 4-second metal electrode layer; 5-capacitor dielectric layer; 6-functional layer; 7-third metal electrode layer; 8-fourth metal electrode layer; 9-fifth metal electrode layer. DETAILED DESCRIPTION

[0034] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0035] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0036] Example 1

[0037] This embodiment provides a three-dimensional memory, such as Figure 1 As shown, the three-dimensional memory includes: a horizontal peripheral electrode layer, a vertical functional layer and a capacitor dielectric layer, etc. Specifically, the peripheral electrode layer includes a substrate 1, a plurality of first metal electrode layers 2 and a plurality of dielectric layers 3; the dielectric layer and the first metal electrode layer are alternately stacked and grown on the substrate. In other words, a plurality of the first metal electrode layers and a plurality of the dielectric layers are arranged in an interlaced and stacked manner; in the interlaced and stacked structure, the topmost layer is the dielectric layer and the bottommost layer is the first metal electrode layer; the bottommost first metal electrode layer is arranged on the upper surface of the substrate.

[0038] The peripheral electrode layer has a number of holes that penetrate in the vertical direction. The holes are arranged in an array according to a certain rule, and the bottom of the hole extends at least to the bottom of the substrate. The inner wall of the hole is covered with the capacitor dielectric layer and the second metal electrode layer in turn. Figure 1 As shown, for each of the second metal electrode layers, the second metal electrode layers are all T-shaped structures; the vertical section of each of the second metal electrode layers penetrates from the upper surface of the top dielectric layer toward the substrate and extends to the inside of the substrate; the horizontal section of each of the second metal electrode layers is arranged on the upper surface of the top dielectric layer. The outer surface of the vertical section of each of the second metal electrode layers is covered with the capacitor dielectric layer.

[0039] There is an annular groove outside each hole, the hole is located at the center of the annular groove, the annular groove surrounds the hole and vertically cuts off the peripheral electrode layer, and the bottom of the annular groove extends to at least the bottom substrate. The annular groove is uniformly filled with a functional layer; the number of the functional layer and the second metal electrode layer is the same and corresponds one to one; Figure 1 As shown, each of the functional layers is a hollow columnar structure centered on the corresponding second metal electrode layer; each of the functional layers penetrates from the upper surface of the topmost dielectric layer toward the substrate and extends to the interior of the substrate.

[0040] The bottoms of the functional layer, the capacitor dielectric layer and the second metal electrode layer are vertically lower than the bottom first metal electrode layer, that is, the bottoms of the functional layer, the capacitor dielectric layer and the second metal electrode layer are all located in the area where the substrate is located.

[0041] The resistance of the third metal electrode layer and the fourth metal electrode layer is the same and higher than that of the first metal electrode layer; the area where the second metal electrode layer faces the first metal electrode layer constitutes a storage unit.

[0042] In this embodiment, the gating device is fabricated in the annular groove and the capacitor dielectric layer is fabricated on the side wall of the hole, thereby solving the thickness limitation of the annular groove on the capacitor dielectric, and the most advanced capacitor dielectric technology can be applied to the development of 3D 1S1C. At the same time, the width of the annular groove can be about 30nm under the existing semiconductor process. This thickness is within the appropriate functional layer thickness range of the gating device and will not affect the performance of the gating device.

[0043] As an optional implementation, the position where the first metal electrode layer contacts the annular groove is concave inward, and the inside is filled with the third metal electrode layer and the fourth metal electrode layer respectively. The third metal electrode layer and the fourth metal electrode layer only exist in the concave area where the annular groove contacts the first metal electrode layer. The third metal electrode layer and the fourth metal electrode layer are discontinuous on the side wall of the annular groove, so that the inner side wall of the annular groove remains smooth. Therefore, the three-dimensional memory further includes: a third metal electrode layer and a fourth metal electrode layer;

[0044] The third metal electrode layer is evenly arranged between the inner wall of each functional layer of the hollow columnar structure and each layer of the first metal electrode layer.

[0045] The fourth metal electrode layer is evenly arranged between the outer wall of each functional layer of the hollow columnar structure and each layer of the first metal electrode layer.

[0046] As an optional implementation manner, the width of the third metal electrode layer and the width of the fourth metal electrode layer are the same as the width of the corresponding first metal electrode layer.

[0047] The purpose of the third metal electrode layer and the fourth metal electrode layer is to regulate the holding voltage of the gating device, because the current poor 1S1C operating window is mainly caused by the low holding voltage during the high-speed operation of the gating device; and the functional layer has two states: high resistance state and low resistance state. When the voltage across the functional layer exceeds the threshold voltage Vth of the functional layer, the functional layer switches from the high resistance state to the low resistance state. When the voltage across the functional layer in the low resistance state is lower than the holding voltage Vhold of the functional layer, the functional layer switches from the low resistance state to the high resistance state; the total holding voltage VHold of the functional layer and the third metal electrode layer and the fourth metal electrode layer is VHold = Vhold + Vhold*R / R_low, where R_low is the resistance of the low resistance state of the functional layer, and R is the resistance of the third metal electrode layer and the fourth metal electrode layer, with a value range of 0≤R≤Rmax, where Rmax is the value of R when VHold is equal to Vth. The total holding voltage VHold of the gating device can be adjusted by adjusting the resistance of the third metal electrode layer and the fourth metal electrode layer; the 1S1C operation window can be increased by selecting the third metal electrode layer and the fourth metal electrode layer materials with suitable larger resistance.

[0048] If the third metal electrode layer and the fourth metal electrode layer are eliminated, the purpose of increasing the 1S1C operation window can also be achieved by increasing the resistance of the first metal electrode layer. However, the first metal electrode layer is not only the electrode of the storage device, it also acts as a word line in the storage array. If the resistance of the first metal electrode layer is increased in order to increase the holding voltage of the selection device, the transmission speed of the read and write signals in the three-dimensional storage array will be greatly reduced, which is unacceptable for the 3D 1S1C memory of the target DRAM scenario.

[0049] If the position where the first metal electrode layer contacts the annular groove is not concave, but the third metal electrode layer and the fourth metal electrode layer are directly deposited on the side wall of the annular groove, it is equivalent to forming a complete third metal electrode layer and a complete fourth metal electrode layer on the side wall of the annular groove. Since the resistance of the third metal electrode layer and the fourth metal electrode layer is only higher than that of the first metal electrode layer, at 102 Ω However, its resistance value still cannot separate two adjacent cells in the vertical direction, which is equivalent to the same string of storage cells in the vertical direction sharing one selection device, thus losing the advantage of high density of 3D 1S1C memory.

[0050] If the third metal electrode layer and the fourth metal electrode layer are placed in the hole, there will also be the problem of the same string of storage cells sharing a selection device in the vertical direction. Therefore, the only feasible solution for regulating the 1S1C operating window is to concave the position near the first metal electrode layer in the annular groove inward to fill the third metal electrode layer and the fourth metal electrode layer material with higher resistance.

[0051] In the traditional 3D 1S1C preparation process, since it is necessary to consider the deep etching of the hole and the annular groove, the first metal electrode layer is required to be compatible with the high aspect ratio etching process, and the first metal electrode layer is also used as the word line of the storage array at the same time, and it is required to meet the low resistance requirement, but usually the electrode material of the capacitor needs to have a good matching ability with the capacitor dielectric, including considerations such as energy band and work function. Therefore, after the annular groove is prepared, it is necessary to use a capacitor electrode material that matches the capacitor dielectric to replace part of the first metal electrode layer to achieve the purpose of reducing the leakage current of the storage unit. And it is necessary to ensure that after the replacement is completed, the side wall of the annular groove can still be kept smooth to ensure the uniform distribution of the capacitor electric field. The position where the first metal electrode layer contacts the hole needs to be concave inward, and the inside is filled with a fifth metal electrode layer that is well compatible with the capacitor dielectric layer. Therefore, the three-dimensional memory also includes: a fifth metal electrode layer.

[0052] The fifth metal electrode layer is evenly arranged between the outer surface of the capacitor dielectric layer and each of the first metal electrode layers.

[0053] The second metal electrode layer and the fifth metal electrode layer need to be made of materials that can effectively limit leakage current in the capacitor dielectric layer. The second metal electrode layer and the fifth metal electrode layer are made of the same electrode material.

[0054] The alternately stacked dielectric layers and the first metal electrode layers are periodically repeated in the vertical direction as required, and the number of repetitions is the same as the number of memory cell layers required by the three-dimensional 1S1C memory. That is, the first metal electrode layer and the dielectric layer have the same number of layers, and the number of layers is the same as the number of memory cell layers required by the three-dimensional memory.

[0055] This embodiment has the following advantages:

[0056] (1) By setting the capacitor dielectric layer in the hole, the thickness of the capacitor dielectric in the 3D 1S1C is no longer limited by the width of the annular groove. The most advanced capacitor dielectric technology can be applied to the 3D 1S1C to improve the data retention time of the 3D 1S1C.

[0057] (2) The third metal electrode layer and the fourth metal electrode layer are arranged at the position where the annular groove contacts the first metal electrode layer, thereby increasing the data operation window of the 3D 1S1C memory and reducing the bit error rate of the memory, thus solving the problem of small operation window and high bit error rate of the current 3D 1S1C memory.

[0058] (3) A fifth metal electrode layer is arranged at the position where the hole contacts the first metal electrode layer, thereby optimizing the electrode preparation process of the capacitor in the 3D1S1C memory, reducing the leakage current of the memory device, and solving the problem that the current 3D 1S1C preparation process will cause large leakage current of the capacitor.

[0059] Example 2

[0060] This embodiment provides a method for preparing a three-dimensional memory. The method first performs a preparation process of a gate device, and then performs a preparation process of a capacitor on this basis. Specifically, Figure 2 As shown, the method for preparing the three-dimensional memory includes:

[0061] (a1) A first metal electrode layer and a dielectric layer are alternately stacked and grown on a substrate to form a base sheet; in the staggered stacked structure, the topmost layer is the dielectric layer and the bottommost layer is the first metal electrode layer; the bottommost first metal electrode layer is disposed on the upper surface of the substrate.

[0062] (a2) at least one annular groove is formed on the substrate; each of the annular grooves penetrates from the upper surface of the topmost dielectric layer toward the substrate and extends to the interior of the substrate.

[0063] (a3) For each of the annular grooves, a functional layer is uniformly deposited in the annular groove.

[0064] Steps (a1) to (a3) ​​are the preparation process of the gating device, corresponding to Figure 2 and Figure 3 The preparation operations shown in (a), (b) and (e).

[0065] (a4) After filling the functional layers, a hole is formed at the center of each of the functional layers; each of the holes penetrates from the upper surface of the topmost dielectric layer toward the substrate and extends to the interior of the substrate.

[0066] (a5) For each of the holes, a capacitor dielectric layer is uniformly deposited on the inner wall of the hole.

[0067] (a6) After depositing the capacitor dielectric layer, fill the remaining space of the hole with a second metal electrode layer; the second metal electrode layer extends from the area of ​​the hole to a preset area on the upper surface of the topmost dielectric layer.

[0068] Steps (a4) to (a6) are the preparation process of the capacitor, corresponding to Figure 2 The preparation process shown in (f), (i) and (j) Figure 4 The preparation operations shown in (a), (d) and (e).

[0069] As an optional implementation, before performing step (a3) ​​of "for each of the annular grooves, uniformly depositing a functional layer in the annular groove", the method for preparing the three-dimensional memory further includes:

[0070] (1) A portion of the first metal electrode layer exposed in the annular groove is uniformly removed inward. This step corresponds to Figure 2 and Figure 3 The preparation operation shown in (c).

[0071] (2) Selectively depositing the third and fourth metal electrode layers at the location where the first metal electrode layer is removed, and keeping the inner walls on both sides of the annular groove smooth, so that the functional layer can be uniformly deposited in the annular groove to fill the annular groove. This step corresponds to Figure 2 and Figure 3 The preparation operation shown in (d).

[0072] As an optional implementation, before performing step (a5) of "uniformly depositing a capacitor dielectric layer on the inner wall of each of the holes", the method for preparing the three-dimensional memory further includes:

[0073] (1) A portion of the first metal electrode layer exposed in the hole is uniformly removed inward. This step corresponds to Figure 2 (g) and Figure 4 The preparation operation shown in (b).

[0074] (2) Selectively depositing and filling the fifth metal electrode layer at the position where the first metal electrode layer is removed, and the inner wall of the circular hole remains smooth. This step corresponds to Figure 2 (h) and Figure 4 The preparation operation shown in (c).

[0075] The following is a method for preparing a three-dimensional memory after specific materials are introduced into each layer, and the preparation process of the gate device is first performed, and then the preparation process of the capacitor is performed. The specific preparation process flow is:

[0076] like Figure 2 In (a), first, a three-layer stack of 50nmW (tungsten) and 100nm SiO2 (silicon dioxide) is prepared on substrate 1, and the top layer is SiO2; that is, the dielectric layer uses SiO2 and the first metal electrode layer uses W.

[0077] like Figure 2 In (b), a ring pattern is formed on the stack by photolithography, and ICP etching with good anisotropy is used. SF6+C4F8 (sulfur hexafluoride+octafluorocyclobutane) is used as the etching gas to etch the stack, and the width of the obtained ring groove is 30nm.

[0078] like Figure 2In (c), a mixture of hydrofluoric acid (HF) and nitric acid (HNO3) is used to selectively remove 20nm of exposed W.

[0079] like Figure 2 In (d), a layer of TiN (tin) electrode with a thickness of 20 nm is uniformly grown on the W surface by the ALD process using a precursor with selective growth ability for W and SiO2, so that the side wall of the annular groove remains flat. That is, the third metal electrode layer and the fourth metal electrode layer are made of TiN.

[0080] like Figure 2 In (e), a layer of 15nm GeTE9 material is evenly deposited on the side wall of the circular hole through the ALD process to fill the annular groove.

[0081] like Figure 2 In (f), a circular pattern is formed on the stack by photolithography at the center of the annular groove. The stack is etched using ICP etching with good anisotropy and SF6+C4F8 as the etching gas. The diameter of the circular hole is 100 nm.

[0082] like Figure 2 In (g), a mixture of hydrofluoric acid (HF) and nitric acid (HNO3) is used to selectively remove the exposed W5nm;

[0083] like Figure 2 (h) in which a layer of TiN electrode with a thickness of 5 nm is uniformly grown on the W surface through the ALD process;

[0084] like Figure 2 In (i), a layer of 2nmZrO2 (zirconium dioxide), 1nmAl2O3 (aluminum oxide), and 2nm ZrO2 are continuously deposited on the sidewall of the circular hole through the ALD process.

[0085] like Figure 2 In (j), a 30nm TiN electrode is deposited on the sidewall of the circular hole using the ALD process. Thus, the preparation of the three-dimensional memory is completed.

[0086] When TiN is used as the capacitor electrode material, i.e. the material of the fifth metal electrode layer, the leakage current of the capacitor is reduced from 2×10 -6 A / cm 2 Down to 6×10 -8 A / cm 2 , which greatly reduces the leakage current of the capacitor and improves the data retention time of the storage device. And by preparing the capacitor on the side wall of the circular hole, the thickness of the capacitor dielectric can be reduced to 5nm, greatly increasing the capacitance of the capacitor by 6 times.

[0087] In addition, by adding a layer of high-resistance TiN (ie, the third metal electrode layer and the fourth metal electrode layer) between the functional layer and the first metal electrode layer, the holding voltage of the selection device is increased from 0.5V to 1V, and the corresponding operation window of the memory is also increased by 0.5V.

[0088] Example 3

[0089] This embodiment provides a method for preparing a three-dimensional memory. The method adopts a process for preparing a capacitor first, and then a process for preparing a gate device on this basis. Specifically, the method for preparing the three-dimensional memory includes:

[0090] (b1) growing a first metal electrode layer and a dielectric layer by alternating stacking on a substrate to form a base sheet; in the staggered stacking structure, the topmost layer is the dielectric layer and the bottommost layer is the first metal electrode layer; the bottommost first metal electrode layer is disposed on the upper surface of the substrate.

[0091] (ab2) forming at least one hole on the substrate; the hole penetrates from the upper surface of the topmost dielectric layer toward the substrate and extends to the interior of the substrate.

[0092] (b3) uniformly depositing a capacitor dielectric layer on the inner wall of each of the holes.

[0093] Steps (b1) to (b3) are the preparation process of the capacitor, corresponding to Figure 4 The preparation operations shown in (a), (d) and (e).

[0094] (b4) After depositing the capacitor dielectric layer, the remaining space in the hole is filled with a second metal electrode layer; the third metal electrode layer extends from the area of ​​the hole to a preset area on the upper surface of the topmost dielectric layer.

[0095] (b5) After filling the second metal electrode layers, an annular groove is formed on the substrate with each of the second metal electrode layers as the center; the annular groove penetrates from the upper surface of the topmost dielectric layer toward the substrate and extends to the interior of the substrate.

[0096] (b6) For each of the annular grooves, a functional layer is uniformly deposited in the annular groove.

[0097] Steps (b4) to (b6) are the preparation process of the gating device, corresponding to Figure 3 The preparation operations shown in (a), (b) and (e).

[0098] As an optional implementation, before performing step (b3) of "uniformly depositing a capacitor dielectric layer on the inner wall of each of the holes", the method for preparing the three-dimensional memory further includes:

[0099] (1) A portion of the first metal electrode layer exposed in the hole is uniformly removed inward. This step corresponds to Figure 4 The preparation process shown in (b).

[0100] (2) Selectively depositing and filling the fifth metal electrode layer at the position where the first metal electrode layer is removed, and the inner wall of the circular hole remains smooth. This step corresponds to Figure 4 The preparation operation shown in (c).

[0101] Before performing step (b6) of "for each of the annular grooves, uniformly depositing a functional layer in the annular groove", the method for preparing the three-dimensional memory further includes:

[0102] (1) A portion of the first metal electrode layer exposed in the annular groove is uniformly removed inward. This step corresponds to Figure 3 The preparation operation shown in (c).

[0103] (2) Selectively depositing the third and fourth metal electrode layers at the location where the first metal electrode layer is removed, and keeping the inner walls on both sides of the annular groove smooth, so that the functional layer can be uniformly deposited in the annular groove to fill the annular groove. This step corresponds to Figure 3 The preparation operation shown in (d).

[0104] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0105] This article uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for those skilled in the art, according to the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A three-dimensional memory, characterized in that: The three-dimensional memory comprises: a substrate, a plurality of first metal electrode layers, a plurality of dielectric layers, at least one second metal electrode layer, at least one functional layer and at least one capacitor dielectric layer; A plurality of the first metal electrode layers and a plurality of the dielectric layers are arranged in a staggered stacking manner; in the staggered stacking structure, the topmost layer is the dielectric layer, and the bottommost layer is the first metal electrode layer; the bottommost first metal electrode layer is arranged on the upper surface of the substrate; Each of the second metal electrode layers is a T-shaped structure; the vertical section of each of the second metal electrode layers penetrates from the upper surface of the top dielectric layer toward the substrate and extends to the inside of the substrate; the horizontal section of each of the second metal electrode layers is arranged on the upper surface of the top dielectric layer; The outer surface of each vertical segment of the second metal electrode layer is covered with the capacitor dielectric layer. The functional layers and the second metal electrode layers are the same in number and correspond one to one; Each of the functional layers is a hollow columnar structure with the corresponding second metal electrode layer as the center; each of the functional layers penetrates from the upper surface of the topmost dielectric layer toward the direction where the substrate is located and extends to the inside of the substrate.

2. The three-dimensional memory according to claim 1, characterized in that: The three-dimensional memory further includes: a third metal electrode layer and a fourth metal electrode layer; The third metal electrode layer is evenly arranged between the inner wall of each functional layer of the hollow columnar structure and each layer of the first metal electrode layer; The fourth metal electrode layer is evenly arranged between the outer wall of each functional layer of the hollow columnar structure and each layer of the first metal electrode layer.

3. The three-dimensional memory according to claim 2, characterized in that: The width of the third metal electrode layer and the width of the fourth metal electrode layer are the same as the corresponding width of the first metal electrode layer.

4. The three-dimensional memory according to claim 1, characterized in that: The three-dimensional memory further includes: a fifth metal electrode layer; The fifth metal electrode layer is evenly arranged between the outer surface of the capacitor dielectric layer and each of the first metal electrode layers.

5. The three-dimensional memory according to claim 1, characterized in that: The second metal electrode layer and the fifth metal electrode layer are made of materials that limit leakage current in the capacitor dielectric layer.

6. The three-dimensional memory according to claim 1, characterized in that: The resistance of the third metal electrode layer is the same as that of the fourth metal electrode layer and is higher than that of the first metal electrode layer.

7. The three-dimensional memory according to claim 1, characterized in that: The bottom of the functional layer, the bottom of the capacitor dielectric layer and the bottom of the second metal electrode layer are all located in the area where the substrate is located.

8. The three-dimensional memory according to claim 1, characterized in that: The number of layers of the first metal electrode layer and the dielectric layer is the same, and the number of layers is the same as the number of memory cell layers required by the three-dimensional memory.

9. A method for preparing a three-dimensional memory, characterized in that: The method for preparing the three-dimensional memory comprises: Alternately stacking and growing a first metal electrode layer and a dielectric layer on a substrate to form a base sheet; in the staggered stacked structure, the topmost layer is the dielectric layer, and the bottommost layer is the first metal electrode layer; the bottommost first metal electrode layer is disposed on the upper surface of the substrate; At least one hole is formed on the substrate; the hole penetrates from the upper surface of the topmost dielectric layer toward the substrate and extends to the interior of the substrate; Uniformly depositing a capacitor dielectric layer on the inner wall of each hole; After depositing the capacitor dielectric layer, the remaining space of the hole is filled with a second metal electrode layer; the third metal electrode layer extends from the area of ​​the hole to a preset area on the upper surface of the topmost dielectric layer; After filling the second metal electrode layer, an annular groove is formed on the substrate with each of the second metal electrode layers as the center; the annular groove penetrates from the upper surface of the topmost dielectric layer toward the substrate and extends to the inside of the substrate; For each of the annular grooves, a functional layer is uniformly deposited in the annular groove.

10. A method for preparing a three-dimensional memory, characterized in that: The method for preparing the three-dimensional memory comprises: Alternately stacking and growing a first metal electrode layer and a dielectric layer on a substrate to form a base sheet; in the staggered stacked structure, the topmost layer is the dielectric layer, and the bottommost layer is the first metal electrode layer; the bottommost first metal electrode layer is disposed on the upper surface of the substrate; At least one annular groove is formed on the substrate; each of the annular grooves penetrates from the upper surface of the topmost dielectric layer toward the substrate and extends to the interior of the substrate; For each of the annular grooves, uniformly depositing a functional layer in the annular groove; After filling the functional layers, a hole is formed at the center of each functional layer; each hole penetrates from the upper surface of the topmost dielectric layer toward the substrate and extends to the inside of the substrate; For each of the holes, a capacitor dielectric layer is uniformly deposited on the inner wall of the hole; After depositing the capacitor dielectric layer, the remaining space in the hole is filled with a second metal electrode layer; the second metal electrode layer extends from the area of ​​the hole to a preset area on the upper surface of the topmost dielectric layer.

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