Three-dimensional memory and methods of making the same

Abstract

The application discloses a three-dimensional memory and a preparation method thereof, relates to the field of memories, and the three-dimensional memory comprises a substrate, a first metal electrode layer, a dielectric layer, a second metal electrode layer, a functional layer and a capacitor dielectric layer; the first metal electrode layer and the dielectric layer are staggeredly arranged in layers; the second metal electrode layer has a T-shaped structure; a vertical segment of the second metal electrode layer penetrates and extends to the inside of the substrate from the direction of the dielectric layer at the topmost layer; a horizontal segment of the second metal electrode layer is arranged on the upper surface of the dielectric layer at the topmost layer; and the outer surfaces of the vertical segment of the second metal electrode layer are all coated with the capacitor dielectric layer. The functional layer has a hollow columnar structure with the corresponding second metal electrode layer as the center; and the functional layer penetrates and extends to the inside of the substrate from the direction of the dielectric layer at the topmost layer. The application can make the thickness of the capacitor dielectric in the three-dimensional memory no longer be limited by the width of the annular groove, and improve the data retention time of the three-dimensional memory.

Description

Technical Field

[0001] This application relates to the field of memory, and in particular to a three-dimensional memory and a method for fabricating the same. Background Technology

[0002] 3D 1S1C is considered a strong alternative to DRAM when facing the challenges of 3D stacking due to its ease of 3D stacking, high density, and performance close to DRAM (Dynamic Random Access Memory). However, in its current structure, the thickness of the capacitor dielectric film mainly depends on the ring width of the etched annular groove. This results in the capacitor dielectric being too thick in 3D 1S1C. Compared to DRAM, where the capacitor dielectric film thickness can be controlled, the excessively thick dielectric film in 3D 1S1C leads to a lower capacitance value, affecting the data retention time of the memory cell and thus limiting the further development of 3D 1S1C. Summary of the Invention

[0003] The purpose of this application is to provide a three-dimensional memory and its fabrication method, which can solve the problem that the capacitance value of the capacitor is low due to the excessively thick dielectric of the capacitor in the three-dimensional memory, thus affecting the data retention time of the storage cell.

[0004] To achieve the above objectives, this application provides the following solution:

[0005] In a first aspect, this application provides a three-dimensional memory, comprising: a substrate, a plurality of first metal electrode layers, a plurality of dielectric layers, at least one second metal electrode layer, at least one functional layer, and at least one capacitor dielectric layer;

[0006] The plurality of first metal electrode layers and the plurality of dielectric layers are arranged in an alternating stacked manner; in the alternating stacked structure, the top layer is the dielectric layer and the bottom layer is the first metal electrode layer; the bottom first metal electrode layer is disposed on the upper surface of the substrate.

[0007] Each of the second metal electrode layers is a T-shaped structure; the vertical segment of each of the second metal electrode layers extends from the upper surface of the top dielectric layer toward the substrate and into the interior of the substrate; the horizontal segment of each of the second metal electrode layers is arranged on the upper surface of the top dielectric layer.

[0008] The outer surface of each vertical segment of the second metal electrode layer is covered with the capacitor dielectric layer.

[0009] The number of functional layers and the number of the second metal electrode layers are the same, and they correspond one-to-one;

[0010] Each of the functional layers is a hollow columnar structure centered on the corresponding second metal electrode layer; each of the functional layers extends from the upper surface of the top dielectric layer toward the substrate and into the interior of the substrate.

[0011] Secondly, this application provides a method for fabricating a three-dimensional memory, comprising:

[0012] A first metal electrode layer and a dielectric layer are alternately stacked and grown on a substrate to form a substrate; in the staggered stacked structure, the top layer is the dielectric layer and the bottom layer is the first metal electrode layer; the bottom first metal electrode layer is disposed on the upper surface of the substrate;

[0013] At least one hole is formed on the substrate; the hole extends from the upper surface of the top dielectric layer toward the substrate and into the interior of the substrate;

[0014] A capacitor dielectric layer is uniformly deposited on the inner wall of each of the aforementioned holes;

[0015] After depositing the capacitor dielectric layer, the remaining space in the hole is filled with a second metal electrode layer; the third metal electrode layer extends from the area of ​​the hole to a predetermined area on the upper surface of the top dielectric layer;

[0016] After filling the second metal electrode layer, an annular groove is formed on the substrate with each second metal electrode layer as the center; the annular groove extends from the upper surface of the top dielectric layer toward the substrate and into the interior of the substrate;

[0017] For each of the aforementioned annular grooves, a functional layer is uniformly deposited within the annular groove.

[0018] Secondly, this application provides a method for fabricating a three-dimensional memory, comprising:

[0019] A first metal electrode layer and a dielectric layer are alternately stacked and grown on a substrate to form a substrate; in the staggered stacked structure, the top layer is the dielectric layer and the bottom layer is the first metal electrode layer; the bottom first metal electrode layer is disposed on the upper surface of the substrate;

[0020] At least one annular groove is formed on the substrate; each annular groove extends from the upper surface of the top dielectric layer toward the substrate and into the interior of the substrate;

[0021] For each of the aforementioned annular grooves, a functional layer is uniformly deposited within the annular groove;

[0022] After the functional layers are filled, a hole is formed at the center of each functional layer; each hole extends from the upper surface of the top dielectric layer toward the substrate and into the interior of the substrate.

[0023] For each of the aforementioned holes, a capacitor dielectric layer is uniformly deposited on the inner wall of the hole;

[0024] After depositing the capacitor dielectric layer, the remaining space in the hole is filled with a second metal electrode layer; the second metal electrode layer extends from the region of the hole to a predetermined region on the upper surface of the top dielectric layer.

[0025] According to the specific embodiments provided in this application, the following technical effects are disclosed:

[0026] This application provides a three-dimensional memory and its fabrication method. The gating device (functional layer) is fabricated in an annular groove, and the capacitor dielectric layer is fabricated on the sidewall of the hole. This allows the thickness of the capacitor dielectric in the three-dimensional memory to no longer be limited by the width of the annular groove, thereby improving the data retention time of the three-dimensional memory. It solves the problem of the thickness limitation of the capacitor dielectric by the annular groove, and allows the application of the most advanced capacitor dielectric technology to the development of three-dimensional memory. At the same time, the annular groove width can be made to about 30nm under current semiconductor processes. This thickness is within the appropriate functional layer thickness range of the gating device and will not affect the performance of the gating device. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a schematic diagram of the structure of a three-dimensional memory provided in Embodiment 1 of this application;

[0029] Figure 2 This is a schematic flowchart of a method for fabricating a three-dimensional memory provided in Embodiment 2 of this application;

[0030] Figure 3 This is a schematic flowchart of the fabrication process of the gating device provided in Embodiment 2 of this application;

[0031] Figure 4 This is a schematic flowchart illustrating the manufacturing process of the capacitor provided in Embodiment 2 of this application.

[0032] Figure label:

[0033] 1-Substrate; 2-First metal electrode layer; 3-Dielectric layer; 4-Second metal electrode layer; 5-Capacitor dielectric layer; 6-Functional layer; 7-Third metal electrode layer; 8-Fourth metal electrode layer; 9-Fifth metal electrode layer. Detailed Implementation

[0034] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0035] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0036] Example 1

[0037] This embodiment provides a three-dimensional memory, such as Figure 1 As shown, the three-dimensional memory includes a horizontal peripheral electrode layer, a vertical functional layer, and a capacitor dielectric layer. Specifically, the peripheral electrode layer includes a substrate 1, several first metal electrode layers 2, and several dielectric layers 3; the dielectric layers and the first metal electrode layers are alternately stacked and grown on the substrate. That is, the several first metal electrode layers and the several dielectric layers are arranged in an alternating stacked manner; in the alternating stacked structure, the top layer is the dielectric layer, and the bottom layer is the first metal electrode layer; the bottom first metal electrode layer is disposed on the upper surface of the substrate.

[0038] The outer electrode layer contains several vertically penetrating holes arranged in an array according to a certain pattern, with the bottom of each hole extending at least to the bottommost substrate. The inner walls of the holes are sequentially covered by a capacitor dielectric layer and a second metal electrode layer. For example... Figure 1 As shown, for each of the second metal electrode layers, the second metal electrode layer has a T-shaped structure; the vertical segment of each second metal electrode layer extends from the upper surface of the top dielectric layer toward the substrate and into the interior of the substrate; the horizontal segment of each second metal electrode layer is disposed on the upper surface of the top dielectric layer. The outer surface of the vertical segment of each second metal electrode layer is covered by the capacitor dielectric layer.

[0039] Each hole is surrounded by an annular groove, with the hole located at the center of the groove. The groove encircles the hole and perpendicularly cuts off the outer electrode layer, with the bottom extending at least to the bottommost substrate. The annular groove is uniformly filled with a functional layer; the number of functional layers and the number of the second metal electrode layers are the same, and they correspond one-to-one. Figure 1 As shown, each of the functional layers is a hollow columnar structure centered on the corresponding second metal electrode layer; each of the functional layers extends from the upper surface of the top dielectric layer toward the substrate and into the interior of the substrate.

[0040] Specifically, the bottom of the functional layer, the capacitor dielectric layer, and the second metal electrode layer is lower than the bottommost first metal electrode layer in the vertical direction. That is, the bottom of the functional layer, the bottom of the capacitor dielectric layer, and the bottom of the second metal electrode layer are all located within the region of the substrate.

[0041] The resistance of the third and fourth metal electrode layers is the same and higher than that of the first metal electrode layer; the area of ​​the second metal electrode layer opposite to the first metal electrode layer constitutes a memory cell.

[0042] In this embodiment, by placing the gating device inside the annular groove and the capacitor dielectric layer on the sidewall of the hole, the thickness limitation of the capacitor dielectric by the annular groove is solved. This allows the most advanced capacitor dielectric technology to be applied to the development of 3D 1S1C. At the same time, the ring width of the annular groove can be made to about 30nm under existing semiconductor processes. This thickness is within the appropriate functional layer thickness range of the gating device and will not affect the performance of the gating device.

[0043] As an optional implementation, the position where the first metal electrode layer contacts the annular groove is concave inward, and the interior is filled with the third metal electrode layer and the fourth metal electrode layer, respectively. The third metal electrode layer and the fourth metal electrode layer exist only in the concave region where the annular groove contacts the first metal electrode layer. The third metal electrode layer and the fourth metal electrode layer are discontinuous on the sidewall of the annular groove, so that the inner sidewall of the annular groove remains smooth. Therefore, the three-dimensional memory further includes: the third metal electrode layer and the fourth metal electrode layer.

[0044] The third metal electrode layer is evenly distributed between the inner wall of the functional layer of each hollow columnar structure and the first metal electrode layer of each layer.

[0045] The fourth metal electrode layer is evenly distributed between the outer wall of the functional layer of each hollow columnar structure and the first metal electrode layer of each layer.

[0046] As an optional implementation, the width of the third metal electrode layer and the width of the fourth metal electrode layer are the same as the width of the corresponding first metal electrode layer.

[0047] The purpose of the third and fourth metal electrode layers is to regulate the holding voltage of the gating device, because the current 1S1C operating window difference is mainly due to the low holding voltage during the high-speed operation of the gating device. The functional layer has two states: high resistance and low resistance. When the voltage across the functional layer exceeds the functional layer threshold voltage Vth, the functional layer switches from the high resistance state to the low resistance state. When the voltage across the functional layer in the low resistance state is lower than the functional layer holding voltage Vhold, the functional layer switches from the low resistance state to the high resistance state. The total holding voltage VHold of the functional layer, the third metal electrode layer, and the fourth metal electrode layer is Vhold + Vhold * R / R_low, where R_low is the resistance of the functional layer in the low resistance state, and R is the resistance of the third and fourth metal electrode layers, with a value range of 0 ≤ R ≤ Rmax, where Rmax is the value of R that makes VHold equal to Vth. The total holding voltage VHold of the gating device can be adjusted by adjusting the resistance values ​​of the third and fourth metal electrode layers; the 1S1C operating window can be increased by selecting appropriate materials with larger resistance values ​​for the third and fourth metal electrode layers.

[0048] If the third and fourth metal electrode layers are removed, the 1S1C operating window can also be increased by increasing the resistance of the first metal electrode layer. However, the first metal electrode layer is not only an electrode of the memory device, but also acts as a word line in the memory array. If the resistance of the first metal electrode layer is increased in order to increase the holding voltage of the gating device, the transmission speed of read and write signals in the three-dimensional memory array will be greatly reduced, which is unacceptable for the 3D 1S1C memory in the target DRAM scenario.

[0049] If the contact point between the first metal electrode layer and the annular groove is not recessed inward, but instead the third and fourth metal electrode layers are directly deposited on the sidewall of the annular groove, it is equivalent to forming a complete third metal electrode layer and a complete fourth metal electrode layer on the sidewall of the annular groove. Since the resistance of the third and fourth metal electrode layers is only higher than that of the first metal electrode layer, at 102... Ω Although the resistance is on the order of magnitude, it is still insufficient to separate two adjacent cells in the vertical direction. This is equivalent to the same string of memory cells in the vertical direction sharing a single gating device, thus losing the high-density advantage of 3D 1S1C memory.

[0050] If the third and fourth metal electrode layers are placed inside the hole, the same problem of sharing a single gate device for the same string of memory cells in the vertical direction will also exist. Therefore, the only feasible solution to control the 1S1C operation window is to recess the annular groove inward near the first metal electrode layer to fill the material of the third and fourth metal electrode layers with higher resistance.

[0051] In traditional 3D 1S1C fabrication processes, due to the need for deep etching of holes and annular grooves, the first metal electrode layer must be compatible with high aspect ratio etching processes. Furthermore, the first metal electrode layer also serves as the word line of the memory array, requiring it to meet low resistance requirements. However, the electrode material of the capacitor typically needs to have good matching capabilities with the capacitor dielectric, considering factors such as band structure and work function. Therefore, after fabricating the annular groove, a portion of the first metal electrode layer needs to be replaced with a capacitor electrode material that matches the capacitor dielectric to reduce leakage current in the memory cells. It is also necessary to ensure that the sidewalls of the annular groove remain smooth after the replacement, ensuring a uniform distribution of the capacitor's electric field. This requires the location where the first metal electrode layer contacts the hole to be recessed inwards, filled with a fifth metal electrode layer that is well-compatible with the capacitor dielectric layer. Therefore, the 3D memory also includes a fifth metal electrode layer.

[0052] The fifth metal electrode layer is evenly distributed between the outer surface of the capacitor dielectric layer and each of the first metal electrode layers.

[0053] The second and fifth metal electrode layers must be made of materials that can effectively limit leakage current in the capacitor dielectric layer. The second and fifth metal electrode layers are made of the same electrode material.

[0054] In this configuration, the dielectric layer and the first metal electrode layer are alternately stacked and periodically repeated in the vertical direction as needed, and the number of repetitions is the same as the number of storage cell layers required for the three-dimensional 1S1C memory. That is, the number of the first metal electrode layer and the dielectric layer is the same, and the number of layers is the same as the number of storage cell layers required for the three-dimensional memory.

[0055] This embodiment has the following advantages:

[0056] (1) By placing the capacitor dielectric layer inside the hole, the thickness of the capacitor dielectric in the 3D 1S1C is no longer limited by the width of the annular groove. The most advanced capacitor dielectric technology can be applied to the 3D 1S1C to improve the data retention time of the 3D 1S1C.

[0057] (2) A third metal electrode layer and a fourth metal electrode layer are arranged at the contact position between the annular groove and the first metal electrode layer, which improves the data operation window of the 3D 1S1C memory, reduces the bit error rate of the memory, and solves the problem that the current 3D 1S1C still has a small operation window and a high bit error rate.

[0058] (3) A fifth metal electrode layer is arranged at the position where the hole contacts the first metal electrode layer, which optimizes the electrode fabrication process of the capacitor in the 3D1S1C memory, reduces the leakage current of the memory device, and solves the problem that the current 3D1S1C fabrication process will cause large leakage current of the capacitor.

[0059] Example 2

[0060] This embodiment provides a method for fabricating a three-dimensional memory. This method involves first fabricating a gating device, and then fabricating a capacitor based on that. Specifically, as shown... Figure 2 As shown, the method for fabricating the three-dimensional memory includes:

[0061] (a1) A first metal electrode layer and a dielectric layer are alternately stacked and grown on a substrate to form a substrate; in the staggered stacked structure, the top layer is the dielectric layer and the bottom layer is the first metal electrode layer; the bottom first metal electrode layer is disposed on the upper surface of the substrate.

[0062] (a2) At least one annular groove is formed on the substrate; each annular groove extends from the upper surface of the top dielectric layer toward the substrate and into the interior of the substrate.

[0063] (a3) For each of the annular grooves, a functional layer is uniformly deposited within the annular groove.

[0064] Steps (a1) to (a3) ​​describe the fabrication process of the gating device, corresponding to... Figure 2 and Figure 3 The preparation operations are shown in (a), (b) and (e) in the figure.

[0065] (a4) After filling the functional layers, a hole is formed at the center of each functional layer; each hole extends from the upper surface of the top dielectric layer toward the substrate and into the interior of the substrate.

[0066] (a5) For each of the holes, a capacitor dielectric layer is uniformly deposited on the inner wall of the hole.

[0067] (a6) After depositing the capacitor dielectric layer, the remaining space in the hole is filled with a second metal electrode layer; the second metal electrode layer extends from the area of ​​the hole to a predetermined area on the upper surface of the top dielectric layer.

[0068] Steps (a4) to (a6) describe the capacitor fabrication process, corresponding to... Figure 2 The preparation processes shown in (f), (i), and (j) are as follows: Figure 4 The preparation operations are shown in (a), (d) and (e) in the figure.

[0069] As an optional implementation, before performing step (a3) ​​"uniformly depositing a functional layer within each of the annular grooves", the method for fabricating the three-dimensional memory further includes:

[0070] (1) Remove a portion of the first metal electrode layer exposed within the annular groove evenly inwards. This step corresponds to... Figure 2 and Figure 3 The preparation operation is shown in (c).

[0071] (2) Selectively deposit the third and fourth metal electrode layers at the locations where the first metal electrode layer was removed, keeping the inner walls of the annular groove smooth, so that the functional layer can be uniformly deposited in the annular groove to fill it completely. This step corresponds to... Figure 2 and Figure 3 The preparation operation is shown in (d).

[0072] As an optional implementation, before performing step (a5) "uniformly depositing a capacitor dielectric layer on the inner wall of each of the holes", the method for fabricating the three-dimensional memory further includes:

[0073] (1) Remove a portion of the first metal electrode layer exposed inside the hole evenly inward. This step corresponds to... Figure 2 (g) and Figure 4 The preparation operation is shown in (b).

[0074] (2) Selectively deposit a fifth metal electrode layer at the locations where the first metal electrode layer was removed, ensuring the inner walls of the circular holes remain smooth. This step corresponds to... Figure 2 (h) and Figure 4 The preparation operation is shown in (c).

[0075] The following describes the fabrication method of the 3D memory after introducing specific materials into each layer. The fabrication process involves first fabricating the gating device, followed by the capacitor fabrication process. The specific fabrication process flow is as follows:

[0076] like Figure 2 In (a), a three-layer stack of 50nm W (tungsten) and 100nm SiO2 (silicon dioxide) is first prepared on substrate 1, with the top layer being SiO2; that is, the dielectric layer is SiO2 and the first metal electrode layer is W.

[0077] like Figure 2 In (b), an annular pattern is formed on the stack by photolithography, and ICP etching with good anisotropy is used. The etching gas is SF6+C4F8 (sulfur hexafluoride + octafluorocyclobutane) to etch the stack, and the resulting annular groove has a ring width of 30nm.

[0078] like Figure 2In (c), a mixture of hydrofluoric acid (HF) and nitric acid (HNO3) was used to selectively remove W exposed at 20 nm.

[0079] like Figure 2 In step (d), a TiN (tin) electrode with a thickness of 20 nm is uniformly grown on the W surface using an ALD process with a precursor that has selective growth capability for W and SiO2, ensuring that the sidewalls of the annular groove remain flat. That is, the third and fourth metal electrode layers are made of TiN.

[0080] like Figure 2 In (e), a 15nm GeTE9 material is uniformly deposited on the sidewall of the circular hole using the ALD process to fill the annular groove.

[0081] like Figure 2 In (f), a circular pattern is formed on the stack above the annular groove by photolithography. ICP etching with good anisotropy is used, and SF6+C4F8 is selected as the etching gas to etch the stack. The diameter of the circular hole is 100nm.

[0082] like Figure 2 In the (g) of the sample, the exposed W5nm was selectively removed using a mixture of hydrofluoric acid (HF) and nitric acid (HNO3);

[0083] like Figure 2 In (h), a TiN electrode with a thickness of 5 nm is uniformly grown on the W surface by ALD process;

[0084] like Figure 2 In (i), a layer of 2nm ZrO2 (zirconia), 1nm Al2O3 (aluminum oxide), and 2nm ZrO2 is deposited on the sidewall of the circular hole using the ALD process.

[0085] like Figure 2 In step (j), using the ALD process, a 30nm TiN electrode was deposited on the sidewall of the circular hole. This completes the fabrication of the three-dimensional memory.

[0086] When TiN is used as the capacitor electrode material, i.e., the material of the fifth metal electrode layer, compared to the traditional use of W as the electrode material, the leakage current of the capacitor is reduced from 2 × 10⁻⁶. -6 A / cm 2 Decreased to 6×10 -8 A / cm 2 This significantly reduces capacitor leakage current and improves data retention time in storage devices. Furthermore, by fabricating the capacitor on the sidewall of a circular hole, the dielectric thickness can be reduced to 5 nm, increasing the capacitance by a factor of 6.

[0087] In addition, by adding a high-resistivity TiN layer (i.e., the third and fourth metal electrode layers) between the functional layer and the first metal electrode layer, the holding voltage of the gating device is increased from 0.5V to 1V, and the operating window of the memory is also increased by 0.5V accordingly.

[0088] Example 3

[0089] This embodiment provides a method for fabricating a three-dimensional memory. The method involves first fabricating a capacitor, and then fabricating a gating device based on that capacitor. Specifically, the method for fabricating the three-dimensional memory includes:

[0090] (b1) A first metal electrode layer and a dielectric layer are alternately stacked and grown on a substrate to form a substrate; in the staggered stacked structure, the top layer is the dielectric layer and the bottom layer is the first metal electrode layer; the bottom first metal electrode layer is disposed on the upper surface of the substrate.

[0091] (ab2) Form at least one hole on the substrate; the hole extends from the upper surface of the top dielectric layer toward the substrate and into the interior of the substrate.

[0092] (b3) A capacitor dielectric layer is uniformly deposited on the inner wall of each of the holes.

[0093] Steps (b1) to (b3) describe the capacitor fabrication process, corresponding to... Figure 4 The preparation operations are shown in (a), (d) and (e).

[0094] (b4) After depositing the capacitor dielectric layer, the remaining space in the hole is filled with a second metal electrode layer; the third metal electrode layer extends from the area of ​​the hole to a predetermined area on the upper surface of the top dielectric layer.

[0095] (b5) After filling the second metal electrode layer, an annular groove is formed on the substrate with each second metal electrode layer as the center; the annular groove extends from the upper surface of the top dielectric layer toward the substrate and into the interior of the substrate.

[0096] (b6) For each of the annular grooves, a functional layer is uniformly deposited within the annular groove.

[0097] Steps (b4) to (b6) describe the fabrication process of the gating device, corresponding to... Figure 3 The preparation operations are shown in (a), (b) and (e).

[0098] As an optional implementation, before performing step (b3) "uniformly depositing a capacitor dielectric layer on the inner wall of each of the holes", the method for fabricating the three-dimensional memory further includes:

[0099] (1) Remove a portion of the first metal electrode layer exposed inside the hole evenly inward. This step corresponds to... Figure 4 The preparation process is shown in (b).

[0100] (2) Selectively deposit a fifth metal electrode layer at the locations where the first metal electrode layer was removed, ensuring the inner walls of the circular holes remain smooth. This step corresponds to... Figure 4 The preparation operation is shown in (c).

[0101] Before performing step (b6) "for each of the annular grooves, uniformly depositing a functional layer within the annular grooves", the method for fabricating the three-dimensional memory further includes:

[0102] (1) Remove a portion of the first metal electrode layer exposed within the annular groove evenly inwards. This step corresponds to... Figure 3 The preparation operation is shown in (c).

[0103] (2) Selectively deposit the third and fourth metal electrode layers at the locations where the first metal electrode layer was removed, keeping the inner walls of the annular groove smooth, so that the functional layer can be uniformly deposited in the annular groove to fill it completely. This step corresponds to... Figure 3 The preparation operation is shown in (d).

[0104] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0105] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A three-dimensional memory, comprising: The three-dimensional memory comprises a substrate, a plurality of first metal electrode layers, a plurality of dielectric layers, at least one second metal electrode layer, at least one functional layer and at least one capacitor dielectric layer; The plurality of first metal electrode layers and the plurality of dielectric layers are arranged in an interlaced manner; in the interlaced structure, the top layer is the dielectric layer, and the bottom layer is the first metal electrode layer; the bottom layer of the first metal electrode layer is arranged on the upper surface of the substrate; Each of the second metal electrode layers is in a T-shaped structure; the vertical segment of each of the second metal electrode layers penetrates and extends to the inside of the substrate from the upper surface of the top layer of the dielectric layer to the direction of the substrate; the horizontal segment of each of the second metal electrode layers is arranged on the upper surface of the top layer of the dielectric layer; The outer surface of the vertical segment of each of the second metal electrode layers is coated with the capacitor dielectric layer; The number of the functional layers is the same as that of the second metal electrode layers, and each of the functional layers corresponds to one of the second metal electrode layers; Each of the functional layers is a hollow columnar structure with the corresponding second metal electrode layer as the center; each of the functional layers penetrates and extends to the inside of the substrate from the upper surface of the top layer of the dielectric layer to the direction of the substrate.

2. The three-dimensional memory of claim 1, wherein, The three-dimensional memory further comprises a third metal electrode layer and a fourth metal electrode layer; The third metal electrode layer is arranged between the inner wall of each of the hollow columnar structures and each of the first metal electrode layers; The fourth metal electrode layer is arranged between the outer wall of each of the hollow columnar structures and each of the first metal electrode layers.

3. The three-dimensional memory of claim 2, wherein, The width of the third metal electrode layer, the width of the fourth metal electrode layer and the width of the corresponding first metal electrode layer are the same.

4. The three-dimensional memory of claim 1, wherein, The three-dimensional memory further comprises a fifth metal electrode layer; The fifth metal electrode layer is arranged between the outer surface of the capacitor dielectric layer and each of the first metal electrode layers.

5. The three-dimensional memory of claim 4, wherein, The second metal electrode layer and the fifth metal electrode layer are made of a material that limits the leakage current in the capacitor dielectric layer.

6. The three-dimensional memory of claim 2, wherein, The resistance of the third metal electrode layer and the resistance of the fourth metal electrode layer are the same and higher than the resistance of the first metal electrode layer.

7. The three-dimensional memory of claim 1, wherein, The bottom of the functional layer, the bottom of the capacitor dielectric layer and the bottom of the second metal electrode layer are all located in the area where the substrate is located.

8. The three-dimensional memory of claim 1, wherein, The number of the first metal electrode layers is the same as the number of the dielectric layers, and the number is the same as the number of the required storage units of the three-dimensional memory.

9. A method of making a three-dimensional memory, comprising: The preparation method of the three-dimensional memory comprises: The first metal electrode layers and the dielectric layers are alternately stacked and grown on the substrate to form a substrate; in the interlaced structure, the top layer is the dielectric layer, and the bottom layer is the first metal electrode layer; the bottom layer of the first metal electrode layer is arranged on the upper surface of the substrate; At least one hole is formed on the substrate; the hole penetrates and extends to the inside of the substrate from the upper surface of the top layer of the dielectric layer to the direction of the substrate; The capacitor dielectric layer is uniformly deposited on the inner wall of each of the holes. After the capacitor dielectric layer is deposited, a second metal electrode layer is filled in the remaining space of the hole; the second metal electrode layer extends from the area of the hole to a preset area of the upper surface of the topmost dielectric layer; After the second metal electrode layer is filled, a ring-shaped groove is formed on the substrate with each second metal electrode layer as the center; the ring-shaped groove penetrates and extends to the inside of the substrate from the upper surface of the topmost dielectric layer to the substrate; For each ring-shaped groove, a functional layer is uniformly deposited in the ring-shaped groove.

10. A method of making a three-dimensional memory, comprising: The preparation method of the three-dimensional memory comprises: a substrate is formed by alternately stacking and growing a first metal electrode layer and a dielectric layer on a substrate; in the interleaved stacked structure, the topmost layer is the dielectric layer, and the bottommost layer is the first metal electrode layer; the bottommost first metal electrode layer is arranged on the upper surface of the substrate; at least one ring-shaped groove is formed on the substrate; each ring-shaped groove penetrates and extends to the inside of the substrate from the upper surface of the topmost dielectric layer to the substrate; for each ring-shaped groove, a functional layer is uniformly deposited in the ring-shaped groove; after the functional layer is filled, a hole is formed at the center of each functional layer; each hole penetrates and extends to the inside of the substrate from the upper surface of the topmost dielectric layer to the substrate; for each hole, a capacitor dielectric layer is uniformly deposited on the inner wall of the hole; after the capacitor dielectric layer is deposited, a second metal electrode layer is filled in the remaining space of the hole; the second metal electrode layer extends from the area of the hole to a preset area of the upper surface of the topmost dielectric layer.

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