Method for forming a semiconductor device

Abstract

The present invention provides a method for forming a semiconductor device, comprising: forming a shallow trench isolation structure higher than the surface of a floating gate layer in a substrate in a peripheral region; etching a portion of the width of the shallow trench isolation structure so that the height of the shallow trench isolation structure located above the floating gate layer meets the standard and the width becomes smaller, thereby causing steps to appear on the side of the shallow trench isolation structure; forming a gate dielectric layer on the surface of the floating gate layer, the gate dielectric layer simultaneously covering the steps of the shallow trench isolation structure; forming a control gate layer and a word line passing through the control gate layer and the floating gate layer on the surface of the gate dielectric layer in a storage region; forming a first control gate sidewall on the surface of the gate dielectric layer in the storage region, and forming a second control gate sidewall covering the sidewall of the shallow trench isolation structure on the surface of the gate dielectric layer in the peripheral region, the second control gate sidewall being located at the step of the shallow trench isolation structure; and removing uncovered portions of the gate dielectric layer, the floating gate layer and the pad oxide layer to expose a portion of the substrate surface.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for forming a semiconductor device. Background Art

[0002] Some memory semiconductors are divided into a memory region for forming a memory device and a peripheral region for forming related peripheral circuits.

[0003] Please refer to Figure 1 A conventional memory semiconductor device includes: a pad oxide layer 102, a floating gate layer 103, a gate dielectric layer 104, and a control gate layer 105 are sequentially formed on the surface of a substrate 101 in the storage region. A first spacer 106 is formed on the surface of the control gate layer 105. A second spacer 107 is formed within the opening of the first spacer 106. The second spacer covers the sidewalls of the pad oxide layer 102, the sidewalls of the floating gate layer 103, the sidewalls of the gate dielectric layer 104, and the sidewalls of the control gate layer 105. The top end of the second spacer is connected to the first spacer 106, and the bottom end is connected to the substrate 101. The first spacer 106 and the second spacer 107 form a source line opening, and a source line 108 is formed within the source line opening. A control gate spacer 109 is formed outside the source line to isolate the control gate from a subsequently formed word line. A shallow trench isolation structure 110 is formed in the substrate in the peripheral region. The surface of the shallow trench isolation structure 110 is higher than the surface of the substrate 101. The sidewalls of the shallow trench isolation structure 110 are inclined, that is, the shallow trench isolation structure 110 is wide at the top and narrow at the bottom.

[0004] However, when forming the floating gate and control gate sidewalls 109 in the storage region, they are also formed simultaneously in the peripheral region. The control gate sidewalls 109 and floating gate layer 103 in the peripheral region are then removed by etching. However, due to the tilted shallow trench isolation structure 110, the control gate sidewalls 109 remain in the corners of the outer wall. Furthermore, due to the obstruction of the control gate sidewalls 109, the floating gate layer 103 beneath the control gate sidewalls 109 cannot be completely removed, resulting in a continuous, uninterrupted strip. The remaining floating gate layer 103 has caused standby current failures in the product CP1 test. Summary of the Invention

[0005] The object of the present invention is to provide a method for forming a semiconductor device, which can completely remove the floating gate layer in the peripheral region and reduce the failure rate of the CP1 test.

[0006] In order to achieve the above object, the present invention provides a method for manufacturing a memory, comprising:

[0007] providing a substrate, dividing the substrate into adjacent storage areas and a peripheral area;

[0008] forming a pad oxide layer and a floating gate layer in sequence on the surface of the substrate;

[0009] forming a shallow trench isolation structure in the substrate of the peripheral region, wherein the surface of the shallow trench isolation structure is higher than the surface of the floating gate layer;

[0010] Etching a shallow trench isolation structure of partial height and a shallow trench isolation structure of partial width, so that the height of the shallow trench isolation structure located above the floating gate layer meets the standard and the width becomes smaller, thereby causing steps to appear on the side of the shallow trench isolation structure;

[0011] forming a gate dielectric layer on the surface of the floating gate layer, wherein the gate dielectric layer also covers the steps of the shallow trench isolation structure;

[0012] A control gate layer and a word line passing through the control gate layer and the floating gate layer are formed on the surface of the gate dielectric layer in the storage area, a first spacer is further formed on the surface of the control gate layer, and the word line is separated from the control gate layer and the floating gate layer by a second spacer;

[0013] forming a first control gate spacer on the surface of the gate dielectric layer in the storage region, the first control gate spacer covering the first spacer and the sidewall of the control gate layer; and forming a second control gate spacer on the surface of the gate dielectric layer in the peripheral region, the second control gate spacer covering the sidewall of the shallow trench isolation structure, the second control gate spacer being located at a step of the shallow trench isolation structure;

[0014] The uncovered portions of the gate dielectric layer, the floating gate layer and the pad oxide layer are removed to expose a portion of the surface of the substrate.

[0015] Optionally, in the memory manufacturing method, a method of forming a shallow trench isolation structure in the substrate of the peripheral region, wherein the surface of the shallow trench isolation structure is higher than the surface of the floating gate layer, includes:

[0016] forming a sacrificial oxide layer on a surface of the floating gate layer;

[0017] Sequentially etching a portion of the sacrificial oxide layer, the floating gate layer, the pad oxide layer, and the substrate in the peripheral region to form a shallow trench in the substrate;

[0018] Filling the shallow trench with oxide to form a shallow trench isolation structure;

[0019] The sacrificial oxide layer is removed.

[0020] Optionally, in the memory manufacturing method, the substrate includes a wafer.

[0021] Optionally, in the memory manufacturing method, the gate dielectric layer includes an ONO layer.

[0022] Optionally, in the memory manufacturing method, the floating gate layer and the control gate layer both include polysilicon.

[0023] Optionally, in the above-mentioned method for manufacturing a memory, a method in which a control gate layer and a word line passing through the control gate layer and the floating gate layer are formed on a surface of the gate dielectric layer in the memory region, a first spacer is further formed on a surface of the control gate layer, and the word line is separated from the control gate layer and the floating gate layer by a second spacer includes:

[0024] forming a control gate layer and a hard mask on a surface of the gate dielectric layer, wherein the hard mask has a first opening;

[0025] forming a first sidewall in the first opening;

[0026] removing portions of the control gate layer, the gate dielectric layer, the floating gate layer, and the pad oxide layer not covered by the first spacer to expose the surface of the substrate;

[0027] forming a second spacer, wherein the second spacer covers the sidewall of the control gate layer, the sidewall of the gate dielectric layer, the sidewall of the floating gate layer, and the sidewall of the pad oxide layer, and the first spacer and the second spacer form a source line opening;

[0028] A source line is formed in the source line opening.

[0029] Optionally, in the memory manufacturing method, the method of forming a source line in the source line opening includes:

[0030] The source line opening is filled with polysilicon to form a source line.

[0031] Optionally, in the memory manufacturing method, the pad oxide layer includes oxide.

[0032] Optionally, in the memory manufacturing method, the first spacer, the first control gate spacer, and the second control gate spacer all include oxide.

[0033] Optionally, in the memory manufacturing method, the second sidewall spacer includes nitride.

[0034] The method for forming a semiconductor device provided by the present invention includes: providing a substrate, dividing the substrate into adjacent storage areas and peripheral areas; forming a liner oxide layer and a floating gate layer in sequence on the surface of the substrate; forming a shallow trench isolation structure in the substrate of the peripheral area, wherein the surface of the shallow trench isolation structure is higher than the surface of the floating gate layer; etching a shallow trench isolation structure of a portion of height and a shallow trench isolation structure of a portion of width, so that the height of the shallow trench isolation structure located above the floating gate layer meets the standard and the width becomes smaller, thereby causing steps to appear on the side of the shallow trench isolation structure; forming a gate dielectric layer on the surface of the floating gate layer, wherein the gate dielectric layer also covers the steps of the shallow trench isolation structure; etching the shallow trench isolation structure in the storage area; etching the shallow trench isolation structure in the peripheral ... A control gate layer and a word line passing through the control gate layer and the floating gate layer are formed on the surface of the gate dielectric layer in the storage region. A first sidewall is also formed on the surface of the control gate layer. The word line is separated from the control gate layer and the floating gate layer by a second sidewall. A first control gate sidewall is formed on the surface of the gate dielectric layer in the storage region, the first control gate sidewall covering the first sidewall and the sidewall of the control gate layer. Simultaneously, a second control gate sidewall is formed on the surface of the gate dielectric layer in the peripheral region, the second control gate sidewall covering the sidewall of the shallow trench isolation structure, the second control gate sidewall being located at a step of the shallow trench isolation structure. The uncovered portion of the gate dielectric layer, the floating gate layer, and the pad oxide layer are removed to expose a portion of the substrate surface. The shallow trench isolation structure formed by the present invention has a step, and the second control gate sidewall formed covers the step. Therefore, when removing the floating gate layer in the peripheral region, it will not be blocked by the second control gate sidewall, thereby completely removing the floating gate layer in the peripheral region and reducing the failure rate of the CP1 test. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a schematic structural diagram of a semiconductor device in the prior art;

[0036] Figure 2 is a flow chart of a method for forming a semiconductor device according to an embodiment of the present invention;

[0037] Figures 3 to 7 is a structural schematic diagram of a semiconductor device during formation according to an embodiment of the present invention;

[0038] In the figure: 101-substrate, 102-pad oxide layer, 103-floating gate layer, 104-gate dielectric layer, 105-control gate layer, 106-first sidewall, 107-second sidewall, 108-source line, 109-control gate sidewall, 110-shallow trench isolation structure, 201-substrate, 201A-storage area, 201B-peripheral area, 202-pad oxide layer, 203-floating gate layer, 204-shallow trench isolation structure, 205-first oxide layer, 206-nitride layer, 207-second oxide layer, 208-control gate layer, 209-first sidewall, 210-second sidewall, 211-source line, 212-first control gate sidewall, 213-second control gate sidewall. DETAILED DESCRIPTION

[0039] The following is a more detailed description of the specific embodiments of the present invention with reference to schematic diagrams. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are greatly simplified and not to exact scale, and are only used for the purpose of conveniently and clearly illustrating the embodiments of the present invention.

[0040] Hereinafter, the terms "first," "second," and the like are used to distinguish between similar elements and are not necessarily used to describe a particular order or chronological sequence. It is to be understood that these terms used in this manner are interchangeable where appropriate. Similarly, if a method described herein comprises a series of steps, the order in which the steps are presented herein is not necessarily the only order in which the steps may be performed, and some of the steps described may be omitted and / or other steps not described herein may be added to the method.

[0041] Furthermore, it should be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, and / or pattern, it can be directly on another layer or substrate, and / or intervening layers can also be present. Additionally, it should be understood that when a layer is referred to as being "under" another layer, it can be directly under another layer, and / or one or more intervening layers can also be present. Additionally, references to being "on" and "under" various layers can be made based on the accompanying drawings.

[0042] Please refer to Figure 2 The present invention provides a method for manufacturing a memory, comprising:

[0043] S11: providing a substrate, and dividing the substrate into adjacent storage areas and peripheral areas;

[0044] S12: forming a pad oxide layer and a floating gate layer in sequence on the surface of the substrate;

[0045] S13: forming a shallow trench isolation structure in the substrate of the peripheral region, wherein a surface of the shallow trench isolation structure is higher than a surface of the floating gate layer;

[0046] S14: etching a portion of the shallow trench isolation structure in height and a portion of the shallow trench isolation structure in width, so that the height of the shallow trench isolation structure located above the floating gate layer meets the standard and the width becomes smaller, thereby causing steps to appear on the side of the shallow trench isolation structure;

[0047] S15: forming a gate dielectric layer on the surface of the floating gate layer, wherein the gate dielectric layer also covers the step of the shallow trench isolation structure;

[0048] S16: forming a control gate layer and a word line passing through the control gate layer and the floating gate layer on a surface of the gate dielectric layer in the storage region, wherein a first spacer is further formed on the surface of the control gate layer, and the word line is separated from the control gate layer and the floating gate layer by a second spacer;

[0049] S17: forming a first control gate sidewall on the surface of the gate dielectric layer in the storage region, the first control gate sidewall covering the first sidewall and the sidewall of the control gate layer; and simultaneously forming a second control gate sidewall on the surface of the gate dielectric layer in the peripheral region, the second control gate sidewall covering the sidewall of the shallow trench isolation structure, the second control gate sidewall being located at a step of the shallow trench isolation structure;

[0050] S18: removing uncovered portions of the gate dielectric layer, the floating gate layer, and the pad oxide layer to expose a portion of the substrate surface.

[0051] Please refer to Figure 3 First, a substrate 201 is provided. The substrate 201 can be a silicon substrate, such as a wafer. The substrate is divided into adjacent storage areas 201A and peripheral areas 201B. Next, a pad oxide layer 202 is formed on the surface of the substrate 201. The material of the pad oxide layer 202 can be silicon dioxide and can be formed by deposition. Next, a floating gate layer 203 is formed on the surface of the pad oxide layer 202. The material of the floating gate layer 203 can be polysilicon and can be formed by deposition. Next, a sacrificial oxide layer is formed on the surface of the floating gate layer 203. The material of the sacrificial oxide layer can be silicon dioxide and can be formed by deposition. Starting from the surface of the sacrificial oxide layer, the sacrificial oxide layer, the floating gate layer 203, the pad oxide layer 202, and a portion of the thickness of the substrate 201 are etched downward. The etching stops within the substrate 201, thereby forming a shallow trench in the substrate 201. The shallow trench is filled with oxide to form a shallow trench isolation structure 204. Next, the sacrificial oxide layer is removed, so that the surface of the shallow trench isolation structure 204 is higher than the surface of the floating gate layer 203. Moreover, the height of the shallow trench isolation structure 204 at this time is higher than the final target height of the shallow trench isolation structure 204.

[0052] Next, please refer to Figure 4 , etching a portion of the height of the shallow trench isolation structure 204 and a portion of the width of the shallow trench isolation structure 204, so that the height of the shallow trench isolation structure 204 located above the floating gate layer 203 meets the standard and the width becomes smaller, thereby causing steps to appear on the side of the shallow trench isolation structure 204.

[0053] Next, please refer to Figure 5A gate dielectric layer is formed on the surface of the floating gate layer 203. The gate dielectric layer is an ONO layer. Specifically, the gate dielectric layer includes a first oxide layer 205, a nitride layer 206, and a second oxide layer 207. The materials of the first oxide layer 205 and the second oxide layer 207 can be silicon dioxide, and the material of the nitride layer 206 can be silicon nitride. The gate dielectric layer can be formed by sequentially depositing the first oxide layer 205, the nitride layer 206, and the second oxide layer 207. Next, a control gate layer 208 and a hard mask are formed on the surface of the second oxide layer 207. The material of the control gate layer 208 is polycrystalline silicon. The hard mask is etched to form a first opening through the hard mask. Next, a first spacer 209 is formed on the sidewalls of the hard mask within the first opening. Next, the portion of the control gate layer 117, the gate dielectric layer, the floating gate layer 203, and the pad oxide layer 202 within the first opening not covered by the first spacer 209 is etched to expose the surface of the substrate 201. Next, a second spacer 210 is formed, covering the sidewalls of the control gate layer 207, the gate dielectric layer, the floating gate layer, and the pad oxide layer 202. The top of the second spacer 210 is connected to the first spacer 209, and the bottom is connected to the surface of the substrate 201. A source line opening is formed between the first spacer 209 and the second spacer 210. Next, the source line opening is filled with polysilicon, and the surface of the polysilicon is polished, thereby forming a source line 211 within the source line opening.

[0054] Next, please refer to Figure 6 A first control gate sidewall 212 is formed on the surface of the gate dielectric layer in the storage area 201A, and the first control gate sidewall 212 covers the first sidewall 209 and the sidewall of the control gate layer 208. At the same time, a second control gate sidewall 213 is formed on the surface of the gate dielectric layer in the peripheral area 201B, and the second control gate sidewall 213 covers the sidewall of the shallow trench isolation structure 204. The second control gate sidewall 213 is located at the step of the shallow trench isolation structure 204.

[0055] Next, please refer to Figure 7 The uncovered portions of the gate dielectric layer, floating gate layer 203, and pad oxide layer 202 in the storage region 201A and the peripheral region 201B are removed, exposing a portion of the surface of the substrate 201. At this point, since the second control gate spacer 213 is on the step of the shallow trench isolation structure 204 and does not cover the floating gate layer 203, the floating gate layer 203 in the peripheral region 201B can be completely removed.

[0056] In summary, the method for forming a semiconductor device provided in an embodiment of the present invention includes: providing a substrate, dividing the substrate into adjacent storage areas and peripheral areas; forming a liner oxide layer and a floating gate layer in sequence on the surface of the substrate; forming a shallow trench isolation structure in the substrate of the peripheral area, wherein the surface of the shallow trench isolation structure is higher than the surface of the floating gate layer; etching a shallow trench isolation structure of a portion of height and a shallow trench isolation structure of a portion of width, so that the height of the shallow trench isolation structure located above the floating gate layer meets the standard and the width becomes smaller, thereby causing steps to appear on the side of the shallow trench isolation structure; forming a gate dielectric layer on the surface of the floating gate layer, wherein the gate dielectric layer also covers the steps of the shallow trench isolation structure. A control gate layer and a word line passing through the control gate layer and the floating gate layer are formed on the surface of the gate dielectric layer in the storage area. A first sidewall is also formed on the surface of the control gate layer. The word line is separated from the control gate layer and the floating gate layer by a second sidewall. A first control gate sidewall is formed on the surface of the gate dielectric layer in the storage area, the first control gate sidewall covering the first sidewall and the sidewall of the control gate layer. At the same time, a second control gate sidewall is formed on the surface of the gate dielectric layer in the peripheral area, the second control gate sidewall covering the sidewall of the shallow trench isolation structure, and the second control gate sidewall is located at a step of the shallow trench isolation structure. The uncovered portion of the gate dielectric layer, the floating gate layer, and the pad oxide layer are removed to expose a portion of the substrate surface. The shallow trench isolation structure formed by the present invention has a step, and the second control gate sidewall formed covers the step. Therefore, when removing the floating gate layer in the peripheral area, it will not be blocked by the second control gate sidewall, thereby completely removing the floating gate layer in the peripheral area and reducing the failure rate of the CP1 test.

[0057] The above description is merely a preferred embodiment of the present invention and does not limit the present invention in any way. Any person skilled in the art who, without departing from the scope of the present invention, makes any equivalent substitution, modification, or other changes to the technical solution and technical content disclosed in the present invention shall be deemed to be within the scope of the present invention and still fall within the scope of protection of the present invention.

Claims

1. A method for manufacturing a memory, characterized in that: include: providing a substrate, dividing the substrate into adjacent storage areas and a peripheral area; forming a pad oxide layer and a floating gate layer in sequence on the surface of the substrate; forming a shallow trench isolation structure in the substrate of the peripheral region, wherein the surface of the shallow trench isolation structure is higher than the surface of the floating gate layer; Etching a shallow trench isolation structure of partial height and a shallow trench isolation structure of partial width, so that the height of the shallow trench isolation structure located above the floating gate layer meets the standard and the width becomes smaller, thereby causing steps to appear on the side of the shallow trench isolation structure; forming a gate dielectric layer on the surface of the floating gate layer, wherein the gate dielectric layer also covers the steps of the shallow trench isolation structure; A control gate layer and a word line passing through the control gate layer and the floating gate layer are formed on the surface of the gate dielectric layer in the storage area, a first spacer is further formed on the surface of the control gate layer, and the word line is separated from the control gate layer and the floating gate layer by a second spacer; forming a first control gate spacer on the surface of the gate dielectric layer in the storage region, the first control gate spacer covering the first spacer and the sidewall of the control gate layer; and forming a second control gate spacer on the surface of the gate dielectric layer in the peripheral region, the second control gate spacer covering the sidewall of the shallow trench isolation structure, the second control gate spacer being located at a step of the shallow trench isolation structure; The uncovered portions of the gate dielectric layer, the floating gate layer and the pad oxide layer are removed to expose a portion of the surface of the substrate.

2. The method for manufacturing a memory according to claim 1, wherein: The method of forming a shallow trench isolation structure in a substrate in a peripheral region, wherein a surface of the shallow trench isolation structure is higher than a surface of the floating gate layer, comprises: forming a sacrificial oxide layer on a surface of the floating gate layer; Sequentially etching a portion of the sacrificial oxide layer, the floating gate layer, the pad oxide layer, and the substrate in the peripheral region to form a shallow trench in the substrate; Filling the shallow trench with oxide to form a shallow trench isolation structure; The sacrificial oxide layer is removed.

3. The method for manufacturing a memory according to claim 1, wherein: The substrate includes a wafer.

4. The method for manufacturing a memory according to claim 1, wherein: The gate dielectric layer includes an ONO layer.

5. The method for manufacturing a memory according to claim 1, wherein: The floating gate layer and the control gate layer both include polysilicon.

6. The method for manufacturing a memory according to claim 1, wherein: A method of forming a control gate layer and a word line passing through the control gate layer and the floating gate layer on a surface of the gate dielectric layer in the storage region, wherein a first spacer is further formed on the surface of the control gate layer, and the word line is separated from the control gate layer and the floating gate layer by a second spacer comprises: forming a control gate layer and a hard mask on a surface of the gate dielectric layer, wherein the hard mask has a first opening; forming a first sidewall in the first opening; removing portions of the control gate layer, the gate dielectric layer, the floating gate layer, and the pad oxide layer not covered by the first spacer to expose the surface of the substrate; forming a second spacer, wherein the second spacer covers the sidewall of the control gate layer, the sidewall of the gate dielectric layer, the sidewall of the floating gate layer, and the sidewall of the pad oxide layer, and the first spacer and the second spacer form a source line opening; A source line is formed in the source line opening.

7. The method for manufacturing a memory according to claim 6, wherein: The method of forming a source line in the source line opening includes: The source line opening is filled with polysilicon to form a source line.

8. The method for manufacturing a memory according to claim 1, wherein: The pad oxide layer includes oxide.

9. The method for manufacturing a memory according to claim 1, wherein: The first spacer, the first control gate spacer and the second control gate spacer all comprise oxide.

10. The method for manufacturing a memory according to claim 1, wherein: The second spacer comprises nitride.

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