Quasi-vertical super junction diode and monolithic integrated full-bridge rectifier circuit

Abstract

The application discloses a quasi-vertical super-junction diode and a monolithic integrated full-bridge rectifier circuit. The diode comprises, from bottom to top, a Si substrate, an N+ GaN conducting layer and a hetero super-junction structure layer. The hetero super-junction structure layer is provided with P-BN ring regions and N GaN ring regions in a concentric ring distribution mode along the longitudinal direction. The P-BN ring regions and the side surface of the hetero super-junction structure layer are P-type BN materials doped with Mg. The surface of the hetero super-junction structure layer is provided with an anode. The surface of the N+ GaN conducting layer is provided with a cathode surrounding the hetero super-junction structure layer and having a spacing. The monolithic integrated full-bridge rectifier circuit comprises two alternating current input ends, a rectifier circuit composed of four diodes, a filter circuit composed of two filter capacitors and a filter resistor and two output ends. The diode is a quasi-vertical super-junction diode. The application can improve the voltage resistance of the diode, the circuit integration, widen the voltage application window, enhance the power processing capacity and improve the conversion efficiency.

Description

Technical Field

[0001] This invention belongs to the field of semiconductors, specifically relating to a quasi-vertical superjunction diode and a monolithically integrated full-bridge rectifier circuit. Background Technology

[0002] Third-generation semiconductor materials, such as GaN, possess superior electrical properties compared to Si-based materials, including a large bandgap, high critical breakdown electric field, high saturation velocity, good thermal conductivity, high temperature resistance, and corrosion resistance. These properties make them suitable for applications in high-frequency, high-power, and high-radiation environments. In recent years, thanks to its excellent characteristics such as low saturation velocity, low breakdown voltage, low inversion layer mobility, and high device resistance, GaN-based power devices have developed rapidly and are widely used in power systems.

[0003] Full-bridge rectifier circuits are mostly composed of discrete components, resulting in low integration. Currently, most GaN power devices are still used as single transistors in rectifier circuits. However, with increasing demands for power handling capabilities and miniaturization in rectifier systems, as well as the diversification of application scenarios, higher requirements are being placed on the reliability of circuit systems. Existing board-level integrated rectifier systems are becoming increasingly inadequate to meet the needs of modern development. Compared to traditional GaN integrated circuits, silicon-based GaN monolithic integrated circuits offer smaller size, lower parasitic emissions, higher power density, lower cost, and higher reliability, enabling their application in power systems with complex operating environments and limited space, such as small-volume high-power power supplies, new energy vehicles, photovoltaic inverters, and electric locomotive traction modules.

[0004] However, existing GaN-based monolithic rectifier circuits have low waveform rectification efficiency and low circuit load capacity. Moreover, full-bridge rectifier circuits have a narrow voltage application window and low voltage withstand capability of their core component diodes, all of which restrict the performance and development of full-bridge rectifier circuits. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a quasi-vertical superjunction diode and a monolithically integrated full-bridge rectifier circuit. The technical problem to be solved by this invention is achieved through the following technical solution:

[0006] In a first aspect, embodiments of the present invention provide a quasi-vertical superjunction diode, comprising:

[0007] The structure consists of a Si substrate, an N+GaN conductive layer, and a heterojunction structure layer arranged sequentially from bottom to top. Within the heterojunction structure layer, P-BN ring regions and N GaN ring regions are arranged in concentric rings along the longitudinal direction. The P-BN ring regions and the sides of the heterojunction structure layer are made of Mg-doped P-type BN material. An anode is disposed on the surface of the heterojunction structure layer. A cathode is disposed on the surface of the N+GaN conductive layer, surrounding the heterojunction structure layer and spaced apart.

[0008] In one embodiment of the present invention, the Si doping concentration in the N+GaN conductive layer is 1.0 × 10⁻⁶. 18 cm -3 ~1.0×10 20 cm -3 .

[0009] In one embodiment of the present invention, the Si doping concentration in the N GaN ring region is 1.8 × 10⁻⁶. 15 cm -3 ~1.5×10 16 cm -3 .

[0010] In one embodiment of the present invention, the Mg doping concentration in the p-type BN material is 1.7 × 10⁻⁶. 14 cm -3 ~1.0×10 16 cm -3 .

[0011] In one embodiment of the present invention, the depth of the P-BN ring region is 1 μm to 6 μm; the width of the P-BN ring region and the N GaN ring region is 3 μm to 5 μm.

[0012] In a second aspect, embodiments of the present invention provide a method for fabricating a quasi-vertical superjunction diode, used to fabricate the quasi-vertical superjunction diode described in the first aspect, the method comprising:

[0013] A Si-based GaN epitaxial layer structure is obtained, wherein the Si-based GaN epitaxial layer structure includes, from bottom to top, a Si substrate, an N+ GaN conductive layer and an N-type GaN drift layer;

[0014] Etching removes the outer N+GaN conductive layer and N-type GaN drift layer to expose the Si substrate, forming a stepped structure;

[0015] The outer N-type GaN drift layer is etched away, so that the retained N-type GaN drift layer and the exposed N+GaN conductive layer form a stepped structure;

[0016] Multiple groove structures arranged in a concentric ring are etched downwards from the top of the N-type GaN drift layer, with the etching depth reaching the exposed N+GaN conductive layer;

[0017] Magnetron sputtering is used to sputter Mg-doped P-type BN material inside the trench structure, on the device surface, and on the side of the N-type GaN drift layer, followed by thermal annealing, so that the N-type GaN drift layer forms P-BN ring regions and N GaN ring regions with concentric rings spaced apart.

[0018] A passivation layer is grown on all exposed surfaces and sides above the upper surface of the Si substrate;

[0019] The passivation layer on the upper surface of the device is removed to expose the P-type BN material layer, and the passivation layer at predetermined positions on both sides of the N+GaN conductive layer is removed to form cathode contact openings; opening etching is performed in the exposed P-type BN material layer at the position corresponding to the N GaN ring region to form anode contact openings.

[0020] An anode is formed by metal evaporation inside and on the surface of the anode contact opening, and a cathode is formed by metal evaporation inside and on the surface of the cathode contact opening, surrounding the N-type GaN drift layer with a certain spacing.

[0021] Thirdly, embodiments of the present invention provide a monolithic integrated full-bridge rectifier circuit, comprising:

[0022] The system includes a first AC input terminal, a second AC input terminal, a positive terminal forward diode, a positive terminal reverse diode, a negative terminal forward diode, a negative terminal reverse diode, a first filter capacitor, a filter resistor, a second filter capacitor, a first output terminal, and a second output terminal; wherein,

[0023] The first AC input terminal is connected to the anode of the positive terminal forward diode and the cathode of the positive terminal reverse diode;

[0024] The second AC input terminal is connected to the anode of the negative polarity forward diode and the cathode of the negative polarity reverse diode;

[0025] The cathode of the positive terminal forward diode is connected to the cathode of the negative terminal forward diode, the first terminal of the first filter capacitor, and the first terminal of the filter resistor.

[0026] The second end of the filter resistor is connected to the first end of the second filter capacitor and the first output end;

[0027] The anode of the positive polarity reverse diode is connected to the anode of the negative polarity reverse diode, the second terminal of the first filter capacitor, the second terminal of the second filter capacitor, and the second output terminal;

[0028] The positive terminal forward diode, the positive terminal reverse diode, the negative terminal forward diode, and the negative terminal reverse diode constitute a rectifier circuit. Each diode is implemented using the quasi-vertical superjunction diode described in the first aspect, and the preparation method is the same as the preparation method of the quasi-vertical superjunction diode described in the second aspect. The first filter capacitor, the filter resistor, and the second filter capacitor constitute an RC filter circuit.

[0029] In one embodiment of the present invention, the working principle of the monolithic integrated full-bridge rectifier circuit includes:

[0030] The rectifier circuit is used to convert the bidirectional AC power input at the first AC input terminal and the second AC input terminal into a unidirectional pulsating current.

[0031] The RC filter circuit is used to remove the high-frequency AC component from the unidirectional pulsating current, converting it into DC and outputting it through the first output terminal and the second output terminal.

[0032] In one embodiment of the present invention, the operating principle of the rectifier circuit includes:

[0033] When the input signal is a positive periodic voltage, the first AC input terminal is positive and the second AC input terminal is negative. The forward diode of the positive terminal is turned on, and the reverse diode of the positive terminal is turned off. The reverse diode of the negative terminal is turned on, and the forward diode of the negative terminal is turned off. The input AC voltage value is the voltage difference between the first AC input terminal and the second AC input terminal. The first output terminal is positive and the second output terminal is negative.

[0034] When the input signal is a negative periodic voltage, the first AC input terminal is negative and the second AC input terminal is positive; the forward diode of the positive terminal is off, the reverse diode of the positive terminal is on, the reverse diode of the negative terminal is off, and the forward diode of the negative terminal is on; the input AC voltage value is the voltage difference between the second AC input terminal and the first AC input terminal; the first output terminal is positive and the second output terminal is negative.

[0035] Fourthly, embodiments of the present invention provide a method for fabricating a monolithic integrated full-bridge rectifier circuit, used to fabricate the monolithic integrated full-bridge rectifier circuit described in the third aspect, wherein the method for fabricating the monolithic integrated full-bridge rectifier circuit includes:

[0036] Multiple quasi-vertical superjunction diodes are fabricated on a Si substrate with the same Si-based GaN epitaxial layer structure; wherein the Si-based GaN epitaxial layer structure includes, from bottom to top, a Si substrate, an N+ GaN conducting layer and an N-type GaN drift layer; each quasi-vertical superjunction diode is fabricated using the quasi-vertical superjunction diode fabrication method described in the second aspect;

[0037] A resistive thin film is formed on the surface of the passivation layer on the Si substrate by sputtering using a TaN target.

[0038] Passivation layers are regrown on all surfaces and sides of the multi-device structure exposed on the Si substrate. Holes are made by etching the passivation layers and metal is deposited inside the holes. The first layer of metal interconnect is formed according to the connection requirements of the monolithic integrated full-bridge rectifier circuit.

[0039] A passivation layer is regrown, and holes are made by etching the passivation layer. Metal is then deposited inside the holes, and filter capacitors are prepared. Based on the connection requirements of the monolithic integrated full-bridge rectifier circuit, a second layer of metal interconnect is formed.

[0040] The beneficial effects of this invention are:

[0041] The diode in this invention uses silicon-based GaN material, which reduces circuit cost. By filling grooves with Mg-doped P-type BN material on a silicon-based gallium nitride substrate, a heterojunction structure composed of P-BN and N-GaN can be formed, thus creating a Mg-doped P-type BN-SJ superjunction quasi-vertical diode. In the superjunction structure, the P-BN and N-GaN layers are arranged in a vertical groove structure. After applying a reverse voltage, the depletion layer diffuses laterally, eventually forming a depletion layer "equivalent to the groove depth". At this point, as long as the depletion layer diffuses to half the groove spacing in each PN junction, a depletion layer with a thickness equivalent to the groove depth can be obtained, thereby improving the device's breakdown voltage. This invention uses a quasi-vertical diode with improved Mg-doped P-type BN superjunction technology to replace the traditional Schottky diode. Utilizing the high breakdown field strength of the BN material (boron nitride), the electric field modulation capability of the JBS ring structure, and the suppression of sidewall leakage current by the P-BN device sidewall coverage, the breakdown voltage of the diode can be improved.

[0042] The monolithic integrated full-bridge rectifier circuit provided in this invention is based on a quasi-vertical superjunction diode. It is the first time a monolithic integrated circuit based on a silicon-based GaN quasi-vertical Schottky diode has been proposed for a full-bridge rectifier, achieving increased integration density, significantly reducing circuit size, and improving circuit reliability. Currently, the voltage withstand capability of diodes, the core component of rectifier circuits, is relatively low. This invention uses Mg-doped P-type BN superjunction technology to improve the quasi-vertical diode, replacing the traditional Schottky diode. Utilizing the high breakdown field strength of BN material and the electric field modulation capability of the superjunction structure, the voltage withstand capability of the Schottky diode is greatly improved, broadening the voltage application window of the full-bridge rectifier circuit and enhancing its power handling capability. Existing half-wave rectifier circuits have low conversion efficiency, utilizing only half of the AC signal, resulting in low utilization of the input AC power. This invention uses a bridge full-wave rectifier circuit, which can fully utilize both the positive and negative half-cycles of the AC signal, effectively improving conversion efficiency. Attached Figure Description

[0043] Figure 1 A three-dimensional schematic diagram of a quasi-vertical superjunction diode provided in an embodiment of the present invention;

[0044] Figure 2 A three-dimensional cross-sectional schematic diagram of a quasi-vertical superjunction diode provided in an embodiment of the present invention;

[0045] Figure 3 A comparative schematic diagram of quasi-vertical superjunction diodes of different sizes provided in embodiments of the present invention;

[0046] Figure 4 This is a schematic flowchart illustrating a method for fabricating a quasi-vertical superjunction diode according to an embodiment of the present invention.

[0047] Figures 5a to 5j A schematic diagram of the process flow for fabricating a quasi-vertical superjunction diode according to an embodiment of the present invention;

[0048] Figure 6 A circuit schematic diagram of a monolithic integrated full-bridge rectifier circuit provided for an embodiment of the present invention;

[0049] Figure 7 A three-dimensional schematic diagram of a monolithic integrated full-bridge rectifier circuit provided in an embodiment of the present invention;

[0050] Figure 8 A top view schematic diagram of a monolithic integrated full-bridge rectifier circuit provided for an embodiment of the present invention;

[0051] Figure 9 A schematic flowchart illustrating a method for fabricating a monolithic integrated full-bridge rectifier circuit according to an embodiment of the present invention;

[0052] Figures 10a to 10h This is a schematic diagram of the process flow for a method of fabricating a monolithic integrated full-bridge rectifier circuit according to an embodiment of the present invention. Detailed Implementation

[0053] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0054] In a first aspect, embodiments of the present invention provide a quasi-vertical superjunction diode, see [link to previous document]. Figure 1 A three-dimensional schematic diagram of the quasi-vertical superjunction diode shown. Figure 2 The schematic diagram of the three-dimensional cross-section of the quasi-vertical superjunction diode shown is as follows: Figure 3 The diagram shows a comparison of quasi-vertical superjunction diodes of different sizes. These quasi-vertical superjunction diodes include:

[0055] The structure consists of a Si substrate, an N+GaN conductive layer, and a heterojunction structure layer arranged sequentially from bottom to top. Within the heterojunction structure layer, P-BN ring regions and N GaN ring regions are arranged in concentric rings along the longitudinal direction. The P-BN ring regions and the sides of the heterojunction structure layer are made of Mg-doped P-type BN material. An anode is disposed on the surface of the heterojunction structure layer. A cathode is disposed on the surface of the N+GaN conductive layer, surrounding the heterojunction structure layer and spaced apart.

[0056] in, Figures 1-3 In this context, Si Substrate represents the Si substrate; N+GaN represents the N+GaN conductive layer; N GaN represents the N-type GaN drift layer; P-BN represents Mg-doped P-type BN material; P-BN SJ (SJ represents superjunction) pillar represents the pillar-shaped region exhibited in the cross-section of the P-BN ring region; N GaN SJ pillar represents the pillar-shaped region exhibited in the cross-section of the N GaN ring region; P-BN ring represents the P-BN ring region; and NGaN ring represents the N GaN ring region.

[0057] Specifically, the Si substrate can use the 111 crystal plane.

[0058] The N+GaN conductive layer is located on the upper surface of the Si substrate and has a cylindrical structure. Its thickness can be set as needed, for example, it can be around 0.6μm to 1μm.

[0059] In one optional embodiment, the Si doping concentration in the N+GaN conductive layer can be 1.0 × 10⁻⁶. 18 cm -3 ~1.0×10 20 cm -3Understandably, the higher the doping concentration, the lower the cathode electrode contact resistance, and the lower the overall on-resistance after the device is turned on. However, an excessively high concentration may reduce the device's withstand voltage to some extent, so it is necessary to select the appropriate concentration based on the requirements.

[0060] The N-type GaN drift layer is located in the central region of the upper surface of the N+GaN conductive layer. It has a cylindrical structure, and its thickness can be set as needed, for example, around 3μm to 5μm. The N-type GaN drift layer is etched to create concentric ring regions of P-BN and N GaN along the longitudinal direction. (See also...) Figure 2 and Figure 3 The P-BN and N GaN ring regions are nested in size and spaced apart, arranged concentrically. The number of P-BN and N GaN rings can be determined according to current flow requirements; a single ring or multiple rings are acceptable.

[0061] Figure 2 The depth of the P-BN SJ pillar represents the depth of the P-BN ring region, and the width of the P-BN SJ pillar represents the width of the P-BN ring region. The depth of the N GaN SJ pillar represents the depth of the N GaN ring region, and the width of the N GaN SJ pillar represents the width of the N GaN ring region. In this embodiment of the invention, the lower surfaces of the P-BN ring region and the N GaN ring region are flush and both contact the N+GaN conductive layer. In one optional embodiment, the depth of the P-BN ring region can be 1 μm to 6 μm, and the widths of the P-BN ring region and the N GaN ring region can be 3 μm to 5 μm.

[0062] The Si doping concentration in the N-type GaN drift layer, i.e., the Si doping concentration in the N GaN ring region, can be 1.8 × 10⁻⁶. 15 cm -3 ~1.5×10 16 cm -3 This doping concentration also affects the device's breakdown voltage. Theoretically, the lower the concentration, the higher the breakdown voltage, but it also affects the device's forward conduction characteristics. The lower the doping concentration, the higher the forward conduction resistance. Therefore, this value needs to be considered in conjunction with the Si doping concentration in the N+GaN conducting layer and the Mg doping concentration in the P-BN layer. Furthermore, in a superjunction structure, to obtain the optimal breakdown voltage level, the concentration of the N region needs to be matched with the concentration of the P-BN layer to ensure that the depletion layer can fully expand before breakdown occurs. For details, please refer to the concentration relationship in the basic superjunction structure described in the relevant part of formula (1) below.

[0063] The P-BN ring region and the side surfaces of the heterojunction structure layer are both composed of Mg-doped P-type BN material, such as... Figure 3As shown, the Mg-doped P-type BN material also covers part of the upper surface of the N-type GaN drift layer, that is, the upper surface of the P-BN ring region is slightly higher than the upper surface of the N GaN ring region, and occupies part of the upper surface area of ​​the N GaN ring region. Figure 3 The cross-section of the P-BN ring region described herein is T-shaped.

[0064] The Mg doping concentration in p-type BN materials affects the depletion capability of the P-BN ring in the reverse direction. Generally, a higher concentration means a stronger depletion capability, which also improves the reverse breakdown voltage of the device. However, when the concentration rises to a certain level, the breakdown voltage will not continue to increase and may even degrade. In one optional embodiment, the Mg doping concentration in the p-type BN material can be 1.7 × 10⁻⁶. 14 cm -3 ~1.0×10 16 cm -3 .

[0065] An anode is disposed on the surface of the heterojunction structure layer; a cathode with spacing is disposed on the surface of the N+GaN conductive layer, surrounding the heterojunction structure layer. Figure 1 and Figure 2 As can be seen, the cathode is also ring-shaped.

[0066] The anode metal can be Ni / Au; the cathode metal can be Ti / Al / Ni / Au.

[0067] It should be noted that for quasi-vertical superjunction diodes used alone, the passivation layer on the side may not be necessary. The passivation layer, such as... Figure 3 The white area on the side of the device is shown.

[0068] The diode in this embodiment of the invention adopts a quasi-vertical diode structure. Unlike traditional vertical devices where current only exists in the vertical direction, the anode and cathode are located on the front and back sides of the wafer, respectively. In this quasi-vertical device, the anode and cathode are both on the same plane (see [reference]). Figure 1 and 2 (Understanding) This quasi-vertical structure facilitates the subsequent connection of devices using on-chip wiring to complete the circuit construction.

[0069] The diode in this invention uses silicon-based GaN material, which reduces circuit cost. By filling grooves with Mg-doped P-type BN material on a silicon-based gallium nitride substrate, a heterojunction structure composed of P-BN and N-GaN can be formed, thus creating a Mg-doped P-type BN-SJ superjunction quasi-vertical diode. In the superjunction structure, the P-BN and N-GaN layers are arranged in a vertical groove structure. After applying a reverse voltage, the depletion layer diffuses laterally, eventually forming a depletion layer "equivalent to the groove depth". At this point, as long as the depletion layer diffuses to half the groove spacing for each PN junction, a depletion layer with a thickness equivalent to the groove depth can be obtained, thereby improving the device's breakdown voltage. This invention replaces the traditional Schottky diode with a quasi-vertical diode improved by Mg-doped P-type BN superjunction technology. By utilizing the high breakdown field strength of BN material (boron nitride), the electric field modulation capability of the JBS (junction barrier Schottky diode) ring structure, and the suppression of sidewall leakage current by the sidewall covering of the P-BN device, the breakdown voltage of the diode can be improved. If the proposed quasi-vertical superjunction diode is used to construct a monolithic integrated full-bridge rectifier circuit, the power handling capability of the rectifier circuit can be enhanced.

[0070] In this embodiment of the invention, to ensure the superjunction achieves optimal reverse breakdown voltage performance, the N-GaN and P-BN regions in the drift region are required to be completely depleted at the critical breakdown voltage, and optimal charge compensation must be achieved. The widths of the N-GaN and P-GaN regions in the drift region are related to the doping concentrations Q of the N and P regions. n With Q p The following relationship must be satisfied between them:

[0071]

[0072] Among them, Q n and Q p ε represents the doping concentration of the N and P regions, respectively, i.e., the total charge density of ionized impurities in the depletion layer; for simplicity, it is described using the N and P regions respectively; sn and ε sp E represents the relative permittivity of the N-region and P-region materials, respectively. cn and E cp These represent the critical breakdown electric fields of the N-region and P-region materials, respectively. In this embodiment of the invention, the N-region material is N-type doped GaN material; the P-region material is Mg-doped BN material; q represents the elementary charge constant, which is 1.6 × 10⁻⁶. -19 W n and W p These represent the widths of the N-pillar and P-pillar within the superstructure, respectively; N D and N A These represent the impurity concentrations activated in the N-region and P-region, respectively.

[0073] Secondly, embodiments of the present invention provide a method for fabricating a quasi-vertical superjunction diode, used to fabricate the quasi-vertical superjunction diode described in the first aspect. See [link to previous section]. Figure 4 The fabrication method of the quasi-vertical superjunction diode may include the following steps:

[0074] S1, Obtain a Si-based GaN epitaxial layer structure, wherein the Si-based GaN epitaxial layer structure comprises, from bottom to top, a Si substrate, an N+GaN conductive layer and an N-type GaN drift layer;

[0075] Please refer to the structure of the Si-based GaN epitaxial layer. Figure 5a To understand, Si Substrate represents a Si substrate; N+GaN represents an N+GaN conductive layer; and N GaN represents an N-type GaN drift layer.

[0076] The Si substrate can have a 111 crystal plane. The Si doping concentration in the N+GaN conductive layer is 1.0 × 10⁻⁶. 18 cm -3 ~1.0×10 20 cm -3 The Si doping concentration in the N-type GaN drift layer is 1.8 × 10⁻⁶. 15 cm -3 ~1.5×10 16 cm -3 .

[0077] S2, etching removes the outer N+GaN conductive layer and N-type GaN drift layer to expose the Si substrate, forming a stepped structure;

[0078] This step involves mesa isolation etching to isolate the various active device regions. Specifically, the etching proceeds downwards from the outer sides of the N-type GaN drift layer and the N+GaN conductive layer until the Si substrate is exposed. It can be understood that the retained N-type GaN drift layer and N+GaN conductive layer form a cylindrical structure. The etching employs Cl-based ICP (inductively coupled plasma) etching, with Cl2 and BCl3 as the primary etching gases. BCl3 serves as the sidewall protection gas, effectively improving selectivity and etching morphology. Fast etching conditions are used, with upper power between 130W and 140W, lower power between 40W and 50W, and cavity pressure between 5 and 7 mT. The device structure formed in this step is shown in [link to image / image / description]. Figure 5b As shown.

[0079] S3, etch away the outer N-type GaN drift layer, so that the retained N-type GaN drift layer and the exposed N+GaN conductive layer form a stepped structure;

[0080] This step involves mesa etching, which etches downwards from the outer perimeter of the N-type GaN drift layer to expose the N+ GaN conductive layer for subsequent cathode metal deposition. Understandably, the retained N-type GaN drift layer remains a cylindrical structure. The etching conditions for this step are consistent with S2, with an etching depth of approximately 1 μm. The device structure formed in this step is shown in [link to image / image / description]. Figure 5c As shown.

[0081] S4, etch out multiple groove structures in a concentric ring shape from the top of the N-type GaN drift layer downwards, with the etching depth reaching the exposed N+GaN conductive layer;

[0082] This step involves SJ deep trench etching of the P-type superjunction region in the anodic area. Cl-based ICP etching is also used, but because the N+GaN conductive layer has higher requirements for etching damage compared to MESA (mesa), a lower etching power is required. The upper electrode power is between 55W and 70W, and the lower electrode power is between 14W and 20W. The etched trench structure is distributed in a concentric ring pattern. The depth of the trench structure can be 1μm to 6μm, and the width can be 3μm to 5μm.

[0083] The device structure formed in this step is shown in [link / reference]. Figure 5d As shown.

[0084] S5, using magnetron sputtering technology, Mg-doped P-type BN material is sputtered inside the trench structure, on the device surface, and on the side of the N-type GaN drift layer, and then subjected to thermal annealing treatment, so that the N-type GaN drift layer forms P-BN ring regions and N GaN ring regions with concentric rings spaced apart.

[0085] This step involves sputtering P-BN followed by thermal annealing to activate impurities and achieve P-BN deposition. Specifically, a dual-target RF magnetron sputtering method is used to grow P-BN layers inside the trench structure, on the device surface, and on the sides of the N-type GaN drift layer. The chamber pressure is between 4 and 6 mt, the sputtering gas is Ar, and the sputtering power is 140–150 W. The sputtering depth needs to be adjusted according to the depth of the trench structure (i.e., the P-BN trench), and should be slightly greater than the etching depth of the P-BN trench. After sputtering, annealing is performed at 1100–1200 °C for at least 10 minutes to activate Mg impurities. The device structure formed in this step is shown in [link to device structure]. Figure 5e As shown, it can be understood that the N-type GaN drift layer forms P-BN ring regions and N GaN ring regions distributed in concentric rings, and there are also Mg-doped P-type BN materials (referred to as P-BN) on the surface and sides.

[0086] S6, a passivation layer is grown on all exposed surfaces and sides above the upper surface of the Si substrate;

[0087] like Figure 5fAs shown, a SiN passivation layer with a target thickness of approximately 120 nm was grown on the entire upper and side surfaces of the device, excluding the Si substrate side surface, using a PECVD (plasma-enhanced chemical vapor deposition) device. The reaction gases were SiH4 and NH3, and the carrier gas was He. The growth was carried out at a pressure of 600 mt and a temperature of 250 °C.

[0088] To distinguish it from the fabrication method of the monolithic integrated full-bridge rectifier circuit described later, the passivation layer grown here is referred to as the first passivation layer.

[0089] S7, remove the passivation layer on the upper surface of the device to expose the P-type BN material layer, and remove the passivation layer at predetermined positions on both sides of the N+GaN conductive layer to form a cathode contact opening; perform opening etching at the position corresponding to the N GaN ring region in the exposed P-type BN material layer to form an anode contact opening.

[0090] Figure 5g The diagram shows the passivation layer etching process. First, the passivation layer on the upper surface of the device is removed, exposing the P-type BN material layer. Simultaneously, the passivation layer at predetermined positions on both sides of the N+GaN conductive layer can be removed to form cathode contact openings. The cathode contact openings are located on both sides of the N+GaN conductive layer and are spaced apart from the N-type GaN drift layer.

[0091] The passivation layer etching uses F-based ICP etching to remove the SiN layer in the opening area. To ensure that the metal contact area is cleanly etched, at least 40% to 50% over-etching is required.

[0092] Figure 5h The image shows P-BN etching. An anode contact opening is formed by etching at the center of the exposed P-type BN material layer, corresponding to the N GaN ring region. This etching employs fluorine-based ICP etching, with SF6, CF4, and CHF3 as the primary etching gases. Due to the difficulty of BN etching, a relatively high power is used, with the upper power between 150W and 200W and the lower power controlled at around 65-70W. Because of the high selectivity of fluorine-based etching for GaN, an over-etching depth greater than 30% of the target depth can be set, ensuring that the required BN region is completely etched.

[0093] S8 forms an anode by metal evaporation inside and on the surface of the anode contact opening, and forms a cathode with a certain spacing around the N-type GaN drift layer by metal evaporation inside and on the surface of the cathode contact opening.

[0094] See Figure 5i For the anode Schottky contact, Ni / Au metal is vapor-deposited to form the anode. The metal layer is formed by evaporation, with a thickness of 45 / 400 nm under thick gate conditions. The metal pattern is formed by metal stripping.

[0095] See Figure 5j For the cathode ohmic contact, Ti / Al / Ni / Au metals are vapor-deposited to form the cathode. The metal layers are formed by evaporation, and the thickness of each layer is [missing information]. The metal pattern is formed by metal stripping.

[0096] In this way, a quasi-vertical superjunction diode is finally formed. If the quasi-vertical superjunction diode is used alone, the passivation layer can be removed. If other devices still need to be interconnected later, the passivation layer is retained.

[0097] As mentioned above, the diode in this embodiment of the invention is a Mg-doped P-type BN-SJ superjunction diode, which is obtained by growing Mg-doped P-type BN material in a groove on a silicon-based gallium nitride substrate. While reducing circuit cost, the diode can improve the breakdown voltage by forming a quasi-vertical heterojunction structure diode from P-BN and NGaN.

[0098] Thirdly, based on the proposed quasi-vertical superjunction diode, this embodiment of the invention provides a monolithic integrated full-bridge rectifier circuit. Please refer to [link to relevant documentation]. Figure 6 The circuit schematic shown illustrates that this monolithic integrated full-bridge rectifier circuit includes:

[0099] The system includes a first AC input terminal, a second AC input terminal, a positive terminal forward diode, a positive terminal reverse diode, a negative terminal forward diode, a negative terminal reverse diode, a first filter capacitor, a filter resistor, a second filter capacitor, a first output terminal, and a second output terminal; wherein,

[0100] The first AC input terminal is connected to the anode of the positive terminal forward diode and the cathode of the positive terminal reverse diode;

[0101] The second AC input terminal is connected to the anode of the negative polarity forward diode and the cathode of the negative polarity reverse diode;

[0102] The cathode of the positive terminal forward diode is connected to the cathode of the negative terminal forward diode, the first terminal of the first filter capacitor, and the first terminal of the filter resistor.

[0103] The second end of the filter resistor is connected to the first end of the second filter capacitor and the first output end;

[0104] The anode of the positive polarity reverse diode is connected to the anode of the negative polarity reverse diode, the second terminal of the first filter capacitor, the second terminal of the second filter capacitor, and the second output terminal;

[0105] The positive terminal forward diode, the positive terminal reverse diode, the negative terminal forward diode, and the negative terminal reverse diode constitute a rectifier circuit. Each diode is implemented using the quasi-vertical superjunction diode described in the first aspect, and the preparation method is the same as the preparation method of the quasi-vertical superjunction diode described in the second aspect. The first filter capacitor, the filter resistor, and the second filter capacitor constitute an RC filter circuit.

[0106] Figure 6 In this circuit, the first AC input terminal is labeled 1, the second AC input terminal is labeled 2, the first output terminal is labeled 3, and the second output terminal is labeled 4; the positive terminal forward diode, the positive terminal reverse diode, the negative terminal forward diode, and the negative terminal reverse diode are labeled D1, D2, D3, and D4, respectively; the first filter capacitor and the second filter capacitor are labeled C1 and C2, respectively, and the filter resistor is labeled R;

[0107] Figure 7 This is a 3D schematic diagram of the entire monolithic integrated full-bridge rectifier circuit. Figure 8 This is a top view of the monolithically integrated full-bridge rectifier circuit. Ports 1 through 4 are the first AC input, second AC input, first output, and second output, respectively. Light-colored connecting lines correspond to the first layer, and light-colored connecting lines correspond to the second layer. For the connection relationships of each diode group on the first or second layer, please refer to [link to relevant documentation]. Figure 7 and Figure 8 The comparison is for reference only; detailed explanations will not be provided here.

[0108] The working principle of the monolithic integrated full-bridge rectifier circuit includes:

[0109] The rectifier circuit is used to convert the bidirectional AC power input at the first AC input terminal and the second AC input terminal into a unidirectional pulsating current.

[0110] The RC filter circuit is used to remove the high-frequency AC component from the unidirectional pulsating current, converting it into DC and outputting it through the first output terminal and the second output terminal.

[0111] The working principle of the rectifier circuit includes:

[0112] 1) When the input signal is a positive periodic voltage, the first AC input terminal is positive and the second AC input terminal is negative. The forward diode of the positive terminal is turned on and the reverse diode of the positive terminal is turned off. The reverse diode of the negative terminal is turned on and the forward diode of the negative terminal is turned off. The input AC voltage value is the voltage difference between the first AC input terminal and the second AC input terminal. The first output terminal is positive and the second output terminal is negative.

[0113] Specifically, when the input signal at the input terminal is a positive periodic voltage, the first AC input terminal 1 is positive and the second AC input terminal 2 is negative. Due to the presence of the positive voltage at the first AC input terminal 1, the forward diode D1 at the positive terminal is conducting, and the reverse diode D2 at the positive terminal is cut off. Due to the presence of the negative voltage at the second AC input terminal 2, the reverse diode D4 at the negative terminal is conducting, and the forward diode D3 at the negative terminal is cut off. Therefore, at this time, the input terminal forms a closed loop starting from the first AC input terminal 1, through the forward diode D1 at the positive terminal, the load (and the RC filter circuit integrated at the output terminal), and the reverse diode D4 at the negative terminal. At this time, the output port voltage is the difference between the voltages of the first AC input terminal 1 and the second AC input terminal 2, which is the input AC voltage value, and the first output terminal 3 is positive and the second output terminal 4 is negative.

[0114] 2) When the input signal is a negative periodic voltage, the first AC input terminal is negative and the second AC input terminal is positive; the forward diode of the positive terminal is off and the reverse diode of the positive terminal is on, the reverse diode of the negative terminal is off and the forward diode of the negative terminal is on; the input AC voltage value is the voltage difference between the second AC input terminal and the first AC input terminal, the first output terminal is positive and the second output terminal is negative.

[0115] Specifically, when the input signal at the input terminal is a negative periodic voltage, the first AC input terminal 1 is negative and the second AC input terminal 2 is positive. Due to the negative voltage at the first AC input terminal 1, the positive diode D1 is cut off, and the positive diode D2 is turned on. Due to the positive voltage at the second AC input terminal 2, the negative diode D4 is cut off, and the negative diode D3 is turned on. Therefore, the input terminal forms a closed loop starting from the first AC input terminal, through the positive diode D2, the load (and the RC filter circuit), and the negative diode D3. At this time, the output port voltage is the difference between the voltage at the second AC input terminal 2 and the voltage at the first AC input terminal 1, which is the input AC voltage value. Furthermore, the first output terminal 3 remains positive, and the second output terminal 4 remains negative.

[0116] The waveform after rectification by the rectifier circuit changes from bidirectional alternating current at the input to unidirectional pulsating current.

[0117] In this embodiment of the invention, both the first filter capacitor and the second filter capacitor are MIM parallel plate dielectric capacitors suitable for monolithic integrated circuits. The dielectric layer material is silicon nitride, and the dielectric layer thickness ranges from 0.5μm to 5μm. The length and width of the capacitor plates are adjustable from 10μm to 100μm. Different capacitance values ​​can be obtained by adjusting the dielectric layer thickness and the area of ​​the capacitor plates.

[0118] The filter resistor is a TFR on-chip microstrip resistor, and the materials constituting the resistor include TaN, NiCr, etc.; the required resistance value and corresponding current carrying capacity can be achieved by different aspect ratios.

[0119] For RC filter circuits, after the AC current is rectified by the rectifier circuit, it becomes a unidirectional pulsating current. This current still contains too much AC component, so an RC low-pass filter circuit is needed to remove the high-frequency AC component and convert the pulsating current into DC.

[0120] The RC filter circuit is an improved version of the single-capacitor filter circuit, consisting of two capacitors and one resistor. During the rising phase of a positive unidirectional pulsating signal, the first filter capacitor C1 charges. Since capacitor discharge takes time, the charge in the first filter capacitor C1 is not completely released before the next rising cycle arrives, thus achieving first-stage filtering. A filter resistor R is added between the first filter capacitor C1 and the second filter capacitor C2, ensuring that most of the AC ripple after filtering by the first filter capacitor C1 is applied to the filter resistor R, and then filtered a second time by the second filter capacitor C2 before being output to the load.

[0121] The filtering effect of the circuit is related to the RC value of the low-pass filter network and the frequency of the input signal. The larger the values ​​of the filter resistor R and the second filter capacitor C2, the better the filtering effect. However, an excessively large filter resistor R will affect the output voltage of the circuit. That is, the value of the filter resistor R1 should not be too large.

[0122] The monolithic integrated full-bridge rectifier circuit provided in this invention is based on a quasi-vertical superjunction diode. It is the first time a monolithic integrated circuit based on a silicon-based GaN quasi-vertical Schottky diode has been proposed for a full-bridge rectifier, achieving increased integration density, significantly reducing circuit size, and improving circuit reliability. Currently, the voltage withstand capability of diodes, the core component of rectifier circuits, is relatively low. This invention uses Mg-doped P-type BN superjunction technology to improve the quasi-vertical diode, replacing the traditional Schottky diode. Utilizing the high breakdown field strength of BN material and the electric field modulation capability of the superjunction structure, the voltage withstand capability of the Schottky diode is greatly improved, broadening the voltage application window of the full-bridge rectifier circuit and enhancing its power handling capability. Existing half-wave rectifier circuits have low conversion efficiency, utilizing only half of the AC signal, resulting in low utilization of the input AC power. This invention uses a bridge full-wave rectifier circuit, which can fully utilize both the positive and negative half-cycles of the AC signal, effectively improving conversion efficiency.

[0123] Fourthly, embodiments of the present invention provide a method for fabricating a monolithic integrated full-bridge rectifier circuit, used to fabricate the monolithic integrated full-bridge rectifier circuit described in the third aspect. Please refer to [link to previous section]. Figure 9 The fabrication method of the monolithic integrated full-bridge rectifier circuit includes the following steps:

[0124] S100, on a Si substrate with the same Si-based GaN epitaxial layer structure, a plurality of quasi-vertical superjunction diodes are prepared; wherein, the Si-based GaN epitaxial layer structure includes, from bottom to top, a Si substrate, an N+ GaN conducting layer and an N-type GaN drift layer; each quasi-vertical superjunction diode is prepared using the quasi-vertical superjunction diode preparation method described in the second aspect;

[0125] Specifically, please refer to the relevant content in the second aspect. The obtained single quasi-vertical superjunction diode is as follows: Figure 5j As shown in the diagram. Since S100 fabricates multiple quasi-vertical superjunction diodes on a Si substrate with the same Si-based GaN epitaxial layer structure, the results are shown in [link to diagram]. Figure 10a As shown, SiN x This represents the passivation layer, which is the first passivation layer mentioned earlier. Layer1 represents the first layer.

[0126] S200, a resistive thin film is formed on the surface of the passivation layer on the Si substrate by sputtering using a TaN target;

[0127] This step involves vapor deposition of a resistive thin film; see [link / reference]. Figure 10b Specifically, a TaN target is used to form a resistive thin film, denoted as Resist Film, which is used to form a filter resistor. See the top view below. Figure 10b As shown on the right side of the middle section.

[0128] S300, passivation layers are regrown on all surfaces and sides of the multi-device structure exposed on the Si substrate, holes are made by etching the passivation layers, and metal is deposited inside the holes. According to the connection requirements of the monolithic integrated full-bridge rectifier circuit, the first layer of metal interconnect is formed.

[0129] First, such as Figure 10c As shown, a second passivation layer is grown (the passivation layer material is the same as the first layer; please refer to SiN). x (layer2 represents the second layer), which covers all surfaces of the current structure.

[0130] Then as Figure 10d As shown, openings are made in the anode and cathode regions of the diode by etching a second passivation layer. Simultaneously, passivation layers are also etched at both ends of the resistive thin film to create openings. Metal Via represents a metal via, and Metal Via1 represents a first-layer metal via.

[0131] After that, as Figure 10e As shown, metal is vapor-deposited in the opening area, forming vias connected to the first layer according to the connection requirements of diodes and other devices in a monolithic integrated full-bridge rectifier circuit. The metal vapor deposition method is consistent with the previous diode fabrication process, achieving circuit connection between diodes. Specifically, anode metal vapor deposition is performed in the anode contact opening, and cathode metal vapor deposition is performed in the cathode contact opening. The process parameters are consistent with the corresponding steps in the second aspect; please refer to the relevant content above for details. For details on which devices are connected to the first layer of metal interconnects and how they are connected, please refer to... Figures 6-8 I understand. I will not go into detail here.

[0132] S400, a passivation layer is grown again, and holes are made by etching the passivation layer. Metal is deposited inside the holes, and filter capacitors are prepared. According to the connection requirements of the monolithic integrated full-bridge rectifier circuit, a second layer of metal interconnect is formed.

[0133] like Figure 10f As shown, a third passivation layer (referred to as layer3) is grown to cover all surfaces of the current structure.

[0134] Then as Figure 10g As shown, openings are made by etching a third passivation layer for the anode region, cathode region, and both ends of the resistive thin film of the diode. Metal Via 2 indicates the second metal via.

[0135] After that, as Figure 10hAs shown, metal is vapor-deposited in the opening area, and filter capacitors are fabricated simultaneously. Based on the connection requirements of diodes and other devices in a monolithic integrated full-bridge rectifier circuit, through-holes are formed to connect to the second layer. The metal vapor deposition method is consistent with the previous description, and circuit connections between diodes are performed. The process parameters for S400 can be kept consistent with those for S300.

[0136] For details on which devices are connected in the second-layer metal interconnect and how they are connected, please refer to [link to relevant documentation]. Figures 6-8 I understand. I will not go into detail here.

[0137] Please refer to the final circuit structure, diode locations, interconnections, etc. Figures 6-8 As shown.

[0138] The method for fabricating a monolithic integrated full-bridge rectifier circuit provided in this invention, based on the method for fabricating quasi-vertical superjunction diodes, involves fabricating multiple quasi-vertical superjunction diodes on the same Si substrate. Then, a resistive thin film is formed on the passivation layer surface of the Si substrate using a TaN target via sputtering. Next, passivation layers are grown again on all surfaces and sides of the multi-device structure exposed on the Si substrate. Through-holes are created by etching the passivation layers, followed by in-hole metal evaporation and filter capacitor fabrication. A first layer of metal interconnects is formed according to the connection requirements of the monolithic integrated full-bridge rectifier circuit. Finally, a passivation layer is grown again, through-holes are created by etching the passivation layers, followed by in-hole metal evaporation. A second layer of metal interconnects is formed according to the connection requirements of the monolithic integrated full-bridge rectifier circuit, thereby fabricating the monolithic integrated full-bridge rectifier circuit.

[0139] This monolithically integrated full-bridge rectifier circuit is implemented based on the provided quasi-vertical superjunction diode, achieving improved integration, significantly reducing circuit size, and enhancing circuit reliability. This invention employs Mg-doped P-type BN superjunction technology to upgrade the quasi-vertical diode to replace the traditional Schottky diode. Utilizing the high breakdown field strength of BN material and the electric field modulation capability of the superjunction structure, the breakdown voltage of the Schottky diode is greatly improved, broadening the voltage application window of the full-bridge rectifier circuit and enhancing its power handling capability. In contrast, existing technologies mostly use traditional Schottky diodes and lack effective junction termination technology to increase the device's operating voltage, limiting the operating range of existing devices.

[0140] This invention employs a bridge full-wave rectifier circuit, which fully utilizes both the positive and negative half-cycles of the AC signal, effectively improving conversion efficiency. The use of a more efficient bridge full-wave rectifier circuit achieves more efficient AC-DC conversion, reducing the rectification pressure on individual transistors and improving circuit economy and reliability. In contrast, the original half-wave rectifier circuit sacrifices half of the AC signal to achieve rectification, resulting in low current utilization.

[0141] It should be noted that, in the description of this invention, the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0142] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0143] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0144] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A monolithically integrated full-bridge rectifier circuit, characterized in that, include: The system includes a first AC input terminal, a second AC input terminal, a positive terminal forward diode, a positive terminal reverse diode, a negative terminal forward diode, a negative terminal reverse diode, a first filter capacitor, a filter resistor, a second filter capacitor, a first output terminal, and a second output terminal; wherein, The first AC input terminal is connected to the anode of the positive terminal forward diode and the cathode of the positive terminal reverse diode; The second AC input terminal is connected to the anode of the negative polarity forward diode and the cathode of the negative polarity reverse diode; The cathode of the positive terminal forward diode is connected to the cathode of the negative terminal forward diode, the first terminal of the first filter capacitor, and the first terminal of the filter resistor. The second end of the filter resistor is connected to the first end of the second filter capacitor and the first output end; The anode of the positive polarity reverse diode is connected to the anode of the negative polarity reverse diode, the second terminal of the first filter capacitor, the second terminal of the second filter capacitor, and the second output terminal; The positive terminal forward diode, the positive terminal reverse diode, the negative terminal forward diode, and the negative terminal reverse diode constitute a rectifier circuit, and each diode is implemented using a quasi-vertical superjunction diode; the first filter capacitor, the filter resistor, and the second filter capacitor constitute an RC filter circuit. The quasi-vertical superjunction diode includes: The structure consists of a Si substrate, an N+GaN conductive layer, and a heterojunction structure layer arranged sequentially from bottom to top. Within the heterojunction structure layer, P-BN ring regions and N GaN ring regions are arranged in concentric rings along the longitudinal direction. The P-BN ring regions and the sides of the heterojunction structure layer are made of Mg-doped P-type BN material. An anode is disposed on the surface of the heterojunction structure layer. A cathode is disposed on the surface of the N+GaN conductive layer, surrounding the heterojunction structure layer and spaced apart.

2. The monolithic integrated full-bridge rectifier circuit according to claim 1, characterized in that, The Si doping concentration in the N+GaN conductive layer is: .

3. The monolithic integrated full-bridge rectifier circuit according to claim 1, characterized in that, The Si doping concentration in the N GaN ring region is .

4. The monolithic integrated full-bridge rectifier circuit according to claim 1, characterized in that, In the p-type BN material, the Mg doping concentration is: .

5. The monolithic integrated full-bridge rectifier circuit according to claim 1, characterized in that, The depth of the P-BN ring region is 1μm to 6μm; the width of the P-BN ring region and the N GaN ring region is 3μm to 5μm.

6. The method for fabricating the quasi-vertical superjunction diode in the monolithic integrated full-bridge rectifier circuit according to claim 1 includes: A Si-based GaN epitaxial layer structure is obtained, wherein the Si-based GaN epitaxial layer structure includes, from bottom to top, a Si substrate, an N+ GaN conductive layer and an N-type GaN drift layer; Etching removes the outer N+GaN conductive layer and N-type GaN drift layer to expose the Si substrate, forming a stepped structure; The outer N-type GaN drift layer is etched away, so that the retained N-type GaN drift layer and the exposed N+GaN conductive layer form a stepped structure; Multiple groove structures arranged in a concentric ring are etched downwards from the top of the N-type GaN drift layer, with the etching depth reaching the exposed N+GaN conductive layer; Magnetron sputtering is used to sputter Mg-doped P-type BN material inside the trench structure, on the device surface, and on the side of the N-type GaN drift layer, followed by thermal annealing, so that the N-type GaN drift layer forms P-BN ring regions and N GaN ring regions with concentric rings spaced apart. A passivation layer is grown on all exposed surfaces and sides above the upper surface of the Si substrate; The passivation layer on the upper surface of the device is removed to expose the P-type BN material layer, and the passivation layer at predetermined positions on both sides of the N+GaN conductive layer is removed to form cathode contact openings. Anode contact openings are formed by etching at the locations corresponding to the N GaN ring regions in the exposed P-type BN material layer. An anode is formed by metal evaporation inside and on the surface of the anode contact opening, and a cathode is formed by metal evaporation inside and on the surface of the cathode contact opening, surrounding the N-type GaN drift layer with a certain spacing.

7. The monolithically integrated full-bridge rectifier circuit according to claim 1, characterized in that, The working principle of the monolithic integrated full-bridge rectifier circuit includes: The rectifier circuit is used to convert the bidirectional AC power input at the first AC input terminal and the second AC input terminal into a unidirectional pulsating current. The RC filter circuit is used to remove the high-frequency AC component from the unidirectional pulsating current, converting it into DC and outputting it through the first output terminal and the second output terminal.

8. The monolithic integrated full-bridge rectifier circuit according to claim 7, characterized in that, The working principle of the rectifier circuit includes: When the input signal is a positive periodic voltage, the first AC input terminal is positive and the second AC input terminal is negative. The forward diode of the positive terminal is turned on, and the reverse diode of the positive terminal is turned off. The reverse diode of the negative terminal is turned on, and the forward diode of the negative terminal is turned off. The input AC voltage value is the voltage difference between the first AC input terminal and the second AC input terminal. The first output terminal is positive and the second output terminal is negative. When the input signal is a negative periodic voltage, the first AC input terminal is negative and the second AC input terminal is positive; the forward diode of the positive terminal is off, the reverse diode of the positive terminal is on, the reverse diode of the negative terminal is off, and the forward diode of the negative terminal is on; the input AC voltage value is the voltage difference between the second AC input terminal and the first AC input terminal; the first output terminal is positive and the second output terminal is negative.

9. A method for fabricating a monolithic integrated full-bridge rectifier circuit, characterized in that, The method for fabricating the monolithic integrated full-bridge rectifier circuit according to any one of claims 1-8 includes: Multiple quasi-vertical superjunction diodes are fabricated on a Si substrate with the same Si-based GaN epitaxial layer structure; wherein, the Si-based GaN epitaxial layer structure includes, from bottom to top, a Si substrate, an N+ GaN conducting layer and an N-type GaN drift layer; A resistive thin film is formed on the surface of the passivation layer on the Si substrate by sputtering using a TaN target. Passivation layers are regrown on all surfaces and sides of the multi-device structure exposed on the Si substrate. Holes are made by etching the passivation layers and metal is deposited inside the holes. The first layer of metal interconnect is formed according to the connection requirements of the monolithic integrated full-bridge rectifier circuit. A passivation layer is regrown, and holes are made by etching the passivation layer. Metal is then deposited inside the holes, and filter capacitors are prepared. Based on the connection requirements of the monolithic integrated full-bridge rectifier circuit, a second layer of metal interconnect is formed.

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