A method for preparing a piezoelectric MEMS chip

Abstract

The present invention discloses a method for preparing a piezoelectric MEMS chip, comprising growing a piezoelectric layer on the front side of a wafer, wherein the piezoelectric layer comprises a first electrode layer located at the bottom layer, and a buffer layer adjacent to the first electrode layer, etching each layer of the piezoelectric layer from top to bottom to the buffer layer, etching the buffer layer, forming an etching groove in the buffer layer, performing small line width etching on the first electrode layer exposed by the etching groove of the buffer layer, patterning the first electrode layer, etching the wafer, forming a back cavity on the back side of the wafer, and forming a pattern corresponding to the piezoelectric layer on the front side of the wafer. The present invention is conducive to the oriented growth of PZT and improves the film forming quality of the PZT piezoelectric film by setting a buffer layer, and uses the buffer layer to replace the protective layer in the traditional process. In the preparation process of the MEMS chip, the process steps of growing and etching the protective layer on the lower metal are reduced, the production cost of the entire preparation process of the MEMS chip is reduced, and it is also conducive to improving the yield rate of the entire preparation process.

Description

Technical Field

[0001] The present invention relates to the technical field of piezoelectric MEMS chip preparation, and in particular to a method for preparing a piezoelectric MEMS chip. Background Art

[0002] When preparing MEMS chips, the lower metal layer sometimes adopts a very fine small line width graphic design. When the PZT wet etching method is used, the side wall angle produced is relatively large. The side wall slope left after PZT etching seriously affects the etching of the bottom electrode, making it difficult to etch the bottom electrode with a small line width.

[0003] To address this problem, the currently commonly used process method is to etch away all the PZT on the surface of the underlying metal, then dry-etch the underlying metal to obtain a small line width pattern, then grow a protective layer to cover the pattern of the underlying metal, and then pattern the protective layer to obtain a small line width pattern of the underlying metal.

[0004] Taking this approach will increase the process steps of growing and etching the protective layer on the underlying metal, which will also increase production costs and affect the yield rate of the entire MEMS chip manufacturing process.

[0005] The patent document with application number 202111252208.9 discloses a MEMS temperature, humidity and pressure three-in-one sensor chip and its manufacturing process. The scheme includes an SOI wafer, which includes a bulk silicon layer, a buried oxide layer and a device silicon layer. A metal film is grown on the SOI wafer, and a temperature measuring resistor and a pressure measuring resistor are patterned on the metal film. A SiO2 layer is deposited outside the metal film as a temperature compensation layer and an inner dielectric. A through hole is patterned on the SiO2 layer, and a conductive metal layer is deposited on the SiO2 layer. Metal pads and metal connecting wires are patterned on the conductive metal layer to connect the varistor into a Wheatstone bridge. The conductive metal layer is also patterned with a forked finger structure for humidity measurement, and a cavity structure is etched on the back of the SOI wafer substrate.

[0006] This patented solution can solve the problems that existing sensors are not conducive to overall size control of smart products in some scenarios, lack convenient design with composite temperature, humidity and pressure measurement function, and some designs with composite measurement function cannot effectively reduce parasitic capacitance.

[0007] However, it can be understood from the plan that the plan adopts the chemical vapor deposition method and the structure of the protective layer. The processing steps are relatively complicated, which is not conducive to the growth of high-quality piezoelectric layers, nor is it conducive to improving the yield rate of the MEMS chip preparation process.

[0008] In summary, a method for preparing a piezoelectric MEMS chip is needed to solve the problems raised by the prior art. Summary of the invention

[0009] In view of the above-mentioned problems, the object of the present invention is to provide a method for preparing a piezoelectric MEMS chip, reduce the steps of the preparation process, and improve the yield rate of the entire preparation process of the MEMS chip.

[0010] The object of the present invention can be achieved by the following technical solution: A method for preparing a piezoelectric MEMS chip, comprising the steps of:

[0011] S1. growing a piezoelectric layer on the front side of the wafer;

[0012] The piezoelectric layer includes a first electrode layer, a buffer layer, a first piezoelectric film, and a second electrode layer which are stacked and grown in sequence from bottom to top;

[0013] S2, etching the second electrode layer, the first piezoelectric film to the buffer layer in sequence from top to bottom;

[0014] S3, etching the buffer layer to form an etching groove in the buffer layer;

[0015] S4, performing small line width etching on the first electrode layer exposed by the buffer layer etching groove to pattern the first electrode layer;

[0016] S5. Etching the wafer.

[0017] As a further solution of the present invention: the piezoelectric layer further includes: a second piezoelectric film stacked and grown on the second electrode layer, and a third electrode layer stacked and grown on the second piezoelectric film.

[0018] As a further solution of the present invention: the material of the buffer layer is metal oxide.

[0019] As a further solution of the present invention: the thickness of the buffer layer is 50-300 nm.

[0020] As a further solution of the present invention: the buffer layer and the first piezoelectric film have the same crystal orientation.

[0021] As a further solution of the present invention: the wafer is an SOI wafer, and the SOI wafer includes bottom silicon, a buried oxide layer and top silicon.

[0022] As a further solution of the present invention: the step of etching the layers of the piezoelectric layer from top to bottom to the buffer layer in S2 comprises:

[0023] S21, etching the third electrode layer to pattern the third electrode layer;

[0024] S22, etching the second piezoelectric film to pattern the second piezoelectric film;

[0025] S23, etching the second electrode layer to pattern the second electrode layer;

[0026] S24, etching the first piezoelectric film to pattern the first piezoelectric film.

[0027] Beneficial effects of the present invention:

[0028] 1. The present invention sets a buffer layer, the buffer layer material adopts metal oxide, and the thickness of the buffer layer is controlled at 10-500nm. The appropriate material and thickness can make the buffer layer have the same crystal orientation as the first piezoelectric film, which is beneficial to the oriented growth of PZT and can improve the film formation quality of the PZT piezoelectric film.

[0029] 2. The present invention uses a buffer layer to replace the protective layer in the traditional process. In the preparation process of the MEMS chip, the process steps of growing and etching the protective layer on the lower metal are reduced, the production cost of the entire preparation process of the MEMS chip is reduced, and it is also beneficial to improve the yield of the entire preparation process. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 This is a schematic diagram of the structure of the piezoelectric MEMS chip used in Example 1 of the present invention;

[0031] Figure 2 This is a schematic diagram of the process of the piezoelectric MEMS chip preparation method used in Example 1 of the present invention;

[0032] Figure 3 This is a schematic diagram of the structure of the piezoelectric MEMS chip used in Example 2 of the present invention;

[0033] Figure 4 A schematic diagram of the process of preparing a piezoelectric MEMS chip used in Example 2 of the present invention;

[0034] Figure 5 This is a schematic diagram of the structure of the piezoelectric MEMS chip used in Example 3 of the present invention.

[0035] 1. Wafer; 11. Bottom silicon; 12. Buried oxide layer; 13. Top silicon;

[0036] 2. piezoelectric layer; 21. first electrode layer; 22. buffer layer; 23. first piezoelectric film; 24. second electrode layer; 25. second piezoelectric film; 26. third electrode layer;

[0037] 3. Etch the groove. DETAILED DESCRIPTION

[0038] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar symbols throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0039] Embodiment 1:

[0040] like Figure 1-Figure 2 As shown, the present invention discloses a method for preparing a piezoelectric MEMS chip.

[0041] Wafer 1 is a silicon wafer, and wafer 1 has a relative front and back side, and a piezoelectric layer 2 is grown on the front side of wafer 1; the piezoelectric layer 2 includes a first electrode layer 21, a buffer layer 22, a first piezoelectric film 23 and a second electrode layer 24 which are stacked in sequence from bottom to top; wherein, the buffer layer 22 is made of metal oxide, and the thickness of the buffer layer 22 is controlled at 10-500nm. Metal oxide is used as the buffer layer 22, and the appropriate material and thickness can make the buffer layer 22 have the same crystal orientation as the first piezoelectric film 23, which is beneficial to the oriented growth of PZT and can improve the film formation quality of the PZT piezoelectric film.

[0042] Using the above structure, the steps for preparing the piezoelectric MEMS chip include:

[0043] The second electrode layer 24, the first piezoelectric film 23 and the buffer layer 22 of the piezoelectric layer 2 are etched in sequence from top to bottom; including: etching the second electrode layer 24 to pattern the second electrode layer 24; etching the first piezoelectric film 23 to pattern the first piezoelectric film 23; then etching the buffer layer 22 to form an etching groove 3 in the buffer layer 22; etching the first electrode layer 21 exposed by the etching groove 3 of the buffer layer 22 with a small line width to pattern the first electrode layer 21; then etching the wafer 1 to pattern the front side of the wafer 1 and form a back cavity on the back side of the wafer 1 to provide a vibration space for the diaphragm.

[0044] Through the above-mentioned MEMS chip preparation process method, the first electrode layer 21 with small line width etching can be obtained. Compared with the traditional preparation process method, there is no need to grow a protective layer after etching the lower metal layer (first electrode layer 21) with small line width, so that the protective layer covers the pattern of the lower metal layer and then patterns the protective layer.

[0045] This reduces the process steps of growing and etching the protective layer on the underlying metal layer, reduces the production cost of the entire MEMS chip manufacturing process, and is also beneficial to improving the yield rate of the entire manufacturing process.

[0046] Embodiment 2:

[0047] Based on the embodiment 1, the structure of the piezoelectric layer 2 is different, such as Figure 3-Figure 4 As shown, the piezoelectric layer 2 includes a first electrode layer 21, a buffer layer 22, a first piezoelectric film 23, a second electrode layer 24, a second piezoelectric film 25 and a third electrode layer 26 which are stacked in sequence from bottom to top. At this time, the piezoelectric layer 2 has a dual piezoelectric film layer and three electrode layers. If the traditional preparation process is used, the product yield cannot be effectively guaranteed.

[0048] Using the above structure, the steps of preparing the piezoelectric MEMS chip using the method of the present invention include:

[0049] The third electrode layer 26, the second piezoelectric film 25, the second electrode layer 24 and the first piezoelectric film 23 of the piezoelectric layer 2 are etched from top to bottom to the buffer layer 22, including: etching the third electrode layer 26 to pattern the third electrode layer 26; etching the second piezoelectric film 25 to pattern the second piezoelectric film 25; etching the second electrode layer 24 to pattern the second electrode layer 24; etching the first piezoelectric film 23 to pattern the first piezoelectric film 23; then etching the buffer layer 22 to form an etching groove 3 in the buffer layer 22; performing small line width etching on the first electrode layer 21 exposed by the etching groove 3 of the buffer layer 22 to pattern the first electrode layer 21; then etching the wafer 1 to pattern the front side of the wafer 1, and forming a back cavity on the back side of the wafer 1 to provide a vibration space for the diaphragm.

[0050] Through the above-mentioned MEMS chip preparation process method, the first electrode layer 21 with small line width etching can be obtained. Compared with the traditional preparation process method, there is no need to grow a protective layer after etching the lower metal layer (first electrode layer 21) with small line width, so that the protective layer covers the pattern of the lower metal layer and then patterns the protective layer.

[0051] This reduces the process steps of growing and etching the protective layer on the underlying metal layer, reduces the production cost of the entire MEMS chip manufacturing process, and is also beneficial to improving the yield rate of the entire manufacturing process.

[0052] Embodiment 3:

[0053] On the basis of Example 1 or 2, Figure 5 As shown, the wafer 1 is a SOI wafer, which includes a bottom silicon 11, a buried oxide layer 12 and a top silicon 13. The back of the SOI wafer is the bottom silicon 11, and the front is the top silicon 13, on which a piezoelectric layer 2 is grown.

[0054] Using the above structure, the steps of preparing the piezoelectric MEMS chip using the method of the present invention include:

[0055] The layers of the piezoelectric layer 2 are etched sequentially from top to bottom to the buffer layer 22; the buffer layer 22 is etched to form an etching groove 3 in the buffer layer 22; the first electrode layer 21 exposed by the etching groove 3 of the buffer layer 22 is etched with a small line width to pattern the first electrode layer 21; the SOI wafer is etched to form a back cavity between the bottom silicon and the buried oxide layer, and the top silicon is patterned.

[0056] Through the above-mentioned MEMS chip preparation process method, the first electrode layer 21 with small line width etching can be obtained. Compared with the traditional preparation process method, there is no need to grow a protective layer after etching the lower metal layer (first electrode layer) with small line width. After the protective layer covers the pattern of the lower metal, the protective layer is patterned.

[0057] This reduces the process steps of growing and etching the protective layer on the underlying metal layer, reduces the production cost of the entire MEMS chip manufacturing process, and is also beneficial to improving the yield rate of the entire manufacturing process.

[0058] In summary, the MEMS chip preparation process proposed in each embodiment of the present invention, by setting a buffer layer 22 and leaving an etching groove 3 for etching the bottom electrode layer of the buffer layer 22, replaces the etching process of etching PZT and adding a protective film in the traditional process, simplifies the process flow, reduces costs, and improves the yield rate.

[0059] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

[0060] It should be understood that the orientation or positional relationship indicated by the terms "upper" and "lower" etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

Claims

1. A method for preparing a piezoelectric MEMS chip, characterized in that: include: S1, growing a piezoelectric layer (2) on the front side of the wafer (1); The piezoelectric layer (2) comprises a first electrode layer (21), a buffer layer (22), a first piezoelectric film (23) and a second electrode layer (24) which are stacked and grown in sequence from bottom to top; S2, etching the second electrode layer (24), the first piezoelectric film (23) to the buffer layer (22) in sequence from top to bottom; S3, etching the buffer layer (22) to form an etching groove (3) in the buffer layer (22); S4, performing small line width etching on the first electrode layer (21) exposed by the etching groove (3) of the buffer layer (22), so as to pattern the first electrode layer (21); S5. Etching the wafer (1).

2. The method for preparing a piezoelectric MEMS chip according to claim 1, characterized in that: The piezoelectric layer (2) further comprises: a second piezoelectric film (25) stacked and grown on the second electrode layer (24), and a third electrode layer (26) stacked and grown on the second piezoelectric film (25).

3. The method for preparing a piezoelectric MEMS chip according to claim 2, characterized in that: The buffer layer (22) and the first piezoelectric film (23) have the same crystal orientation.

4. The method for preparing a piezoelectric MEMS chip according to any one of claims 1 to 3, characterized in that: The material of the buffer layer (22) is metal oxide.

5. The method for preparing a piezoelectric MEMS chip according to any one of claims 1 to 3, characterized in that: The thickness of the buffer layer (22) is 50-300 nm.

6. The method for preparing a piezoelectric MEMS chip according to claim 1 or 2, characterized in that: The wafer (1) is an SOI wafer, and the SOI wafer comprises bottom silicon (11), a buried oxide layer (12) and top silicon (13).

7. The method for preparing a piezoelectric MEMS chip according to claim 2, characterized in that: The step of etching the layers of the piezoelectric layer from top to bottom to the buffer layer in S2 includes: S21, etching the third electrode layer (26) to pattern the third electrode layer (26); S22, etching the second piezoelectric film (25) to pattern the second piezoelectric film (25); S23, etching the second electrode layer (24) to pattern the second electrode layer (24); S24, etching the first piezoelectric film (23) to pattern the first piezoelectric film (23).

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