Self-selecting memory based on 1s1r structure and preparation method and device thereof

Abstract

The present disclosure relates to a self-selecting memory based on 1S1R structure and a preparation method and device thereof, wherein an intermediate layer is additionally arranged between a gating layer and a resistance change layer, the thermal conductivity of the intermediate layer is less than that of the resistance change layer, the intermediate layer is arranged between the resistance change layer and the gating layer, can hinder the heat transfer of the gating layer to the resistance change layer, can improve the temperature rising rate of the gating layer, so that the gating layer quickly rises to the opening temperature, can reduce the opening voltage of the gating layer of the self-selecting memory, and the self-selecting memory realizes self-selection storage; meanwhile, the intermediate layer can improve the thermal stability of the gating layer, delay the temperature reduction of the gating layer, reduce the write voltage and read voltage of the whole self-selecting memory; and can also avoid the mutual diffusion of the materials of the gating layer and the resistance change layer to cause the performance degradation of the self-selecting memory, and improve the reliability and performance stability of the self-selecting memory.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a self-selection memory based on a 1S1R structure and its fabrication method and apparatus. Background Technology

[0002] Resistive Random Access Memory (RRAM) has the advantages of simple structure, small feature size, and fast programming / erasing speed, and has great development potential. At present, most RRAM memories adopt a 1T1R architecture that integrates gating transistors and memristors. The 1T1R architecture has a large feature size, which limits the scalability of RRAM memories and is not conducive to three-dimensional integration.

[0003] The selector, as a threshold switching device integrated with a memristor, forms a 1S1R architecture RRAM memory with a smaller feature size. Utilizing the threshold switching characteristics of the selector, leakage current in the low-resistance RRAM of unselected cells can be suppressed. The 1S1R cell, composed of the selector and resistive switching memory, is suitable for both storage and the implementation of neuromorphic computing systems.

[0004] However, the 1S1R architecture of RRAM memory still has many problems that limit its application. Summary of the Invention

[0005] Therefore, it is necessary to provide a self-selection memory based on the 1S1R structure and its preparation method and device to address the problem of limited application of RRAM memory with the 1S1R architecture in the existing technology.

[0006] In a first aspect, this disclosure provides a self-selecting memory based on a 1S1R structure, including a first functional layer, an intermediate layer and a second functional layer stacked sequentially on a substrate, wherein the second functional layer is separated from the first functional layer through the intermediate layer, the first functional layer is connected to a first electrode and the second functional layer is connected to a second electrode.

[0007] One of the first functional layer and the second functional layer is a gated layer, and the other is a resistive switching layer; the thermal conductivity of the intermediate layer is less than that of the resistive switching layer.

[0008] Optionally, the thermal conductivity of the gate layer is 0.3 W / m·K to 1.5 W / m·K; and the thermal conductivity of the resistive switching layer is 2.2 W / m·K to 5 W / m·K.

[0009] The thermal conductivity of the intermediate layer is 0.2 W / m·K - 2 W / m·K; the electrical conductivity of the intermediate layer is 10. -7 S / m-10 -2 S / m.

[0010] Optionally, the thermal conductivity of the intermediate layer near the resistive switching layer is less than the thermal conductivity of the intermediate layer near the gated layer.

[0011] Optionally, the thermal conductivity of the intermediate layer decreases from the gated layer toward the resistive switching layer.

[0012] Optionally, the material of the intermediate layer includes at least one of amorphous carbon, silicon carbide, tellurium carbide, tellurium carbon sulfide, molybdenum sulfide, tungsten sulfide, molybdenum telluride, indium gallium zinc oxide, indium aluminum zinc oxide, tin-doped indium oxide, manganese telluride, tungsten telluride, and zinc-doped indium oxide.

[0013] Optionally, the material of the gate layer includes at least one of niobium oxide, vanadium oxide, iron oxide, neodymium nickel oxide, samarium nickel oxide, lanthanum cobalt oxide, gadolinium cobalt oxide, germanium telluride, aluminum telluride, boron telluride, germanium selenide, germanium sulfide, and antimony telluride;

[0014] The resistive switching layer is made of at least one of the following materials: tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, silicon oxide, magnesium oxide, aluminum nitride, germanium antimony tellurium, scandium antimony tellurium, indium silver antimony tellurium, germanium antimony, germanium telluride, antimony telluride, copper sulfide, germanium sulfide, germanium selenide, zinc sulfide, aluminum borate, strontium titanate, zirconium titanate, barium titanate, hafnium zirconium oxide, and hafnium aluminum oxide.

[0015] Optionally, the first functional layer is a gating layer, and the second functional layer is a resistive switching layer;

[0016] The first functional layer is made of niobium oxide, the intermediate layer is made of amorphous carbon, and the second functional layer is made of tantalum oxide.

[0017] Optionally, the first functional layer is a resistive switching layer, and the second functional layer is a gating layer;

[0018] The first functional layer is made of tantalum oxide, the intermediate layer is made of amorphous carbon, and the second functional layer is made of niobium oxide.

[0019] Secondly, this disclosure provides a method for fabricating a self-selective memory based on a 1S1R structure, comprising the following steps:

[0020] A substrate is provided, and a first electrode is formed on the substrate;

[0021] A first functional layer is formed on the first electrode;

[0022] An intermediate layer is formed on the first functional layer;

[0023] A second functional layer is formed on the intermediate layer, and the second functional layer is separated from the first functional layer by the intermediate layer; one of the first functional layer and the second functional layer is a gate layer, and the other is a resistive switching layer; the thermal conductivity of the intermediate layer is less than the thermal conductivity of the resistive switching layer;

[0024] A second electrode is formed on the second functional layer.

[0025] Optionally, the thermal conductivity of the gate layer is 0.3 W / m·K to 1.5 W / m·K; and the thermal conductivity of the resistive switching layer is 2.2 W / m·K to 5 W / m·K.

[0026] The thermal conductivity of the intermediate layer is 0.2 W / m·K - 2 W / m·K; the electrical conductivity of the intermediate layer is 10. -7 S / m-10 -2 S / m.

[0027] Optionally, the thermal conductivity of the intermediate layer near the resistive switching layer is less than the thermal conductivity of the intermediate layer near the gated layer.

[0028] Optionally, the thermal conductivity of the intermediate layer decreases from the gated layer toward the resistive switching layer.

[0029] Optionally, the material of the intermediate layer includes at least one of amorphous carbon, silicon carbide, tellurium carbide, tellurium carbon sulfide, molybdenum sulfide, tungsten sulfide, molybdenum telluride, indium gallium zinc oxide, indium aluminum zinc oxide, tin-doped indium oxide, manganese telluride, tungsten telluride, and zinc-doped indium oxide.

[0030] Optionally, the material of the gate layer includes at least one of niobium oxide, vanadium oxide, iron oxide, neodymium nickel oxide, samarium nickel oxide, lanthanum cobalt oxide, gadolinium cobalt oxide, germanium telluride, aluminum telluride, boron telluride, germanium selenide, germanium sulfide, and antimony telluride;

[0031] The resistive switching layer is made of at least one of the following materials: tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, silicon oxide, magnesium oxide, aluminum nitride, germanium antimony tellurium, scandium antimony tellurium, indium silver antimony tellurium, germanium antimony, germanium telluride, antimony telluride, copper sulfide, germanium sulfide, germanium selenide, zinc sulfide, aluminum borate, strontium titanate, zirconium titanate, barium titanate, hafnium zirconium oxide, and hafnium aluminum oxide.

[0032] Optionally, after forming an intermediate layer on the first functional layer, the method further includes:

[0033] The first gas is ionized to generate plasma, which is then used to treat the intermediate layer.

[0034] Optionally, the first functional layer is a gate layer, and the second functional layer is a resistive switching layer; the material of the first functional layer includes niobium oxide, the material of the intermediate layer includes amorphous carbon, and the material of the second functional layer includes tantalum oxide.

[0035] Optionally, the first functional layer is a resistive switching layer, and the second functional layer is a gated layer; the material of the first functional layer includes tantalum oxide, the material of the intermediate layer includes amorphous carbon, and the material of the second functional layer includes niobium oxide.

[0036] Thirdly, this disclosure provides an electronic device, including a self-selecting memory based on the 1S1R structure as described in the first aspect, or a self-selecting memory based on the 1S1R structure fabricated by the method described in the second aspect.

[0037] This disclosure discloses a self-selection memory based on a 1S1R structure, along with its fabrication method and apparatus. An intermediate layer is added between the gate layer and the resistive switching layer. The thermal conductivity of the intermediate layer is lower than that of the resistive switching layer. This intermediate layer, positioned between the resistive switching layer and the gate layer, hinders heat transfer from the gate layer to the resistive switching layer, thereby increasing the temperature rise rate of the gate layer and allowing it to quickly reach the turn-on temperature. This reduces the turn-on voltage of the gate layer in the self-selection memory, enabling self-selection storage. Simultaneously, the intermediate layer improves the thermal stability of the gate layer, delaying its temperature decrease and reducing the overall write and read voltages of the self-selection memory. Furthermore, it prevents material diffusion between the gate layer and the resistive switching layer from degrading the performance of the self-selection memory, thus improving its reliability and performance stability. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a schematic diagram of a self-selection memory based on a 1S1R structure provided in an exemplary embodiment.

[0040] Figure 2 A schematic diagram of a self-selection memory based on a 1S1R structure provided in another exemplary embodiment;

[0041] Figure 3 This is a process flow diagram of a method for fabricating a self-selective memory based on a 1S1R structure, provided in an exemplary embodiment. Detailed Implementation

[0042] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0044] According to an exemplary embodiment, this disclosure provides a self-selecting memory based on a 1S1R structure, with reference to... Figure 1 , Figure 2 It includes a first functional layer 30, an intermediate layer 40 and a second functional layer 50 sequentially stacked on a substrate 10. The second functional layer 50 is separated from the first functional layer 30 by the intermediate layer 40. The first functional layer 30 is connected to the first electrode 20 and the second functional layer 50 is connected to the second electrode 60. One of the first functional layer 30 and the second functional layer 50 is a gate layer 110 and the other is a resistive switching layer 120. The thermal conductivity of the intermediate layer 40 is less than that of the resistive switching layer 120.

[0045] In this embodiment of the self-selection memory based on the 1S1R structure, an intermediate layer 40 is added between the gate layer 110 and the resistive switching layer 120. On one hand, the thermal conductivity of the intermediate layer 40 is lower than that of the resistive switching layer 120. The intermediate layer 40, located between the resistive switching layer 120 and the gate layer 110, can prevent heat transfer from the gate layer 110 to the resistive switching layer 120, allowing the gate layer 110 to quickly rise to the turn-on temperature, thereby reducing the turn-on voltage (V) of the self-selection memory. th The self-selection memory enables self-selection storage; at the same time, the intermediate layer 40 can improve the thermal stability of the gate layer 110, delay the temperature drop of the gate layer 110, and reduce the overall write voltage and read voltage of the self-selection memory; on the other hand, the intermediate layer 40 can also prevent the material cross-diffusion between the gate layer 110 and the resistive switching layer 120 from causing the performance degradation of the self-selection memory, thereby improving the reliability and performance stability of the self-selection memory.

[0046] In one embodiment, reference Figure 1 , Figure 2 The thermal conductivity of the intermediate layer 40 is greater than that of the gate layer 110. This prevents the intermediate layer 40 from affecting the temperature rise of the gate layer 110.

[0047] In one embodiment, the thermal conductivity of the gate layer 110 is 0.3 W / m·K to 1.5 W / m·K; for example, the thermal conductivity of the gate layer 110 can be 0.3 W / m·K, 0.4 W / m·K, 0.5 W / m·K, 0.6 W / m·K, 0.7 W / m·K, 0.8 W / m·K, 0.9 W / m·K, 1.0 W / m·K, 1.1 W / m·K, 1.2 W / m·K, 1.3 W / m·K, or 1.5 W / m·K.

[0048] The thermal conductivity of the resistive switching layer 120 is 2.2 W / m·K to 5 W / m·K; for example, the thermal conductivity of the resistive switching layer 120 can be 2.2 W / m·K, 2.3 W / m·K, 2.4 W / m·K, 2.5 W / m·K, 2.6 W / m·K, 2.7 W / m·K, 3 W / m·K, 3.5 W / m·K, 4 W / m·K, 4.5 W / m·K or 5 W / m·K.

[0049] The thermal conductivity of the intermediate layer 40 is 0.2 W / m·K to 2 W / m·K. For example, the thermal conductivity of the intermediate layer 40 can be 0.2 W / m·K, 0.3 W / m·K, 0.4 W / m·K, 0.5 W / m·K, 0.6 W / m·K, 0.7 W / m·K, 0.72 W / m·K, 0.75 W / m·K, 0.8 W / m·K, 1.0 W / m·K, 1.2 W / m·K, 1.4 W / m·K, 1.5 W / m·K, 1.6 W / m·K, 1.7 W / m·K, 1.9 W / m·K, or 2.0 W / m·K.

[0050] The conductivity of the intermediate layer 40 is 10. -7 S / m-10 -2 S / m. Example, 10 -7 S / m, 10 -6 S / m, 10 -5 S / m, 10 -4 S / m, 10 -3 S / m or 10 -2 S / m.

[0051] The thermal conductivity of the intermediate layer 40 is between 0.2 W / m·K and 2 W / m·K, and the electrical conductivity is between 10 W / m·K. -7 S / m-10 -2 Between S / m, the intermediate layer 40 has good conductivity and a certain degree of heat insulation. Thus, the intermediate layer 40, located between the gate layer 110 and the resistive switching layer 120, will not affect the conduction of the gate layer 110 and the resistive switching layer 120, and can also reduce the turn-on voltage of the self-selection memory.

[0052] In one embodiment, reference Figure 1 , Figure 2The thermal conductivity of the intermediate layer 40 near the resistive switching layer 120 is less than that of the intermediate layer 40 near the gated layer 110.

[0053] It can be understood that the intermediate layer 40 is equivalent to setting a "lid" on the gate layer 110. The intermediate layer 40 prevents the gate layer 110 from transferring heat to the outside and stores the heat inside the gate layer 110. The thermal conductivity of the intermediate layer 40 near the gate layer 110 is greater than that near the resistive switching layer 120. That is, the difficulty of the heat of the gate layer 110 being transferred to the outside through the intermediate layer 40 is increased, which further increases the temperature rise rate of the gate layer 110 so that the gate layer 110 can quickly rise to the opening temperature.

[0054] The thermal conductivity of the intermediate layer 40 near the resistive switching layer 120 is lower than that near the gated layer 110. This can be achieved by making the resistive switching layer 120 multi-layered, with the thermal conductivity of the material layer near the resistive switching layer 120 being lower than that near the gated layer 110. Alternatively, it can be achieved by adjusting the composition content or doping of the material in the intermediate layer 40, or by any one or more other methods. For example, the thermal conductivity of the intermediate layer 40 can be adjusted by adjusting the concentration of dopant ions in the intermediate layer 40.

[0055] In one embodiment, the thermal conductivity of the intermediate layer 40 decreases in the direction from the self-selecting layer 110 to the resistive switching layer 120.

[0056] The intermediate layer 40 may include multiple layers of material stacked between the gate layer 110 and the resistive switching layer 120, with the thermal conductivity of each material layer of the intermediate layer 40 decreasing sequentially from the gate layer 110 to the resistive switching layer 120. Alternatively, the deposition process for forming the intermediate layer 40 can be controlled so that the material composition of the intermediate layer 40 gradually changes from the gate layer 110 to the resistive switching layer 120, resulting in a gradual decrease in the thermal conductivity of the intermediate layer 40.

[0057] In one example, the intermediate layer 40 includes a first intermediate layer and a second intermediate layer stacked sequentially in the direction of the self-selecting layer 110 toward the resistive switching layer 120, wherein the thermal conductivity of the second intermediate layer is less than that of the first intermediate layer.

[0058] In another example, the intermediate layer 40 includes a first intermediate layer, a second intermediate layer, and a third intermediate layer stacked sequentially in the direction of the self-selecting layer 110 toward the resistive switching layer 120, wherein the thermal conductivity of the first intermediate layer, the second intermediate layer, and the third intermediate layer decreases sequentially.

[0059] In one embodiment, the thermal conductivity of the gate layer 110 closer to the intermediate layer 40 is lower than that of the gate layer 110 farther from the intermediate layer 40. Thus, from the gate layer 110 towards the resistive switching layer 120, the gate layer 110 and the intermediate layer 40 form a stack with gradually decreasing thermal conductivity, which can further improve the thermal stability of the gate layer 110, delay the temperature decrease of the gate layer, and reduce the overall write and read voltages of the self-select memory.

[0060] The gate layer 110 can be a single-layer structure, and its thermal conductivity can be modulated by adjusting the composition content or doping of the material in the gate layer 110. The gate layer 110 can also be a multi-layer structure, and its thermal conductivity can be modulated by adjusting the multiple material layers of the gate layer 110.

[0061] In one embodiment, reference Figure 1 , Figure 2 The thermal conductivity of the resistive switching layer 120 on the side away from the intermediate layer 40 is less than that of the gate layer 110 on the side closer to the intermediate layer 40. Thus, from the gate layer 110 towards the resistive switching layer 120, the gate layer 110, the intermediate layer 40, and the resistive switching layer 120 form a stack with gradually decreasing thermal conductivity, which can further improve the thermal stability of the gate layer 110 and improve the performance of the self-selection memory.

[0062] Similarly, the material of the resistive switching layer 120 can be a single-layer structure or a multi-layer structure.

[0063] In one embodiment, the material of the intermediate layer 40 includes at least one of amorphous carbon, silicon carbide, tellurium carbide, tellurium carbon sulfide, molybdenum sulfide, tungsten sulfide, molybdenum telluride, indium gallium zinc oxide, indium aluminum zinc oxide, tin-doped indium oxide, manganese telluride, tungsten telluride, and zinc-doped indium oxide.

[0064] The intermediate layer 40 can be a single-layer structure or a multi-layer structure. For example, the intermediate layer 40 can include a single-layer amorphous carbon layer; or, for another example, the intermediate layer 40 can be a stacked amorphous carbon layer and an indium gallium zinc oxide layer.

[0065] In some embodiments, the material of the intermediate layer 40 includes amorphous carbon, which has good electrical conductivity, as well as good thermal conductivity and heat insulation properties. This helps to maintain the temperature of the gate layer 110, improve the threshold switching characteristics of the gate layer 110, and facilitate the three-dimensional integration of the self-selection memory.

[0066] In one embodiment, the material of the gate layer 110 includes at least one of niobium oxide, vanadium oxide, iron oxide, neodymium nickel oxide, samarium nickel oxide, lanthanum cobalt oxide, gadolinium cobalt oxide, germanium telluride, aluminum telluride, boron telluride, germanium selenide, germanium sulfide, and antimony telluride.

[0067] The resistive switching layer 120 is made of at least one of the following materials: tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, silicon oxide, magnesium oxide, aluminum nitride, germanium antimony tellurium, scandium antimony tellurium, indium silver antimony tellurium, germanium antimony, germanium telluride, antimony telluride, copper sulfide, germanium sulfide, germanium selenide, zinc sulfide, aluminum borate, strontium titanate, zirconium titanate, barium titanate, hafnium zirconium oxide, and hafnium aluminum oxide.

[0068] Thus, by reasonably setting the materials of the gate layer 110 and the resistive switching layer 120 of the self-selection memory, the materials of the gate layer 110 and the resistive switching layer 120 are matched, so that the self-selection memory has a self-rectification effect, which can effectively suppress the leakage current generated by the self-selection memory, which is conducive to further reducing the size of the self-selection memory, and making the self-selection memory into an integrated array, which is conducive to expanding the application fields and application scenarios of the self-selection memory.

[0069] For example, the resistive switching layer 120 is made of tantalum oxide and the gate layer 110 is made of niobium oxide, which can further improve the self-rectification capability of the variable memory and suppress leakage current generated by the self-selection memory.

[0070] In one embodiment, the gate layer 110 is doped with a thermally conductive material to improve the thermal conductivity of the gate layer 110, thereby improving the temperature rise rate and thermal stability of the gate layer 110.

[0071] For example, the thermally conductive material may include one or more of Al, Cu, Au, Ti, etc.

[0072] It is understood that the thermal conductivity of the side of the gate layer 110 closer to the intermediate layer 40 can be made less than the thermal conductivity of the side of the gate layer 110 farther from the intermediate layer 40 by controlling the concentration of the thermally conductive material doped in the gate layer 110.

[0073] In one embodiment, the material of the first electrode 20 may include at least one selected from vanadium (V), niobium (Nb), ruthenium (Ru), tungsten (W), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), aluminum (Al), titanium aluminum tungsten (TiAlW), yttrium (Ir), yttrium oxide (IrO2), indium tin oxide (ITO), titanium aluminum nitride (TiAlN), aluminum nitride (AlNx), titanium aluminum nitride (TiAlN) or (AlTiN), hafnium (Hf), iridium (Ir), manganese (Mn), zinc (Zn), platinum (Pt), palladium (Pd), and copper (Cu). The first electrode 20 may be a single-layer structure or a multi-layer structure.

[0074] The selection range of materials for the second electrode 60 is the same as that for the first electrode 20, and will not be repeated here.

[0075] It is understandable that in actual production, the first electrode 20 and the second electrode 60 may include the same material or different materials.

[0076] In one embodiment, reference Figure 1 The first functional layer 30 is a gate layer 110, and the second functional layer 50 is a resistive switching layer 120. The material of the first functional layer 30 includes niobium oxide, the material of the intermediate layer 40 includes amorphous carbon, and the material of the second functional layer 50 includes tantalum oxide. The first electrode 20, the gate layer 110, the intermediate layer 40, the resistive switching layer 120, and the second electrode 60 are sequentially stacked on the substrate 10. In this way, the self-rectification capability of the variable frequency drive can be further improved, and leakage current generated by the self-selection drive can be suppressed.

[0077] In one embodiment, reference Figure 2 The first functional layer 30 is a resistive switching layer 120, and the second functional layer 50 is a gate layer 110. The material of the first functional layer 30 includes tantalum oxide, the material of the intermediate layer 40 includes amorphous carbon, and the material of the second functional layer 50 includes niobium oxide. The first electrode 20, the resistive switching layer 120, the intermediate layer 40, the gate layer 110, and the second electrode 60 are sequentially stacked on the substrate 10. In this way, the self-rectification capability of the variable frequency drive can be further improved, and leakage current generated by the self-selection drive can be suppressed.

[0078] According to an exemplary embodiment, such as Figure 3 As shown, this disclosure provides a method for fabricating a self-selection memory based on a 1S1R structure, including the following steps:

[0079] Step S10: Provide a substrate and form a first electrode on the substrate;

[0080] Step S20: Form a first functional layer on the first electrode;

[0081] Step S30: Form an intermediate layer on the first functional layer;

[0082] Step S40: A second functional layer is formed on the intermediate layer. The second functional layer is separated from the first functional layer by the intermediate layer. One of the first functional layer and the second functional layer is a gate layer, and the other is a resistive switching layer. The thermal conductivity of the intermediate layer is less than that of the resistive switching layer.

[0083] Step S50: Form a second electrode on the second functional layer.

[0084] The fabrication method of the self-selection memory based on the 1S1R structure in this embodiment forms an intermediate layer between the gate layer and the resistive switching layer. The thermal conductivity of the intermediate layer is lower than that of the resistive switching layer. The intermediate layer, located between the resistive switching layer and the gate layer, can hinder the heat transfer from the gate layer to the resistive switching layer, thereby increasing the temperature rise rate of the gate layer and enabling it to quickly reach the turn-on temperature. This reduces the turn-on voltage of the gate layer in the self-selection memory, allowing it to achieve self-selection storage. Simultaneously, the intermediate layer improves the thermal stability of the gate layer, delays the temperature decrease of the gate layer, and reduces the overall write and read voltages of the self-selection memory. Furthermore, it prevents material diffusion between the gate layer and the resistive switching layer from causing performance degradation of the self-selection memory, thus improving its reliability and performance stability.

[0085] In step S10, refer to Figure 1 or Figure 2 The substrate 10 can be a semiconductor substrate. Semiconductor substrate materials include, for example, silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), etc. Alternatively, in some cases, the substrate 10 can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP).

[0086] The first electrode 20 is deposited on the substrate 10 using physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD) to form the first electrode 20.

[0087] The material of the first electrode 20 may include one or more of the following: vanadium, niobium, ruthenium, tungsten, tantalum, tantalum nitride, titanium, titanium nitride, titanium tungsten, aluminum, titanium aluminum tungsten, aluminum titanium nitride, aluminum nitride, aluminum titanium nitride, AlTiN, hafnium, iridium, manganese, zinc, platinum, palladium, copper, or alloys thereof. The first electrode 20 may be a single-layer structure or a multi-layer structure.

[0088] The thickness of the first electrode 20 can be 10nm-2500nm. For example, the thickness of the first electrode 20 can be 10nm, 100nm, 500nm, 1000nm, 1500nm, 2000nm or 2500nm.

[0089] In step S20, refer to Figure 1 or Figure 2The first functional layer 30 can be formed using PVD, CVD, PECVD, ALD, ion beam sputtering, electron beam evaporation, or thermal evaporation. The first functional layer 30 is either a gated layer 110 or a resistive switching layer 120. The first functional layer 30 can be a single-layer structure or a multi-layer structure.

[0090] In step S30, refer to Figure 1 or Figure 2 The intermediate layer 40 can be deposited using processes such as PVD, ALD, CVD, atmospheric pressure CVD (APCVD), PECVD, or low pressure CVD (LPCVD). The intermediate layer 40 can be a single-layer structure or a multi-layer structure.

[0091] In step S40, refer to Figure 1 or Figure 2 The second functional layer 50 can be formed using PVD, CVD, PECVD, ALD, ion beam sputtering, electron beam evaporation, or thermal evaporation. The second functional layer 50 is either a resistive switching layer 120 or a gated layer 110. The second functional layer 50 can be a single-layer structure or a multi-layer structure.

[0092] Among them, one of the first functional layer 30 and the second functional layer 50 is a gate layer 110, and the other is a resistive switching layer 120. The thermal conductivity of the intermediate layer 40 is less than that of the resistive switching layer 120.

[0093] In step S50, refer to Figure 1 or Figure 2 The second electrode 60 is formed by PVD, CVD, PECVD, or ALD deposition. The material selection range for the second electrode 60 is the same as that for the first electrode 20, and will not be repeated here.

[0094] The thickness of the second electrode 60 can be 10nm-2500nm. For example, the thickness of the second electrode 60 can be 10nm, 100nm, 500nm, 1000nm, 1500nm, 2000nm or 2500nm.

[0095] In one embodiment, the thermal conductivity of the intermediate layer 40 is greater than that of the gate layer 110. This prevents the intermediate layer 40 from affecting the temperature rise of the gate layer 110.

[0096] In one embodiment, the thermal conductivity of the gate layer 110 is 0.3 W / m·K to 1.5 W / m·K; for example, the thermal conductivity of the gate layer 110 can be 0.3 W / m·K, 0.4 W / m·K, 0.5 W / m·K, 0.6 W / m·K, 0.7 W / m·K, 0.8 W / m·K, 0.9 W / m·K, 1.0 W / m·K, 1.1 W / m·K, 1.2 W / m·K, 1.3 W / m·K, or 1.5 W / m·K.

[0097] The thermal conductivity of the resistive switching layer 120 is 2.2 W / m·K to 5 W / m·K; for example, the thermal conductivity of the resistive switching layer 120 can be 2.2 W / m·K, 2.3 W / m·K, 2.4 W / m·K, 2.5 W / m·K, 2.6 W / m·K, 2.7 W / m·K, 3 W / m·K, 3.5 W / m·K, 4 W / m·K, 4.5 W / m·K or 5 W / m·K.

[0098] The thermal conductivity of the intermediate layer 40 is 0.2 W / m·K to 2 W / m·K. For example, the thermal conductivity of the intermediate layer 40 can be 0.2 W / m·K, 0.3 W / m·K, 0.4 W / m·K, 0.5 W / m·K, 0.6 W / m·K, 0.7 W / m·K, 0.72 W / m·K, 0.75 W / m·K, 0.8 W / m·K, 1.0 W / m·K, 1.2 W / m·K, 1.4 W / m·K, 1.5 W / m·K, 1.6 W / m·K, 1.7 W / m·K, 1.9 W / m·K, or 2.0 W / m·K.

[0099] The conductivity of the intermediate layer 40 is 10. -7 S / m-10 -2 S / m. Example, 10 -7 S / m, 10 -6 S / m, 10 -5 S / m, 10 -4 S / m, 10 -3 S / m or 10 -2 S / m.

[0100] The thermal conductivity of the intermediate layer 40 is between 0.2 W / m·K and 2 W / m·K, and the electrical conductivity is between 10 W / m·K. -7 S / m-10 -2 Between S / m, the intermediate layer 40 has good conductivity and a certain degree of heat insulation. Thus, the intermediate layer 40, located between the gate layer 110 and the resistive switching layer 120, will not affect the conduction of the gate layer 110 and the resistive switching layer 120, and can also reduce the turn-on voltage of the self-selection memory.

[0101] In one embodiment, the thermal conductivity of the intermediate layer 40 near the resistive switching layer 120 is less than the thermal conductivity of the intermediate layer 40 near the gated layer 110.

[0102] When forming the intermediate layer 40, at least two layers may be deposited such that the thermal conductivity of the material layer of the intermediate layer 40 near the resistive switching layer 120 is less than the thermal conductivity of the material layer of the intermediate layer 40 near the gated layer 110.

[0103] Alternatively, during the formation of the intermediate layer 40, ions can be doped into the intermediate layer 40. By controlling the concentration of the doped ions, the thermal conductivity of the material layer on the side of the intermediate layer 40 near the resistive switching layer 120 can be made less than the thermal conductivity of the material layer on the side of the intermediate layer 40 near the gated layer 110.

[0104] In one embodiment, the thermal conductivity of the intermediate layer 40 decreases in the direction from the self-selecting layer 110 to the resistive switching layer 120.

[0105] In one embodiment, the material of the intermediate layer 40 includes at least one of amorphous carbon, silicon carbide, tellurium carbide, tellurium carbon sulfide, molybdenum sulfide, tungsten sulfide, molybdenum telluride, indium gallium zinc oxide, indium aluminum zinc oxide, tin-doped indium oxide, manganese telluride, tungsten telluride, and zinc-doped indium oxide.

[0106] For example, the material of the intermediate layer 40 may include amorphous carbon.

[0107] In one embodiment, the material of the gate layer 110 includes at least one of niobium oxide, vanadium oxide, iron oxide, neodymium nickel oxide, samarium nickel oxide, lanthanum cobalt oxide, gadolinium cobalt oxide, germanium telluride, aluminum telluride, boron telluride, germanium selenide, germanium sulfide, and antimony telluride.

[0108] The resistive switching layer 120 is made of at least one of the following materials: tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, silicon oxide, magnesium oxide, aluminum nitride, germanium antimony tellurium, scandium antimony tellurium, indium silver antimony tellurium, germanium antimony, germanium telluride, antimony telluride, copper sulfide, germanium sulfide, germanium selenide, zinc sulfide, aluminum borate, strontium titanate, zirconium titanate, barium titanate, hafnium zirconium oxide, and hafnium aluminum oxide.

[0109] Thus, by reasonably setting the materials of the gate layer 110 and the resistive switching layer 120 of the self-selection memory, the materials of the gate layer 110 and the resistive switching layer 120 are matched, so that the self-selection memory has a self-rectification effect, which can effectively suppress the leakage current generated by the self-selection memory, which is conducive to further reducing the size of the self-selection memory, and making the self-selection memory into an integrated array, which is conducive to expanding the application fields and application scenarios of the self-selection memory.

[0110] In one embodiment, reference Figure 1The first functional layer 30 is a gate layer 110, and the second functional layer 50 is a resistive switching layer 120. The material of the first functional layer 30 includes niobium oxide, the material of the intermediate layer 40 includes amorphous carbon, and the material of the second functional layer 50 includes tantalum oxide.

[0111] In one embodiment, reference Figure 2 The first functional layer 30 is a resistive switching layer 120, and the second functional layer 50 is a gate layer 110. The material of the first functional layer 30 includes tantalum oxide, the material of the intermediate layer 40 includes amorphous carbon, and the material of the second functional layer 50 includes niobium oxide.

[0112] In one embodiment, when forming the gate layer 110, a thermally conductive material may be doped into the gate layer 110 to improve the thermal conductivity of the gate layer 110, thereby improving the temperature rise rate and thermal stability of the gate layer 110.

[0113] For example, the thermally conductive material may include one or more of Al, Cu, Au, Ti, etc. A doping process is preferred.

[0114] For example, thermally conductive materials can be doped into the gate layer 110 using ion implantation (IMP) and / or co-sputtering (Co-Sputter).

[0115] In one embodiment, after the intermediate layer 40 is formed on the first functional layer 30, the method further includes:

[0116] Step S60: Ionize the first gas to generate plasma, and use plasma to treat the intermediate layer 40.

[0117] It can ionize N2 to generate nitrogen plasma, improve the film density of the gate layer 110, and help reduce the thermal budget for forming the gate layer 110, thereby reducing production costs and improving production efficiency.

[0118] According to an exemplary embodiment, this embodiment provides an electronic device, including a self-selecting memory based on the 1S1R structure of the above embodiments, or a self-selecting memory based on the 1S1R structure fabricated by the fabrication method of the self-selecting memory based on the 1S1R structure of the above embodiments.

[0119] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0120] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A self-selecting memory based on a 1S1R structure, characterized in that, It includes a first functional layer, an intermediate layer and a second functional layer stacked sequentially on a substrate. The second functional layer is separated from the first functional layer through the intermediate layer. The first functional layer is connected to a first electrode and the second functional layer is connected to a second electrode. One of the first functional layer and the second functional layer is a gate layer, and the other is a resistive switching layer; the thermal conductivity of the intermediate layer is less than that of the resistive switching layer; the thermal conductivity of the intermediate layer near the resistive switching layer is less than that of the intermediate layer near the gate layer. The thermal conductivity of the gate layer is 0.3 W / m·K to 1.5 W / m·K; the thermal conductivity of the resistive switching layer is 2.2 W / m·K to 5 W / m·K. The thermal conductivity of the intermediate layer is 0.2 W / m·K - 2 W / m·K; the electrical conductivity of the intermediate layer is 10. -7 S / m-10 -2 S / m; The material of the intermediate layer includes at least one of amorphous carbon, silicon carbide, tellurium carbide, tellurium carbon sulfide, molybdenum sulfide, tungsten sulfide, molybdenum telluride, indium gallium zinc oxide, indium aluminum zinc oxide, tin-doped indium oxide, manganese telluride, tungsten telluride, and zinc-doped indium oxide.

2. The self-selecting memory based on the 1S1R structure according to claim 1, characterized in that, The thermal conductivity of the intermediate layer decreases from the gated layer toward the resistive switching layer.

3. The self-selecting memory based on the 1S1R structure according to claim 1, characterized in that, The material of the gate layer includes at least one of niobium oxide, vanadium oxide, iron oxide, neodymium nickel oxide, samarium nickel oxide, lanthanum cobalt oxide, gadolinium cobalt oxide, germanium telluride, aluminum telluride, boron telluride, germanium selenide, germanium sulfide, and antimony telluride; The resistive switching layer is made of at least one of the following materials: tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, silicon oxide, magnesium oxide, aluminum nitride, germanium antimony tellurium, scandium antimony tellurium, indium silver antimony tellurium, germanium antimony, germanium telluride, antimony telluride, copper sulfide, germanium sulfide, germanium selenide, zinc sulfide, aluminum borate, strontium titanate, zirconium titanate, barium titanate, hafnium zirconium oxide, and hafnium aluminum oxide.

4. The self-selecting memory based on the 1S1R structure according to any one of claims 1-3, characterized in that, The first functional layer is a gating layer, and the second functional layer is a resistive switching layer; The first functional layer is made of niobium oxide, the intermediate layer is made of amorphous carbon, and the second functional layer is made of tantalum oxide.

5. The self-selecting memory based on the 1S1R structure according to any one of claims 1-3, characterized in that, The first functional layer is a resistive switching layer, and the second functional layer is a gating layer; The first functional layer is made of tantalum oxide, the intermediate layer is made of amorphous carbon, and the second functional layer is made of niobium oxide.

6. A method for fabricating a self-selection memory based on a 1S1R structure, characterized in that, Includes the following steps: A substrate is provided, and a first electrode is formed on the substrate; A first functional layer is formed on the first electrode; An intermediate layer is formed on the first functional layer; A second functional layer is formed on the intermediate layer, and the second functional layer is separated from the first functional layer by the intermediate layer; one of the first functional layer and the second functional layer is a gate layer, and the other is a resistive switching layer; the thermal conductivity of the intermediate layer is less than the thermal conductivity of the resistive switching layer; the thermal conductivity of the intermediate layer near the resistive switching layer is less than the thermal conductivity of the intermediate layer near the gate layer. A second electrode is formed on the second functional layer; The thermal conductivity of the gate layer is 0.3 W / m·K to 1.5 W / m·K; the thermal conductivity of the resistive switching layer is 2.2 W / m·K to 5 W / m·K. The thermal conductivity of the intermediate layer is 0.2 W / m·K - 2 W / m·K; the electrical conductivity of the intermediate layer is 10. -7 S / m-10 -2 S / m; The material of the intermediate layer includes at least one of amorphous carbon, silicon carbide, tellurium carbide, tellurium carbon sulfide, molybdenum sulfide, tungsten sulfide, molybdenum telluride, indium gallium zinc oxide, indium aluminum zinc oxide, tin-doped indium oxide, manganese telluride, tungsten telluride, and zinc-doped indium oxide.

7. The method for fabricating a self-selective memory based on a 1S1R structure according to claim 6, characterized in that, The thermal conductivity of the intermediate layer decreases from the gated layer toward the resistive switching layer.

8. The method for fabricating a self-selective memory based on a 1S1R structure according to claim 6, characterized in that, The material of the gate layer includes at least one of niobium oxide, vanadium oxide, iron oxide, neodymium nickel oxide, samarium nickel oxide, lanthanum cobalt oxide, gadolinium cobalt oxide, germanium telluride, aluminum telluride, boron telluride, germanium selenide, germanium sulfide, and antimony telluride; The resistive switching layer is made of at least one of the following materials: tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, silicon oxide, magnesium oxide, aluminum nitride, germanium antimony tellurium, scandium antimony tellurium, indium silver antimony tellurium, germanium antimony, germanium telluride, antimony telluride, copper sulfide, germanium sulfide, germanium selenide, zinc sulfide, aluminum borate, strontium titanate, zirconium titanate, barium titanate, hafnium zirconium oxide, and hafnium aluminum oxide.

9. The method for fabricating a self-selective memory based on a 1S1R structure according to any one of claims 6-8, characterized in that, After forming the intermediate layer on the first functional layer, it also includes: The first gas is ionized to generate plasma, which is then used to treat the intermediate layer.

10. The method for fabricating a self-selective memory based on a 1S1R structure according to any one of claims 6-8, characterized in that, The first functional layer is a gated layer, and the second functional layer is a resistive switching layer; the material of the first functional layer includes niobium oxide, the material of the intermediate layer includes amorphous carbon, and the material of the second functional layer includes tantalum oxide.

11. The method for fabricating a self-selective memory based on a 1S1R structure according to any one of claims 6-8, characterized in that, The first functional layer is a resistive switching layer, and the second functional layer is a gated layer; the material of the first functional layer includes tantalum oxide, the material of the intermediate layer includes amorphous carbon, and the material of the second functional layer includes niobium oxide.

12. An electronic device, characterized in that, The invention includes a self-selecting memory based on a 1S1R structure as described in any one of claims 1-5, or a self-selecting memory based on a 1S1R structure fabricated by a method described in any one of claims 6-11.

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