Balanced throughput for replicating partitions in presence of inoperable arithmetic units

Abstract

An apparatus and method for efficiently managing balanced performance between replica partitions of an integrated circuit despite functional loss due to manufacturing defects. The processing unit comprises at least two copy partitions, each copy partition being assigned to an operating parameter of a respective power domain. The partition includes a plurality of computing units. The computing unit includes a plurality of execution channels. Due to various types of manufacturing defects, one or more of the partitions of the processing unit have less than a predetermined number of operational computing units. To balance the throughput of the plurality of partitions, the power manager generates a static scaling factor and a dynamic scaling factor based on at least a corresponding number of operational computing units. Using these scaling factors, the power manager adjusts operating parameters of the power domain relative to each other for the partitions.

Description

Background Art

[0001] Description of Related Technology

[0002] Both planar transistors and non-planar transistors are manufactured for use in integrated circuits within semiconductor chips. There are multiple options for placing processing circuits in a system package to integrate multiple types of integrated circuits. Some examples are system on chip (SOC), multi-chip module (MCM) and system-in-package (SiP). Mobile devices, desktop systems and servers use these packages. Regardless of the choice of system package, during the assembly of the semiconductor chip, one or more semiconductor dies (or dies) are placed on a single substrate or package, and these dies are susceptible to electrostatic discharge events. Electrostatic discharge events provide unintentional charges that can cause current density to flow through metal lines and transistors (devices) exceeding safety thresholds. Therefore, one or more processing units and other functional blocks on the die may fail, which reduces manufacturing yield.

[0003] One or more processing units and other functional blocks on a die may also fail during the semiconductor manufacturing process steps prior to packaging and the die. These failures are caused by manufacturing defects that inadvertently cause open circuits, stuck-at faults, etc. Any defects are discovered during die testing and during subsequent testing of the package. In some cases, defects occur in functional blocks that are replicated in partitions of a processing unit. Although a particular functional block is no longer operational and the overall throughput of the processing unit is reduced, the partitions in the processing unit remain operational.

[0004] By using fuse arrays and fuse read-only memories (ROMs), access to specific functional blocks that lack defects within a partition can be restricted on the die. The semiconductor die is still used, but the resulting package is placed in a category or statistical pile with reduced performance. However, for a die using a highly parallel data microarchitecture, a partition that uses all of its duplicate functional blocks completes its task before another partition that uses a smaller number of duplicate functional blocks. There is an imbalance in throughput between partitions, which further reduces performance. In some cases, although it is still available, due to the high demand in the market for running certain applications at a relatively high minimum performance level, a package with reduced performance is unacceptable.

[0005] In view of the foregoing, apparatus and methods are desired for managing balanced performance between replicated partitions of an integrated circuit despite loss of functionality due to manufacturing defects. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a generalized block diagram of an apparatus for managing balanced performance between replicated partitions of an integrated circuit despite loss of functionality due to manufacturing defects.

[0007] Figure 2 is a generalized block diagram of a method for managing balanced performance between replicated partitions of an integrated circuit despite loss of functionality due to manufacturing defects.

[0008] Figure 3 is a generalized block diagram of a power manager that manages balanced performance among replicated partitions of an integrated circuit despite loss of functionality due to manufacturing defects.

[0009] Figure 4 is a generalized block diagram of a method for managing balanced performance between replicated partitions of an integrated circuit despite loss of functionality due to manufacturing defects.

[0010] Figure 5 It is a generalized block diagram of a computing system.

[0011] Although the present invention is susceptible to various modifications and alternative forms, specific implementations are shown by way of example in the drawings and described in detail herein. However, it should be understood that the drawings and detailed description thereof are not intended to limit the invention to the specific forms disclosed, but on the contrary, the invention is to cover all modifications, equivalents and alternatives within the scope of the invention defined by the appended claims. DETAILED DESCRIPTION

[0012] In the following description, many specific details are set forth to provide a thorough understanding of the present invention. However, it will be appreciated by those of ordinary skill in the art that the present invention may be practiced without these specific details. In some cases, well-known circuits, structures, and techniques are not shown in detail to avoid obscuring the present invention. In addition, it should be understood that for simplicity and clarity of illustration, the elements shown in the figures are not necessarily drawn to scale. For example, the size of some elements is enlarged relative to other elements.

[0013] It is contemplated that despite the loss of functionality due to manufacturing defects, an apparatus and method for efficiently managing balanced performance between replicated partitions of an integrated circuit is provided. In some specific implementations, a processing unit includes at least two replicated partitions. As used herein, the term "replicated" is used to refer to the same instantiation of hardware (such as a circuit) of a specific functional block, a specific type of unit, or another specific type of circuit. For example, a "replicated partition" refers to two or more partitions, each of which is the same instantiation of a specific type of partition. In a specific implementation, each of the partitions is a shader engine of a graphics processing unit (GPU). Similarly, a "replicated computing unit" refers to two or more computing units (or computing units), each of which is an instantiation of a specific type of computing unit. In a specific implementation, a specific type of computing unit includes multiple execution channels that support a parallel data microarchitecture for processing workloads. Therefore, in a specific implementation, each replicated (instantiated) partition is a shader engine of a GPU, and each of the shader engines includes multiple replicated (instantiated) computing units.

[0014] In various specific implementations, the processing unit includes at least two replicated (instantiated) partitions, each partition being assigned to operating parameters of a corresponding power domain. Each of the power domains includes operating parameters, such as at least an operating supply voltage and an operating clock frequency. Each of the power domains also includes control signals for enabling and disabling connections to clock generation circuits and power supply references. Thus, at least two replicated partitions do not share the same connections to the same clock generation circuits and power supply references.

[0015] Due to various types of manufacturing defects, one or more of the partitions of the processing unit has less than a predetermined number of operational computing units. As used herein, an operational computing unit is also referred to as a functional computing unit. Due to the absence of the manufacturing defects, the operational computing unit (functional computing unit) is able to successfully process the task. In one example, the processing unit includes four partitions, each having eight computing units. However, due to a manufacturing defect, one of the four partitions has seven operational computing units instead of the predetermined number of eight operational computing units. In order to balance the throughput of the multiple partitions, the power manager generates a corresponding static scaling factor for each of the multiple partitions relative to each other.

[0016] The power manager generates a static scaling factor for each of the multiple replicated partitions based on the corresponding number of operational computing units. The power manager generates the static scaling factor in a manner that balances the throughput of the multiple replicated partitions, each of which uses a corresponding power domain. In other words, for a partition in the multiple partitions, the power manager uses the corresponding static scaling factor to select separate operating parameters for the partition. The difference in throughput between any two partitions is less than a threshold. By using at least the static scaling factor, a first partition having 6 of 8 running computing units achieves almost the same throughput as a second partition having 8 of 8 running computing units. The difference in throughput between the first partition and the second partition is less than a throughput threshold. Therefore, the difference in completion time of tasks of the first partition and the second partition is less than a time threshold. The static scaling factor of the first partition having 6 of 8 running computing units causes the power manager to select operating parameters of the first power domain that provide a higher transistor switching speed than the operating parameters of the second power domain used by the second partition having 8 of 8 running computing units.

[0017] When the tasks of the workload are executed by multiple replicated partitions in a lockstep format, and one of the partitions is completed much later than the other partitions, the total throughput of the processing unit is reduced. When the tasks of the workload use checkpoints to synchronize the execution on multiple replicated partitions, and one of the partitions is completed much later than the other partitions, the total throughput of the processing unit is reduced. For example, when the first partition has 7 of 8 running computing units, rather than 8 of 8 running computing units, and each partition uses the same power domain, the first partition is completed later than the other partitions with 8 of 8 running computing units. Therefore, the total throughput of the processing unit is reduced. However, when the first partition uses the operating parameters of the independent power domain as described above, the reliance on lockstep execution or synchronization checkpoints does not reduce the performance of the processing unit because the first partition has the same or almost the same completion time. The difference between the completion time of the tasks of the first partition and the other partitions is less than the time threshold. In addition, the power manager can dynamically adjust the operating parameters of the independent power domain at the granularity of the partition rather than at the granularity of the entire processing unit. This dynamic adjustment is based on performance indicators monitored during the processing of the workload. For example, the power manager receives performance indicators from performance counters distributed on the computing units. Further details of efficiently managing balanced performance between replicated partitions of an integrated circuit despite loss of functionality due to manufacturing defects are provided in the following discussion.

[0018] refer to Figure 1, a generalized block diagram of an apparatus 100 for managing balanced performance between replicated partitions of an integrated circuit despite loss of functionality due to manufacturing defects is shown. In the illustrated implementation, the apparatus 100 includes a power manager 170 and at least two partitions, such as partition 110 and partition 150, each of which is assigned to a corresponding power domain by the power manager 170. Each of the power domains includes at least operating parameters, such as at least an operating supply voltage and an operating clock frequency. Each of the power domains also includes control signals for enabling and disabling connections to clock generation circuits and power supply references. Although only two partitions 110 and 150 are shown, other numbers of partitions used by the apparatus 100 are possible and expected, and the number is based on design requirements. For ease of illustration, other components of the apparatus 100 are not shown. For example, a memory controller, one or more input / output (I / O) interface units, an interrupt controller, one or more phase-locked loops (PLLs) or other clock generation circuits, a primary or multi-level cache memory subsystem, and various other functional blocks are not shown, but they may be used by the apparatus 100.

[0019] In some implementations, the functionality of the device 100 is included as a component on a single die (such as a single integrated circuit). In a specific implementation, the functionality of the device 100 is included as one of a plurality of dies on a system on a chip (SOC). In various implementations, the device 100 is used in a desktop computer, a portable computer, a mobile device, a server, a peripheral device, etc. The device 100 is capable of communicating with an external general-purpose central processing unit (CPU), which includes circuits for executing instructions according to a predefined general-purpose instruction set architecture (ISA). The device 100 is also capable of communicating with various other external circuits, such as one or more of a digital signal processor (DSP), a display controller, various application-specific integrated circuits (ASICs), a multimedia engine, etc.

[0020] If the device 100 operates above (below) a threshold limit, the power manager 170 reduces (or increases) power consumption. In some implementations, the power manager 170 selects a corresponding power management state for each of the partitions 110 and 150. As used herein, a "power management state" is one of a plurality of "P-states" or one of a plurality of power performance states, which includes a set of operating parameters, such as an operating clock frequency and an operating supply voltage. In various implementations, the device 100 uses a parallel data microarchitecture that provides high instruction throughput for computationally intensive tasks. In one implementation, the device 100 uses one or more processor cores with a relatively wide single instruction multiple data (SIMD) microarchitecture to achieve high throughput in highly data parallel applications. Each object is processed independently of other objects, but using the same sequence of operations.

[0021] In one implementation, device 100 is a graphics processing unit (GPU). Modern GPUs are efficient for data parallel computations found in application loops, such as in applications for manipulating and displaying computer graphics, molecular dynamics simulations, financial computing, and the like. The highly parallel structure of a GPU makes it more efficient than a general-purpose central processing unit (CPU) for a range of complex algorithms. In various implementations, partition 150 includes the same components as partition 110, because partitions 110 and 150 are replicated partitions within device 100. In a specific implementation, each of partitions 110 and 150 is a shader engine of a GPU, and each of the shader engines includes a plurality of computational units 140A-140C for processing data parallel applications such as graphics shader tasks.

[0022] Each computing unit in computing unit 140A-140C includes multiple channels 142. Each channel is also referred to as a SIMD unit or SIMD channel. In some specific implementations, channel 142 operates in a lockstep manner. In other specific implementations, channel 142 uses a synchronous checkpoint for processing tasks. In various specific implementations, the data flow in each channel in channel 142 is pipelined. Pipeline registers are used to store intermediate results, and the circuit system for arithmetic logic unit (ALU) performs integer arithmetic, floating point arithmetic, Boolean logic operations, branch condition comparisons, etc. For ease of explanation, these components are not shown. Each of the computing units in a given row across channel 142 is the same computing unit. Each of these computing units operates the same instruction, but different data is associated with different threads.

[0023] As shown, each of the computing units 140A-140C also includes a corresponding register file 144, a local data storage 146, and a local cache memory 148. In some specific implementations, the local data storage 146 is shared between the channels 142 in each of the computing units 140A-140C. In other specific implementations, the local data storage is shared between the computing units 140A-140C. Therefore, one or more of the channels 142 in the computing unit 140A can share result data with one or more channels 142 in the computing unit 140B based on the operating mode. The high parallelism provided by the hardware of the computing units 140A-140C is used to render multiple pixels at the same time, but it is also able to process multiple data elements of science, medicine, finance, encryption / decryption and other operations at the same time. For example, the partition 110 is used for real-time data processing, such as rendering multiple pixels, image blending, pixel shading, vertex shading and geometry shading. The circuit of the controller (not shown) receives the task via the memory controller (not shown). In some implementations, the controller is a command processor of the GPU, and the tasks are sequences of commands (instructions) of function calls of an application.

[0024] Partition 110 receives operating parameters 160 of a first power domain from power manager 170, and computing units 140A-140C process tasks using operating parameters 160. Partition 150 receives operating parameters 164 of a second power domain from power manager 170. It is possible and contemplated that the first power domain and the second power domain are different power domains. Thus, power manager 170 is able to dynamically adjust power domains at the granularity of partitions (such as partitions 110 and 150) rather than at the granularity of the entire device 100. In some implementations, power manager 170 is an integrated controller as shown, while in other implementations, power manager 170 is an external unit.

[0025] Due to various types of manufacturing defects, one or more of partitions 110 and 150 have less than a predetermined number of operational computing units, such as computing units 140A-140C. In one example, each of partitions 110 and 150 includes eight computing units. However, due to the manufacturing defect, partition 110 has seven operational computing units instead of the predetermined number of eight operational computing units. In order to balance the throughput of partitions 110 and 150, power manager 170 generates a corresponding static scaling factor for each of the plurality of partitions relative to each other.

[0026] The power manager 170 generates a static scaling factor for each partition 110 and 150 based on the corresponding number of operational computing units. For a partition 110 having seven operational computing units of eight computing units 140A-140C, the power manager 170 generates a static scaling factor for the partition 110, the static scaling factor indicating that the partition 110 uses a set of operating parameters of a power domain that provides a higher transistor switching speed than another set of operating parameters of another power domain used by the partition 150 having eight operational computing units of eight computing units 140A-140C. Thus, the difference between the completion time of the partition 110 and the partition 150 is reduced, especially when compared to a case where each of the partitions 110 and 150 uses the same set of operating parameters of the same power domain. Although the partition 110 has a smaller number of operational computing units of the computing units 140A-140C than the partition 150, when the partition 110 uses the operating parameters of the power domain based on the static scaling factor, the reliance on lockstep execution or synchronization checkpoints does not degrade the performance of the device 100. For example, partitions 110 and 150 have the same or nearly the same completion time. The difference between the completion times of the tasks of partitions 110 and 150 is less than the time threshold.

[0027] In addition, the power manager 170 can dynamically adjust the power domains of the partitions 110 and 150 based on the corresponding number of operational computing units and the performance indicators 162 and 166 monitored during the processing of the workload. For example, the power manager 170 receives the performance indicators 162 and 166 from performance counters (such as performance counters 149) distributed across the computing units 140A-140C and other components (not shown) of the partitions 110 and 150. In some specific implementations, the collected data includes a predetermined sampled signal. The switching of the sampled signal indicates the amount of capacitance switched. Examples of selected signals to be sampled include clock gate enable signals, bus driver enable signals, mismatches in content addressable memory (CAM), CAM word line (WL) drivers, etc. The collected data may also include data indicating the performance or throughput of each of the partitions 110 and 150, such as the number of retired instructions, the number of cache accesses, the monitoring delay of cache accesses, the number of cache hits, the count of issued instructions or issued threads, etc.

[0028] In a specific implementation, the power manager 170 collects data to characterize the power consumption and throughput of the partitions 110 and 150 during a specific sampling interval. When one or more of the estimated power consumption and the estimated throughput of the partitions 110 and 150 change significantly, the power manager 170 updates the operating parameters 160 and 164 of the independent power domains of the partitions 110 and 150. The operating parameters 160 and 164 may also be referred to as operating parameter groups 160 and 164. The updated values ​​of the operating parameters 160 and 164 enable the partitions 110 and 150 to achieve almost the same throughput. The difference in throughput between the partitions 110 and 150 is less than a throughput threshold. Therefore, the difference between the completion times of the tasks of the partitions 110 and 150 is less than a time threshold.

[0029] refer to Figure 2 , shows a generalized block diagram of a method 200 for efficiently managing balanced performance between replicated partitions of an integrated circuit despite loss of functionality due to manufacturing defects. For discussion purposes, the steps in this specific implementation (and Figure 4 However, in other implementations, some steps occur in a different order than shown, some steps are performed simultaneously, some steps are combined with other steps, and some steps do not exist.

[0030] The parallel data processing unit includes at least two partitions, each of which is assigned to a corresponding power domain. Each of the power domains includes operating parameters, such as at least an operating power supply voltage and an operating clock frequency. In some specific implementations, the circuit of the first partition includes a plurality of computing units, each of which has a plurality of execution channels. Hardware (such as a circuit) of a power manager of the parallel data processing unit determines the expected same throughput level for each of the plurality of partitions during the execution of the workload (block 202). The power manager determines the number of computing units that are operable in each of the plurality of partitions (block 204). As used herein, a computing unit is considered "operable" when it is able to process a task. An "operable" computing unit is also referred to as an "operable" computing unit or a "functional" computing unit. In contrast, an "inoperable" computing unit (also referred to as a "non-functional" computing unit) cannot process a task. For example, an inoperable computing unit has one or more manufacturing defects that make it unable to process a task. In a specific implementation, by identifying which computing units are inoperable computing units, a fuse array or a fuse ROM is accessed to determine the number of computing units that are operable in each of the plurality of partitions.

[0031] The power manager generates a static scaling factor for each of the plurality of partitions relative to each other based on the corresponding number of operational computing units (block 206). The power manager converts the scaling factor into specific operating parameters for the independent power domains of the plurality of partitions for achieving a balanced throughput level (block 208). The power manager assigns the operating parameters to the plurality of partitions (block 210). The parallel data processing units process the workload using the assigned operating parameters (block 212).

[0032] refer to Figure 3 , shows a generalized block diagram of a power manager 300 that manages balanced performance between replicated partitions of an integrated circuit despite loss of functionality due to manufacturing defects. As shown, the power manager 300 includes a table 310 and a control unit 330. The control unit 330 includes a plurality of components 332-338 for generating operating parameters 350 that are sent to a plurality of power domains of a plurality of replicated partitions. The table 310 includes a plurality of table entries (or entries), each entry storing information in a plurality of fields (such as at least fields 312-318).

[0033] Table 310 is implemented with one of a flip-flop circuit, a random access memory (RAM), a content addressable memory (CAM), or others. Although specific information is shown as being stored in fields 312-318 in a specific sequential order, in other specific implementations, different orders are used and different quantities and types of information are stored. As shown, field 312 stores a partition identifier (ID) specifying a specific partition in a plurality of partitions used in a parallel data processing unit. In a specific implementation, a partition is a shader engine in a plurality of shader engines of a GPU. Field 314 stores a plurality of computing units in the identified partition. In a specific implementation, the information is found in a fuse read-only memory (ROM) set after the manufacture and testing of the semiconductor package.

[0034] Field 316 stores the static scaling factor of the identified partition. The static scaling factor is set based on the corresponding number of operational computing units in the plurality of partitions. Therefore, the value of the static scaling factor is a relational value. In various specific implementations, the value is set during or shortly after the startup operation and does not change from this value. Field 318 stores the dynamic scaling factor of the identified partition. The value is based on the corresponding number of operational computing units in the plurality of partitions and the measured performance indicators. The dynamic scaling factor changes over time. For example, the dynamic scaling factor is updated based on one or more of determining that a specific time interval has passed, determining that a new workload is allocated for execution, determining by a power manager that the throughput level has changed by more than a threshold amount, etc. In some specific implementations, a corresponding weight value is associated with each of the static scaling factor and the dynamic scaling factor. In a specific implementation, each of the plurality of replicated partitions has its own pair of weight values. It is possible and conceivable that these weight values ​​change over time, and which of the static scaling factor and the dynamic scaling factor has a greater impact on the selection of the operating parameters also changes over time.

[0035] Control unit 330 receives usage measurements 320 representing at least activity level measurements or data from multiple partitions. An example is a sampled signal as previously described. Control unit 330 receives sensor input 322 representing measured temperature values ​​from analog or digital thermal sensors placed throughout the die. Control unit 330 receives performance indicators 324 representing values ​​read from performance counters placed throughout the multiple partitions. Control unit 330 also receives data from table 310, and control unit 330 is able to update information stored in table 310.

[0036] The power reporting unit 332 calculates a power value based on the usage measurement 320. The power reporting unit 332 also calculates a leakage power value included in the total power value. The leakage power value depends on the calculated temperature. In some specific implementations, the power reporting unit 332 associates the total number of power credits of the parallel data processing unit with the thermal design power (TDP) value of the processing unit. The power reporting unit 332 assigns a separate given number of power credits to each of the partitions of the parallel data processing unit. The sum of the associated power credits is equal to the total number of power credits of the tube core 202. The power reporting unit 332 adjusts the number of power credits of each external partition in the external partition over time.

[0037] The calculated temperature is determined by the temperature reporting unit 334 and utilizes the worst case ambient temperature value. In a specific implementation, when the temperature measured by the sensor is significantly different from the calculated temperature, the calculated power value is not changed. The balanced throughput manager 336 (or manager 336) has a balanced throughput manager 174 ( Figure 1) function. For example, manager 336 determines dynamic scaling factors stored in field 318 of table 310 for the plurality of partitions. Manager 336 calculates these dynamic scaling factors based on the corresponding number of operational computing units and performance indicators 324. Manager 336 determines when a performance bottleneck occurs in any of the plurality of partitions during execution of the workload and recalculates the dynamic scaling factors to be used by operational parameter selector 338 to generate new power domains for the plurality of partitions.

[0038] Operational parameter selector 338 receives temperature-related values ​​from temperature reporting unit 334, receives calculated power values ​​and both the current and updated number of power credits for each partition from power reporting unit 332, and receives updated dynamic scaling factors from manager 336. Based on these inputs, operational parameter selector 338 generates updated operational parameters for the independent power domains for the plurality of partitions. The updated operational parameters include operational parameters 350. Although operational parameter selector 338 receives various input values, performance indicator 324, the predetermined static scaling factor stored in field 314, and the updated dynamic scaling factor from manager 336 are the values ​​that adjust operational parameters 350 so that the partitions have approximately equal throughput.

[0039] refer to Figure 4 , a generalized block diagram of a method 400 for efficiently managing balanced performance between replicated partitions of an integrated circuit despite loss of functionality due to manufacturing defects is shown. Multiple partitions of a parallel data processing unit process a workload using corresponding assigned operating parameters of independent power domains (block 402). In a specific implementation, each of the partitions is a shader engine of a graphics processing unit (GPU), and each of the shader engines includes multiple compute units. Hardware (such as circuitry) of a power manager of the parallel data processing unit monitors performance indicators of the multiple partitions (block 404). For example, when a particular sampling interval has passed, values ​​stored in performance counters located on the multiple partitions are read and reported to the power manager.

[0040] If the power manager determines that the conditions for updating the operating parameters of the independent power domains are not met (the "No" branch of conditional block 406), the plurality of partitions of the parallel data processing unit continue to process the workload using the corresponding assigned operating parameters of the independent power domains (block 408). In some implementations, the conditions for updating the power domains include the power manager determining that one or more of the specified time intervals have passed, and the power manager determining that the throughput level has changed by more than a threshold amount.

[0041] If the power manager determines that the conditions for updating the operating parameters of the independent power domains have been met (the "yes" branch of conditional block 406), the power manager determines a dynamic scaling factor for each of the plurality of partitions based on the corresponding number of operational computing units and the monitored performance indicator (block 410). Based on at least the dynamic scaling factor, the power manager distributes the updated operating parameters of the independent power domains to the plurality of partitions (block 412). In some implementations, when updating the operating parameters of the independent power domains, the power manager additionally uses a static scaling factor and weight values ​​corresponding to both the static scaling factor and the dynamic scaling factor. The power manager resets one or more performance indicator measurements that meet the reset conditions (block 414).

[0042] Now turn to Figure 5 , shows a specific implementation of a computing system 500. As shown, the computing system 500 includes a processing unit 510, a memory 520, and a parallel data processing unit 530. In some specific implementations, the functions of the computing system 500 are included as components on a single die (such as a single integrated circuit). In other specific implementations, the functions of the computing system 500 are included as multiple dies on a system on a chip (SOC). In various specific implementations, the computing system 500 is used for desktop computers, portable computers, mobile devices, servers, peripheral devices, etc.

[0043] The circuitry of processing unit 510 processes instructions of a predetermined algorithm. The processing includes fetching instructions and data, decoding the instructions, executing the instructions, and storing the results. In one implementation, processing unit 510 uses one or more processor cores having circuitry for executing instructions according to a predefined general instruction set. In various implementations, processing unit 510 is a central processing unit (CPU). Parallel data processing unit 530 includes apparatus 100 ( Figure 1 ) circuits and functions.

[0044] Balanced throughput manager 532 (or manager 532) has a balanced throughput manager 174 ( Figure 1 ) and the balanced throughput manager 336 ( Figure 3 ) functions. For example, manager 532 determines dynamic scaling factors for dynamically updating power domains of multiple partitions of parallel data processing unit 530. Manager 532 calculates these dynamic scaling factors based on corresponding numbers of operational computing units of the multiple partitions and performance indicators monitored over time during processing of one or more workloads. Manager 532 determines when a performance bottleneck occurs in any of the multiple partitions during execution of the workload, and recalculates dynamic scaling factors for generating new power domains for the multiple partitions.

[0045] In various implementations, threads are scheduled on one of the processing unit 510 and the parallel data processing unit 530 in a manner that each thread has the highest instruction throughput based at least in part on the runtime hardware resources of the processing unit 510 and the parallel data processing unit 530. In some implementations, some threads are associated with general algorithms scheduled on the processing unit 510, while other threads are associated with parallel data operation intensive algorithms (such as video graphics rendering algorithms) scheduled on the parallel data processing unit 530. Applications using these algorithms store copies on the memory 520.

[0046] Some threads that are not video graphics rendering algorithms still exhibit parallel data and intensive throughput. These threads have instructions that can operate on relatively large numbers of different data elements simultaneously. Examples of these threads are threads used for scientific, medical, financial, and encryption / decryption calculations. The high parallelism provided by the hardware of the parallel data processing unit 530 and used to render multiple pixels simultaneously can also process multiple data elements of scientific, medical, financial, encryption / decryption and other operations simultaneously.

[0047] Function calls within the application are converted into commands by a given application programming interface (API). The processing unit 510 sends the converted commands to the memory 520 for storage in the circular buffer 522. The commands are placed in a group called a command group. In some specific implementations, the processing units 510 and 530 use a producer-consumer relationship, which is also called a client-server relationship. The processing unit 510 writes the command to the circular buffer 522. Then, the parallel data processing unit 530 reads the command from the circular buffer 522, processes the command, and writes the result data to the buffer 524. The processing unit 510 is configured to update the write pointer of the circular buffer 522 and provide the size of each command group. The parallel data processing unit 530 updates the read pointer of the circular buffer 522 and indicates the entry in the circular buffer 522 that the next read operation will use.

[0048] It should be noted that one or more of the above-mentioned specific implementations include software. In such specific implementations, the program instructions of the implementation method and / or mechanism are transmitted or stored on a computer-readable medium. Many types of media configured to store program instructions are available and include hard disks, floppy disks, CD-ROMs, DVDs, flash memory, programmable ROMs (PROMs), random access memories (RAMs) and various other forms of volatile or non-volatile storage devices. Generally speaking, a computer-accessible storage medium includes any storage medium that can be accessed by a computer during use to provide instructions and / or data to a computer. For example, a computer-accessible storage medium includes such as magnetic or optical media, such as storage media such as disks (fixed or removable), tapes, CD-ROMs or DVD-ROMs, CD-Rs, CD-RWs, DVD-Rs, DVD-RWs or blue-rays. The storage medium also includes volatile or non-volatile storage media, such as RAM (e.g., synchronous dynamic RAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM, low power DDR (LPDDR2, etc.) SDRAM, Rambus DRAM (RDRAM), static RAM (SRAM), etc.), ROM accessible via a peripheral device interface (such as a universal serial bus (USB) interface, etc.), flash memory, non-volatile memory (e.g., flash memory). The storage medium includes micro-electromechanical systems (MEMS), and storage media accessible via communication media such as a network and / or a wireless link.

[0049] In addition, in various specific implementations, the program instructions include a behavioral level description or a register transfer level (RTL) description of the hardware functionality in a high-level programming language such as C or a design language (HDL) such as Verilog, VHDL, or a database format such as GDS II stream format (GDSII). In some cases, the description is read by a synthesis tool, which synthesizes the description to produce a netlist including a list of gates from a synthesis library. The netlist includes a set of gates, which also represents the functionality of the hardware comprising the system. The netlist is then placed and threaded to produce a data set describing the geometry to be applied to the mask. The mask is then used in various semiconductor manufacturing steps to produce a semiconductor circuit or circuit corresponding to the system. Alternatively, the instructions on the computer-accessible storage medium are a netlist (with or without a synthesis library) or a data set as desired. In addition, the instructions are used by the computer-accessible storage medium such as and Mentor Such vendors' hardware-based types of emulators are used for emulation purposes.

[0050] Although the above embodiments have been described in considerable detail, numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to encompass all such variations and modifications.

Claims

1. A device, comprising: Multiple partitions, each partition includes multiple replication computing units; A power manager, the power manager being configured to: assigning a first set of operating parameters to the first partition of the plurality of partitions based at least in part on the number of replicated computing units capable of operation in the first partition; as well as A second set of operating parameters is assigned to the second partition of the plurality of partitions based at least in part on the number of replica computing units capable of operation in the second partition.

2. The device according to claim 1, wherein: The first partition and the second partition are configured to process tasks of a workload using the first set of operating parameters and the second set of operating parameters, respectively.

3. The device according to claim 2, wherein: Based on the first set of operating parameters and the second set of operating parameters, a difference between a throughput of the first partition and a throughput of the second partition is less than a threshold.

4. The device according to claim 2, wherein: Each of the plurality of partitions is configured to process the workload using a parallel data micro-architecture.

5. The device according to claim 2, wherein: In response to determining that conditions for updating operating parameters of the plurality of partitions have been met, the power manager is further configured to assign updated values ​​to the first set of operating parameters and the second set of operating parameters.

6. The device according to claim 5, wherein: The updated values ​​of the first set of operating parameters and the second set of operating parameters are based at least in part on the power manager receiving a plurality of performance indicators monitored during processing of the workload.

7. The device according to claim 5, wherein: The conditions for updating the power domain include one or more of the following: determining, by the power manager, that a time interval has elapsed; and A determination is made by the power manager that a throughput of the plurality of partitions has changed by more than a threshold amount.

8. A method comprising: Tasks are processed by multiple partitions, each of which includes multiple replicated computing units; assigning, by the power manager, a first set of operating parameters to a first partition of the plurality of partitions based at least in part on a number of replica computing units capable of operation in the first partition; as well as A second set of operating parameters is assigned, by the power manager, to a second partition of the plurality of partitions based at least in part on a number of replica computing units capable of operation in the second partition. 9 . The method of claim 8 , further comprising processing tasks of the workload by the first partition and the second partition using the first set of operating parameters and the second set of operating parameters, respectively.

10. The method according to claim 9, wherein: Based on the first set of operating parameters and the second set of operating parameters, a difference between a throughput of the first partition and a throughput of the second partition is less than a threshold.

11. The method of claim 9, further comprising processing the workload using a parallel data micro-architecture by each of the plurality of partitions.

12. The method according to claim 9, wherein: In response to determining that conditions for updating operating parameters of the plurality of partitions have been met, the method further includes assigning, by the power manager, updated values ​​for the first set of operating parameters and the second set of operating parameters.

13. The method according to claim 12, wherein: The updated values ​​of the first set of operating parameters and the second set of operating parameters are based at least in part on the power manager receiving a plurality of performance indicators monitored during processing of the workload.

14. The method according to claim 12, wherein: The conditions for updating the power domain include one or more of the following: determining, by the power manager, that a time interval has elapsed; and A determination is made by the power manager that a throughput of the plurality of partitions has changed by more than a threshold amount.

15. A computing system, comprising: a memory configured to store one or more applications of the workload; and A processing unit, the processing unit comprising: Multiple partitions, each partition includes multiple replication computing units; A power manager, the power manager being configured to: assigning a first set of operating parameters to the first partition of the plurality of partitions based at least in part on the number of replica computing units capable of operation in the first partition; and A second set of operating parameters is assigned to the second partition of the plurality of partitions based at least in part on the number of replica computing units capable of operation in the second partition.

16. The computing system of claim 15, wherein: The first partition and the second partition are configured to process tasks of a workload using the first set of operating parameters and the second set of operating parameters, respectively.

17. The computing system of claim 16, wherein: Based on the first set of operating parameters and the second set of operating parameters, a difference between a throughput of the first partition and a throughput of the second partition is less than a threshold.

18. The computing system of claim 16, wherein: Each of the plurality of partitions is configured to process the workload using a parallel data micro-architecture.

19. The computing system of claim 16, wherein: In response to determining that conditions for updating operating parameters of the plurality of partitions have been met, the power manager is further configured to assign updated values ​​to the first set of operating parameters and the second set of operating parameters.

20. The computing system of claim 19, wherein: The updated values ​​of the first set of operating parameters and the second set of operating parameters are based at least in part on the power manager receiving a plurality of performance indicators monitored during processing of the workload.

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