Display device and electronic apparatus

Abstract

Provided is a display device having a laminated structure provided with: a light-emitting element, the brightness of which is changed according to a supplied current; a current source transistor electrically connected to the current source and the light emitting element and supplying a current corresponding to the signal voltage to the light emitting element; a capacitor unit connected to a control terminal of the current source transistor; and a selection transistor connected to a control terminal of the current source transistor and supplying a signal voltage to the current source transistor via the capacitance unit, the stacked structure including: a semiconductor substrate to which the current source transistor is provided; a wiring layer laminated on the semiconductor substrate and including a selection transistor including a thin film transistor; and a light emitting element laminated on the wiring layer.

Description

Technical Field

[0001] The present disclosure relates to a display device and an electronic device. Background Art

[0002] Recently, a display device using an electroluminescent (EL) element as a light-emitting element has been developed. For example, such a display device includes a plurality of light-emitting elements, including a lower electrode, a light-emitting layer stacked on the lower electrode, and an upper electrode stacked on the light-emitting layer. In addition to the above-mentioned light-emitting elements, the display device also includes a driving circuit for driving the light-emitting elements.

[0003] Reference List

[0004] Patent Literature

[0005] Patent Document 1: JP 2020-154323 A

[0006] Patent Document 2: JP 2021-9401A Summary of the invention

[0007] Technical issues

[0008] As light-emitting elements are miniaturized, display devices are required to reduce the layout size of the drive circuit in consideration of the withstand voltage and characteristic variation range required for various transistors included in the drive circuit. However, there is a limitation in reducing the size of the transistors included in the drive circuit while satisfying the desired withstand voltage, and therefore there is also a limitation in reducing the layout size of the drive circuit.

[0009] The present disclosure provides a display device and an electronic device capable of reducing the layout size of a driving circuit.

[0010] Solution to the problem

[0011] According to the present disclosure, a display device is provided, including a stacked structure, which includes: a light-emitting element, the brightness of the light-emitting element varies according to the current provided; a current source transistor, which is electrically connected to the current source and the light-emitting element, and the current source transistor provides a current corresponding to a signal voltage to the light-emitting element; a capacitor, which is connected to a control terminal of the current source transistor; and a selection transistor, which is connected to the control terminal of the current source transistor, and the selection transistor provides a signal voltage to the current source transistor via the capacitor, wherein the stacked structure includes: a semiconductor substrate, on which the current source transistor is arranged; a wiring layer, which is stacked on the semiconductor substrate, and the wiring layer includes a capacitor and a selection transistor formed by a thin film transistor; and the light-emitting element is stacked on the wiring layer.

[0012] According to the present disclosure, an electronic device equipped with a display device is also provided, the display device includes a stacked structure, the stacked structure includes: a light-emitting element, the brightness of the light-emitting element changes according to the current provided; a current source transistor, which is electrically connected to the current source and the light-emitting element, and the current source transistor provides a current corresponding to the signal voltage to the light-emitting element; a capacitor, which is connected to the control terminal of the current source transistor; and a selection transistor, which is connected to the control terminal of the current source transistor, and the selection transistor provides the signal voltage to the current source transistor via the capacitor, wherein the stacked structure includes: a semiconductor substrate, on which the current source transistor is arranged; a wiring layer, which is stacked on the semiconductor substrate, and the wiring layer includes a capacitor formed by a thin film transistor and a selection transistor; and the light-emitting element is stacked on the wiring layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a schematic diagram illustrating an example of an overall configuration of a display device according to an embodiment of the present disclosure.

[0014] Figure 2 is a circuit diagram showing an embodiment of a pixel of a display device according to an embodiment of the present disclosure.

[0015] Figure 3 is a schematic diagram showing an example of a cross-sectional configuration of a pixel according to the first embodiment of the present disclosure (part 1 ).

[0016] Figure 4 1 is a schematic diagram showing an example of a planar configuration of a pixel according to the first embodiment of the present disclosure (Part 1).

[0017] Figure 5 is a schematic diagram showing an example of a planar configuration of a pixel according to the first embodiment of the present disclosure (part 2).

[0018] Figure 6 is a schematic diagram showing an example of a cross-sectional configuration of a pixel according to the first embodiment of the present disclosure (part 2).

[0019] Figure 7 is a circuit diagram showing a modified example of the pixel according to the first embodiment of the present disclosure.

[0020] Figure 8 : is a schematic diagram showing a modification example of the cross-sectional configuration of the pixel according to the first embodiment of the present disclosure.

[0021] Fig. 9 : is a schematic diagram showing an example of the overall configuration of a display device according to a second embodiment of the present disclosure.

[0022] Fig.10is a circuit diagram showing an example of a pixel of a display device according to a second embodiment of the present disclosure.

[0023] Fig.11 is a schematic diagram illustrating a cross-sectional configuration of a pixel according to a second embodiment of the present disclosure.

[0024] Fig.12 is a schematic diagram showing an example of a planar configuration of a pixel according to the second embodiment of the present disclosure (part 1).

[0025] Fig.13 is a schematic diagram showing an example of a planar configuration of a pixel according to the second embodiment of the present disclosure (Part 2).

[0026] Fig.14 is a schematic diagram showing an example of a planar configuration of a pixel according to the second embodiment of the present disclosure (Part 3).

[0027] Fig.15 is a circuit diagram (Part 1 ) showing an example of a pixel of a display device 10 according to a third embodiment of the present disclosure.

[0028] Fig.16 is a circuit diagram (Part 2 ) showing an example of a pixel of the display device 10 according to the third embodiment of the present disclosure.

[0029] Fig.17 is a circuit diagram (Part 3) showing an example of a pixel of the display device 10 according to the third embodiment of the present disclosure.

[0030] Fig.18A is a cross-sectional view (Part 1) for describing a method for manufacturing a pixel according to a fourth embodiment of the present disclosure.

[0031] Fig.18B is a cross-sectional view (Part 2) for describing a method for manufacturing a pixel according to a fourth embodiment of the present disclosure.

[0032] Fig. 18C is a cross-sectional view (Part 3) for describing a method for manufacturing a pixel according to a fourth embodiment of the present disclosure.

[0033] Fig.18D is a cross-sectional view (Part 4) for describing a method for producing a pixel according to a fourth embodiment of the present disclosure.

[0034] Fig.18E is a cross-sectional view (Part 5 ) for describing a method for manufacturing a pixel according to a fourth embodiment of the present disclosure.

[0035] Fig.18Fis a schematic diagram for describing a method for manufacturing a pixel according to a fourth embodiment of the present disclosure (Part 6).

[0036] Figure 18G is a schematic diagram for describing a method for preparing a pixel according to a fourth embodiment of the present invention (Part 7).

[0037] Fig.18H is a schematic diagram for describing a method for manufacturing a pixel according to a fourth embodiment of the present disclosure (Part 8).

[0038] Fig.19A is a front view showing an example of the appearance of a digital camera.

[0039] Fig.19B is a rear view showing an example of the appearance of a digital still camera.

[0040] Fig. 20 is the external view of the head mounted display.

[0041] Fig.21 is the external view of the see-through head mounted display.

[0042] Fig. 22 is an external view of the television set.

[0043] Fig.23 is an external view of a smart phone.

[0044] Fig.24A is a diagram showing the interior configuration of a car (part 1).

[0045] Fig. 24B is a diagram showing the interior configuration of a car (part 2). DETAILED DESCRIPTION

[0046] Hereinafter, preferred embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In this specification and the accompanying drawings, components having substantially the same functional configuration are represented by the same reference numerals, and redundant descriptions are omitted. In this specification and the accompanying drawings, multiple components having substantially the same or similar functional configurations can be distinguished by appending different alphabets after the same reference symbol. When it is not particularly necessary to distinguish each of the multiple components having substantially the same or similar functional configurations, only the same reference numerals are assigned.

[0047] The drawings referred to in the following description are drawings for describing the embodiments of the present disclosure and facilitating understanding thereof, and for the sake of clarity, the shapes, sizes, ratios, etc. shown in the drawings may be different from the actual ones. The display device shown in the drawings may be appropriately modified in design in consideration of the following description and known technologies.

[0048] In the following description, “electrically connected” means that a plurality of elements are connected directly or indirectly via another element.

[0049] In the following description, “shared” means that one element (eg, a diffusion region, etc.) is commonly used in other elements (eg, a transistor, etc.) different from each other.

[0050] The description will be given in the following order.

[0051] 1. Display device according to an embodiment of the present disclosure

[0052] 1.1 Display Device

[0053] 1.2 px

[0054] 2. Background of the embodiments of the present disclosure

[0055] 3. First Implementation

[0056] 3.1 Detailed structure

[0057] 3.2 Variations

[0058] 4. Second Implementation

[0059] 4.1 Display Device

[0060] 4.2 px

[0061] 4.3 Stacking Structures

[0062] 5. Third Implementation

[0063] 6. Fourth Implementation

[0064] 7. Conclusion

[0065] 8. Application Examples

[0066] 9. Supplement

[0067] <<1. Display device according to an embodiment of the present disclosure>>

[0068] <1.1 Display Device>

[0069] Reference Figure 1 An example of the overall configuration of the display device 10 used as a display device or a lighting device according to an embodiment of the present disclosure is described. Figure 1 is a schematic diagram showing an example of the overall configuration of the display device 10 according to an embodiment of the present disclosure.

[0070] The display device 10 is, for example, a device in which light-emitting elements such as organic light-emitting diodes (OLEDs) or micro OLEDs are arranged. Such a display device 10 can be applied to, for example, a display device for virtual reality (VR), mixed reality (MR) or augmented reality (AR), an electronic viewfinder (EVF), a small projector, etc.

[0071] In an embodiment of the present disclosure, the light-emitting element may be a self-luminous element and may be a current-driven electro-optical element. In addition to OLED, examples of current-driven electro-optical elements include inorganic EL elements, LED elements, and semiconductor laser elements. An organic EL display device using OLED as a light-emitting element has the following characteristics. Specifically, in an organic EL display device, because OLED is a self-luminous element, the organic EL display device has high visibility of an image compared to a liquid crystal display device of the same flat display device, and in addition, it does not require an illumination component such as a backlight, and therefore it is easy to reduce weight and thickness. In addition, since the response speed of OLED is as high as several microseconds, afterimages do not occur in the organic EL display device during the display of moving images.

[0072] Here, as an example, a case where an active matrix type organic EL display device using, for example, an OLED as a light-emitting element, which is a current-driven light-emitting element whose light-emitting brightness changes according to the value of the current flowing through the device, will be described. Hereinafter, the "active matrix type organic EL display device" is simply referred to as a "display device".

[0073] like Figure 1 As shown, the display device 10 includes a pixel array unit 30, in which a plurality of pixels 20 including light emitting elements are two-dimensionally arranged in a matrix form, and a driving circuit unit disposed around the pixel array unit 30. For example, the driving circuit unit includes a writing scanning unit 40, a driving scanning unit 50, and a signal output unit 70 installed on the same display panel 80 on which the pixel array unit 30 is installed, and drives each pixel 20 of the pixel array unit 30.

[0074] Here, when the display device 10 is compatible with color display, one pixel (unit pixel / pixel) used as a unit for forming a color image includes a plurality of sub-pixels. At this time, each sub-pixel corresponds to Figure 1. More specifically, in a display device 10 compatible with color display, one pixel 20 may include, for example, three sub-pixels of a sub-pixel emitting red light, a sub-pixel emitting green light, and a sub-pixel emitting blue light, and may include, for example, one, two or more sub-pixels without particular limitation. One pixel 20 is not limited to a combination of sub-pixels of three primary colors, such as red, green, and blue, and one pixel 20 may be configured by further adding sub-pixels of one color or a plurality of colors to the sub-pixels of the three primary colors. More specifically, in the display device 10, for example, one pixel 20 may be configured by adding a sub-pixel emitting white light to increase brightness, or one pixel 20 may be configured by adding at least one sub-pixel emitting complementary color light to expand a color reproduction range.

[0075] In the pixel array unit 30, the scanning lines 31 (311 to 31 m ) and drive line 32 (321 to 32 m ) is wired for each pixel row along the row direction (array direction of the pixels 20 of the pixel row / horizontal direction) with respect to the array of the pixels 20 of m rows and n columns. In addition, the signal lines 34 (341 to 34 n ) Each pixel column is wired along the column direction (array direction of the pixels 20 of the pixel column / vertical direction) relative to the array of the pixels 20 of m rows and n columns.

[0076] Scan lines 311 to 31 m Each of the drive lines 321 to 32 is electrically connected to an output terminal of a corresponding row of the write scanning unit 40. m Each of the signal lines 341 to 342 is electrically connected to an output terminal of a corresponding row of the drive scanning unit 50. n Each of them is electrically connected to an output terminal of a corresponding column of the signal output unit 70 .

[0077] The write scanning unit 40 includes a shift register circuit, etc. When the signal voltage of the video signal is written into each pixel 20 of the pixel array unit 30, the write scanning unit 40 writes the scanning signal WS (WS1 to WS2). m ) are sequentially supplied to the scanning lines 31 (311 to 31 m ), and thus each pixel 20 of the pixel array unit 30 can be sequentially scanned row by row.

[0078] Similar to the write scanning unit 40, the drive scanning unit 50 includes a shift register circuit, etc. The drive scanning unit 50 can transmit the light emitting control signal DS (DS1 to DS2) to the write scanning unit 40 in synchronization with the line sequential scanning. m ) is provided to the driving lines 32 (321 to 32 m) to control the light emission / non-light emission (extinction) of the pixel 20. In the embodiment of the present disclosure, the display device 10 does not need to be provided with the drive scanning unit 50 capable of controlling the light emission / non-light emission (extinction) of the pixel 20.

[0079] The signal output unit 70 selectively outputs a signal voltage (hereinafter, simply referred to as "signal voltage") Vsig of a video signal corresponding to brightness information provided from a signal supply source (not shown) and a reference voltage Vofs. Here, the reference voltage Vofs is a voltage corresponding to a voltage serving as a reference of the signal voltage Vsig of the video signal or a voltage in the vicinity thereof.

[0080] The signal voltage Vsig / reference voltage Vofs alternately output from the signal output unit 70 is written into each pixel 20 of the pixel array unit 30 via the signal line 34 (341 to 34n) in units of pixel rows selected by line sequential scanning of the write scanning unit 40. That is, the signal output unit 70 can write the signal voltage Vsig in units of pixel rows (lines).

[0081] <1.2 pixels>

[0082] Next, we will describe Figure 1 2 is a circuit configuration of a pixel (pixel circuit) 20 of a display device 10 according to an embodiment of the present disclosure shown in FIG. Figure 2 is a circuit diagram showing an example of a pixel 20 of a display device 10 according to an embodiment of the present disclosure. Figure 2 The circuit configuration shown in corresponds to the pixel 20 of the display device 10 without providing the drive scanning unit 50 capable of controlling light emission / non-light emission (light extinction) of the pixel 20.

[0083] In the embodiments of the present disclosure, Figure 2 As shown, the pixel 20 includes a light emitting element EL and a driving circuit for driving the light emitting element EL. The light emitting element EL is an example of a current-driven electro-optical element in which the light emission brightness changes according to the current value flowing through the device, and is made of, for example, an OLED. The cathode of the light emitting element EL is electrically connected to, for example, a node V for generating a current. SS .

[0084] The drive circuit includes a drive transistor Tr1, a write transistor Tr2, and a capacitor C1. The anode of the light emitting element EL is electrically connected to the drive transistor Tr1, and is capable of emitting light when a current flows through the drive transistor Tr1. The drive transistor Tr1 and the write transistor Tr2 are, for example, field effect transistors (FETs). More specifically, the drive transistor Tr1 is formed by a P-channel transistor, and the write transistor Tr2 is formed by an N-channel transistor.

[0085] Specifically, Figure 2As shown, the source and drain of the write transistor Tr2 are electrically connected to the signal line (Vsig) and the gate (control terminal) of the drive transistor Tr1, respectively, and the gate of the write transistor Tr2 is electrically connected to the scan line (WS). The write transistor Tr2 can write the signal voltage Vsig provided from the signal output unit 70 into the gate node of the drive transistor Tr1 by sampling. The expression "write" here means applying a signal voltage to the gate node and maintaining the potential of the gate node at a potential based on the signal voltage.

[0086] The source and drain of the driving transistor Tr1 are electrically connected to the power supply voltage V DD and an anode of the light emitting element EL. The driving transistor Tr1 can drive the light emitting element EL by causing a driving current corresponding to a holding voltage of the capacitor C1 described later to flow through the light emitting element EL.

[0087] The capacitor C1 is connected between the gate and source of the drive transistor Tr1 , and it can hold the signal voltage Vsig sampled and written by the write transistor Tr2 .

[0088] exist Figure 2 The circuit configuration example shown in FIG. 1 is an example of the circuit configuration of the pixel 20 according to the embodiment of the present disclosure, and the circuit configuration of the pixel 20 according to the embodiment of the present disclosure is not limited to the circuit configuration of the pixel 20 shown in FIG. Figure 2 The circuit configuration shown in FIG.

[0089] <<2. Background of the present disclosure>>

[0090] Next, before describing the embodiments of the present disclosure, the background in which the inventors of the present invention created the embodiments of the present disclosure will be described.

[0091] As the light-emitting element EL is miniaturized, the display device 10 is required to reduce the layout size of the drive circuit in consideration of the withstand voltage and characteristic variation range required for various transistors in the drive circuit of the pixel 20. However, there is a limitation in reducing the size of the transistor included in the drive circuit while satisfying the desired withstand voltage, and therefore there is also a limitation in reducing the layout size of the mobile circuit. Specifically, when an OLED is used as the light-emitting element EL, a high voltage is applied to drive the OLED, and the drive transistor Tr1 requires a high withstand voltage, so there is a limitation in reducing the layout size of the drive transistor Tr1.

[0092] Therefore, in view of this situation, the inventors of the present disclosure have created the embodiment of the present disclosure described below. In the embodiment of the present disclosure, by configuring some transistors included in the driving circuit as thin film transistors (TFTs) provided in the wiring layer stacked on the semiconductor substrate, the layout size of the driving circuit can be reduced, and the display device 10 can be miniaturized eventually. Hereinafter, the details of this embodiment of the present disclosure will be described in order.

[0093] <<3. First embodiment>>

[0094] <3.1 Detailed structure>

[0095] First, refer to Figure 3 and Figure 4 A detailed structure of the pixel 20 according to the first embodiment of the present disclosure is described. Figure 3 2 is a schematic diagram showing an example of a cross-sectional configuration of the pixel 20 according to the present embodiment, and specifically corresponds to a cross section formed when the stacked structural body of the pixel 20 is cut along the stacking direction. Figure 4 is a schematic diagram showing an example of a planar configuration of the pixel 20 according to the present embodiment, and specifically corresponds to when Figure 3 Each line segment (line AA', line B-B', line CC', line D-D', line EE' and line F-F') shown in FIG. 2 forms a cross section when the pixel 20 is cut. Figure 3 and Figure 4 The pixel 20 shown in the configuration has the above Figure 2 The circuit configuration shown in .

[0096] like Figure 3 As shown, the pixel 20 according to the present embodiment has a stacked structure including a semiconductor substrate 100 made of, for example, n-type conductive type silicon, a wiring layer 200 stacked on the semiconductor substrate 100, and a light-emitting element EL arranged on the wiring layer 200. As described above, the light-emitting element EL is a current-driven electro-optical element, in which the light-emitting brightness changes according to the current value flowing through the device. In the present embodiment, the semiconductor substrate 100 and the wiring layer 200 include a driving circuit for driving the light-emitting element EL. In addition, the wiring layer 200 includes an insulating film 202 (for example, formed of a silicon oxide film (SiO2), a silicon nitride film (Si3N4), etc.), a wiring 204 (for example, formed of a metal film of tungsten (W) or the like) and a via 206 (for example, formed of a metal film of tungsten or the like) in addition to the elements described below.

[0097] As reference Figure 2As described, the drive circuit includes a drive transistor (current source transistor) Tr1, a write transistor (select transistor) Tr2, and a capacitor C1. In the following, the stacked structure of the pixel 20 will be described, but the description will be from the position located Figure 3 Starting from the bottom semiconductor substrate 100 .

[0098] The driving transistor Tr1 is a field effect transistor provided on the semiconductor substrate 100, and is specifically a P-channel transistor. Figure 3 As shown, the driving transistor Tr1 includes a gate electrode 104, which is provided on a region having an n-type conductivity type via an insulating film 202, and the n-type conductivity type serves as a channel of the driving transistor Tr1 provided in the semiconductor substrate 100 (see Figure 4 ' portion in FIG. 1 ). In addition, the drive transistor Tr1 is provided in the semiconductor substrate 100 so as to sandwich a region having an n-type conductivity type serving as a channel, and has a source / drain including a diffusion region 102 containing an impurity having a p-type conductivity type. In the present embodiment, providing the drive transistor Tr1 on the semiconductor substrate 100 in this manner makes it possible to stabilize the characteristics of the drive transistor Tr1 and obtain a transistor having a high withstand voltage. In the present embodiment, the drive transistor Tr1 may be an N-channel transistor, although the details will be described later.

[0099] The source and drain of the driving transistor Tr1 are electrically connected to a power source (V DD ) and the anode 310 of the light emitting element EL. In addition, the gate electrode 104 of the drive transistor Tr1 is electrically connected to the electrode 210 of the capacitor C1 described later and the source or drain of the write transistor Tr2 through the via 206.

[0100] Furthermore, the driving transistor Tr1 is separated from other elements by a shallow trench isolation (STI) 106 provided in the semiconductor substrate 100 .

[0101] like Figure 3 As shown, the capacitor C1 is provided in the wiring layer 200 stacked above the driving transistor Tr1. Specifically, the capacitor C1 has a metal-insulator-metal (MIM) structure including a pair of electrodes (metal films) 210 and 212 sandwiching an insulating film 214 from the upper and lower directions along the stacking direction of the stacked structure (see Figure 4 In this embodiment, the insulating film 214 may be formed of, for example, a silicon nitride film, or an oxide film such as a silicon oxide film or a hafnium oxide film (HfO2) containing at least one element selected from silicon (Si), hafnium (Hf), zirconium oxide (Zr), tantalum (Ta), and yttrium (Y).

[0102] Furthermore, one electrode 210 of the capacitor C1 is electrically connected to the source or drain of the drive transistor Tr1 via the via 206. The other electrode 212 of the capacitor C1 is electrically connected to the source or drain of the drive transistor Tr1 and the source or drain of the write transistor Tr2 described later via the via 206.

[0103] In addition, Figure 3 In the structure shown, the write transistor Tr2 is provided above the capacitor C1 in the wiring layer 200. In other words, Figure 3 In the wiring layer 200 shown in FIG. 1 , the capacitor C1 is provided on the semiconductor substrate 100 side, and the write transistor Tr2 is provided on the light emitting element EL side. Although the details will be described later, the present embodiment is not limited to this structure, and the write transistor Tr2 may be provided on the semiconductor substrate 100 side, and the capacitor C1 may be provided above the write transistor Tr2C.

[0104] In this embodiment, if Figure 3 As shown, the write transistor Tr2 is configured as a thin film transistor (TFT) provided in the wiring layer 200, and it may be specifically an N-channel transistor. In this embodiment, the write transistor Tr2 may be a P-channel transistor, and the details will be described later.

[0105] Specifically, the write transistor Tr2 includes a thin film semiconductor layer 220 provided in the wiring layer 200, and a gate electrode 224 in contact with the thin film semiconductor layer 220 via the insulating film 202 (see Figure 4 The thin film semiconductor layer 220 may be formed of, for example, a silicon film, or may be formed of an oxide film containing at least one element selected from the group consisting of aluminum (Al), indium (In), gallium (Ga), and zinc (Zn), etc. More specifically, the thin film semiconductor layer 220 may be formed of polycrystalline silicon (poly-Si), indium oxide (In2O3), indium gallium zinc oxide (In and Ga are added to ZnO4 as dopants, such as IGZO), aluminum zinc oxide (Al is added to ZnO as a dopant, such as AZO), indium zinc oxide (In is added to ZnO as a dopant, such as IZO), etc. In the present embodiment, since an oxide film such as IGZO has an extremely small leakage current, leakage in the write transistor Tr2 can be suppressed, and therefore the thin film semiconductor layer 220 is preferably formed of an oxide film such as IGZO. With this configuration, according to the present embodiment, an increase in power consumption of the display device 10 can be suppressed.

[0106] In addition, Figure 3, the write transistor Tr2 is configured as a bottom gate structure in which the gate electrode 224 is located below the thin film semiconductor layer 220. However, the present embodiment is not limited to this configuration, and the write transistor Tr2 may have a top gate structure in which the gate electrode 224 is located above the thin film semiconductor layer 220 or a double gate structure having two gate electrodes 224.

[0107] The source or drain of the write transistor Tr2 is electrically connected to the wiring 204 (signal voltage Vsig) provided in the wiring layer 200 through the via 206 (see Figure 4 In addition, the gate electrode 224 of the write transistor Tr2 is electrically connected to the wiring 204 connected to the scanning line (WS) through the through hole 206 (see Figure 4 Part C-C' in.

[0108] like Figure 3 As shown, the light emitting element EL is provided on the wiring layer 200. Specifically, the light emitting element EL mainly includes an anode electrode 310 (see Figure 4 ), a light-emitting layer 314 stacked on the anode electrode 310 and emitting light, and a cathode electrode 312 stacked on the light-emitting layer 314 and transmitting light from the light-emitting layer 314.

[0109] The anode electrode 310 may also function as a reflective layer, and is preferably formed of a metal film having as high a reflectivity as possible and a large work function to improve light extraction efficiency. Examples of such metal films include metal films containing at least one of a single substance and an alloy of metal elements such as chromium (Cr), gold (Au), platinum (Pt), nickel (Ni), copper (Cu), molybdenum (Mo), titanium (Ti), tantalum (Ta), aluminum, magnesium (Mg), iron (Fe), tungsten, and silver (Ag).

[0110] The light-emitting layer 314 disposed on the anode electrode 310 is made of an organic material or an inorganic material, and is, for example, a layer capable of emitting white light. The light-emitting layer 314 may include a hole injection layer (not shown) and a hole transport layer (not shown) disposed adjacent to the anode electrode 310, and an electron transport layer (not shown) disposed adjacent to the cathode electrode 312. In other words, the light-emitting layer 314 may have a structure in which a hole injection layer, a hole transport layer, a light-emitting layer 314, and an electron transport layer (not shown) are stacked from the anode electrode 310 side. The hole injection layer serves as a layer for improving the hole injection efficiency into the light-emitting layer 314, and the layer also serves as a buffer layer for suppressing leakage. The hole transport layer serves as a layer for improving the hole transport efficiency to the light-emitting layer 314. In the light-emitting layer 314, the generation of an electric field causes the recombination of electrons and holes, which can generate light. The electron transport layer serves as a layer for improving the electron transport efficiency to the light-emitting layer 314. In addition, the light-emitting layer 314 may have an electron injection layer (not shown) between the electron transport layer and the cathode electrode 312. The electron injection layer is used as a layer to improve the electron injection efficiency. In this embodiment, the configuration of the light-emitting layer 314 is not limited to the above configuration, and layers other than the hole injection layer and the light-emitting layer 314 are provided as needed.

[0111] In this embodiment, the light-emitting layer 314 is not limited to a layer that emits white light, and the layer may be a layer that emits red light (e.g., visible light having a wavelength of approximately 640nm to 770nm), blue light (e.g., visible light having a wavelength of approximately 430nm to 490nm), or green light (e.g., visible light having a wavelength of approximately 490nm to 550nm).

[0112] In addition, the cathode electrode 312 provided on the light emitting layer 314 is a transparent electrode having transparency to the light generated in the light emitting layer 314, and in the following description, the transparent electrode also includes a semi-transparent electrode. The cathode electrode 312 may be formed of a metal film or an oxide film containing at least one of a simple substance and an alloy of metal elements such as aluminum, magnesium, calcium (Ca), sodium (Na), silver, indium, and zinc.

[0113] In this way, in the present embodiment, the drive transistor Tr1 included in the drive circuit is provided in the semiconductor substrate 100, and the write transistor Tr2 is provided as a thin film transistor (TFT) in the wiring layer 200 stacked on the semiconductor substrate 100. With this configuration, according to the present embodiment, the layout size of the drive circuit can be reduced, and ultimately, the display device 10 can be miniaturized.

[0114] In this embodiment, by forming the thin film semiconductor layer 220 of the write transistor Tr2 as a thin film transistor (TFT) using an oxide film such as IGZO, leakage in the write transistor Tr2 can be suppressed, and as a result, an increase in power consumption of the display device 10 can be suppressed.

[0115] In this embodiment, the pixel 20 is not limited to Figure 3 and Figure 4 The configuration shown in , and may have, for example, the configuration described below.

[0116] For example, in the present embodiment, the capacitor C1 is not limited to the MIM structure including a pair of electrodes 210 and 212 sandwiching the insulating film 214 from the upper and lower directions along the stacking direction of the stacked structure. Figure 5 As shown in part B-BCH and part CC' in FIG. 1 (which is a schematic diagram showing an example of a planar configuration of the pixel 20 according to the present embodiment), the capacitor C1 may have a MIM structure (or metal-oxide-metal: MOM structure) including a pair of electrodes sandwiching an insulating film (oxide film) from a planar direction perpendicular to the stacking direction of the stacked structure. In other words, the capacitor C1 may include a pair of electrodes arranged on the same plane and facing each other, with an insulating film interposed between the pair of electrodes. By doing so, in the present embodiment, the number of layers stacked along the stacking direction constituting the capacitor C1 can be reduced, and therefore, the pixel 20 can be thinned. Figure 5 Corresponding to when Figure 3 The portion formed by cutting the pixel 20 at each line segment (line AA', line BB', line CC', line DD', line EE' and line FF') shown in FIG. Figure 5 The pixel 20 shown in the configuration has the above Figure 2 The circuit configuration shown in .

[0117] For example, in this embodiment, if Figure 6 As shown in Figure 6 is a schematic diagram showing an example of a cross-sectional configuration of the pixel 20 according to the present embodiment, the write transistor Tr2 may be provided on the semiconductor substrate 100 side, and the capacitor C1 may be provided above the write transistor Tr2C. Figure 6 Corresponds to a portion formed when the stacked structural body of the pixels 20 is cut along the stacking direction.

[0118] <3.2 Modifications>

[0119] In this embodiment, as described above, the driving transistor Tr1 may be an N-channel transistor. Figure 7 and Figure 8 Describe this deformation. Figure 72 is a circuit diagram showing a modified example of the pixel 20a of the present embodiment. Figure 8 is a schematic diagram showing a modified example of the cross-sectional configuration of the pixel 20a according to the present embodiment. Specifically, Figure 8 Corresponds to a cross section formed when the stacked structural body of the pixels 20 a is cut along the stacking direction.

[0120] When the driving transistor Tr1 is an N-channel transistor, the circuit configuration of the pixel 20a may be as follows: Figure 7 Specifically, the drain and source of the driving transistor Tr1 are electrically connected to the power supply voltage V DD and the anode of the light emitting element EL. The source and drain of the write transistor Tr2 are electrically connected to the signal line (Vsig) and the gate (control terminal) of the drive transistor Tr1, respectively, and the gate of the write transistor Tr2 is electrically connected to the scan line (WS). In addition, the capacitor C1 is connected between the gate of the drive transistor Tr1 and the ground (GND).

[0121] In this case, the cross-sectional configuration of the pixel 20a has the following Figure 8 Specifically, the source and drain of the driving transistor Tr1 are electrically connected to the power supply (V DD ) and the anode 310 of the light emitting element EL. In addition, the gate electrode 104 of the driving transistor Tr1 is electrically connected to one electrode (not shown) of the capacitor C1 described later and the source or drain of the write transistor Tr2 through the via 206. One electrode 210 of the capacitor C1 is electrically connected to the wiring 204 connected to the ground line (GND) through the via 206.

[0122] As described above, also in the present modification, the drive transistor Tr1 included in the drive circuit is provided in the semiconductor substrate 100, and the write transistor Tr2 is provided as a thin film transistor (TFT) in the wiring layer 200 stacked on the semiconductor substrate 100. With this configuration, according to the modification, the layout size of the drive circuit can be reduced, and ultimately the display device 10 can be miniaturized.

[0123] <<4. Second Embodiment>>

[0124] <4.1 Display Device>

[0125] In the display device 10 according to the first embodiment of the present disclosure, by switching the driving transistor Tr1 to off, the current supply to the light emitting element EL is cut off, and thus, the light emission of the light emitting element EL is suppressed, and a black grayscale can be displayed. However, when the driving transistor Tr1 is switched to an off state, current leaks between the source and the drain of the driving transistor Tr1, and the contrast when the black grayscale is displayed may be reduced. Therefore, in order to avoid a decrease in the contrast when the black grayscale is displayed, the inventors of the present invention have studied the following display device 10a. In the following, reference will be made to Fig. 9 The configuration of such a display device 10a is described. Fig. 9 : is a schematic diagram showing an example of the overall configuration of the display device 10 a according to the present embodiment.

[0126] like Fig. 9 As shown, the display device 10a includes: a pixel array unit 30 in which a plurality of pixels 20 including light emitting elements EL are arranged two-dimensionally in a matrix; and a driving circuit unit arranged around the pixel array unit 30. In the same manner as in the above-described display device 10a, for example, the driving circuit unit includes a writing scanning unit 40 and a signal output unit 70 mounted on the same display panel 80 on which the pixel array unit 30 is mounted, and unlike the display device 10a, the driving circuit unit further includes a first driving scanning unit 50 and a second driving scanning unit 60. In the driving unit of the display device 10a according to the present embodiment, the first driving scanning unit 50 corresponds to the driving scanning unit 50 in the driving unit of the display device 10.

[0127] The driving unit of the display device 10a according to the present embodiment is different from the driving unit of the display device 10 in that the driving unit includes a second drive scanning unit 60, and a second drive line 33 (331 to 33m) is wired for each pixel row along the row direction. Each of the second drive lines 331 to 33m is connected to the output terminal of the corresponding row of the second drive scanning unit 60.

[0128] Similar to the write scanning unit 40, the second drive scanning unit 60 includes a shift register circuit, etc. The second drive scanning unit 60 provides the drive signal AZ (AZ1 to AZm) to the second drive line 33 (331 to 33m) in synchronization with the line sequential scanning by the write scanning unit 40, and thus can control the pixel 20 not to emit light in the non-light-emitting period.

[0129] <4.2 pixels>

[0130] Next, we will describe Fig. 9 The pixel 20b of the display device 10a according to the present embodiment is shown. Fig.102 is a circuit diagram showing an example of a pixel 20b of the display device 10a according to the present embodiment. Description of the same points as those of the pixel 20 according to the above-described first embodiment will be omitted here.

[0131] In the embodiments of the present disclosure, Fig.10 As shown, the pixel 20b includes a light emitting element EL and a driving circuit for driving the light emitting element EL. The cathode of the light emitting element EL is electrically connected to a node VSS, for example, for generating a current. The driving circuit includes a driving transistor Tr1, a writing transistor Tr2, a light emitting control transistor Tr3, a switching transistor Tr4, and capacitors C1 and C2. The driving transistor Tr1 and the light emitting control transistor Tr3 are P-channel transistors, and the writing transistor Tr2 and the switching transistor Tr4 are N-channel transistors.

[0132] exist Fig.10 In the circuit configuration shown in FIG. 1 , the write transistor Tr2 can write to the gate node (gate electrode) of the drive transistor Tr1 by sampling the signal voltage Vsig provided from the signal output unit 70. The light emission control transistor Tr3 is connected to the power supply voltage V DD between the power node of and the source node (source electrode) of the driving transistor Tr1, and controls light emission / non-light emission of the light emitting element EL under driving performed by the light emission control signal DS.

[0133] The switching transistor Tr4 is connected between the drain node (drain) of the driving transistor Tr1 and the current discharge target node VSS, and performs control so that the light-emitting element EL does not emit light during the non-light-emitting period of the light-emitting element EL driven by the driving signal AZ. That is, when the switching transistor Tr4 enters the on state, the switching transistor Tr4 is used to form a path that bypasses the light-emitting element EL (that is, performs bypassing) so that the current is not supplied to the light-emitting element EL. By doing so, even when the current between the source and the drain of the driving transistor Tr1 is leaked when the driving transistor Tr1 is switched to the off state, the switching transistor Tr4 enters the on state, and thus it is possible to prevent the current from being supplied to the light-emitting element EL. As a result, according to the present embodiment, the reduction in contrast at the time of black grayscale display can be suppressed.

[0134] The capacitor C1 is connected between the gate node and the source node of the drive transistor Tr1, and holds the signal voltage Vsig sampled and written by the write transistor Tr2. The drive transistor Tr1 drives the light emitting element EL by causing a drive current corresponding to the held voltage of the capacitor C1 to flow through the light emitting element EL.

[0135] The capacitor C2 is connected between the source node of the driving transistor Tr1 and a node of a fixed potential (eg, a power supply voltage V DDThe capacitor C2 has the following actions: suppressing the fluctuation of the source voltage of the drive transistor Tr1 when the signal voltage Vsig is written, and making the gate-source voltage Vgs of the drive transistor Tr1 equal to the threshold voltage Vth of the drive transistor Tr1.

[0136] Fig.10 The circuit configuration example shown in FIG. 1 is an example of the circuit configuration of the pixel 20 b according to the present embodiment, and the circuit configuration of the pixel 20 b according to the present embodiment is not limited to Fig.10 The circuit configuration shown in FIG.

[0137] <4.3 Stacked Structure>

[0138] Next, we will refer to Fig.11 and Fig.12 A detailed structure of the pixel 20 b according to the present embodiment is described. Fig.11 2 is a schematic diagram showing a cross-sectional configuration of the pixel 20 b according to the present embodiment, and specifically, corresponds to a cross section formed when the stacked structural body according to the pixel 20 b is cut along the stacking direction. Fig.12 is a schematic diagram showing an example of a planar configuration of a pixel 20b according to the present embodiment, and specifically, corresponds to Fig.11 Each line segment (line A-A', line B-B', line C-C', line D-D', line E-E', line F-F' and line G-G') shown in the figure forms a cross section when cutting a pixel. Fig.11 and Fig.12 The pixel 20b shown in the configuration has the above Fig.10 The circuit configuration shown in FIG.

[0139] like Fig.11 As shown, the pixel 20b according to the present embodiment has a stacked structure including a semiconductor substrate 100 made of, for example, n-type conductive type silicon, a wiring layer 200 stacked on the semiconductor substrate 100, and a light emitting element EL disposed on the wiring layer 200. In the present embodiment, the semiconductor substrate 100 and the wiring layer 200 include a driving circuit for driving the light emitting element EL. In addition, the wiring layer 200 includes an insulating film 202, wiring 204, and a via 206 in addition to the elements described below.

[0140] In addition, as referenced Fig.10 As described, the drive circuit includes a drive transistor Tr1, a write transistor Tr2, a light emission control transistor Tr3, a switch transistor Tr4, and capacitors C1 and C2. In the following, the stacked structure of the pixel 20b will be described, but the description will be from the position located Fig.11 Starting from the bottom of the semiconductor substrate 100 .

[0141] Specifically, Fig.11 As shown, in the same manner as the first embodiment, the driving transistor Tr1 includes a gate electrode 104 provided on a region having an n-type conductivity type via an insulating film 202, and the n-type conductivity type serves as a channel of the driving transistor Tr1 provided in the semiconductor substrate 100 (see Fig.12 In addition, the drive transistor Tr1 is provided in the semiconductor substrate 100 so as to sandwich a region having an n-type conductivity type serving as a channel, and has a source / drain including a diffusion region 102 containing an impurity having a p-type conductivity type. Also in the present embodiment, providing the drive transistor Tr1 on the semiconductor substrate 100 in this manner makes it possible to stabilize the characteristics of the drive transistor Tr1 and obtain a transistor having a high withstand voltage.

[0142] The source or drain of the driving transistor Tr1 shares a diffusion region 102 provided in the semiconductor substrate 100 with the source or drain of the light emission control transistor Tr3 provided in the semiconductor substrate 100. That is, the driving transistor Tr1 and the light emission control transistor Tr3 have a series gate structure in which one diffusion region 102 is shared by the source or drain of one transistor and the source or drain of the other transistor. In the present embodiment, the series gate structure is preferably selected to suppress an increase in the layout area of ​​the driving transistor Tr1 and the light emission control transistor Tr3, but the present embodiment is not limited to this configuration.

[0143] In addition, the source and gate of the drive transistor Tr1 are electrically connected to the electrode 210a of the capacitor C2 described later and the anode 310 of the light emitting element EL, respectively, through the via 206. In addition, the gate electrode 104 of the drive transistor Tr1 is electrically connected to the electrode 210 of the capacitor C1 described later and the source or drain of the write transistor Tr2 through the via 206.

[0144] like Fig.11 As shown, in the same manner as the driving transistor Tr1, the light emission control transistor Tr3 includes a gate 104a provided on a region having an n-type conductivity type via an insulating film 202, the n-type conductivity type serving as a channel of the light emission control transistor Tr3 provided in the semiconductor substrate 100 (see Fig.12In addition, the light emission control transistor Tr3 has a source / drain formed by a diffusion region 102 containing an impurity having a p-type conductivity type, and the source / drain sandwiches a region having an n-type conductivity type used as a channel. In this way, in the present embodiment, by providing the light emission control transistor Tr3 on the semiconductor substrate 100, a transistor having a high driving force and a high withstand voltage can be provided while stabilizing the characteristics. In addition, the light emission control transistor Tr3 is separated from the drive transistor Tr1 by a shallow trench isolation 106 provided in the semiconductor substrate 100.

[0145] The source or drain of the light emission control transistor Tr3 is electrically connected to the electrode 210a of the capacitor C2 provided in the wiring layer 200 and to the power source (V DD ) wiring 204. In addition, the gate electrode 104a of the light emission control transistor Tr3 is electrically connected to the signal source of the light emission control signal DS through the through hole 206.

[0146] like Fig.11 As shown, the capacitor C2 is disposed in the wiring layer 200 stacked above the driving transistor Tr1 and the light emission control transistor Tr3. Specifically, the capacitor C2 has a MIM structure including a Fig.11 The stacking direction of the stacked structure shown in FIG. 1 is a pair of electrodes (metal films) sandwiching the insulating film 214a from the top and bottom (see FIG. 214a ). Fig.12 In addition, one side of the capacitor C2 is electrically connected to the source / drain shared by the above-mentioned drive transistor Tr1 and the light emission control transistor Tr3 through the through hole 206. The other side of the capacitor C1 is electrically connected to the power supply (V DD ) wiring 204.

[0147] like Fig.11 As shown, the capacitor C1 is disposed in the wiring layer 200 stacked above the capacitor C2. Specifically, the capacitor C1 has a MIM structure including a Fig.11 The stacking direction of the stacked structure shown in FIG. 1 is a pair of electrodes (metal films) sandwiching the insulating film 214 from the upper and lower directions (see Fig.12 In addition, one side of the capacitor C1 is electrically connected to the gate of the above-mentioned drive transistor Tr1 through the through hole 206. The other side of the capacitor C1 is electrically connected to the source / drain of the write transistor Tr2 to be described later through the through hole 206.

[0148] In this embodiment, the capacitor C1 is not limited to being disposed above the capacitor C2. For example, the capacitor C1 may be disposed below the capacitor C2, or may be disposed at the same height, that is, in the same layer in the stacked structure of the pixel 20b.

[0149] In addition, Fig.11 In the structure shown, the switching transistor Tr4 is arranged above the capacitor C1 in the wiring layer 200. In other words, Fig.11 In the wiring layer 200 shown in FIG. 1 , the capacitor C1 is provided on the semiconductor substrate 100 side, and the switching transistor Tr4 is provided on the light emitting element EL side. The present embodiment is not limited to this structure, and the switching transistor Tr4 may be provided on the semiconductor substrate 100 side, and the capacitor C1 and the capacitor C2 may be provided above the switching transistor Tr4.

[0150] In this embodiment, if Fig.11 As shown, the switching transistor Tr4 is configured as a thin film transistor (TFT) provided in the wiring layer 200, and it can be, for example, an N-channel transistor. Specifically, the switching transistor Tr4 includes a thin film semiconductor layer 220a provided in the wiring layer 200 and a gate electrode 224a (see FIG. 2 ) contacting the thin film semiconductor layer 220a via the insulating film 202. Fig.12 Part E-E' in the figure). In the present embodiment, since an oxide film such as IGZO has an extremely small leakage current, leakage in the switching transistor Tr4 can be suppressed, and therefore the thin film semiconductor layer 220a is preferably formed of an oxide film such as IGZO. Thus, according to the present embodiment, an increase in power consumption of the display device 10a can be suppressed. In addition, when the thin film semiconductor layer 220a is formed of IGZO or the like, it is easy to form the switching transistor Tr4 as an N-channel transistor. Therefore, the switching transistor Tr4 as an N-channel transistor can stably control the cathode-anode of the light-emitting element EL to 0V, and can prevent current from being provided to the light-emitting element EL. As a result, according to the present embodiment, a decrease in contrast during black grayscale display can be suppressed.

[0151] The source or drain of the switching transistor Tr4 is electrically connected to the anode 310 of the light emitting element EL provided on the wiring layer 200 through the through hole 206. In addition, the gate electrode 224 of the switching transistor Tr4 is electrically connected to the wiring 204 connected to the driving signal source (AZ) through the through hole 206 (see Fig.12 D-D' in the figure.

[0152] exist Fig.11 In the structure shown in , the write transistor Tr2 is provided above the capacitor C1 in the wiring layer 200. Fig.11In the embodiment, the switching transistor Tr4 and the writing transistor Tr2 are arranged at the same height, that is, on the same layer in the stacked structure of the pixel 20b. However, in the present embodiment, it is not limited to this structure, and for example, the switching transistor Tr4 and the writing transistor Tr2 can be arranged at different heights, that is, in different layers, and can be stacked on each other in the stacked structure of the pixel 20b.

[0153] Furthermore, in this embodiment, if Fig.11 As shown, the write transistor Tr2 is configured as a thin film transistor (TFT) provided in the wiring layer 200, and it can be, for example, an N-channel transistor. Specifically, the write transistor Tr2 includes a thin film semiconductor layer 220 provided in the wiring layer 200, and a gate electrode 224 (see Fig.12 EE" part in the figure). Also in this embodiment, since an oxide film such as IGZO has an extremely small leakage current, leakage in the write transistor Tr2 can be suppressed, and therefore the thin film semiconductor layer 220 is preferably formed of an oxide film such as IGZO. Thus, according to this embodiment, an increase in power consumption of the display device 10a can be suppressed.

[0154] The source or drain of the write transistor Tr2 is electrically connected to the wiring 204, which is connected to the signal line (Vsig) provided in the wiring layer 200 through the via 206. In addition, the gate electrode 224 of the write transistor Tr2 is electrically connected to the wiring 204 connected to the scanning line (WS) through the via 206 (see Fig.12 Part F-F' in.

[0155] In addition, if Fig.11 As shown, the light emitting element EL is provided on the wiring layer 200. Specifically, the light emitting element EL mainly includes an anode electrode 310 (see Fig.12 , a portion G-G' in the figure), a light-emitting layer 314 stacked on the anode electrode 310 and emitting light, and a cathode electrode 312 stacked on the light-emitting layer 314 and transmitting light from the light-emitting layer 314.

[0156] In this manner, also in the present embodiment, the drive transistor Tr1 and the light emission control transistor Tr3 included in the drive circuit are provided in the semiconductor substrate 100, and the write transistor Tr2 and the switch transistor Tr4 are provided as thin film transistors (TFTs) stacked in the wiring layer 200 on the semiconductor substrate 100. With this configuration, according to the present embodiment, the layout size of the drive circuit can be reduced, and ultimately, the display device 10 can be miniaturized.

[0157] In addition, in this embodiment, the thin film semiconductor layers 220 and 220a of the write transistor Tr2 and the switch transistor Tr4 as the thin film transistor (TFT) are formed using an oxide film such as IGZO so that leakage from the write transistor Tr2 and the switch transistor Tr4 can be suppressed. As a result, in this embodiment, an increase in power consumption of the display device 10a can be suppressed. In addition, this embodiment capable of suppressing leakage facilitates intermittent driving of the switch transistor Tr4, which can also suppress an increase in power consumption of the display device 10a.

[0158] In addition, according to this embodiment, when the thin film semiconductor layer 220a of the switching transistor Tr4 is formed of IGZO or the like, it is easy to form the switching transistor Tr4 as an N-channel transistor. Therefore, the switching transistor Tr4 as an N-channel transistor can stably control the cathode-anode of the light-emitting element EL to 0V, and can prevent the current from being supplied to the light-emitting element EL. As a result, according to this embodiment, the reduction in contrast at the time of black grayscale display can be suppressed.

[0159] In this embodiment, the pixel 20b is not limited to Fig.11 and Fig.12 The configuration shown in , for example, may have the configuration described below.

[0160] For example, in this embodiment, Fig.13 As shown in the cross section B / C in FIG. 1 (which is a schematic diagram showing an example of a planar configuration of the pixel 20b according to the present embodiment), the capacitors C1 and C2 can be arranged at the same height, that is, at the same layer in the stacked structure of the pixel 20b. Thus, in the present embodiment, since the capacitors C1 and C2 can be formed at the same time, the increase in the manufacturing process of the pixel 20b can be suppressed. Fig.13 Corresponding to when along Fig.11 The segments formed when each line segment (line A-A', line D-D', line E-E', and line F-F') shown in FIG. 2 cuts the pixel 20b, and only the segment B / C is a segment existing between the segments obtained by cutting the pixel 20b along the line B-B' and the line CC'. Fig.13 The pixel 20b shown in the configuration has the above Fig.10 The circuit configuration shown in FIG.

[0161] In this embodiment, if Fig.14(is a schematic diagram showing an example of the planar configuration of the pixel 20b according to the present embodiment), a butt contact structure can be adopted in which contacts V1 and V2 of different conductivity types are arranged side by side and electrically connected via a connecting electrode. Specifically, the source contact V2 of the driving transistor Tr1 and the contact V1 of the well region of the semiconductor substrate 100 can be electrically connected via an electrode (not shown). Thus, in the present embodiment, the increase in the planar layout of the pixel 20b can be suppressed. Fig.14 Corresponding to when along Fig.11 The segments formed when each line segment (line A-A', line D-D', line E-E', and line F-F') shown in FIG. 2 cuts the pixel 20b, and only the segment B / C is a segment existing between the segments obtained by cutting the pixel 20b along the line B-B' and the line CC'. Fig.14 The pixel 20b shown in the configuration has the above Fig.10 The circuit configuration shown in FIG.

[0162] <<5. Third embodiment>>

[0163] The embodiments of the present disclosure are not limited to being applied to the configuration of the above-mentioned pixel 20, and they can be applied to pixels 20 having various circuit configurations. Figures 15 to 17 Application examples of the pixel 20 having various circuit configurations are described. Figure 15 to Figure 17 is a circuit diagram showing an example of pixels 20 c , 20 d , and 20 e of the display device 10 according to the present embodiment.

[0164] First, in Fig.15 In the circuit configuration of the pixel 20c shown, the pixel 20c includes a light emitting element EL and a driving circuit for driving the light emitting element EL. The driving circuit includes a driving transistor Tr1, a writing transistor Tr2, a light emitting control transistor Tr3, two switching transistors Tr4a and Tr4b, and a capacitor C1. The driving transistor Tr1 and the light emitting control transistor Tr3 are P-channel transistors, and the writing transistor Tr2 and the two switching transistors Tr4a and Tr4b are N-channel transistors.

[0165] When the embodiments of the present disclosure are applied to Fig.15 When the circuit configuration is as follows, for example, the drive transistor Tr1 and the light emission control transistor Tr3 can be Si FETs provided in the semiconductor substrate 100 made of silicon, while the write transistor Tr2 and the two switching transistors Tr4a and Tr4b can be TFTs provided in the wiring layer 200 on the semiconductor substrate 100.

[0166] exist Fig.16In the circuit structure of the pixel 20d shown, the pixel 20d includes a light emitting element EL and a driving circuit for driving the light emitting element EL. The driving circuit includes a driving transistor Tr1, two writing transistors Tr2a and Tr2b, a light emitting control transistor Tr3, two switching transistors Tr4a and Tr4b, and capacitors C1, C2, and C3. The driving transistor Tr1, the light emitting control transistor Tr3, and the switching transistor Tr4b are P-channel transistors, and the two writing transistors Tr2a and Tr2b and the switching transistor Tr4a are N-channel transistors.

[0167] When the embodiments of the present disclosure are applied to Fig.16 When the circuit configuration is as follows, for example, the driving transistor Tr1, the light emission control transistor Tr3 and the switching transistor Tr4b can be Si FETs set in the semiconductor substrate 100 made of silicon, while the two writing transistors Tr2a and Tr2b and the switching transistor Tr4a can be TFTs set in the wiring layer 200 on the semiconductor substrate 100.

[0168] exist Fig.17 In the circuit configuration of the pixel 20e shown, the pixel 20e includes a light emitting element EL and a driving circuit for driving the light emitting element EL. The driving circuit includes a driving transistor Tr1, a writing transistor Tr2, a light emitting control transistor Tr3, a switching transistor Tr4, and a capacitor C1. The driving transistor Tr1, the writing transistor Tr2, the light emitting control transistor Tr3, and the switching transistor Tr4 are N-channel transistors.

[0169] When the embodiments of the present disclosure are applied to Fig.17 When the circuit configuration is as follows, for example, the drive transistor Tr1 and the switching transistor Tr4 may be Si FETs provided in the semiconductor substrate 100 made of silicon, while the write transistor Tr2 and the light emission control transistor Tr3 may be TFTs provided in the wiring layer 200 on the semiconductor substrate 100.

[0170] In this way, in this embodiment, by configuring some transistors included in the driving circuit as thin film transistors (TFTs) provided in a wiring layer stacked on a semiconductor substrate, the layout size of the driving circuit can be reduced and ultimately the display device 10 can be miniaturized.

[0171] <<6. Fourth embodiment>>

[0172] Next, we will refer to 18A to 18H An example of a method for producing the pixel 20 according to the first embodiment of the present disclosure is described. 18A to 18H are cross-sectional views for describing a method for manufacturing a pixel (pixel circuit) 20 according to the present embodiment, and they specifically correspond to Figure 3The cross section shown in .

[0173] First, if Fig.18A As shown in the upper left part of FIG. , for example, a semiconductor substrate 100 made of silicon and having n-type conductivity is prepared. Next, as shown in FIG. Fig.18A As shown in the second portion of the top left side of FIG. 1 , an insulating film 202 made of, for example, a silicon oxide film (SiO 2 ) is formed on the surface of the semiconductor substrate 100. In addition, as shown in FIG. Fig.18A As shown in the third portion from the top on the left side, a mask 260 made of a silicon nitride film (Si3N4) is formed on the insulating film 202, and according to the pattern (opening) of the mask 260, a trench serving as a shallow trench isolation 106 is formed in the semiconductor substrate 100 by dry etching.

[0174] Next, if Fig.18A As shown in the upper right part of FIG. , an insulating film 202 made of a silicon oxide film is formed in such a manner as to fill the trenches using chemical vapor deposition (CVD). Next, as shown in FIG. Fig.18A As shown in the second portion of the top right side of FIG. , after the surface is planarized using chemical mechanical polishing (CMP), the mask 260 is removed by wet etching. Fig.18A As shown in the third portion at the top right side of , a predetermined area of ​​the semiconductor substrate 100 is covered with a mask (resist) 270, and p-type conductive impurities are ion-implanted into the semiconductor substrate 100 to form a diffusion region 102 which becomes the source / drain of the driving transistor Tr.

[0175] Next, if Fig.18B As shown in the upper left part of FIG. , the gate electrode 104 is formed on the insulating film 202 on the semiconductor substrate 100 sandwiched between the diffusion regions 102 serving as the source / drain of the driving transistor Tr. At this time, by forming a mask 272 on the metal film to become the gate electrode 104 and performing dry etching, the gate electrode 104 can be patterned. Fig.18B As shown in the second portion of the top left side of FIG. , a silicon nitride film 230 serving as an interlayer insulating film and an insulating film 202 made of, for example, a silicon oxide film are stacked on the semiconductor substrate 100 using CVD. Fig.18B As shown in the third portion from the top on the left, the surface of the interlayer insulating film is flattened using CMP.

[0176] Next, if Fig.18B As shown in the upper right portion of FIG. , a mask 274 is formed on the interlayer insulating film, and dry etching is performed according to the pattern of the mask 274 to form a hole. Fig.18B As shown in the second part of the top right side of FIG, a conductive material such as tungsten is embedded by CVD in such a way as to fill the inside of the hole, and the upper part is flattened by CMP. Fig.18BAs shown in the third portion from the top right side of , a metal film as an electrode 210 is formed on a flat surface by sputtering, and a film as an insulating film 214 of the capacitor C1 is formed by sputtering or atomic layer deposition (ALD).

[0177] Then, if Fig. 18C As shown in the upper left portion of FIG. 2 , the insulating film 214 is patterned by dry etching using a mask 276. Fig. 18C As shown in the lower left part of FIG, the electrode 210 and the like are patterned by dry etching using a mask 278. Fig. 18C As shown in the upper right part of FIG. 1 , an insulating film 202 made of a silicon oxide film is formed by CVD in such a manner as to cover the insulating film 214 and the like. Fig. 18C As shown in the lower right part of , after the insulating film 202 is planarized by CMP, a mask 280 is formed, and holes are formed by dry etching according to the pattern of the mask 280.

[0178] Next, as in Fig.18D As shown in the upper left part of , a conductive material is embedded in a manner that fills the inside of the hole by CVD, and the upper part thereof is flattened by CMP. In addition, wiring 240 is formed thereon by sputtering, and wiring 240 is patterned by dry etching using mask 282. Fig.18D As shown in the lower left part of , an insulating film 202 made of a silicon oxide film is formed by CVD, the insulating film 202 is flattened by CMP, and then a mask is formed, holes are formed by dry etching according to the pattern of the mask, a conductive material is embedded in a manner of filling the holes by a CVD method, and the upper portion thereof is flattened by a CMP method.

[0179] In addition, if Fig.18D As shown in the upper right portion of FIG. 2 , a conductive material to be the gate electrode 224 of the write transistor Tr2 is formed on the insulating film 202 by CVD, and dry etching is performed using the mask 284 to pattern the gate electrode 224. In addition, as shown in FIG. Fig.18D As shown in the lower right portion of , the insulating film 202 is formed on the gate electrode 224 .

[0180] Next, as in Fig.18E As shown in the upper left portion of FIG. , after the insulating film 202 is planarized by CMP, the insulating film 202 to be the gate insulating film of the write transistor Tr2 is formed by the ALD method. Fig.18E As shown in the lower left part of FIG. 2 , a thin film semiconductor layer 220 is formed by sputtering, and the thin film semiconductor layer 220 is patterned by dry etching using a mask 286. Fig.18EAs shown in the lower right part of , an insulating film 202 made of a silicon oxide film is formed by CVD, the insulating film 202 is flattened by CMP, and then a mask 288 is formed, and holes are formed by dry etching according to the pattern of the mask 288.

[0181] Then, if Fig.18F As shown on the left side of , a conductive material is formed by CVD in such a manner as to fill the inside of the hole, and the upper portion thereof is flattened by CMP. In addition, a mask 290 is formed, and according to the pattern of the mask 290, a hole is formed using dry etching. Next, as Fig.18F As shown on the right side of , a conductive material is formed by CVD in such a way as to fill the inside of the hole, and its upper portion is flattened by CMP. In addition, wiring 242 is formed thereon, and wiring 242 is patterned by dry etching using mask 292.

[0182] Then, if Figure 18G As shown on the left side of FIG. 1 , an insulating film 202 made of a silicon oxide film is formed by CVD, the surface of the insulating film 202 is flattened by CMP, and then a mask 322 is formed, and holes are formed by dry etching according to the pattern of the mask 322. In addition, as Figure 18G As shown on the right side of , a conductive material is formed by CVD in such a way as to fill the inside of the hole, and the upper part thereof is flattened by CMP. In addition, an electrode 310 is formed thereon, and the electrode 310 is patterned by dry etching using a mask 324.

[0183] Next, if Fig.18H As shown on the left side of FIG. 3 , an insulating film 202 made of a silicon oxide film is formed by CVD, and dry etching is performed on the insulating film 202 according to the pattern of the mask 326 to form an opening that exposes a portion of the electrode 310. In addition, as shown in FIG. Fig.18H As shown on the right side of FIG. 3 , after the mask 326 is removed, the light-emitting layer 314 is formed on the electrode 310 by a vapor deposition method, and the electrode 312 is formed on the light-emitting layer 314 .

[0184] <<7. Conclusion>>

[0185] In this way, according to an embodiment of the present disclosure, by configuring some transistors included in the driving circuit as thin film transistors (TFTs) arranged in a wiring layer stacked on a semiconductor substrate, the layout size of the driving circuit can be reduced and ultimately the display device 10 can be miniaturized.

[0186] The technology of the present disclosure can be applied not only to the display device 10 but also to a lighting device and the like.

[0187] In the above-described embodiments of the present disclosure, the semiconductor substrate 100 is not necessarily a silicon substrate, and it may be another substrate (eg, a silicon-on-insulator (SOI) substrate, a SiGe substrate, etc.).

[0188] The display device 10 according to the embodiment of the present disclosure can be manufactured by using a method, a device, and conditions for manufacturing a typical semiconductor device. That is, the display device 10 according to the present embodiment can be manufactured using an existing method for manufacturing a semiconductor device.

[0189] Examples of the above methods include physical vapor deposition (PVD), CVD, and ALD. Examples of PVD include vacuum vapor deposition, electron beam (EB) vapor deposition, various sputtering methods (magnetron sputtering, radio frequency (RF)-direct current (DC) coupled bias sputtering, electron cyclotron resonance (ECR) sputtering, reverse target sputtering, high frequency sputtering, etc.), ion plating, laser ablation, molecular beam epitaxy (MBE), and laser transfer. Examples of CVD methods include plasma CVD, thermal CVD, metal organic (MO) CVD, and optical CVD. In addition, other methods include electroplating, chemical plating, spin coating; immersion; casting; micro-contact printing; droplet casting; various printing methods such as screen printing, inkjet printing, offset printing, gravure printing, and flexographic printing; stamping; spraying; and various coating methods such as air blade coater, blade coater, rod coater, blade coater, extrusion coater, reverse roll coater, transfer roll coater, gravure coater, kiss coater, cast coater, sprayer, slit hole coater, and calender coater. In addition, examples of patterning methods include chemical etching, laser transfer or photolithography, and physical etching using ultraviolet rays, lasers, etc. Examples of planarization techniques include CMP, laser planarization, reflow, and the like.

[0190] <<8. Application Examples>>

[0191] For example, the technology according to the present disclosure can be applied to display units of various electronic devices, etc. Hereinafter, examples of electronic devices to which the present technology can be applied will be described below.

[0192] (Specific example 1)

[0193] Fig.19A is a front view showing an example of the appearance of a digital camera 500, Fig.19Bis a rear view showing an example of the appearance of a digital camera 500. The digital still camera 500 is a single-lens reflex type of an interchangeable lens, which includes an interchangeable imaging lens unit (interchangeable lens) 512 substantially at the center of the front of a camera body 511, and a grip portion 513 to be gripped by a photographer on the left front side.

[0194] The monitor 514 is provided at a position offset to the left from the center of the rear surface of the camera body 511. An electronic viewfinder (eyepiece window) 515 is provided above the monitor 514. The photographer can visually recognize the optical image of the subject guided from the imaging lens unit 512, and determine the composition by observing the electronic viewfinder 515. As the monitor 514 and the electronic viewfinder 515, the display device 10 according to the embodiment of the present disclosure can be used. (Specific implementation method 2)

[0196] Fig. 20 600. The head-mounted display 600 includes, for example, ear hooks 612 worn on the user's head on both sides of a glasses-shaped display unit 611. The display device 10 according to an embodiment of the present disclosure can be used as the display unit 611 in the head-mounted display 600.

[0197] (Specific example 3)

[0198] Fig.21 634 is an external view of the see-through head-mounted display 634. The see-through head-mounted display 634 includes a main body 632, an arm 633, and a lens barrel 631.

[0199] The body 632 is connected to the arm 643 and the glasses 630. Specifically, the end of the body 632 in the long side direction is coupled to the arm 633, and one side surface of the body 632 is coupled to the glasses 630 via a connecting member. The body 632 can be directly worn on the head of a human body.

[0200] The body 632 includes a control panel and a display unit for controlling the operation of the see-through head mounted display 634. The arm 633 connects the body 632 and the lens barrel 631 and supports the lens barrel 631. Specifically, the arm 633 is coupled to one end of the body 632 and one end of the lens barrel 631 to fix the lens barrel 631. The arm 633 includes a signal line for communicating data related to an image provided from the body 632 to the lens barrel 631.

[0201] The lens barrel 631 projects image light provided from the main body 632 via the arm 633 toward the eyes of the user wearing the see-through head mounted display 634 through the eyepiece lens. The display device 10 according to the embodiment of the present disclosure can be used as a display unit of the main body 632 in the see-through head mounted display 634.

[0202] (Specific example 4)

[0203] Fig. 22 An example of the appearance of a television device 710 is shown. The television device 710 includes, for example, a video display screen unit 711 including a front panel 712 and a filter glass 713, and the video display screen unit 711 includes the display device 10 according to the embodiment of the present disclosure.

[0204] (Specific Example 5)

[0205] Fig.23 An example of the appearance of a smartphone 800 is shown. The smartphone 800 includes a display unit 802 that displays various types of information, and an operation unit including buttons and the like that receive operation inputs from a user. The display unit 802 may be the display device 10 according to the present embodiment.

[0206] (Specific Example 6)

[0207] Fig.24A and Fig. 24B is a diagram showing an interior configuration of a car including the display device 10 according to an embodiment of the present disclosure as a display device. Specifically, Fig.24A is a diagram showing a state of the interior of a car from the rear to the front of the car, and Fig. 24B 1 is a diagram showing a state of the interior of a car from the oblique rear to the oblique front of the car.

[0208] Fig.24A and 24B The car shown in FIG. 1 has a central display 911, a console display 912, a head-up display 913, a digital rear mirror 914, a steering wheel display 915, and a rear entertainment display 916. The display device 10 according to an embodiment of the present disclosure may be applied to some or all of these displays.

[0209] The central display 911 is provided at a position on the central console 907 facing the driver's seat 901 and the passenger seat 902 . Fig.24A and Fig. 24BAn example of a central display 911 having a laterally long shape extending from the driver's seat 901 side to the passenger seat 902 side is shown, but the screen size and arrangement position of the central display 911 can be freely selected. The central display 911 is capable of displaying information detected by various sensors (not shown). As a specific example, the central display 911 is capable of displaying a captured image captured by an image sensor, a distance image to obstacles in front of or to the side of the vehicle measured by a time-of-flight (ToF) sensor, a passenger's body temperature detected by an infrared sensor, and the like. The central display 911 can be used to display, for example, at least one of safety-related information, operation-related information, life log, health-related information, authentication / identification-related information, and entertainment-related information.

[0210] Safety-related information is information such as dozing detection, looking away detection, prank detection of children riding together, presence or absence of seat belts, and detection of passengers leaving, and is information detected by, for example, a sensor (not shown) superimposed on the rear side of the central display 1911. Operation-related information uses a sensor to detect gestures related to the operation of the occupant. The gestures to be detected may include the operation of various types of equipment in the car. For example, the operation of air conditioning equipment, navigation equipment, audio / video (AV) equipment, lighting equipment, etc. is detected. The life log includes the life logs of all occupants. For example, the life log includes a record of the actions of each occupant in the car. Acquiring and storing the life log makes it possible to confirm the state of the occupant at the time of the accident. Health-related information uses a temperature sensor to detect the body temperature of the occupant, and estimates the health status of the occupant based on the detected body temperature. Alternatively, the face of the occupant can be imaged using an image sensor, and the health status of the occupant can be estimated from the imaged facial expression. In addition, an automatic voice can be used to talk to the occupant, and the health status of the occupant can be estimated based on the content of the occupant's answer. Authentication / identification related information includes a keyless entry function that uses a sensor to perform face authentication and an automatic adjustment function of paper height and position with face recognition. Entertainment related information includes a function in which a passenger detects operation information of an AV device using a sensor, and a function in which a passenger's face is recognized by a sensor and content suitable for the passenger is provided using the AV device.

[0211] For example, the console display 912 may be used to display life log information. The console display 912 is arranged near the shift lever 908 of the center console 907 between the driver's seat 901 and the passenger seat 902. The console display 912 may also display information detected by different sensors (not shown). The console display 912 may display an image of the vehicle's periphery captured by an image sensor, or may display an image of the distance to obstacles around the vehicle.

[0212] The head-up display 913 is virtually displayed behind the windshield 904 in front of the driver's seat 901. The head-up display 913 can be used to display, for example, at least one of safety-related information, operation-related information, life log, health-related information, authentication / identification-related information, and entertainment-related information. In many cases, since the head-up display 913 is virtually set in front of the driver's seat 901, the head-up display is suitable for displaying information directly related to the operation of the car, for example, the speed of the car and the remaining amount of fuel (battery).

[0213] The digital rear mirror 914 can display not only the rear of the car but also the status of passengers in the rear seats and can therefore be used to display life log information, for example, by providing a sensor (not shown) overlapping the rear surface side of the digital rear mirror 914.

[0214] The steering wheel display 915 is provided near the center of the steering wheel 906 of the car. The steering wheel display 915 may be used to display, for example, at least one of safety-related information, operation-related information, life log, health-related information, authentication / identification-related information, and entertainment-related information. Specifically, since the steering wheel display 915 is close to the driver's hand, it is suitable for displaying life log information such as the driver's body temperature, or for displaying information related to the operation of AV equipment, air conditioning equipment, etc.

[0215] The rear entertainment display 916 is attached to the rear side of the driver's seat 901 and the passenger seat 902, and is used to be viewed by the passengers in the rear seats. The rear entertainment display 916 can be used to display, for example, at least one of safety-related information, operation-related information, life log, health-related information, authentication / identification-related information, and entertainment-related information. In particular, since the rear entertainment display 916 is in front of the passengers in the rear seats, information related to the passengers in the rear seats is displayed. For example, information about the operation of an AV device or an air-conditioning device can be displayed, or the result of measuring the body temperature of a passenger in the rear seat using a temperature sensor (not shown) can be displayed.

[0216] <<9.Supplement>>

[0217] Although the preferred embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the technical scope of the present disclosure is not limited to such examples. Obviously, for ordinary technicians in the technical field of the present disclosure, several improvements and modifications can be made without departing from the technical concept of the present disclosure, and these improvements and modifications should also be regarded as the technical scope of the present disclosure.

[0218] The effects described in this specification are merely illustrative or exemplary, and are not restrictive. That is, according to the description of this specification, the technology according to the present disclosure may exhibit other effects that are obvious to those skilled in the art together with or in place of the above effects.

[0219] The present technology may also take the following configurations.

[0220] (1) A display device comprising:

[0221] The stack structure includes:

[0222] a light emitting element, the brightness of which varies according to the current supplied thereto;

[0223] a current source transistor electrically connected to the current source and the light emitting element, and the current source transistor supplies a current corresponding to the signal voltage to the light emitting element;

[0224] a capacitor connected to the control terminal of the current source transistor; and

[0225] a selection transistor connected to a control terminal of the current source transistor, and the selection transistor supplies a signal voltage to the current source transistor via the capacitor, wherein

[0226] The stack structure includes:

[0227] a semiconductor substrate on which a current source transistor is disposed;

[0228] a wiring layer stacked on the semiconductor substrate, and the wiring layer includes a capacitor formed of a thin film transistor and a selection transistor; and

[0229] The light emitting elements are stacked on the wiring layer.

[0230] (2) The display device according to (1), wherein:

[0231] In the wiring layer,

[0232] The capacitor is provided on the semiconductor substrate side, and

[0233] The select transistor is disposed above the capacitor.

[0234] (3) The display device according to (1), wherein:

[0235] In the wiring layer,

[0236] The selection transistor is provided on the semiconductor substrate side, and

[0237] The capacitor is disposed above the select transistor.

[0238] (4) The display device according to any one of (1) to (3), wherein the selection transistor is an N-channel transistor.

[0239] (5) The display device according to any one of (1) to (4), wherein:

[0240] The stack structure also includes:

[0241] a switching transistor connected to the light emitting element or the current source transistor, and the switching transistor controls the light emitting element not to emit light during a non-light emitting period, and

[0242] The switching transistor is formed of a thin film transistor provided in a wiring layer.

[0243] (6) The display device according to (5), wherein the switching transistor is an N-channel transistor.

[0244] (7) The display device according to (5) or (6), wherein, in the stacked structure, the plurality of thin film transistors are stacked along a stacking direction of the stacked structure.

[0245] (8) The display device according to any one of (1) to (7), wherein the thin film transistor includes, as a channel, a thin film semiconductor layer containing at least one element selected from the group consisting of silicon, aluminum, indium, gallium, and zinc.

[0246] (9) The display device according to (8), wherein the thin film semiconductor layer is formed of polycrystalline silicon or IGZO.

[0247] (10) The display device according to any one of (1) to (9), wherein in the stacked structure, the thin film transistor has a top gate structure, a bottom gate structure, or a double gate structure.

[0248] (11) The display device according to any one of (1) to (4), wherein:

[0249] The stack structure also includes:

[0250] a switching transistor connected to the light emitting element or the current source transistor, and the switching transistor controls the light emitting element not to emit light during a non-light emitting period, and

[0251] The switching transistor is formed of a thin film transistor provided in a wiring layer.

[0252] (12) The display device according to any one of (1) to (11), wherein the capacitor has a MIM structure formed by a pair of metal films sandwiching an insulating film from a top and bottom direction along a stacking direction of the stacked structure.

[0253] (13) The display device according to (12), wherein the insulating film is composed of a silicon nitride film.

[0254] (14) The display device according to (12), wherein the insulating film is formed of an oxide film containing at least one element selected from the group consisting of silicon, hafnium, zirconium oxide, tantalum, and yttrium.

[0255] (15) The display device according to any one of (1) to (11), wherein the capacitor has a MIM structure formed by sandwiching an insulating film by a metal film from a plane direction perpendicular to a stacking direction of the stacked structure.

[0256] (16) The display device according to any one of (1) to (15), wherein the current source transistor is a P-channel transistor.

[0257] (17) The display device according to any one of (1) to (15), wherein the current source transistor is an N-channel transistor.

[0258] (18) The display device according to any one of (1) to (17), wherein:

[0259] The stack structure also includes:

[0260] a light emission control transistor connected to the current source transistor, and the light emission control transistor controls light emission of the light emitting element, and

[0261] The light emission control transistor is disposed on the semiconductor substrate.

[0262] (19) The display device according to (18), wherein:

[0263] The current source transistor and the light emission control transistor have a series gate structure in which a source or a drain of one transistor shares a diffusion region with a source or a drain of another transistor.

[0264] (20) The display device according to any one of (1) to (17), wherein:

[0265] The stack structure also includes:

[0266] a light emission control transistor connected to the current source transistor, and the light emission control transistor controls light emission of the light emitting element, and

[0267] The light emission control transistor is disposed on the semiconductor substrate.

[0268] (21) The display device according to (20), wherein the light emission control transistor is an N-channel transistor.

[0269] (22) A display device according to any one of (1) to (21), wherein the semiconductor substrate has a butting contact structure in which a source contact of the current source transistor and a contact of a well region of the semiconductor substrate are electrically connected.

[0270] (23) The display device according to any one of (1) to (22), wherein the light-emitting element is an OLED.

[0271] (24) An electronic device equipped with a display device,

[0272] The display device comprises:

[0273] A stacking structure, the stacking structure comprising:

[0274] a light emitting element, the brightness of which varies according to the current supplied thereto;

[0275] a current source transistor electrically connected to the current source and the light emitting element, and the current source transistor supplies a current corresponding to the signal voltage to the light emitting element;

[0276] a capacitor connected to the control terminal of the current source transistor; and

[0277] a selection transistor connected to a control terminal of the current source transistor, and the selection transistor supplies a signal voltage to the current source transistor via the capacitor, wherein

[0278] The stack structure includes:

[0279] a semiconductor substrate on which a current source transistor is disposed;

[0280] a wiring layer stacked on the semiconductor substrate, and the wiring layer includes a capacitor formed of a thin film transistor and a selection transistor; and

[0281] The light emitting elements are stacked on the wiring layer.

[0282] Reference Numbers List

[0283] 10, 10a Display device

[0284] 20, 20a, 20b, 20c, 20d, 20e pixels

[0285] 30 pixel array unit

[0286] 31 scan lines

[0287] 32, 33 drive lines

[0288] 34 Signal Line

[0289] 40 Write scanning unit

[0290] 50, 60 drive scanning unit

[0291] 70 Signal output unit

[0292] 80 Display Panel

[0293] 100 Semiconductor substrate

[0294] 102 Diffusion Zone

[0295] 104, 104a, 224, 224a gate electrode

[0296] 106 Shallow Trench Isolation

[0297] 200 wiring layers

[0298] 202, 214, 214a Insulation film

[0299] 204, 240, 242 wiring

[0300] 206 through hole

[0301] 210, 210a, 212, 310, 312 electrodes

[0302] 220, 220a Thin film semiconductor layer

[0303] 230 Nitride Film

[0304] 260, 270, 272, 274, 276, 278, 280, 282, 284, 286, 288, 290, 292, 322, 324, 326 masks

[0305] 314 Luminous Layer

[0306] EL light emitting element

[0307] Tr1, Tr2, Tr2a, Tr2b, Tr3, Tr4, Tr4a, Tr4b transistors

[0308] C1, C2, C3 capacitors

[0309] V1, V2 contact.

Claims

1. A display device, comprising: The stacking structure includes: a light emitting element, the brightness of which varies according to a supplied current; a current source transistor electrically connected to a current source and the light emitting element, and the current source transistor supplies a current corresponding to a signal voltage to the light emitting element; a capacitor connected to a control terminal of the current source transistor; and a selection transistor connected to the control terminal of the current source transistor, and the selection transistor provides the signal voltage to the current source transistor via the capacitor, wherein, The stacked structure comprises: a semiconductor substrate on which the current source transistor is disposed; a wiring layer stacked on the semiconductor substrate, and the wiring layer includes the capacitor and the selection transistor formed of a thin film transistor; and The light emitting element is stacked on the wiring layer.

2. The display device according to claim 1, wherein: In the wiring layer, The capacitor is provided on the semiconductor substrate side, and The selection transistor is disposed above the capacitor.

3. The display device according to claim 1, wherein: In the wiring layer, The selection transistor is provided on the semiconductor substrate side, and The capacitor is disposed over the selection transistor.

4. The display device according to claim 1, wherein: The selection transistor is an N-channel transistor.

5. The display device according to claim 1, wherein: The stacked structure further comprises: a switching transistor connected to the light emitting element or the current source transistor, and the switching transistor controls the light emitting element not to emit light during a non-light emitting period, and The switching transistor is formed by the thin film transistor provided in the wiring layer.

6. The display device according to claim 5, wherein: The switch transistor is an N-channel transistor.

7. The display device according to claim 5, wherein: In the stacked structure, a plurality of the thin film transistors are stacked along a stacking direction of the stacked structure.

8. The display device according to claim 1, wherein: The thin film transistor includes, as a channel, a thin film semiconductor layer containing at least one element selected from the group consisting of silicon, aluminum, indium, gallium, and zinc.

9. The display device according to claim 1, wherein: In the stacked structure, the thin film transistor has a top gate structure, a bottom gate structure or a double gate structure.

10. The display device according to claim 1, wherein: The capacitor has a MIM structure formed by a pair of metal films sandwiching an insulating film from a top and bottom direction along a stacking direction of the stacked structure.

11. The display device according to claim 10, wherein: The insulating film is composed of a silicon nitride film.

12. The display device according to claim 10, wherein: The insulating film is composed of an oxide film containing at least one element selected from the group consisting of silicon, hafnium, zirconium oxide, tantalum, and yttrium.

13. The display device according to claim 1, wherein: The capacitor has a MIM structure formed by metal films sandwiching an insulating film from a plane direction perpendicular to a stacking direction of the stacked structural body.

14. The display device according to claim 1, wherein: The current source transistor is a P-channel transistor.

15. The display device according to claim 1, wherein: The current source transistor is an N-channel transistor.

16. The display device according to claim 1, wherein: The stacked structure further comprises: a light emission control transistor connected to the current source transistor, wherein the light emission control transistor controls light emission of the light emitting element, and The light emission control transistor is disposed on the semiconductor substrate.

17. The display device according to claim 16, wherein: The current source transistor and the light emission control transistor have a series gate structure in which a source or a drain of one transistor shares a diffusion region with a source or a drain of another transistor.

18. The display device according to claim 1, wherein: The semiconductor substrate has a butted contact structure in which a source contact of the current source transistor and a contact of a well region of the semiconductor substrate are electrically connected.

19. The display device according to claim 1, wherein: The light emitting element is an OLED.

20. An electronic device equipped with a display device, The display device comprises: A stacked structure, comprising: a light emitting element, the brightness of which varies according to a supplied current; a current source transistor electrically connected to a current source and the light emitting element, and the current source transistor supplies a current corresponding to a signal voltage to the light emitting element; a capacitor connected to a control terminal of the current source transistor; and a selection transistor connected to the control terminal of the current source transistor, and the selection transistor provides the signal voltage to the current source transistor via the capacitor, wherein, The stacked structure comprises: a semiconductor substrate on which the current source transistor is disposed; a wiring layer stacked on the semiconductor substrate, and the wiring layer includes the capacitor and the selection transistor formed of a thin film transistor; and The light emitting element is stacked on the wiring layer.

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