Display substrate, preparation method thereof and display device

Abstract

A display substrate comprises a substrate (101) and a driving circuit layer (102) arranged on the substrate (101). The driving circuit layer (102) at least comprises a plurality of circuit units, at least one circuit unit comprises a pixel circuit, and the pixel circuit at least comprises a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4) and a first capacitor (C1). The gate electrode of the first transistor (T1) is electrically connected to the first scanning signal lines (GL1, 61), and the first pole is electrically connected to the first initial signal lines (INIT1, 81). The gate electrode of the second transistor (T2) is electrically connected to the second scanning signal lines (GL2, 62). The extension directions of the first initial signal lines (INIT1, 81), the first scanning signal lines (GL1, 61) and the second scanning signal lines (GL2, 62) are at least partially the same and are located on the same side of the first transistor (T1), and the first initial signal lines (INIT1, 81) are located between the first scanning signal lines (GL1, 61) and the second scanning signal lines (GL2, 62).

Description

Display substrate and manufacturing method thereof, and display device Technical Field

[0001] This article relates to but is not limited to display technology, in particular to a display substrate and its preparation method, and a display device. Background Art

[0002] Organic light-emitting diodes (OLEDs) and quantum-dot light-emitting diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] Embodiments of the present disclosure provide a display substrate, a method for manufacturing the same, and a display device.

[0006] In one aspect, embodiments of the present disclosure provide a display substrate, comprising: a substrate and a driving circuit layer disposed on the substrate, the driving circuit layer comprising at least a plurality of circuit units, at least one of which comprises a pixel circuit; the pixel circuit comprising at least a first transistor, a second transistor, a third transistor, a fourth transistor, and a first capacitor. The gate electrode of the first transistor is electrically connected to a first scan signal line, the first electrode of the first transistor is electrically connected to a first initial signal line, and the second electrode of the first transistor is electrically connected to the gate electrode of the third transistor; the gate electrode of the second transistor is electrically connected to a second scan signal line, the first electrode of the second transistor is electrically connected to the gate electrode of the third transistor, and the second electrode of the second transistor is electrically connected to the second electrode of the third transistor; the gate electrode of the fourth transistor is electrically connected to a third scan signal line, the first electrode of the fourth transistor is electrically connected to a data signal line, and the second electrode of the fourth transistor is electrically connected to the second end of the first capacitor; and the first end of the first capacitor is electrically connected to the gate electrode of the third transistor. The first initial signal line, the first scan signal line, and the second scan signal line extend in at least partially the same direction and are located on the same side of the first transistor, with the first initial signal line being located between the first scan signal line and the second scan signal line.

[0007] In some exemplary embodiments, the first preliminary signal line, the first scan signal line, and the second scan signal line are in the same layer structure.

[0008] In some exemplary embodiments, the active layer of the first transistor includes a first region, a second region, and a channel region located between the first region and the second region, wherein the first region of the active layer of the first transistor is connected to the first initial signal line. The driving circuit layer further includes at least one first power line; the orthographic projection of the first power line on the substrate overlaps the orthographic projection of the first region of the active layer of the first transistor on the substrate.

[0009] In some exemplary embodiments, the pixel circuit further includes: a second capacitor; the second capacitor includes at least: a second plate serving as the second end of the second capacitor and a fourth plate serving as the first end of the second capacitor, the orthographic projection of the second plate on the substrate at least partially overlapping the orthographic projection of the fourth plate on the substrate. The first capacitor includes at least a first plate serving as the first end of the first capacitor and a third plate serving as the second end of the first capacitor, the orthographic projection of the first plate on the substrate at least partially overlapping the orthographic projection of the third plate on the substrate. The second capacitor includes at least a second plate and a fourth plate, the orthographic projection of the second plate on the substrate at least partially overlapping the orthographic projection of the fourth plate on the substrate. The fourth plate is connected to the first power line, the second plate is connected to the third plate, and the first plate serves as the gate electrode of the third transistor.

[0010] In some exemplary embodiments, the first electrode plate and the second electrode plate are in the same layer structure, and the third electrode plate and the fourth electrode plate are in the same layer structure.

[0011] In some exemplary embodiments, a second electrode plate connecting line extending toward the fourth electrode plate is provided on the third electrode plate, and a second groove recessed away from the third electrode plate is provided on the fourth electrode plate; the second electrode plate connecting line is provided in the second groove, and the end of the second electrode plate connecting line away from the third electrode plate is connected to the second electrode plate through a via and a connecting electrode.

[0012] In some exemplary embodiments, the driving circuit layer further includes: at least one first power connection line extending along a first direction, and at least one first power line extending along a second direction, wherein the first direction intersects the second direction; the first power lines are connected to the first power connection lines to form a mesh structure for transmitting a first power signal.

[0013] In some exemplary embodiments, the driving circuit layer further includes: at least one second power connection line extending along a first direction, and at least one second power connection line extending along a second direction, the first direction intersecting the second direction; the second power line and the second power connection line are connected to form a mesh structure for transmitting a second power signal; the second power connection line is located on a side of the first power connection line away from the second capacitor.

[0014] In some exemplary embodiments, the first power connection line and the second power connection line are in the same layer structure, the first power line and the second power line are in the same layer structure, and the first power line is located on a side of the first power connection line away from the substrate.

[0015] In some exemplary embodiments, the first capacitor and the second capacitor are located on the same side of the first transistor and the second transistor, the second capacitor is located on a side of the first capacitor away from the first transistor and the second transistor, and an orthographic projection of the third transistor on the substrate at least partially overlaps with an orthographic projection of the first capacitor on the substrate.

[0016] In some exemplary embodiments, the fourth plates of the second capacitors of the pixel circuits of the circuit units adjacent to each other along the first direction are connected to each other in an integrated structure.

[0017] In some exemplary embodiments, the at least one circuit unit further includes: a first shielding electrode, wherein the orthographic projection of the first shielding electrode on the substrate at least partially overlaps with the orthographic projection of the first active layer between the two gate electrodes of the first transistor in the present circuit unit on the substrate, and also at least partially overlaps with the orthographic projection of the second active layer between the two gate electrodes of the second transistor in the adjacent circuit unit on the substrate.

[0018] In some exemplary embodiments, the first shielding electrode includes: a first shielding end and a second shielding end; an orthographic projection of the first shielding end on the substrate at least partially overlaps with an orthographic projection of a first active layer between two gate electrodes of a first transistor in the current circuit unit on the substrate; and the first shielding end is electrically connected to a first power line. An orthographic projection of the second shielding end on the substrate at least partially overlaps with an orthographic projection of a second active layer between two gate electrodes of a second transistor in an adjacent circuit unit on the substrate; and the second shielding end is electrically connected to the first power line.

[0019] In some exemplary embodiments, the first shielding electrode and the fourth plate of the second capacitor are an integral structure connected to each other.

[0020] In some exemplary embodiments, the pixel circuit further includes: a fifth transistor, a gate electrode of the fifth transistor being electrically connected to the first light-emitting signal line, a first electrode of the fifth transistor being electrically connected to the first power supply line, and a second electrode of the fifth transistor being electrically connected to the first electrode of the third transistor; the first light-emitting signal line being located on a side of the second scanning signal line away from the first initial signal line.

[0021] In some exemplary embodiments, the film layer where the first light-emitting signal line is located is located on a side of the film layer where the first initial signal line is located close to the substrate; or, the first light-emitting signal line and the first initial signal line are in the same layer structure.

[0022] In some exemplary embodiments, the pixel circuit further includes a sixth transistor, wherein a gate electrode of the sixth transistor is electrically connected to a second light-emitting signal line, a first electrode of the sixth transistor is electrically connected to a second electrode of the third transistor, and a second electrode of the sixth transistor is electrically connected to a light-emitting device. The second light-emitting signal line is located on a side of the first light-emitting signal line away from the first initial signal line. The second light-emitting signal line and the first light-emitting signal line are co-layered.

[0023] In some exemplary embodiments, the pixel circuit further includes a ninth transistor. A gate electrode of the ninth transistor is electrically connected to the fifth scan signal line, a first electrode of the ninth transistor is electrically connected to the first reference signal line, and a second electrode of the ninth transistor is electrically connected to the second plate of the second capacitor and the third plate of the first capacitor. The fifth scan signal line and the second scan signal line output the same scan signal. The fourth and ninth transistors are located on a side of the second capacitor away from the first capacitor. The active layer of the fourth transistor and the active layer of the ninth transistor are interconnected and integrally formed.

[0024] In some example embodiments, active layers of at least two ninth transistors adjacent to each other along the first direction are connected into an integrated structure through a first active connection line.

[0025] In some exemplary embodiments, the pixel circuit further includes: a seventh transistor and an eighth transistor; wherein the gate electrode of the seventh transistor is electrically connected to the fourth scan signal line, the first electrode of the seventh transistor is electrically connected to the second initial signal line, and the second electrode of the seventh transistor is electrically connected to the light-emitting device; the gate electrode of the eighth transistor is electrically connected to the fourth scan signal line, the first electrode of the eighth transistor is electrically connected to the second reference signal line, and the second electrode of the eighth transistor is electrically connected to the first electrode of the third transistor.

[0026] In some exemplary embodiments, the driving circuit layer includes, in a direction perpendicular to the display substrate, a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially disposed on the base. The active layers of the first, second, and third transistors are located in the semiconductor layer. The gate electrodes, first and second plates of the first, second, and third transistors are located in the first conductive layer. The third and fourth plates are located in the second conductive layer. The first initial signal line, the first scan signal line, and the second scan signal line are located in the third conductive layer.

[0027] On the other hand, an embodiment of the present disclosure provides a display device including the display substrate as described above.

[0028] In another aspect, an embodiment of the present disclosure provides a method for manufacturing a display substrate, comprising: forming a drive circuit layer on a substrate, the drive circuit layer comprising at least a plurality of circuit units, at least one of which comprises a pixel circuit; the pixel circuit comprising at least a first transistor, a second transistor, a third transistor, a fourth transistor, and a first capacitor. The gate electrode of the first transistor is electrically connected to a first scan signal line, the first electrode of the first transistor is electrically connected to a first initial signal line, and the second electrode of the first transistor is electrically connected to the gate electrode of the third transistor; the gate electrode of the second transistor is electrically connected to a second scan signal line, the first electrode of the second transistor is electrically connected to the gate electrode of the third transistor, and the second electrode of the second transistor is electrically connected to the second electrode of the third transistor; the gate electrode of the fourth transistor is electrically connected to a third scan signal line, the first electrode of the fourth transistor is electrically connected to a data signal line, and the second electrode of the fourth transistor is electrically connected to the second end of the first capacitor; and the first end of the first capacitor is electrically connected to the gate electrode of the third transistor. The first initial signal line, the first scan signal line, and the second scan signal line extend in at least partially the same direction and are located on the same side of the first transistor, with the first initial signal line being located between the first scan signal line and the second scan signal line.

[0029] On the other hand, embodiments of the present disclosure provide a display substrate, comprising: a base and a driving circuit layer disposed on the base, the driving circuit layer comprising at least a plurality of circuit units, at least one of the plurality of circuit units comprising a pixel circuit, the pixel circuit comprising at least a first transistor, a second transistor, a third transistor, a fourth transistor, and a first capacitor. The gate electrode of the first transistor is electrically connected to a first scan signal line, the first electrode of the first transistor is electrically connected to a first initial signal line, and the second electrode of the first transistor is electrically connected to the gate electrode of the third transistor; the gate electrode of the second transistor is electrically connected to a second scan signal line, the first electrode of the second transistor is electrically connected to the gate electrode of the third transistor, and the second electrode of the second transistor is electrically connected to the second electrode of the third transistor; the gate electrode of the fourth transistor is electrically connected to a third scan signal line, the first electrode of the fourth transistor is electrically connected to a data signal line, and the second electrode of the fourth transistor is electrically connected to the second end of the first capacitor; and the first end of the first capacitor is electrically connected to the gate electrode of the third transistor. The second transistor is located on one side of the first transistor in a first direction, and the third and fourth transistors are located on the same side of the first and second transistors in a second direction, with the first direction intersecting the second direction. The first initial signal line, the first scan signal line, and the second scan signal line all extend along the first direction and are located on a side of the first transistor away from the third transistor in the second direction. The first initial signal line is located between the first scan signal line and the second scan signal line.

[0030] In some exemplary embodiments, an orthographic projection of the first scan signal line on the substrate partially overlaps with an orthographic projection of the gate electrode of the first transistor and an orthographic projection of the gate electrode of the second transistor on the substrate.

[0031] In some exemplary embodiments, the pixel circuit further includes: a second capacitor; the second capacitor includes at least a second plate serving as a second end of the second capacitor and a fourth plate serving as a first end of the second capacitor, wherein an orthographic projection of the second plate on the substrate at least partially overlaps with an orthographic projection of the fourth plate on the substrate. The first capacitor includes at least a first plate serving as a first end of the first capacitor and a third plate serving as a second end of the first capacitor, wherein an orthographic projection of the first plate on the substrate at least partially overlaps with an orthographic projection of the third plate on the substrate. The fourth plate is connected to a first power line, the second plate is connected to the third plate, and the first plate serves as a gate electrode of the third transistor.

[0032] In some exemplary embodiments, a second electrode plate connecting line extending toward the fourth electrode plate is provided on the third electrode plate, and a second groove recessed away from the third electrode plate is provided on the fourth electrode plate; the second electrode plate connecting line is provided in the second groove, and an end of the second electrode plate connecting line away from the third electrode plate is connected to the second electrode plate through a via and a connecting electrode.

[0033] In some exemplary embodiments, the at least one circuit unit further includes: a first shielding electrode; the first shielding electrode includes: a first shielding end and a second shielding end; an orthographic projection of the first shielding end on the substrate at least partially overlaps with an orthographic projection of a first active layer between two gate electrodes of a first transistor in the circuit unit on the substrate; the first shielding end is electrically connected to a first power line; an orthographic projection of the second shielding end on the substrate at least partially overlaps with an orthographic projection of a second active layer between two gate electrodes of a second transistor in an adjacent circuit unit on the substrate; the second shielding end is electrically connected to the first power line.

[0034] In some exemplary embodiments, the pixel circuit further includes a fifth transistor and a sixth transistor. The gate electrode of the fifth transistor is electrically connected to the first light-emitting signal line, the first electrode of the fifth transistor is electrically connected to the first power line, and the second electrode of the fifth transistor is electrically connected to the first electrode of the third transistor. The gate electrode of the sixth transistor is electrically connected to the second light-emitting signal line, the first electrode of the sixth transistor is electrically connected to the second electrode of the third transistor, and the second electrode of the sixth transistor is electrically connected to the light-emitting device. The first light-emitting signal line is located on one side of the second scan signal line in the second direction, and the second light-emitting signal line is located on one side of the first light-emitting signal line in the second direction.

[0035] In some exemplary embodiments, the first light emitting signal line, the second light emitting signal line, and the first initial signal line are in the same layer structure.

[0036] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0037] Summary of the Figures

[0038] The accompanying drawings are intended to provide a further understanding of the technical solutions of the present disclosure and constitute part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of one or more components in the accompanying drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0039] FIG1 is a schematic structural diagram of a display device;

[0040] FIG2 is a schematic diagram of a planar structure of a display substrate;

[0041] FIG3 is a schematic diagram of a partial cross-sectional structure of a display substrate;

[0042] FIG4 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0043] FIG5 is an exemplary diagram of the working timing of the pixel circuit shown in FIG4 ;

[0044] FIG6 is a schematic planar structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0045] FIG7 is a schematic partial cross-sectional view along the QQ' direction in FIG6;

[0046] FIG8 is a schematic diagram of the display substrate after the semiconductor layer is formed in FIG6;

[0047] FIG9A is a schematic diagram of the display substrate after the first conductive layer is formed in FIG6 ;

[0048] FIG9B is a schematic diagram of the first conductive layer in FIG9A ;

[0049] FIG10A is a schematic diagram of the display substrate after forming the second conductive layer in FIG10 ;

[0050] FIG10B is a schematic diagram of the second conductive layer in FIG10A ;

[0051] FIG11 is a schematic diagram of the display substrate after forming the third insulating layer in FIG6 ;

[0052] FIG12A is a schematic diagram of the display substrate after forming the third conductive layer in FIG6 ;

[0053] FIG12B is a schematic diagram of the third conductive layer in FIG12A;

[0054] FIG13 is a schematic diagram of the display substrate after forming the fourth insulating layer in FIG6;

[0055] FIG14 is a schematic diagram of the fourth conductive layer in FIG6;

[0056] FIG15 is a schematic plan view of the structure of another display substrate according to at least one embodiment of the present disclosure;

[0057] FIG16A is a schematic diagram of the display substrate after the first conductive layer is formed in FIG15 ;

[0058] FIG16B is a schematic diagram of the first conductive layer in FIG16A ;

[0059] FIG17A is a schematic diagram of the display substrate after forming the second conductive layer in FIG15;

[0060] FIG17B is a schematic diagram of the second conductive layer in FIG17A;

[0061] FIG18 is a schematic diagram of the display substrate after the third insulating layer is formed in FIG15;

[0062] FIG19A is a schematic diagram of the display substrate after forming the third conductive layer in FIG15;

[0063] FIG19B is a schematic diagram of the third conductive layer in FIG19A ;

[0064] FIG20 is a schematic diagram of the display substrate after forming the fourth insulating layer in FIG15;

[0065] FIG21 is a schematic diagram of the fourth conductive layer in FIG15 ;

[0066] FIG22 is a schematic plan view of the structure of another display substrate according to at least one embodiment of the present disclosure;

[0067] FIG23 is a schematic diagram of the display substrate after the first conductive layer is formed in FIG22;

[0068] FIG24A is a schematic diagram of the display substrate after the second conductive layer is formed in FIG22;

[0069] FIG24B is a schematic diagram of the second conductive layer in FIG24A ;

[0070] FIG25 is a schematic diagram of the display substrate after the third insulating layer is formed in FIG22;

[0071] FIG26A is a schematic diagram of the display substrate after the third conductive layer is formed in FIG22;

[0072] FIG26B is a schematic diagram of the third conductive layer in FIG26A ;

[0073] FIG27 is a schematic diagram of the display substrate after forming the fourth insulating layer in FIG22;

[0074] FIG28 is a schematic diagram of the fourth conductive layer in FIG22;

[0075] FIG. 29 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.

[0076] Details

[0077] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the method and content can be transformed into other forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other in any manner.

[0078] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0079] In this specification, ordinal numbers such as "first," "second," and "third" are provided to avoid confusion among constituent elements, and are not intended to limit the number. "Multiple" in this disclosure means two or more.

[0080] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the orientation of the constituent elements being described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced depending on the circumstances.

[0081] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate piece, or a connection between the two elements. For those of ordinary skill in the art, the meanings of the above terms in this disclosure can be understood according to the circumstances. Among them, "electrical connection" includes the situation where constituent elements are connected together through an element with some electrical function. There is no special restriction on "elements with some electrical function" as long as they can transmit electrical signals between connected constituent elements. Examples of "elements with some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with one or more functions.

[0082] In this specification, a transistor refers to a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, channel region, and source. In this specification, the channel region refers to the region through which current primarily flows.

[0083] In this specification, to distinguish the two electrodes of a transistor other than the gate, one electrode is referred to as the first electrode, and the other electrode is referred to as the second electrode. The first electrode can be either the source or the drain, and the second electrode can be either the drain or the source. Furthermore, the gate of the transistor is referred to as the control electrode. The functions of "source" and "drain" are sometimes interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source" and "drain" can be interchanged.

[0084] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0085] In this specification, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0086] In the present disclosure, "about" and "substantially" are used without strict limits and allow for process and measurement errors. In the present disclosure, "substantially the same" means that the numerical values ​​differ by less than 10%.

[0087] In this disclosure, "A extends along direction B" means that A can include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions. In the following description, "A extends along direction B" means "the main portion of A extends along direction B."

[0088] Figure 1 is a schematic diagram of the structure of a display device. In some examples, as shown in Figure 1, the display device may include: a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller may be connected to the data driver, the scan driver, and the light-emitting driver, respectively. The data driver is respectively connected to a plurality of data signal lines (for example, D1 to Dr), the scan driver is respectively connected to a plurality of scan signal lines (for example, S1 to Sm), and the light-emitting driver is respectively connected to a plurality of light-emitting signal lines (for example, E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit, the circuit unit may include at least a pixel circuit, the pixel circuit may be respectively connected to the scan signal line, the light-emitting signal line, and the data signal line, the light-emitting unit may include a light-emitting device, and the light-emitting device may be electrically connected to the pixel circuit of the circuit unit.

[0089] In some examples, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, clock signals and scan start signals suitable for the specifications of the scan driver to the scan driver, and clock signals and emission stop signals suitable for the specifications of the light-emitting driver to the light-emitting driver. The data driver may use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to the data signal lines D1, D2, D3, ..., and Dr. For example, the data driver may use the clock signal to sample the grayscale values ​​and apply data voltages corresponding to the grayscale values ​​to the data signal lines D1 to Dr on a pixel row basis, where r can be a natural number. The scan driver may use the clock signal, scan start signal, etc. received from the timing controller to generate scan signals to be provided to the scan signal lines S1, S2, S3, ..., and Sm. For example, the scan driver may sequentially provide scan signals having on-horizontal pulses to the scan signal lines S1 to Sm, where m can be a natural number. For example, the scan driver can be constructed in the form of a shift register, and can generate a scan signal in a manner that sequentially transmits a scan start signal provided in the form of a conduction horizontal pulse to the next level circuit under the control of a clock signal, and m can be a natural number. The light-emitting driver can generate an emission signal to be provided to the light-emitting signal lines E1, E2, E3, ... and Eo by receiving a clock signal, an emission stop signal, etc. from a timing controller. For example, the light-emitting driver can sequentially provide an emission signal with a cut-off level pulse to the light-emitting signal lines E1 to Eo. For example, the light-emitting driver can be constructed in the form of a shift register, and can generate an emission signal in a manner that sequentially transmits an emission stop signal provided in the form of a cut-off level pulse to the next level circuit under the control of a clock signal, and o can be a natural number. In some examples, the pixel array can be provided on a display substrate.

[0090] Figure 2 is a schematic diagram of a planar structure of a display substrate. In some examples, the display substrate may include a display area and a border area located around the display area. As shown in Figure 2, the display area of ​​the display substrate may include a plurality of pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 that emits a first color light, a second sub-pixel P2 that emits a second color light, and a third sub-pixel P3 that emits a third color light. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel circuit. The pixel circuit may be electrically connected to a scan signal line, a data signal line, and a light-emitting signal line, respectively. The pixel circuit may be configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting unit. The light-emitting unit may include at least a light-emitting device. The light-emitting device may be electrically connected to the pixel circuit of the sub-pixel in which it is located. The light-emitting device may be configured to emit light of a corresponding brightness in response to the current output by the pixel circuit of the sub-pixel in which it is located.

[0091] In some examples, a pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may have a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. In the above circuit structure, T refers to a thin-film transistor, and C refers to a capacitor. The number before T represents the number of thin-film transistors in the circuit, and the number before C represents the number of capacitors in the circuit.

[0092] In some examples, the first sub-pixel P1 can be a red sub-pixel (R) that emits red light, the second sub-pixel P2 can be a blue sub-pixel (B) that emits blue light, and the third sub-pixel P3 can be a green sub-pixel (G) that emits green light. In some examples, the shape of the light-emitting device can be a rectangle, a rhombus, a pentagon, or a hexagon. When a pixel unit includes three sub-pixels, the light-emitting devices of the three sub-pixels can be arranged horizontally, vertically, or in a triangular pattern. When a pixel unit includes four sub-pixels, the light-emitting devices of the four sub-pixels can be arranged horizontally, vertically, or in a square pattern. However, this embodiment is not limited to this.

[0093] FIG3 is a schematic diagram of a partial cross-sectional structure of a display substrate. FIG3 illustrates the structure of three sub-pixels of the display substrate. In some examples, as shown in FIG3 , in a direction perpendicular to the display substrate, the display area of ​​the display substrate may include: a substrate 101, a driving circuit layer 102 disposed on the substrate 101, a light-emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on a side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer. This disclosure is not limited thereto.

[0094] In some examples, the substrate 101 may be a flexible substrate or a rigid substrate. The driving circuit layer 101 may include a plurality of circuit units, the circuit units may include at least pixel circuits, and the pixel circuits may include a plurality of transistors and at least one capacitor. The light-emitting structure layer 103 may include a plurality of light-emitting units, and the light-emitting units may include at least light-emitting devices. The encapsulation structure layer 104 may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer may be arranged between the first encapsulation layer and the third encapsulation layer to form a laminated structure of inorganic material / organic material / inorganic material, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0095] In some examples, the light-emitting device may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including mini-LED or micro-LED), etc. For example, the light-emitting device may be an OLED, and the light-emitting device may emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit. The color of the light emitted by the light-emitting device may be determined according to needs. In some examples, the light-emitting device may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting device may be electrically connected to the corresponding pixel circuit, the organic light-emitting layer may be connected to the anode, and the cathode may be connected to the organic light-emitting layer. The organic light-emitting layer may emit light of corresponding colors when driven by the anode and the cathode. However, this embodiment is not limited to this.

[0096] In some examples, the organic light-emitting layer may include an emitting layer (EML) and any one or more of the following layers: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0097] This embodiment provides a display substrate, comprising: a substrate; and a driving circuit layer disposed on the substrate, the driving circuit layer comprising at least a plurality of circuit units. At least one circuit unit comprises a pixel circuit. The pixel circuit comprises at least a first transistor, a second transistor, a third transistor, a fourth transistor, and a first capacitor. The gate electrode of the first transistor is electrically connected to a first scan signal line, the first electrode of the first transistor is electrically connected to a first initial signal line, and the second electrode of the first transistor is electrically connected to the gate electrode of the third transistor. The gate electrode of the second transistor is electrically connected to a second scan signal line, the first electrode of the second transistor is electrically connected to the gate electrode of the third transistor, and the second electrode of the second transistor is electrically connected to the second electrode of the third transistor. The gate electrode of the fourth transistor is electrically connected to a third scan signal line, the first electrode of the fourth transistor is electrically connected to a data signal line, and the second electrode of the fourth transistor is electrically connected to the second end of the first capacitor; the first end of the first capacitor is electrically connected to the gate electrode of the third transistor. The first initial signal line, the first scan signal line, and the second scan signal line extend in at least partially the same direction and are located on the same side of the first transistor, with the first initial signal line being located between the first scan signal line and the second scan signal line.

[0098] In the display substrate provided in this embodiment, the first transistor is configured to initialize the gate electrode of the third transistor (i.e., the first end of the first capacitor) using a first initialization signal provided by a first initialization signal line under the control of a first scan signal line. By arranging the first initialization signal line between the first scan signal line and the second scan signal line, the layout and wiring can be optimized, and the initialization path length of the first initialization signal can be reduced, thereby optimizing the initialization effect.

[0099] In some exemplary embodiments, the active layer of the first transistor may include: a first region, a second region, and a channel region located between the first region and the second region, and the first region of the active layer of the first transistor is connected to the first initial signal line. The driving circuit layer also includes: at least one first power line. The orthographic projection of the first power line on the substrate covers the orthographic projection of the first region of the active layer of the first transistor on the substrate. The orthographic projection of the first power line on the substrate may cover the orthographic projection of the connection position of the first region of the active layer of the first transistor and the first initial signal line on the substrate. In this example, by setting the first power line to shield the first region of the active layer of the first transistor connected to the first initial signal line, other signals can be prevented from affecting the first region of the active layer of the first transistor receiving the first initial signal, thereby ensuring the transmission accuracy of the first initial signal to ensure the initialization effect.

[0100] In some exemplary embodiments, the pixel circuit may further include: a second capacitor. The second capacitor includes at least: a second plate serving as the second end of the second capacitor and a fourth plate serving as the first end of the second capacitor, wherein the orthographic projection of the second plate on the substrate at least partially overlaps with the orthographic projection of the fourth plate on the substrate. The first capacitor includes at least a first plate serving as the first end of the first capacitor and a third plate serving as the second end of the first capacitor, wherein the orthographic projection of the first plate on the substrate at least partially overlaps with the orthographic projection of the third plate on the substrate. The fourth plate is connected to the first power line, the second plate is connected to the third plate, and the first plate serves as the gate electrode of the third transistor.

[0101] In some exemplary embodiments, a second plate connection line is provided on the third plate, extending toward the fourth plate, and a second groove is provided on the fourth plate, recessed away from the third plate. The second plate connection line can be disposed within the second groove, and the end of the second plate connection line distal from the third plate can be connected to the second plate via a via and a connecting electrode. The design structure of the third and fourth plates of this example can increase the distance between the first and fifth nodes of the pixel circuit and facilitate the arrangement of more space for lateral wiring.

[0102] In some exemplary embodiments, at least one circuit unit may further include: a first shielding electrode. The orthographic projection of the first shielding electrode on the substrate at least partially overlaps with the orthographic projection of the first active layer between the two gate electrodes of the first transistor in the present circuit unit on the substrate, and also at least partially overlaps with the orthographic projection of the second active layer between the two gate electrodes of the second transistor in the adjacent circuit unit on the substrate. In some examples, the first shielding electrode may include: a first shielding end and a second shielding end. The orthographic projection of the first shielding end on the substrate at least partially overlaps with the orthographic projection of the first active layer between the two gate electrodes of the first transistor in the present circuit unit on the substrate, and the first shielding end is electrically connected to the first power line. The orthographic projection of the second shielding end on the substrate at least partially overlaps with the orthographic projection of the second active layer between the two gate electrodes of the second transistor in the adjacent circuit unit on the substrate, and the second shielding end is electrically connected to the first power line. The structural design of the first shielding electrode in this example can improve signal crosstalk.

[0103] The display substrate of this embodiment is described below with reference to some examples.

[0104] FIG4 is an equivalent circuit diagram of a pixel circuit of at least one embodiment of the present disclosure. The pixel circuit of this example can be a 9T2C structure, which can include nine transistors (e.g., a first transistor T1 to a ninth transistor T9) and two capacitors (e.g., a first capacitor C1 and a second capacitor C2). The pixel circuit can be electrically connected to 12 signal lines (e.g., a first scan signal line GL1, a second scan signal line GL2, a third scan signal line GL3, a fourth scan signal line GL4, a first light-emitting signal line EM1, a second light-emitting signal line EM2, a first initial signal line INIT1, a second initial signal line INIT2, a first reference signal line REF1, a second reference signal line REF2, a data signal line DL, and a first power line VDD).

[0105] In some examples, as shown in FIG4 , the pixel circuit may include a first node N1, a second node N2, a third node N3, a fourth node N4, and a fifth node N5. The first node N1 may be connected to the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first end of the first capacitor C1, respectively. The second node N2 may be connected to the first electrode of the third transistor T3, the second electrode of the eighth transistor T8, and the second electrode of the fifth transistor T5, respectively. The third node N3 may be connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, respectively. The fourth node N4 may be connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, respectively. The fifth node N5 may be connected to the second electrode of the fourth transistor T4, the second electrode of the ninth transistor T9, the second end of the first capacitor C1, and the second end of the second capacitor C2, respectively. The fourth node N4 may also be connected to the anode of the light-emitting device EL.

[0106] In some examples, a first end (lower plate) of the first capacitor C1 is connected to the first node N1, and a second end (upper plate) of the first capacitor C1 is connected to the fifth node N5. A first end (upper plate) of the second capacitor C2 is connected to the first power line VDD, and a second end (lower plate) of the second capacitor C2 is connected to the fifth node N5.

[0107] In some examples, a gate electrode of the first transistor T1 is connected to a first scan signal line GL1, a first electrode of the first transistor T1 is connected to a first initialization signal line INIT1, and a second electrode of the first transistor is connected to a first node N1. When a turn-on signal is applied to the first scan signal line GL1, the first transistor T1 transmits a first initialization voltage to a gate electrode of the third transistor T3 and a first terminal of the first capacitor C1, thereby releasing charge accumulated in the first capacitor C1 and achieving initialization.

[0108] In some examples, a gate electrode of the second transistor T2 is coupled to the second scan signal line GL2, a first electrode of the second transistor T2 is coupled to the first node N1, and a second electrode of the second transistor T2 is coupled to the third node N3. When a turn-on signal is applied to the second scan signal line GL2, the second transistor T2 couples the gate electrode of the third transistor T3 to the second electrode.

[0109] In some examples, the gate electrode of the third transistor T3 is connected to the first node N1, that is, the gate electrode of the third transistor T3 is connected to the first end of the first capacitor C1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called a driving transistor, and the third transistor T3 determines the magnitude of the driving current based on the potential difference between its gate electrode and the first electrode.

[0110] In some examples, a gate electrode of the fourth transistor T4 is connected to the third scan signal line GL3, a first electrode of the fourth transistor T4 is connected to the data signal line DL, and a second electrode of the fourth transistor T4 is connected to the fifth node N5. When a turn-on signal is applied to the third scan signal line GL3, the fourth transistor T4 causes the data voltage of the data signal line DL to be input to the fifth node N5 (i.e., the second end of the first capacitor C1 and the second end of the second capacitor C2).

[0111] In some examples, a gate electrode of the fifth transistor T5 is connected to the first light emitting signal line EM1, a first electrode of the fifth transistor T5 is connected to the first power line VDD, and a second electrode of the fifth transistor T5 is connected to the second node N2. A gate electrode of the sixth transistor T6 is connected to the second light emitting signal line EM2, a first electrode of the sixth transistor T6 is connected to the third node N3, and a second electrode of the sixth transistor T6 is connected to the fourth node N4. When a turn-on signal is applied to the first light emitting signal line EM1 and the second light emitting signal line EM2, the fifth transistor T5 and the sixth transistor T6 form a drive current path between the first power line VDD and the second power line VSS, causing the light emitting device EL to emit light.

[0112] In some examples, a gate electrode of the seventh transistor T7 is connected to the fourth scan signal line GL4, a first electrode of the seventh transistor T7 is connected to the second initialization signal line INIT2, and a second electrode of the seventh transistor T7 is connected to the fourth node N4. When a turn-on signal is applied to the fourth scan signal line GL4, the seventh transistor T7 transmits the second initialization voltage to the first electrode of the light-emitting device EL, thereby releasing the charge accumulated in the first electrode of the light-emitting device EL and achieving initialization.

[0113] In some examples, a gate electrode of the eighth transistor T8 is connected to the fourth scan signal line GL4, a first electrode of the eighth transistor T8 is connected to the second reference signal line REF2, and a second electrode of the eighth transistor T8 is connected to the second node N2. When a turn-on signal is applied to the fourth scan signal line GL4, the eighth transistor T8 transmits the second reference signal to the second node N2.

[0114] In some examples, a gate electrode of the ninth transistor T9 is connected to the second scan signal line GL2, a first electrode of the ninth transistor T9 is connected to the first reference signal line REF1, and a second electrode of the ninth transistor T9 is connected to the fifth node N5. When a turn-on signal is applied to the second scan signal line GL2, the ninth transistor T9 transmits the first reference signal to the fifth node N5.

[0115] In some examples, the light-emitting device EL may be an OLED, including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or may be a QLED, including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode). The first electrode of the light-emitting device EL is connected to the fourth node N4, and the second electrode of the light-emitting device EL is connected to the second power line VSS. In some examples, the signal of the second power line VSS may be a continuously provided low-level signal, and the signal of the first power line VDD may be a continuously provided high-level signal.

[0116] In some examples, the first transistor T1 to the ninth transistor T9 of the pixel circuit may be a P-type transistor or an N-type transistor. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the ninth transistor T9 may include P-type transistors and N-type transistors.

[0117] In some examples, the first transistor T1 to the ninth transistor T9 of the pixel circuit may be a low-temperature polysilicon thin film transistor, or an oxide thin film transistor, or a low-temperature polysilicon thin film transistor and an oxide thin film transistor. The active layer of the low-temperature polysilicon thin film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin film transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, and oxide thin film transistors have the advantages of low leakage current. Integrating low-temperature polysilicon thin film transistors and oxide thin film transistors on a display substrate, i.e., an LTPS+Oxide (LTPO for short) display substrate, can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0118] Figure 5 is an example diagram of the operating timing of the pixel circuit shown in Figure 4. In some examples, taking the pixel circuit shown in Figure 4 where the first transistor T1 to the ninth transistor T9 are all P-type transistors, the operating process of the pixel circuit may include the following stages.

[0119] In the first phase S1, the signal on the first light-emitting signal line EM1 is a low-level signal, while the signals on the second light-emitting signal line EM2, the third scan signal line GL3, and the fourth scan signal line GL4 are high-level signals. The low-level signal on the first light-emitting signal line EM1 turns on the fifth transistor T5, and the first power signal on the first power line VDD is supplied to the second node N2. The high-level signals on the second light-emitting signal line EM2, the third scan signal line GL3, and the fourth scan signal line GL4 turn off the sixth transistor T6, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8.

[0120] The first phase S1 may include at least a first sub-phase S11, a second sub-phase S12, a third sub-phase S13, a fourth sub-phase S14, a fifth sub-phase S15, and a sixth sub-phase S16. In the first sub-phase S11, the signal on the first scan signal line GL1 is a low-level signal, turning on the first transistor T1; the signal on the second scan signal line GL2 is a high-level signal, turning off the second transistor T2 and the ninth transistor T9. The first transistor T1 is turned on, and the first initial signal on the first initial signal line INIT1 is provided to the first node N1, initializing the first node N1. In the second sub-phase S12, the signal on the first scan signal line GL1 is a high-level signal, turning off the first transistor T1; the signal on the second scan signal line GL2 is a low-level signal, turning on the second transistor T2 and the ninth transistor T9. The second transistor T2 is turned on, connecting the first node N1 and the third node N3, performing threshold compensation on the third transistor T3, and writing the threshold voltage of the third transistor T3 to the first node N1. The ninth transistor T9 is turned on, and the first reference signal of the first reference signal line REF1 can be provided to the fifth node N5, thereby initializing the fifth node N5. The third sub-stage S13 and the fifth sub-stage S15 are substantially the same as the first sub-stage S11. The fourth sub-stage S14 and the sixth sub-stage S16 are substantially the same as the second sub-stage S12, and therefore are not further described here.

[0121] When the driving transistor (i.e., the third transistor) is in one state for a long time, electrons are trapped in a trap, which causes hysteresis. Therefore, in this stage, performing the initialization and threshold voltage writing process on the first node N1 multiple times (e.g., three times) can reduce the hysteresis of the driving transistor and ensure the potential stability of the first node N1.

[0122] The second stage S2 can be called the data writing stage. The signals on the first emitting signal line EM1, the second emitting signal line EM2, the first scanning signal line GL1, the second scanning signal line GL2, and the fourth scanning signal line GL4 are high-level signals, turning off the fifth transistor T5, the sixth transistor T6, the first transistor T1, the ninth transistor T9, the second transistor T2, the seventh transistor T7, and the eighth transistor T8. The signal on the third scanning signal line GL3 is low-level, turning on the fourth transistor T4. The data voltage provided by the data signal line DL is written to the fifth node N5, and the data voltage is also written to the first node N1 via the first capacitor C1.

[0123] In the third stage S3, the signals on the first light-emitting signal line EM1, the second light-emitting signal line EM2, the first scan signal line GL1, the second scan signal line GL2, and the third scan signal line GL3 are high-level signals, turning off the fifth transistor T5, the sixth transistor T6, the first transistor T1, the second transistor T2, the ninth transistor T9, and the fourth transistor T4. The signal on the fourth scan signal line GL4 is low-level, turning on the seventh transistor T7 and the eighth transistor T8. When the seventh transistor T7 is turned on, the second initial signal on the second initial signal line INIT2 can be written to the fourth node N4. By initializing the fourth node N4, residual signals from the previous frame can be prevented from affecting the display of the current frame. The eighth transistor T8 is turned on, and the second reference signal on the second reference signal line REF2 can be written to the second node N2, helping to reduce hysteresis in the drive transistor.

[0124] In the fourth stage S4, the signals on the first light-emitting signal line EM1, the first scan signal line GL1, the second scan signal line GL2, the third scan signal line GL3, and the fourth scan signal line GL4 are high-level signals, turning off the fifth transistor T5, the first transistor T1, the second transistor T2, the ninth transistor T9, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8. The signal on the second light-emitting signal line EM2 is low-level, turning on the sixth transistor T6, connecting the third node N3 and the fourth node N4, so that the potential of the fourth node N4 is the same as that of the third node N3. Connecting the fourth node N4 and the third node N3 helps to increase the potential of the fourth node N4, thereby reducing the time required to reach the turn-on voltage of the light-emitting device.

[0125] In the fifth stage S5, the signals on the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are low-level signals, turning on the fifth transistor T5 and the sixth transistor T6. The first power signal on the first power line VDD can provide a driving signal to the light-emitting device EL via the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, thereby driving the light-emitting device EL to emit light. The signals on the first scan signal line GL1, the second scan signal line GL2, the third scan signal line GL3, and the fourth scan signal line GL4 are high-level signals, turning off the first transistor T1, the second transistor T2, the ninth transistor T9, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8.

[0126] The pixel circuit of this example can improve the hysteresis of the driving transistor, which is beneficial to improving the display effect.

[0127] Figure 6 is a schematic diagram of the planar structure of a display substrate according to at least one embodiment of the present disclosure. Figure 6 illustrates the structure of the pixel circuits in the three circuit units (i.e., the first circuit unit, the second circuit unit, and the third circuit unit) of the display substrate. Figure 7 is a schematic diagram of a partial cross-section taken along the Q-Q' direction in Figure 6.

[0128] In some examples, a display substrate may include: a driving circuit layer disposed on a base, and a light-emitting structure layer disposed on a side of the driving circuit layer away from the base. The driving circuit layer may include at least a plurality of circuit units, and the light-emitting structure layer may include at least a plurality of light-emitting units. At least one circuit unit may include a pixel circuit, and at least one light-emitting unit may include a light-emitting device. The light-emitting device may include at least an anode, an organic light-emitting layer, and a cathode. The anode of the light-emitting device may be connected to the pixel circuit in the corresponding circuit unit.

[0129] The term "circuit unit" as used herein refers to an area divided according to pixel circuits; the term "light-emitting unit" as used herein refers to an area divided according to light-emitting devices. In some examples, the position of the orthographic projection of the light-emitting unit on the substrate may correspond to the position of the orthographic projection of the circuit unit on the substrate, or the position of the orthographic projection of the light-emitting unit on the substrate may not correspond to the position of the orthographic projection of the circuit unit on the substrate.

[0130] In some examples, a plurality of circuit units sequentially arranged along a first direction X may be referred to as a unit row, and a plurality of circuit units sequentially arranged along a second direction Y may be referred to as a unit column. The plurality of unit rows and the plurality of unit columns may constitute an array of circuit units arranged in an array. The first direction X and the second direction Y may intersect, for example, the first direction X may be perpendicular to the second direction Y.

[0131] In some examples, as shown in Figures 6 and 7, in a direction perpendicular to the display substrate, the driving circuit layer may include: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer, sequentially disposed on the substrate 101. A first insulating layer 201 may be disposed between the semiconductor layer and the first conductive layer, a second insulating layer 202 may be disposed between the first and second conductive layers, a third insulating layer 203 may be disposed between the second and third conductive layers, and a fourth insulating layer 204 may be disposed between the third and fourth conductive layers. In some examples, the first insulating layer 201, the second insulating layer 202, and the third insulating layer 203 may be inorganic insulating layers, and the fourth insulating layer 204 may be an organic insulating layer. However, this embodiment is not limited to this. In other examples, a buffer layer may be disposed between the substrate and the semiconductor layer. In other examples, a passivation layer may be disposed between the third and fourth conductive layers, located on the side of the fourth insulating layer closer to the substrate.

[0132] In some examples, as shown in Figure 6, at least one pixel circuit may include a first transistor T1 as a first initialization transistor, a second transistor T2 as a compensation transistor, a third transistor T3 as a driving transistor, a fourth transistor T4 as a data writing transistor, a fifth transistor T5 as a first light-emitting control transistor, a sixth transistor T6 as a second light-emitting control transistor, a seventh transistor T7 as a second initialization transistor, an eighth transistor T8 as a second reference transistor, a ninth transistor T9 as a first reference transistor, a first capacitor, and a second capacitor.

[0133] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating, and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating, or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern".

[0134] As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0135] In some examples, taking three circuit units (ie, a first circuit unit, a second circuit unit, and a third circuit unit) in the nth unit row as an example, the preparation process of the display substrate of this embodiment may include the following operations.

[0136] (1-1) Forming a semiconductor layer. In some examples, a semiconductor thin film is deposited on a substrate and patterned using a patterning process to form a semiconductor layer, as shown in FIG8 . FIG8 is a schematic diagram of the display substrate after the semiconductor layer is formed in FIG6 .

[0137] In some examples, the semiconductor layer of each circuit unit in the display substrate may include at least a first active layer 11 of a first transistor T1, a second active layer 12 of a second transistor T2, a third active layer 13 of a third transistor T3, a fourth active layer 14 of a fourth transistor T4, a fifth active layer 15 of a fifth transistor T5, a sixth active layer 16 of a sixth transistor T6, a seventh active layer 17 of a seventh transistor T7, an eighth active layer 18 of an eighth transistor T8, and a ninth active layer 19 of a ninth transistor T9. The first to third active layers 11 to 13 and the fifth to eighth active layers 15 to 18 may be interconnected as an integral structure, and the fourth active layer 14 and the ninth active layer 19 may be interconnected as an integral structure.

[0138] In some examples, the fourth active layer 14 and the ninth active layer 19 of the nth unit row can be located on a side of the third active layer 13 close to the n-1th unit row, that is, the fourth active layer 14 and the ninth active layer 19 can be located on a side of the third active layer 13 of the circuit unit in the opposite direction of the second direction Y. The first active layer 11, the second active layer 12, and the fifth active layer 15 to the eighth active layer 18 of the nth unit row can be located on a side of the third active layer 13 close to the n+1th unit row, that is, the first active layer 11, the second active layer 12, and the fifth active layer 15 to the eighth active layer 18 can be located on a side of the third active layer 13 of the circuit unit in the second direction Y.

[0139] In some examples, the first active layer 11 may be located on one side of the third active layer 13 of the present circuit unit in the second direction Y, the fifth active layer 15 may be located on one side of the first active layer 11 of the present circuit unit in the second direction Y, and the eighth active layer 18 may be located on one side of the fifth active layer 15 of the present circuit unit in the second direction Y. The second active layer 12 may be located on one side of the third active layer 13 of the present circuit unit in the second direction Y, the sixth active layer 16 may be located on one side of the second active layer 12 of the present circuit unit in the second direction Y, and the seventh active layer 17 may be located on one side of the sixth active layer 16 of the present circuit unit in the second direction Y.

[0140] In some examples, the first active layer 11, the fourth active layer 14, the fifth active layer 15 and the eighth active layer 18 can be located on one side of the first direction X of the circuit unit (for example, on the side opposite to the first direction X), and the second active layer 12, the sixth active layer 16, the seventh active layer 17 and the ninth active layer 19 can be located on the other side of the first direction X of the circuit unit (for example, on one side of the first direction X).

[0141] In some examples, the shape of the first active layer 11 and the second active layer 12 can be roughly "L"-shaped, the shape of the third active layer 13 can be roughly "C"-shaped, the shape of the fourth active layer 14 and the ninth active layer 19 can be roughly "n"-shaped, and the shape of the fifth active layer 15, the sixth active layer 16, the seventh active layer 17 and the eighth active layer 18 can be roughly "I"-shaped.

[0142] In some examples, the active layer of each transistor can include a first region, a second region, and a channel region located between the first region and the second region. In some examples, the second region 112 of the first active layer 11 and the first region 121 of the second active layer 12 can be connected to each other, and the second region 112 of the first active layer 11 can serve as the first region 121 of the second active layer 12. The first region 131 of the third active layer 13, the second region 152 of the fifth active layer 15, and the second region 182 of the eighth active layer 18 can be connected to each other, and the first region 131 of the third active layer 13 can simultaneously serve as the second region 152 of the fifth active layer 15 and the second region 182 of the eighth active layer 18, forming a second node N2 of the pixel circuit. The second region 122 of the second active layer 12, the second region 132 of the third active layer 13, and the first region 161 of the sixth active layer 16 can be connected to each other. The second region 132 of the third active layer 13 can simultaneously serve as the second region 122 of the second active layer 12 and the first region 161 of the sixth active layer 16, forming a third node N3 of the pixel circuit. The second region 142 of the fourth active layer 14 and the second region 192 of the ninth active layer 19 can be connected to each other. The second region 142 of the fourth active layer 14 can serve as the second region 192 of the ninth active layer 19. The second region 162 of the sixth active layer 16 and the second region 172 of the seventh active layer 17 can be connected to each other. The second region 162 of the sixth active layer 16 can serve as the second region 172 of the seventh active layer 17, forming a fourth node N4 of the pixel circuit. The first region 111 of the first active layer 11, the first region 141 of the fourth active layer 14, the first region 151 of the fifth active layer 15, and the first region 181 of the eighth active layer 18 can be provided separately. The first region 141 of the fourth active layer 14 can be located on a side of the channel region of the fourth active layer 14 close to the third active layer 13, and the first region 191 of the ninth active layer 19 can be located on a side of the channel region of the ninth active layer 19 close to the third active layer 13.

[0143] In some examples, in at least one cell row, the semiconductor layers of adjacent circuit cells in the first direction X can be interconnected. For example, the semiconductor layer of the first circuit cell in the nth cell row can be connected to the semiconductor layer of the second circuit cell in the nth cell row, and the semiconductor layer of the second circuit cell in the nth cell row can be connected to the semiconductor layer of the third circuit cell in the nth cell row. In the nth cell row, the semiconductor layers of adjacent circuit cells in the first direction X can be connected via a first active connection line 10 and a second active connection line 20. For example, the first region 191 of the ninth active layer 19 of the ninth transistor T9 in adjacent circuit cells in the first direction X can be interconnected via the first active connection line 10, and the first region 171 of the seventh active layer 17 of the seventh transistor T7 can be interconnected via the second active connection line 20. The first active connection line 10 and the second active connection line 20 can extend at least along the first direction X. The first active connection line 10 can be located on a side of the fourth active layer 14 that is closer to the third active layer 13, and the second active connection line 20 can be located on a side of the eighth active layer 18 that is farther from the fifth active layer 15.

[0144] In some examples, the first active connection line 10 may be shaped like a zigzag line with a main portion extending along the first direction X. The first active connection line 10 and the ninth active layer 19 of the plurality of circuit units may be interconnected as an integral structure. Since the first region 191 of the ninth active layer 19 is connected to a subsequently formed first reference signal line, the first active connection line 10 can be reused as a first reference signal line extending along the first direction X. This not only ensures that the first regions 191 of the plurality of ninth active layers 19 in a unit row have the same potential, but also reduces the voltage drop of the first reference signal, thereby improving the uniformity of the substrate, avoiding display defects on the display substrate, and ensuring the display effect of the display substrate.

[0145] In some examples, the second active connection line 20 can be shaped as a straight line with a main portion extending along the first direction X. The second active connection line 20 and the seventh active layer 17 of multiple circuit units can be an integrated structure that is interconnected. Because the first region 171 of the seventh active layer 17 is connected to the subsequently formed second initial signal line, the second active connection line 20 can be reused as the second initial signal line extending along the first direction X. This not only ensures that the first regions 171 of multiple seventh active layers 17 in a unit row have the same potential, but also reduces the voltage drop of the second initial signal, which is beneficial to improving the uniformity of the substrate, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0146] In some examples, a first groove K1 may be formed between the edges of two adjacent first active connection lines 10 in the first direction X and the edge of the first region 191 of the ninth active layer 19. The first groove K1 may be configured to accommodate the first protrusion of the second electrode plate of the second capacitor, thereby increasing the space for disposing the second capacitor.

[0147] In some examples, in at least one cell column, semiconductor layers in adjacent circuit cells in the second direction Y may be spaced apart from each other. For example, the semiconductor layer of the first circuit cell in the (n-1)th cell row may not be connected to the semiconductor layer of the first circuit cell in the (n)th cell row, and the semiconductor layer of the first circuit cell in the (n)th cell row may not be connected to the semiconductor layer of the first circuit cell in the (n+1)th cell row.

[0148] (1-2) Forming a first conductive layer. In some examples, a first insulating film and a first conductive film are sequentially deposited on the substrate on which the aforementioned pattern is formed. The first conductive film is patterned by a patterning process to form a first insulating layer covering the semiconductor layer, and a first conductive layer disposed on the first insulating layer, as shown in Figures 9A and 9B. Figure 9A is a schematic diagram of the display substrate after the first conductive layer is formed in Figure 6. Figure 9B is a schematic diagram of the first conductive layer in Figure 9A. In some examples, the first conductive layer may also be referred to as a first gate metal (GATE1) layer.

[0149] In some examples, the first conductive layer of each circuit unit in the display substrate may include at least: a first gate electrode 21 of the first transistor T1, a second gate electrode 22 of the second transistor T2, a fourth gate electrode 24 of the fourth transistor T4, a fifth gate electrode 25 of the fifth transistor T5, a sixth gate electrode 26 of the sixth transistor T6, a ninth gate electrode 29 of the ninth transistor T9, a fourth scanning signal line 64, a first plate 71 of the first capacitor, and a second plate 72 of the second capacitor.

[0150] In some examples, the shape of the first gate electrode 21 can be roughly "L"-shaped, the first gate electrode 21 can be located on one side of the first plate 71 of the first capacitor in the second direction Y, and the area where the first gate electrode 21 overlaps with the first active layer can serve as the gate electrode of the first transistor T1 of the dual-gate structure.

[0151] In some examples, the shape of the second gate electrode 22 can be roughly "T"-shaped, the second gate electrode 22 can be located on one side of the first plate 71 of the first capacitor in the second direction Y, and the area where the second gate electrode 22 overlaps with the second active layer can serve as the gate electrode of the second transistor T2 of the dual-gate structure.

[0152] In some examples, the shape of the fourth gate electrode 24 can be roughly "L"-shaped, the fourth gate electrode 24 can be located on the side of the second plate 72 of the second capacitor in the opposite direction of the second direction Y, and the area where the fourth gate electrode 24 overlaps with the fourth active layer can serve as the gate electrode of the fourth transistor T4 of the dual-gate structure.

[0153] In some examples, the shape of the fifth gate electrode 25 can be roughly a strip shape extending along the second direction Y, the fifth gate electrode 25 can be located on one side of the first gate electrode 21 in the second direction Y, and the area where the fifth gate electrode 25 overlaps with the fifth active layer can serve as the gate electrode of the fifth transistor T5.

[0154] In some examples, the shape of the sixth gate electrode 26 can be roughly a strip shape extending along the first direction X, the sixth gate electrode 26 can be located on one side of the second gate electrode 22 in the second direction Y, and the area where the sixth gate electrode 26 overlaps with the sixth active layer can serve as the gate electrode of the sixth transistor T6.

[0155] In some examples, the shape of the ninth gate electrode 29 can be roughly a strip shape extending along the first direction X, the ninth gate electrode 29 can be located on the side of the second plate 72 of the second capacitor in the opposite direction of the second direction Y, and the area where the ninth gate electrode 29 overlaps with the ninth active layer can serve as the gate electrode of the ninth transistor T9 of the dual-gate structure.

[0156] In some examples, the fourth scan signal line 64 may be in the shape of a straight line with a main portion extending along the first direction X. The fourth scan signal line 64 may be located on one side of the fifth gate electrode 25 and the sixth gate electrode 26 in the second direction Y. The region where the fourth scan signal line 64 overlaps with the seventh active layer may serve as the gate electrode of the seventh transistor T7, and the region where the fourth scan signal line 64 overlaps with the eighth active layer may serve as the gate electrode of the eighth transistor T8.

[0157] In some examples, the shape of the first plate 71 of the first capacitor can be rectangular, the corners of the rectangle can be chamfered, the orthographic projection of the first plate 71 on the substrate and the orthographic projection of the third active layer of the third transistor T3 on the substrate can at least partially overlap, and the first plate 71 can serve as the lower plate of the first capacitor and the gate electrode of the third transistor T3 at the same time.

[0158] In some examples, the shape of the second plate 72 of the second capacitor can be rectangular, and the corners of the rectangle can be chamfered. The second plate 72 can be located on the side of the first plate 71 opposite to the second direction Y, and on the side of the fourth gate electrode 24 and the ninth gate electrode 29 in the second direction Y, that is, in the second direction Y, the second plate 72 can be located between the first plate 71 and the fourth gate electrode 24 (or the ninth gate electrode 29), and the orthographic projection of the second plate 72 on the substrate and the orthographic projection of the semiconductor layer on the substrate can not overlap. The second plate 72 can serve as the lower plate of the second capacitor. A first protrusion 72-1 is provided on the side of the second plate 72 near the ninth gate electrode 29. The shape of the first protrusion 72-1 can be roughly rectangular. The first end of the first protrusion 72-1 is connected to the second plate 72, and the second end extends toward the direction of the ninth gate electrode 29 and extends into the first groove K1. The second plate 72 and the first protrusion 72-1 can be an integrated structure connected to each other.

[0159] In some examples, the first side edge (e.g., right edge) of the first electrode plate 71 in the first direction X and the first side edge (e.g., right edge) of the second electrode plate 72 in the first direction X can be roughly aligned in the second direction Y, and the second side edge (e.g., left edge) of the first electrode plate 71 in the first direction X and the second side edge (e.g., left edge) of the second electrode plate 72 in the first direction X can be roughly aligned. The first side edge (e.g., right edge) of the first protrusion 72-1 in the first direction X can be flush with the first side edge (e.g., right edge) of the second electrode plate 72 in the first direction X in the second direction Y. The shape of the integrated structure formed by the second electrode plate 72 and the first protrusion 72-1 being connected to each other can be roughly "L"-shaped.

[0160] In some examples, the orthographic projection areas of the first electrode plate 71 and the second electrode plate 72 on the substrate may be the same or different. For example, the orthographic projection area of ​​the second electrode plate 72 on the substrate may be smaller than the orthographic projection area of ​​the first electrode plate 71 on the substrate.

[0161] In some examples, after forming the first conductive layer pattern, the first conductive layer can be used as a shield to perform conductorization on the semiconductor layer. The semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first transistor T1 to the ninth transistor T9, and the semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first and second areas of the first active layer 11 to the ninth active layer 19 and the first active connecting line 10 and the second active connecting line 20 can all be conductorized.

[0162] (1-3) Forming a second conductive layer. In some examples, a second insulating film and a second conductive film are sequentially deposited on the substrate on which the aforementioned pattern is formed. The second conductive film is patterned using a patterning process to form a second insulating layer covering the first conductive layer, and a second conductive layer disposed on the second insulating layer, as shown in Figures 10A and 10B. Figure 10A is a schematic diagram of the display substrate after the second conductive layer is formed in Figure 10. Figure 10B is a schematic diagram of the second conductive layer in Figure 10A. In some examples, the second conductive layer can be referred to as a second gate metal (GATE2) layer.

[0163] In some examples, the second conductive layer of each circuit unit in the display substrate may include at least: a first light-emitting signal line 31, a second light-emitting signal line 32, a repair line 33, a second reference signal line 35, a first shielding electrode 36, a second shielding electrode 37, a third shielding electrode 38, a third plate 73 of the first capacitor, and a fourth plate 74 of the second capacitor.

[0164] In some examples, the first lighting signal line 31 , the second lighting signal line 32 , the repair line 33 , and the second reference signal line 35 may be in the shape of a straight line with a main portion extending along the first direction X. The first lighting signal line 31 , the second lighting signal line 32 , and the repair line 33 may be located between the first gate electrode 21 and the fourth scanning signal line 64 , and the second reference signal line 35 may be located on a side of the fourth gate electrode 24 opposite to the second direction Y.

[0165] In some examples, the first light-emitting signal line 31 can be located on one side of the first gate electrode 21 of the circuit unit in the second direction Y, the second light-emitting signal line 32 can be located on one side of the first light-emitting signal line 31 in the second direction Y, and the repair line 33 can be located on one side of the second light-emitting signal line 32 in the second direction Y, that is, the second light-emitting signal line 32 can be located between the first light-emitting signal line 31 and the repair line 33.

[0166] In some examples, a first light-emitting connection block 31-1 may be provided on a side of the first light-emitting signal line 31 near the second light-emitting signal line 32. The first light-emitting connection block 31-1 may be provided in each circuit unit. A first end of the first light-emitting connection block 31-1 is connected to the first light-emitting signal line 31, and a second end of the first light-emitting connection block 31-1 extends toward the second light-emitting signal line 32. The first light-emitting connection block 31-1 may be configured to be connected to the fifth gate electrode 25 via a subsequently formed seventh connection electrode. In some examples, the first light-emitting signal line 31 and the plurality of first light-emitting connection blocks 31-1 may be an integrated structure connected to each other.

[0167] In some examples, a second light-emitting connection block 32-1 may be provided on a side of the second light-emitting signal line 32 adjacent to the first light-emitting signal line 31. The second light-emitting connection block 32-1 may be provided in each circuit unit. A first end of the second light-emitting connection block 32-1 is connected to the second light-emitting signal line 32, and a second end of the second light-emitting connection block 32-1 extends toward the first light-emitting signal line 31. The second light-emitting connection block 32-1 may be configured to be connected to the sixth gate electrode 26 via a subsequently formed eighth connection electrode. In some examples, the second light-emitting signal line 32 and the plurality of second light-emitting connection blocks 32-1 may be an interconnected, integrated structure.

[0168] In some examples, a second reference connection block 35-1 may be provided on a side of the second reference signal line 35 of the nth cell row away from the second electrode plate 72 of the nth cell row. The second reference connection block 35-1 may be provided in each circuit cell. A first end of the second reference connection block 35-1 is connected to the second reference signal line 35, and a second end of the second reference connection block 35-1 may extend away from the second electrode plate 72, i.e., toward the n-1th cell row. In some examples, the second reference connection block 35-1 of the second reference signal line 35 in the nth cell row is configured to connect to the first region of the eighth active layer in the n-1th cell row via a subsequently formed sixth connection electrode, thereby providing a second reference signal to the first electrode of the eighth transistor T8 in the n-1th cell row. In some examples, the second reference signal line 35 and the plurality of second reference connection blocks 35-1 may be an interconnected, integral structure.

[0169] In some examples, the contour shape of the third plate 73 of the first capacitor can be rectangular, and the corners of the rectangle can be chamfered. The third plate 73 can be located between the first light-emitting signal line 31 and the second reference signal line 35 of the circuit unit. The positive projection of the third plate 73 on the substrate and the positive projection of the first plate 71 on the substrate can at least partially overlap. The third plate 73 can serve as the upper plate of the first capacitor (i.e., the second end of the first capacitor C1). The first plate 71 and the third plate 73 can constitute the first capacitor C1 of the pixel circuit.

[0170] In some examples, the contour shape of the fourth plate 74 of the second capacitor can be rectangular, and the corners of the rectangle can be chamfered. The fourth plate 74 can be located between the second reference signal line 35 and the third plate 73 of the circuit unit. The positive projection of the fourth plate 74 on the substrate and the positive projection of the second plate 72 on the substrate can at least partially overlap. The fourth plate 74 can serve as the upper plate of the second capacitor (i.e., the first end of the second capacitor C2). The second plate 72 and the fourth plate 74 can constitute the second capacitor C2 of the pixel circuit.

[0171] In some examples, the orthographic projection areas of the third plate 73 and the fourth plate 74 on the substrate may be the same or different. For example, the orthographic projection area of ​​the fourth plate 74 on the substrate may be smaller than the orthographic projection area of ​​the third plate 73 on the substrate.

[0172] In some examples, a first plate connecting line 74-1 may be provided on one side of the fourth plate 74 in the first direction X or in the opposite direction of the first direction X. The first end of the first plate connecting line 74-1 is connected to the fourth plate 74 of the circuit unit, and the second end of the first plate connecting line 74-1 extends along the first direction X or in the opposite direction of the first direction X to connect to the fourth plate 74 of the adjacent circuit unit, so that the fourth plates 74 of adjacent circuit units in a unit row can be interconnected. In some examples, multiple fourth plates 74 and multiple first plate connecting lines 74-1 can be an integrated structure connected to each other. For example, the length of the first plate connecting line 74-1 along the second direction Y can be approximately the same as the length of the fourth plate 74 along the second direction Y. Since the fourth electrode plate 74 is connected to the first power line formed subsequently, the fourth electrode plate 74 of the integrated structure of multiple circuit units can be reused as a horizontal power line extending along the first direction X. This not only ensures that the multiple fourth electrodes 74 in a unit row have the same potential, but also reduces the voltage drop of the first power signal, which is beneficial to improving the uniformity of the display substrate, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0173] In some examples, a first opening 730 may be provided on the third electrode plate 73 of each circuit unit. The first opening 730 may be located in the middle of the third electrode plate 73. The first opening 730 may be rectangular, so that the third electrode plate 73 forms a ring structure. The first opening 730 may expose the second insulating layer covering the first electrode plate 71, and the orthographic projection of the first electrode plate 71 on the substrate may include the orthographic projection of the first opening 730 on the substrate. In some examples, the first opening 730 may be configured to accommodate a tenth via hole formed subsequently. The tenth via hole may be located within the first opening 730 and expose a portion of the surface of the first electrode plate 71, so that a first connecting electrode formed subsequently is connected to the first electrode plate 71.

[0174] In some examples, a second opening 740 may be provided on the fourth electrode plate 74 of each circuit unit. The second opening 740 may be located in the middle of the fourth electrode plate 74. The second opening 740 may be rectangular, so that the fourth electrode plate 74 forms a ring structure. The second opening 740 may expose the second insulating layer covering the second electrode plate 72, and the orthographic projection of the second electrode plate 72 on the substrate may include the orthographic projection of the second opening 740 on the substrate. In some examples, the second opening 740 may be configured to accommodate a subsequently formed eleventh via. The eleventh via may be located within the second opening 740 and expose a portion of the surface of the second electrode plate 72, so that a subsequently formed third connecting electrode is connected to the second electrode plate 72. In some examples, the second opening 740 is not aligned with the first opening 730 in the second direction Y.

[0175] In some examples, a second protrusion 74-2 may be provided on a side of the fourth electrode 74 near the second reference signal line 35, and the second protrusion 74-2 may be provided in each circuit unit. The second protrusion 74-2 may be located on a side of the second opening 740 opposite to the second direction Y. The first end of the second protrusion 74-2 is connected to the fourth electrode 74, and the second end of the second protrusion 74-2 extends in the direction of the second reference signal line 35. The orthographic projection of the second protrusion 74-2 on the substrate may be located between the first and second regions of the fourth active layer of this circuit unit. The second protrusion 74-2 of this example may be configured to shield the influence of the data voltage jump on the fifth node, thereby preventing the data voltage jump from affecting the normal operation of the pixel circuit and improving the display effect. In some examples, the fourth electrode 74 and the second protrusion 74-2 may be an integrated structure connected to each other.

[0176] In some examples, a third protrusion 74-3 may be provided on a side of the fourth electrode 74 near the second reference signal line 35. The third protrusion 74-3 may be provided in each circuit unit. The second protrusion 74-2 and the third protrusion 74-3 may be adjacent to each other in the first direction X. For example, the third protrusion 74-3 may be located on one side of the second protrusion 74-2 in the first direction X. The first end of the third protrusion 74-3 is connected to the fourth electrode 74, and the second end of the third protrusion 74-3 extends toward the second reference signal line 35 and into the first groove K1. The orthographic projection of the third protrusion 74-3 on the substrate may at least partially overlap with the orthographic projection of the first protrusion 72-1 of the second electrode 72 on the substrate, for example, the two may overlap with each other. For example, the length of the second protrusion 74-2 along the second direction Y can be greater than the length of the third protrusion 74-3 along the second direction Y, and the length of the second protrusion 74-2 along the first direction X can be less than the length of the third protrusion 74-3 along the first direction X. In this example, by providing the third protrusion 74-3 with at least a partial overlap of the first protrusion 74-1, the area of ​​the second capacitor can be increased, and the total capacity of the second capacitor can be effectively increased, thereby improving the operating performance of the pixel circuit and enhancing the display effect. In some examples, the fourth plate 74 and the third protrusion 74-3 can be an integrated structure connected to each other.

[0177] In some examples, the first shielding electrode 36 can be roughly T-shaped. The first shielding electrode 36 can be located on a side of the fourth electrode plate 74 that is close to the first light-emitting signal line 31. The first shielding electrode 36 can be provided in each circuit unit. The T-shaped first shielding electrode 36 can include a first extension segment 36-1 and a first shielding segment 36-2. The first end of the first extension segment 36-1 is connected to the fourth electrode plate 74, and the second end of the first extension segment 36-1 extends toward the first light-emitting signal line 31 and then connects to the first shielding segment 36-2. The first shielding segment 36-2 can be in the shape of a strip extending along the first direction X. The first shielding segment 36-2 can include a first shielding end located on one side of the first extension segment 36-1 in the first direction X, and a second shielding end located on a side of the first extension segment 36-1 opposite to the first direction X. The orthographic projection of the first shielding end on the substrate at least partially overlaps with the orthographic projection of the first active layer between the two gate electrodes of the first transistor T1 in this circuit unit on the substrate, and the orthographic projection of the second shielding end on the substrate at least partially overlaps with the orthographic projection of the second active layer between the two gate electrodes of the second transistor T2 in the adjacent circuit unit on the substrate. In some examples, the first shielding electrode 36 can be configured to shield the impact of data voltage jumps on the first transistor T1 and the second transistor T2, thereby preventing the data voltage jumps from affecting the normal operation of the pixel circuit and improving the display effect. In some examples, the fourth plate 74 and the first shielding electrode 36 can be an integrated structure that is interconnected.

[0178] In some examples, the orthographic projection of the first shielding end of the first shielding segment 36-2 on the substrate partially overlaps the orthographic projection of the first region of the third active layer 13 (also the second region of the fifth active layer and the second region of the eighth active layer) of the third transistor in the circuit unit on the substrate. Because the first region of the third active layer 13 (also the second region of the fifth active layer and the second region of the eighth active layer) is a conductor layer that has undergone a conductorization process, and the first shielding segment 36-2 is also a conductor layer, the first region of the third active layer 13 (also the second region of the fifth active layer and the second region of the eighth active layer) within a circuit unit and the first shielding end of the first shielding segment 36-2 of the first shielding electrode 36 of the circuit unit can form a first stabilizing capacitor. Because the first shielding electrode 36 can subsequently be connected to the first power supply line to receive a constant-voltage, stable first power supply signal, the first stabilizing capacitor can be configured to stabilize the potential of the second node N2, preventing signal crosstalk and the impact of data voltage jumps on the second node N2, thereby ensuring normal operation of the pixel circuit and improving display quality.

[0179] In some examples, the orthographic projection of the second shielding end of the first shielding segment 36-2 on the substrate partially overlaps the orthographic projection of the second region of the third active layer 13 (also the first region of the sixth active layer and the second region of the second active layer) of the third transistor in the adjacent circuit unit on the substrate. Because the second region of the third active layer 13 (also the first region of the sixth active layer and the second region of the second active layer) is a conductor layer that has undergone a conductorization process, and the first shielding segment 36-2 is also a conductor layer, the second region of the third active layer 13 (also the first region of the sixth active layer and the second region of the second active layer) in one circuit unit and the second shielding end of the first shielding segment 36-2 of the first shielding electrode 36 in the adjacent circuit unit can form a second stabilizing capacitor. Because the first shielding electrode 36 can subsequently be connected to the first power supply line to receive a constant-voltage, stable first power supply signal, the second stabilizing capacitor can be configured to stabilize the potential of the third node N3, preventing signal crosstalk and the impact of data voltage jumps on the third node N3, thereby ensuring normal operation of the pixel circuit and improving display quality.

[0180] In some examples, the second shielding electrode 37 and the third shielding electrode 38 can be rectangular in shape and can be located on a side of the second reference signal line 35 near the fourth plate 74. The second shielding electrode 37 and the third shielding electrode 38 can be provided in each circuit unit. The first ends of the second shielding electrode 37 and the third shielding electrode 38 are connected to the second reference signal line 35, and the second ends of the second shielding electrode 37 and the third shielding electrode 38 can extend toward the fourth plate 74. The orthographic projection of the second shielding electrode 37 on the substrate can at least partially overlap with the orthographic projection of the fourth active layer between the two gate electrodes of the fourth transistor T4 in this circuit unit. The orthographic projection of the third shielding electrode 38 on the substrate can at least partially overlap with the orthographic projection of the ninth active layer between the two gate electrodes of the ninth transistor T9 in this circuit unit. In some examples, the second shielding electrode 37 can be configured to shield the fourth transistor T4 from the effects of data voltage jumps, and the third shielding electrode 38 can be configured to shield the ninth transistor T9 from the effects of data voltage jumps, thereby preventing the data voltage jumps from affecting the normal operation of the pixel circuit and improving the display effect.

[0181] In some examples, the repair line 33 can be located on a side of the second light-emitting control line 32 away from the first light-emitting control line 31. For example, when a bright spot defect occurs on the display substrate, the repair line 33 can be configured to input a signal to the anode of the sub-pixel with the bright spot defect through the repair line 33 to repair the sub-pixel to a dark spot.

[0182] (1-4) Forming a third insulating layer. In some examples, a third insulating film is deposited on the substrate having the aforementioned pattern formed thereon, and the third insulating film is patterned using a patterning process to form a third insulating layer. The third insulating layer of each circuit unit is provided with a plurality of vias, as shown in FIG11 . FIG11 is a schematic diagram of the display substrate after the third insulating layer is formed in FIG6 .

[0183] In some examples, the multiple vias of each circuit unit in the display substrate may include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16, a seventeenth via V17, an eighteenth via V18, a nineteenth via V19, a twentieth via V20, a twenty-first via V21, and a twenty-second via V22.

[0184] In some examples, the orthographic projection of the first via V1 on the substrate can be located within the range of the orthographic projection of the first region of the first active layer on the substrate, the third insulating layer, the second insulating layer and the first insulating layer within the first via V1 can be etched away to expose a portion of the surface of the first region of the first active layer, and the first via V1 can be configured to connect a subsequently formed first initial signal line to the first region of the first active layer through the via.

[0185] In some examples, the orthographic projection of the second via V2 on the substrate can be located within the range of the orthographic projection of the second region of the first active layer (also the first region of the second active layer) on the substrate, the third insulating layer, the second insulating layer and the first insulating layer within the second via V2 can be etched away to expose a portion of the surface of the second region of the first active layer (also the first region of the second active layer), and the second via V2 can be configured to connect a subsequently formed first connecting electrode to the second region of the first active layer (also the first region of the second active layer) through the via.

[0186] In some examples, the orthographic projection of the third via V3 on the substrate can be within the range of the orthographic projection of the first region of the fourth active layer on the substrate, the third insulating layer, the second insulating layer and the first insulating layer within the third via V3 can be etched away to expose a portion of the surface of the first region of the fourth active layer, and the third via V3 can be configured to connect a subsequently formed second connecting electrode to the first region of the fourth active layer through the via.

[0187] In some examples, the orthographic projection of the fourth via V4 on the substrate can be located within the range of the orthographic projection of the second region of the fourth active layer (also the second region of the ninth active layer) on the substrate, the third insulating layer, the second insulating layer and the first insulating layer within the fourth via V4 can be etched away to expose a portion of the surface of the second region of the fourth active layer (also the second region of the ninth active layer), and the fourth via V4 can be configured to connect a subsequently formed third connecting electrode to the second region of the fourth active layer (also the second region of the ninth active layer) through the via.

[0188] In some examples, the orthographic projection of the fifth via V5 on the substrate can be located within the range of the orthographic projection of the first region of the fifth active layer on the substrate, the third insulating layer, the second insulating layer and the first insulating layer within the fifth via V5 can be etched away to expose a portion of the surface of the first region of the fifth active layer, and the fifth via V5 can be configured to connect a subsequently formed fourth connecting electrode to the first region of the fifth active layer through the via.

[0189] In some examples, the orthographic projection of the sixth via V6 on the substrate can be located within the range of the orthographic projection of the second region of the sixth active layer (also the second region of the seventh active layer) on the substrate, the third insulating layer, the second insulating layer and the first insulating layer within the sixth via V6 can be etched away to expose a portion of the surface of the second region of the sixth active layer (also the second region of the seventh active layer), and the sixth via V6 can be configured to connect a subsequently formed fifth connecting electrode to the second region of the sixth active layer (also the second region of the seventh active layer) through the via.

[0190] In some examples, the orthographic projection of the seventh via V7 on the substrate can be located within the range of the orthographic projection of the first region of the seventh active layer on the substrate, the third insulating layer, the second insulating layer and the first insulating layer within the seventh via V7 can be etched away to expose a portion of the surface of the first region of the seventh active layer, and the seventh via V7 can be configured to connect a subsequently formed second initial signal line to the first region of the seventh active layer through the via.

[0191] In some examples, the orthographic projection of the eighth via V8 on the substrate can be located within the range of the orthographic projection of the first region of the eighth active layer on the substrate, the third insulating layer, the second insulating layer and the first insulating layer within the eighth via V8 can be etched away to expose a portion of the surface of the first region of the eighth active layer, and the eighth via V8 can be configured to connect a subsequently formed sixth connecting electrode to the first region of the eighth active layer through the via.

[0192] In some examples, the orthographic projection of the ninth via V9 on the substrate can be located within the range of the orthographic projection of the first region of the ninth active layer on the substrate, the third insulating layer, the second insulating layer and the first insulating layer within the ninth via V9 can be etched away to expose a portion of the surface of the first region of the ninth active layer, and the ninth via V9 can be configured to connect a subsequently formed first reference signal line to the first region of the ninth active layer through the via.

[0193] In some examples, the orthographic projection of the tenth via V10 on the substrate can be located within the range of the orthographic projection of the first opening 730 of the third electrode 73 on the substrate, the third insulating layer and the second insulating layer in the tenth via V10 can be etched away to expose a portion of the surface of the first electrode 71, and the tenth via V10 can be configured to connect a subsequently formed first connecting electrode to the first electrode 71 through the via.

[0194] In some examples, the orthographic projection of the eleventh via V11 on the substrate can be located within the range of the orthographic projection of the second opening 740 of the fourth electrode 74 on the substrate, the third insulating layer and the second insulating layer within the eleventh via V11 can be etched away to expose a portion of the surface of the second electrode 72, and the eleventh via V11 is configured to connect a subsequently formed third connecting electrode to the second electrode 72 through the via.

[0195] In some examples, the orthographic projection of the twelfth via V12 on the substrate can be located within the range of the orthographic projection of the third electrode plate 73 on the substrate, the third insulating layer in the twelfth via V12 can be etched away to expose a portion of the surface of the third electrode plate 73, and the twelfth via V12 can be configured to connect a subsequently formed third connecting electrode to the third electrode plate 73 through the via.

[0196] In some examples, the orthographic projection of the thirteenth via V13 on the substrate can be located within the range of the orthographic projection of the fourth electrode plate 74 on the substrate, the third insulating layer in the thirteenth via V13 can be etched away to expose a portion of the surface of the fourth electrode plate 74, and the thirteenth via V13 can be configured to connect a subsequently formed first power connection line to the fourth electrode plate 74 through the via.

[0197] In some examples, the orthographic projection of the fourteenth via V14 on the substrate can be located within the range of the orthographic projection of the first gate electrode 21 on the substrate, the third insulating layer and the second insulating layer in the fourteenth via V14 can be etched away to expose a portion of the surface of the first gate electrode 21, and the fourteenth via V14 can be configured to connect a subsequently formed first scanning signal line to the first gate electrode 21 through the via.

[0198] In some examples, the orthographic projection of the fifteenth via V15 on the substrate can be located within the range of the orthographic projection of the second gate electrode 22 on the substrate, the third insulating layer and the second insulating layer in the fifteenth via V15 can be etched away to expose a portion of the surface of the second gate electrode 22, and the fifteenth via V15 can be configured to connect a subsequently formed second scanning signal line to the second gate electrode 22 through the via.

[0199] In some examples, the orthographic projection of the sixteenth via V16 on the substrate can be located within the range of the orthographic projection of the fourth gate electrode 24 on the substrate, the third insulating layer and the second insulating layer in the sixteenth via V16 can be etched away to expose a portion of the surface of the fourth gate electrode 24, and the sixteenth via V16 can be configured to connect the subsequently formed third scan signal line to the fourth gate electrode 24 through the via.

[0200] In some examples, the orthographic projection of the seventeenth via V17 on the substrate can be located within the range of the orthographic projection of the fifth gate electrode 25 on the substrate, the third insulating layer and the second insulating layer in the seventeenth via V17 can be etched away to expose a portion of the surface of the fifth gate electrode 25, and the seventeenth via V17 can be configured to connect the subsequently formed seventh connecting electrode to the fifth gate electrode 25 through the via.

[0201] In some examples, the orthographic projection of the eighteenth via V18 on the substrate can be located within the range of the orthographic projection of the sixth gate electrode 26 on the substrate, the third insulating layer and the second insulating layer in the eighteenth via V18 can be etched away to expose a portion of the surface of the sixth gate electrode 26, and the eighteenth via V18 can be configured to connect the subsequently formed eighth connecting electrode to the sixth gate electrode 26 through the via.

[0202] In some examples, the orthographic projection of the nineteenth via V19 on the substrate can be located within the range of the orthographic projection of the ninth gate electrode 29 on the substrate, the third insulating layer and the second insulating layer in the nineteenth via V19 can be etched away to expose a portion of the surface of the ninth gate electrode 29, and the nineteenth via V19 can be configured to connect the subsequently formed fifth scanning signal line to the ninth gate electrode 29 through the via.

[0203] In some examples, the orthographic projection of the twentieth via V20 on the substrate can be located within the range of the orthographic projection of the first light-emitting connection block 31-1 of the first light-emitting signal line 31 on the substrate, the third insulating layer in the twentieth via V20 can be etched away to expose at least a portion of the surface of the first light-emitting connection block 31-1, and the twentieth via V20 can be configured to connect the subsequently formed seventh connection electrode to the first light-emitting connection block 31-1 through the via.

[0204] In some examples, the orthographic projection of the twenty-first via V21 on the substrate can be located within the range of the orthographic projection of the second light-emitting connection block 32-1 of the second light-emitting signal line 32 on the substrate, the third insulating layer in the twenty-first via V21 can be etched away to expose at least a portion of the surface of the second light-emitting connection block 32-1, and the twenty-first via V21 can be configured to connect the subsequently formed eighth connection electrode to the second light-emitting connection block 32-1 through the via.

[0205] In some examples, the orthographic projection of the twenty-second via V22 on the substrate can be located within the range of the orthographic projection of the second reference connection block 35-1 of the second reference signal line 35 on the substrate, the third insulating layer in the twenty-second via V22 is etched away to expose the surface of the second reference connection block 35-1, and the twenty-second via V22 can be configured to connect the subsequently formed sixth connection electrode to the second reference connection block 35-1 through the via.

[0206] (1-5) Forming a third conductive layer. In some examples, a third conductive film is deposited on the substrate having the aforementioned pattern formed thereon, and the third conductive film is patterned using a patterning process to form a third conductive layer disposed on the third insulating layer, as shown in Figures 12A and 12B. Figure 12A is a schematic diagram of the display substrate after the third conductive layer is formed in Figure 6. Figure 12B is a schematic diagram of the third conductive layer in Figure 12A. In some examples, the third conductive layer can be referred to as a first source / drain metal (SD1) layer.

[0207] In some examples, the third conductive layer of multiple circuit units in the display substrate can include: a first connecting electrode 41, a second connecting electrode 42, a third connecting electrode 43, a fourth connecting electrode 44, a fifth connecting electrode 45, a sixth connecting electrode 46, a seventh connecting electrode 47, an eighth connecting electrode 48, a first scanning signal line 61, a second scanning signal line 62, a third scanning signal line 63, a fifth scanning signal line 65, a first power connection line 66, a first initial signal line 81, a second initial signal line 82 and a first reference signal line 34.

[0208] In some examples, the first scan signal line 61, the second scan signal line 62, the third scan signal line 63, the fifth scan signal line 65, the first initial signal line 81, the second initial signal line 82, and the first reference signal line 34 may be in the shape of a straight line with a main portion extending along the first direction X. The first power connection line 66 may be in the shape of a broken line with a main portion extending along the first direction X. The third scan signal line 63, the fifth scan signal line 65, and the first reference signal line 34 may be located on a side of the fourth electrode plate 74 opposite to the second direction Y, the first scan signal line 61, the second scan signal line 62, the first initial signal line 81, and the second initial signal line 82 may be located on a side of the third electrode plate 73 in the second direction Y, and the first power connection line 66 may be located in the region where the third electrode plate 73 is located.

[0209] In some examples, the first reference signal line 34 can be located on the side of the fourth electrode 74 in the opposite direction of the second direction Y, the fifth scanning signal line 65 can be located on the side of the first reference signal line 34 in the opposite direction of the second direction Y, and the third scanning signal line 63 can be located on the side of the fifth scanning signal line 65 in the opposite direction of the second direction Y.

[0210] In some examples, the first scan signal line 61 may be located on one side of the third electrode plate 73 in the second direction Y, the first initial signal line 81 may be located on one side of the first scan signal line 61 in the second direction Y, the second scan signal line 62 may be located on one side of the first initial signal line 81 in the second direction Y, and the second initial signal line 82 may be located on one side of the second scan signal line 62 in the second direction Y. The first initial signal line 81 may be located between the first scan signal line 61 and the second scan signal line 62.

[0211] In this example, by arranging the first initial signal line 81 in the third conductive layer, the resistance of the first initial signal line 81 can be reduced, thereby ensuring the transmission effect of the first initial signal. By arranging the first initial signal line 81 between the first scanning signal line 61 and the second scanning signal line 62, the distance between the first initial signal line 81 and the channel region of the first active layer of the first transistor T1 can be reduced. The first initial signal line 81 can provide the first initial signal for initialization processing to the first transistor T1 via the shortest path, thereby facilitating the reduction of the length of the first region of the first active layer, reducing the load on the first initial signal line, and optimizing the initialization effect.

[0212] In this example, by setting the second scanning signal line 62 and the first initial signal line 81 to be of the same layer structure, and the second scanning signal line 62 is located on the side of the first initial signal line 81 away from the first scanning signal line 61, the overlapping capacitance between the second scanning signal line 62 and the first initial signal line 81 can be reduced, and the load of the second scanning signal line 62 can be reduced, thereby reducing the driving load of the scanning driver connected to the second scanning signal line 62.

[0213] In this example, the first light-emitting signal line 31 can be located on one side of the second scanning signal line 62 and the first initial signal line 81 in the second direction Y, and the second light-emitting signal line 31 and the second scanning signal line 62 and the first initial signal line 81 may not overlap in their positive projections on the substrate, thereby reducing the overlapping capacitance between the first light-emitting signal line 31 and the first initial signal line 81 and reducing the load of the first light-emitting signal line 31, thereby reducing the driving load of the light-emitting driver to which the first light-emitting signal line 31 is connected.

[0214] In some examples, the first power connection line 66 can be located on the side of the fourth electrode 74 close to the third electrode 73, and the orthographic projection of the first power connection line 66 on the substrate can partially overlap with the orthographic projection of the third electrode 73 on the substrate. The first power connection line 66 can be configured to be connected to the first power line formed subsequently to form a high-voltage power grid structure with a mesh-like interconnected structure on the display substrate.

[0215] In some examples, the fifth scan signal line 65 can be connected to the ninth gate electrode 29 in each circuit unit through the nineteenth via V19, thereby realizing that the fifth scan signal line 65 is connected to the ninth gate electrode 29 of the ninth transistor T9, and the fifth scan signal line 65 can control the conduction and disconnection of the ninth transistor T9.

[0216] In some examples, the second scan signal line 62 can be connected to the second gate electrode 22 in each circuit unit through the fifteenth via V15, thereby realizing that the second scan signal line 62 is connected to the second gate electrode 22 of the second transistor T2, and the second scan signal line 62 can control the conduction and disconnection of the second transistor T2.

[0217] In some examples, the second scan signal line 62 and the fifth scan signal line 65 can extend to the border area and be connected to the same gate drive circuit to output the same scan signal, that is, the second scan signal line 62 and the fifth scan signal line 65 output the same second scan signal.

[0218] In some examples, the first scan signal line 61 can be connected to the first gate electrode 21 in each circuit unit through the fourteenth via V14, thereby realizing that the first scan signal line 61 is connected to the first gate electrode 21 of the first transistor T1, and the first scan signal line 61 can control the conduction and disconnection of the first transistor T1.

[0219] In some examples, the third scan signal line 63 can be connected to the fourth gate electrode 24 in each circuit unit through the sixteenth via V16, thereby realizing that the third scan signal line 63 is connected to the fourth gate electrode 24 of the fourth transistor T4, and the third scan signal line 63 can control the conduction and disconnection of the fourth transistor T4.

[0220] In some examples, the first initial signal line 81 can be connected to the first region of the first active layer in each circuit unit through the first via V1, thereby realizing that the first initial signal line 81 is connected to the first electrode of the first transistor T1, and the first initial signal line 81 can write the first initial signal into the first electrode of the first transistor T1.

[0221] In some examples, the second initial signal line 82 can be connected to the first region of the seventh active layer in each circuit unit through the seventh via V7, thereby realizing that the second initial signal line 82 is connected to the first electrode of the seventh transistor T7, and the second initial signal line 82 can write the second initial signal into the first electrode of the seventh transistor T7.

[0222] In some examples, a second initial connection block 82-1 may be provided on a side of the second initial signal line 82 adjacent to the second scan signal line 62. The second initial connection block 82-1 may be located between two adjacent circuit units within at least one unit row. A first end of the second initial connection block 82-1 is connected to the second initial signal line 82, and a second end of the second initial connection block 82-1 extends toward the second scan signal line 62. The second initial connection block 82-1 may be configured to connect to a subsequently formed initial signal connection line.

[0223] In some examples, the first reference signal line 34 can be connected to the first region of the ninth active layer in each circuit unit through the ninth via V9, thereby realizing that the first reference signal line 34 is connected to the first electrode of the ninth transistor T9, and the first reference signal line 34 can write the first reference signal into the first electrode of the ninth transistor T9.

[0224] In some examples, a first reference connection block 34-1 may be provided on a side of the first reference signal line 34 close to the first power connection line 66, a first end of the first reference connection block 34-1 is connected to the first reference signal line 34, and a second end of the first reference connection block 34-1 extends toward the direction of the first power connection line 66, and the first reference connection block 34-1 may be configured to be connected to a reference signal connection line formed subsequently.

[0225] In some examples, the first power connection line 66 can be connected to the fourth electrode plate 74 in each circuit unit through the thirteenth via V13, thereby achieving the connection between the first power connection line 66 and the fourth electrode plate 74. Because the first power connection line 66 is connected to the first power line formed later, the first power connection line 66 can write the first power signal to the upper electrode plate of the second capacitor (i.e., the first end of the second capacitor).

[0226] In some examples, a first power connection block 66-1 may be provided on a side of the first power connection line 66 away from the first scan signal line 61. A first end of the first power connection block 66-1 is connected to the first power connection line 66, and a second end of the first power connection block 66-1 extends in a direction away from the first scan signal line 61. In some examples, the first power connection block 66-1 may be configured to be connected to the fourth electrode plate 74 through the thirteenth via V13, and may also be configured to be connected to a first power line formed subsequently.

[0227] In some examples, the first connection electrode 41 can be shaped like a strip with a main portion extending along the second direction Y. The first connection electrode 41 can be located between the first scan signal line 61 and the first power connection line 66. The first end of the first connection electrode 41 can be connected to the second region of the first active layer (also the first region of the second active layer) through the second via V2, and the second end of the first connection electrode 41 can be connected to the first electrode plate 71 through the tenth via V10. In some examples, the first connection electrode 41 can cause the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first electrode plate 71 of the first capacitor (i.e., the first end of the first capacitor) to have the same potential. The first connection electrode 41 can serve as the first node N1 of the pixel circuit.

[0228] In some examples, the second connection electrode 42 can be substantially rectangular in shape and can be located between the first reference signal line 34 and the first power connection line 66. The second connection electrode 42 can be connected to the first region of the fourth active layer through a third via V3. In some examples, the second connection electrode 42 can serve as a first electrode of the fourth transistor T4 and be configured to be connected to a subsequently formed data signal line.

[0229] In some examples, the third connection electrode 43 may be shaped like a zigzag line with a main portion extending along the second direction Y. The third connection electrode 43 may be located between the first reference signal line 34 and the first power connection line 66. The first end of the third connection electrode 43 may be connected to the second region of the fourth active layer (also the second region of the ninth active layer) through a fourth via V4, the second end of the third connection electrode 43 may be connected to the third electrode plate 73 through a twelfth via V12, and the third end between the first and second ends may be connected to the second electrode plate 72 through an eleventh via V11. In some examples, the third connection electrode 43 may enable the second electrode of the fourth transistor T4, the second electrode of the ninth transistor T9, the third electrode plate 73 of the first capacitor (i.e., the second end of the first capacitor), and the second electrode plate 72 of the second capacitor (i.e., the second end of the second capacitor) to have the same potential. The third connection electrode 43 may serve as the fifth node N5 of the pixel circuit.

[0230] In some examples, the fourth connection electrode 44 can be substantially rectangular in shape and can be located between the second scan signal line 62 and the second initial signal line 82. The fourth connection electrode 44 can be connected to the first region of the fifth active layer through a fifth via V5. In some examples, the fourth connection electrode 44 can serve as a first electrode of a fifth transistor T5 and be configured to be connected to a first power line formed subsequently.

[0231] In some examples, the fifth connection electrode 45 can be substantially L-shaped and can be located between the second scan signal line 62 and the second initial signal line 82. The fifth connection electrode 45 can be connected to the second region of the sixth active layer (also the second region of the seventh active layer) through a sixth via V6. In some examples, the fifth connection electrode 45 can serve as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 and be configured to be connected to a subsequently formed anode connection electrode.

[0232] In some examples, the sixth connection electrode 46 can be shaped like a strip with a main portion extending along the first direction X. The sixth connection electrode 46 can be located between the second scan signal line 62 and the second initial signal line 82. A first end of the sixth connection electrode 46 can be connected to the first region of the eighth active layer via an eighth via V8, and a second end of the sixth connection electrode 46 can be connected to the second reference connection block 35-1 via a twenty-second via V22. In some examples, the sixth connection electrode 46 can serve as the first electrode of the eighth transistor T8. Since the second reference connection block 35-1 is connected to the second reference signal line 35, the second reference signal line 35 is connected to the first electrode of the eighth transistor T8. The second reference signal line 35 in the nth cell row can write the second reference signal to the first electrode of the eighth transistor T8 in the (n-1)th cell row.

[0233] In some examples, the seventh connection electrode 47 can be shaped like a bar with a main portion extending along the first direction X. The seventh connection electrode 47 can be located between the second scan signal line 62 and the second initial signal line 82. The first end of the seventh connection electrode 47 can be connected to the fifth gate electrode 25 via a seventeenth via hole V17, and the second end of the seventh connection electrode 47 can be connected to the first light-emitting connection block 31-1 via a twentieth via hole V20. Since the first light-emitting connection block 31-1 is connected to the first light-emitting signal line 31, the first light-emitting signal line 31 is connected to the fifth gate electrode 25 of the fifth transistor T5. The first light-emitting signal line 31 can control the conduction and disconnection of the fifth transistor T5.

[0234] In some examples, the eighth connection electrode 48 may be in the shape of a bar with a main portion extending along the first direction X. The eighth connection electrode 48 may be located between the second scan signal line 62 and the second initial signal line 82. A first end of the eighth connection electrode 48 may be connected to the sixth gate electrode 26 via an eighteenth via hole V18, and a second end of the eighth connection electrode 48 may be connected to the second light-emitting connection block 32-1 via a twenty-first via hole V21. Since the second light-emitting connection block 32-1 is connected to the second light-emitting signal line 32, the second light-emitting signal line 32 is connected to the sixth gate electrode 26 of the sixth transistor T6. The second light-emitting signal line 32 can control the conduction and disconnection of the sixth transistor T6.

[0235] (1-6) Forming a fourth insulating layer. In some examples, a fourth insulating film is coated on the substrate having the aforementioned pattern formed thereon, and the fourth insulating film is patterned using a patterning process to form a fourth insulating layer covering the third conductive layer. The fourth insulating layer in each circuit unit can be provided with multiple vias, as shown in FIG13 . FIG13 is a schematic diagram of the display substrate after the fourth insulating layer is formed in FIG6 . In some examples, the fourth insulating layer can also be referred to as a first planar layer.

[0236] In some examples, the plurality of vias of each circuit unit in the display substrate may include at least a thirty-first via V31 , a thirty-second via V32 , a thirty-third via V33 , a thirty-fourth via V34 , and a thirty-fifth via V35 .

[0237] In some examples, the orthographic projection of the thirty-first via V31 on the substrate can be within the range of the orthographic projection of the second connecting electrode 42 on the substrate, the fourth insulating layer in the thirty-first via V31 can be removed to expose a portion of the surface of the second connecting electrode 42, and the thirty-first via V31 can be configured to connect a subsequently formed data signal line to the second connecting electrode 42 through the via.

[0238] In some examples, the orthographic projection of the thirty-second via V32 on the substrate can be within the range of the orthographic projection of the fourth connecting electrode 44 on the substrate, the fourth insulating layer in the thirty-second via V32 can be removed to expose a portion of the surface of the fourth connecting electrode 44, and the thirty-second via V32 can be configured to connect a subsequently formed first power line to the fourth connecting electrode 44 through the via.

[0239] In some examples, the orthographic projection of the thirty-third via V33 on the substrate can be within the range of the orthographic projection of the fifth connecting electrode 45 on the substrate, the fourth insulating layer in the thirty-third via V33 can be removed to expose a portion of the surface of the fifth connecting electrode 45, and the thirty-third via V33 can be configured to connect a subsequently formed anode connecting electrode to the fifth connecting electrode 45 through the via.

[0240] In some examples, the orthographic projection of the thirty-fourth via V34 on the substrate can be located within the range of the orthographic projection of the first reference connection block 34-1 of the first reference signal line 34 on the substrate, the fourth insulating layer in the thirty-fourth via V34 can be removed to expose a portion of the surface of the first reference connection block 34-1, and the thirty-fourth via V34 can be configured to connect a subsequently formed reference signal connection line to the first reference connection block 34-1 through the via.

[0241] In some examples, the orthographic projection of the thirty-fifth via V35 on the substrate can be located within the range of the orthographic projection of the first power connection block 66-1 of the first power connection line 66 on the substrate, the fourth insulating layer in the thirty-fifth via V35 can be removed to expose a portion of the surface of the first power connection block 66-1, and the thirty-fifth via V35 can be configured to connect the subsequently formed first power line to the first power connection block 66-1 through the via.

[0242] In some examples, at least one circuit unit may further include a thirty-sixth via V36. The orthographic projection of the thirty-sixth via V36 on the substrate may be located within the orthographic projection of the second initial connection block 82-1 of the second initial signal line 82 on the substrate. The fourth insulating layer within the thirty-sixth via V36 is removed, exposing a portion of the surface of the second initial connection block 82-1. The thirty-sixth via V36 may be configured to connect a subsequently formed initial signal connection line to the second initial connection block 82-1 through the via. In some examples, the thirty-sixth via V36 may be located between the first circuit unit and the second circuit unit.

[0243] (1-7) Forming a fourth conductive layer. In some examples, a fourth conductive film is deposited on the substrate having the aforementioned pattern formed thereon, and the fourth conductive film is patterned using a patterning process to form a fourth conductive layer disposed on the fourth insulating layer, as shown in FIG14 . FIG14 is a schematic diagram of the fourth conductive layer in FIG6 . In some examples, the fourth conductive layer can be referred to as a second source / drain metal (SD2) layer.

[0244] In some examples, the fourth conductive layer of the plurality of circuit units in the display substrate may include: a data signal line 51 , a first power line 52 , a reference signal connection line 53 , and an anode connection electrode 55 .

[0245] In some examples, the data signal line 51 , the first power line 52 , and the reference signal connection line 53 may be in the shape of a bar with a main portion extending along the second direction Y. The first power line 52 may be located on one side of the data signal line 51 in the first direction X, and the reference signal connection line 53 may be located on one side of the first power line 52 in the first direction X, that is, the first power line 52 may be located between the data signal line 51 and the reference signal connection line 53 .

[0246] In some examples, the data signal line 51 may be in the shape of a straight line with a main portion extending along the second direction Y. The data signal line 51 may be connected to the second connection electrode 42 through a thirty-first via hole V31. Since the second connection electrode 42 may be connected to the first region of the fourth active layer through the via hole, the data signal line 51 can write the data signal into the first electrode of the fourth transistor T4.

[0247] In some examples, the first power line 52 can be shaped like a zigzag line with a main portion extending along the second direction Y. The first power line 52 can be connected to the fourth connection electrode 44 via the thirty-second via V32 and to the first power connection block 66-1 via the thirty-fifth via V35. Because the fourth connection electrode 44 is connected to the first region of the fifth active layer via the via, the first power line 52 writes the first power signal to the first electrode of the fifth transistor T5. Because the first power connection block 66-1 is connected to the first power connection line 66, the first power connection line 66, whose main portion extends along the first direction X, is interconnected with the first power line 52, whose main portion extends along the second direction Y. This allows the first power lines 52 and 66 to form a mesh structure on the display substrate for transmitting the first power signal. This effectively reduces the resistance of the first power line 52 and the voltage drop of the first power signal, and also effectively improves the uniformity of the first power signal across the display substrate, thereby enhancing display uniformity and improving display quality.

[0248] In some examples, a power shielding block 52-1 is provided on one side of the first power line 52 near the reference signal connection line 53. The first end of the power shielding block 52-1 is connected to the first power line 52, and the second end of the power shielding block 52-1 extends toward the reference signal connection line 53. The shape of the power shielding block 52-1 can be roughly rectangular, and the orthographic projection of the power shielding block 52-1 on the substrate can cover the orthographic projection of the first connection electrode 41 on the substrate. Since the first connection electrode 41 serves as the first node N1 in the pixel circuit, the constant voltage power shielding block 52-1 can effectively shield the influence of other signals in the pixel circuit on the first node N1, preventing other signals (such as data voltage jumps) from affecting the potential of the first node N1 of the pixel circuit, thereby improving the display effect. In some examples, the first power line 52 and the power shielding block 52-1 can be an integrated structure connected to each other.

[0249] In some examples, a second power connection block 52-2 is provided on a side of the first power line 52 near the reference signal connection 53. The second power connection block 52-2 can be located on a side of the power shielding block 52-1 opposite to the second direction Y. The shape of the second power connection block 52-2 can be roughly rectangular, and the orthographic projection of the second power connection block 52-2 on the substrate can at least partially overlap with the orthographic projection of the fourth electrode plate 74 on the substrate. The second power connection block 52-2 can be connected to the first power connection block 66-1 through the thirty-fifth via V35 to achieve the connection between the first power line 52 and the first power connection line 66. The length of the second power connection block 52-2 along the second direction Y can be less than the length of the power shielding block 52-1 along the second direction Y, and the length of the second power connection block 52-2 along the first direction Y can be roughly the same as the length of the power shielding block 52-1 along the first direction X. This embodiment is not limited to this.

[0250] In some examples, the orthographic projection of the first power line 52 on the substrate can at least partially overlap the orthographic projection of the third connection electrode 43 on the substrate. For example, the orthographic projection of the first power line 52 on the substrate can cover the orthographic projection of the third connection electrode 43 on the substrate. Because the third connection electrode 43 serves as the fifth node N5 in the pixel circuit, the constant voltage first power line 52 can effectively shield the influence of other signals in the pixel circuit on the fifth node N5, preventing other signals from affecting the potential of the fifth node N5 of the pixel circuit, thereby improving the display effect.

[0251] In some examples, the orthographic projection of the first power line 52 on the substrate can overlap the orthographic projection of the first region of the first active layer of the first transistor T1 on the substrate. Specifically, the orthographic projection of the first power line 52 on the substrate can overlap the orthographic projection of the connection position between the first region of the first active layer of the first transistor T1 and the first initial signal line 81 on the substrate. By providing the first power line 52 to shield the first region of the first active layer of the first transistor T1 connected to the first initial signal line 81, other signals can be prevented from affecting the reception of the first initial signal by the first region of the first active layer of the first transistor T1, thereby ensuring the transmission accuracy of the first initial signal and ensuring the initialization effect.

[0252] In some examples, the first power lines 52 may be designed with unequal widths. The unequal width design of the first power lines 52 not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the first power lines 52 and the data signal lines 51 .

[0253] In some examples, the reference signal connection line 53 may be shaped as a straight line with a main portion extending along the second direction Y. The reference signal connection line 53 may be connected to the first reference connection block 34-1 via a thirty-fourth via V34. Since the first reference connection block 34-1 is connected to the first reference signal line 34, the first reference signal line 34, whose main portion extends along the first direction X, and the reference signal connection line 53, whose main portion extends along the second direction Y, are interconnected. This allows the first reference signal line 34 and the reference signal connection line 53 to form a mesh structure on the display substrate for transmitting the first reference signal. This effectively reduces the resistance of the first reference signal line and the voltage drop of the first reference signal, and also effectively improves the uniformity of the first reference signal across the display substrate, thereby enhancing display uniformity and improving both display quality and display quality.

[0254] In some examples, the shape of the anode connection electrode 55 can be roughly rectangular. The anode connection electrode 55 can be located between the first power line 52 and the reference signal connection line 53. The anode connection electrode 55 can be connected to the fifth connection electrode 45 through the thirty-third via V33. Since the fifth connection electrode 45 is connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) through the via, the anode connection electrode 55 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. In some examples, the anode connection electrode 55 can be configured to be connected to an anode formed subsequently, thereby enabling the pixel circuit to drive the light-emitting device.

[0255] In some examples, the orthographic projection of the anode connection electrode 55 on the substrate may at least partially overlap with the orthographic projection of the anode repair line 33 on the substrate.

[0256] In some examples, at least one circuit unit may further include an initial signal connection line 54. The initial signal connection line 54 may be shaped as a straight line with a main portion extending along the second direction Y. The initial signal connection line 54 may be connected to the second initial connection block 82-1 via the thirty-sixth via V36. Since the second initial connection block 82-1 is connected to the second initial signal line 82, the second initial signal line 82, whose main portion extends along the first direction X, and the initial signal connection line 54, whose main portion extends along the second direction Y, are interconnected. This allows the initial signal connection line 54 and the second initial signal line 82 to form a mesh structure on the display substrate for transmitting the second initial signal. This not only effectively reduces the resistance of the second initial signal line 82 and the voltage drop of the second initial signal, but also effectively improves the uniformity of the second initial signal across the display substrate, effectively improving display uniformity and enhancing display quality. In some examples, the initial signal connection line 54 may be located between the reference signal connection line 53 of the first circuit unit and the data signal line 51 of the second circuit unit.

[0257] In some examples, the first power connection line 66 of the third conductive layer can be set in each unit row, the first power line 52 of the fourth conductive layer can be set in each unit column, and multiple first power lines 52 can be respectively connected to multiple first power connection lines 66 to form a mesh structure for transmitting the first power signal.

[0258] In some examples, the first reference signal line 34 of the third conductive layer can be set in each unit row, and the reference signal connection line 53 of the fourth conductive layer can be set in each unit column. Multiple first reference signal lines 34 are respectively connected to multiple reference signal connection lines 53 to form a mesh structure for transmitting the first reference signal.

[0259] In some examples, the second initial signal line 82 of the third conductive layer can be set in each unit row, and the initial signal connection line 54 of the fourth conductive layer can be set every two unit columns. Multiple second initial signal lines 82 are respectively connected to multiple initial signal connection lines 54 to form a mesh structure for transmitting the second initial signal.

[0260] The subsequent preparation process may include forming a second flat layer pattern, a plurality of anode vias are provided on the second flat layer, the orthographic projection of the anode vias on the substrate may be located within the range of the orthographic projection of the anode connecting electrode on the substrate, the second flat layer in the anode via is removed to expose at least a portion of the surface of the anode connecting electrode, and the anode via is configured to connect a subsequently formed anode to the anode connecting electrode through the via.

[0261] At this point, the driving circuit layer of this embodiment is prepared on the substrate. In some exemplary embodiments, after the driving circuit layer is prepared, a light emitting structure layer and an encapsulation structure layer can be sequentially prepared on the driving circuit layer, which will not be repeated here.

[0262] In some examples, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may be, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In some examples, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The material of the semiconductor layer may be amorphous silicon (a-Si).

[0263] In some examples, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, Ti / Al / Ti, etc. For example, the first conductive layer and the second conductive layer can be made of a single layer of molybdenum metal, and the third conductive layer and the fourth conductive layer can be made of a three-layer stacked structure of Ti / Al / Ti. The resistivity of the traces of the third conductive layer and the fourth conductive layer can be less than the resistivity of the traces of the first conductive layer and the second conductive layer.

[0264] In some examples, the first insulating layer 201, the second insulating layer 202, and the third insulating layer 203 can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, a multilayer, or a composite layer. The first insulating layer 201 and the second insulating layer 202 can also be referred to as a gate insulating (GI) layer, and the third insulating layer 203 can also be referred to as an interlayer insulating (ILD) layer. The fourth insulating layer 204 can also be referred to as a first planar layer. The fourth insulating layer 204 and the second planar layer can be made of organic materials, such as polyimide, acrylic, or polyethylene terephthalate. The active layer can be made of materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, or polythiophene. In other words, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology, or organic technology.

[0265] The structure of the display substrate and its preparation process in this embodiment are merely illustrative. In some examples, the corresponding structure can be modified and patterning processes can be added or removed as needed. The preparation process in this example can be implemented using currently available manufacturing equipment and is well compatible with existing manufacturing processes. The process is simple to implement, easy to implement, and has high production efficiency, low production costs, and a high yield rate.

[0266] Figure 15 is a schematic planar structural diagram of another display substrate according to at least one embodiment of the present disclosure. Figure 15 illustrates the structure of pixel circuits in three circuit units (i.e., the first circuit unit, the second circuit unit, and the third circuit unit) in the display substrate.

[0267] In some examples, the first power lines 52 extending along the second direction Y are interconnected with the first power connection lines 66 extending along the first direction X, forming a mesh structure for transmitting the first power signal. The second power lines 56 extending along the second direction Y are interconnected with the second power connection lines 67 extending along the first direction X, forming a mesh structure for transmitting the second power signal. The reference signal connection lines 53 extending along the second direction Y are interconnected with the first reference signal lines 34 extending along the first direction X, forming a mesh structure for transmitting the first reference signal.

[0268] In some examples, the third plate 73 of the first capacitor is provided with a second plate connecting line 73-1 extending toward the fourth plate 74 of the second capacitor. The fourth plate 74 is provided with a second groove K2 that is recessed away from the third plate 73. The second plate connecting line 73-1 is disposed within the second groove K2, and the end of the second plate connecting line 73-1 away from the third plate 73 can be connected to the second plate 72 through a via and a connecting electrode. The plate structure design of the first capacitor and the second capacitor in this example can increase the distance between the first node N1 and the fifth node N5, and can increase the arrangement space of the lateral wiring.

[0269] In some examples, at least one circuit unit may further include a first shielding electrode 36. The first shielding electrode 36 may include a first shielding end and a second shielding end. The orthographic projection of the first shielding end on the substrate at least partially overlaps with the orthographic projection of the first active layer between the two gate electrodes of the first transistor in the circuit unit on the substrate, and the first shielding end is electrically connected to the first power line 52 connected to the pixel circuit of the circuit unit. The orthographic projection of the second shielding end on the substrate at least partially overlaps with the orthographic projection of the second active layer between the two gate electrodes of the second transistor in the adjacent circuit unit on the substrate, and the second shielding end is electrically connected to the first power line 52 connected to the pixel circuit of the adjacent circuit unit.

[0270] In some examples, the preparation process of the display substrate of this example may include the following operations.

[0271] (2-1) Forming a semiconductor layer. In some examples, a semiconductor thin film is deposited on a substrate and patterned using a patterning process to form a semiconductor layer, as shown in FIG16A . FIG16A is a schematic diagram of the display substrate after the first conductive layer is formed in FIG15 . The structure of the semiconductor layer of the display substrate in this example is the same as that of the display substrate in the previous embodiment, and therefore will not be further described here.

[0272] (2-2) Forming a first conductive layer. In some examples, a first insulating film and a first conductive film are sequentially deposited on the substrate having the aforementioned pattern formed thereon. The first conductive film is patterned using a patterning process to form a first insulating layer covering the semiconductor layer and a first conductive layer disposed on the first insulating layer, as shown in Figures 16A and 16B. Figure 16B is a schematic diagram of the first conductive layer in Figure 16A.

[0273] In some examples, the first conductive layer of each circuit unit in the display substrate may include at least: a first gate electrode 21 of the first transistor T1, a second gate electrode 22 of the second transistor T2, a fourth gate electrode 24 of the fourth transistor T4, a fifth gate electrode 25 of the fifth transistor T5, a sixth gate electrode 26 of the sixth transistor T6, a ninth gate electrode 29 of the ninth transistor T9, a fourth scanning signal line 64, a first plate 71 of the first capacitor, and a second plate 72 of the second capacitor.

[0274] In some examples, the shape of the second plate 72 of the second capacitor 72 can be rectangular, and the corners of the rectangle can be chamfered. A first protrusion 72-1 can be provided on the side of the second plate 72 near the ninth gate electrode 29. The first end of the first protrusion 72-1 is connected to the second plate 72, and the second end extends toward the ninth gate electrode 29 and extends into the first groove formed in the semiconductor layer. The first side edge (e.g., the right edge) of the first plate 71 in the first direction X and the first side edge (e.g., the right edge) of the second plate 72 in the first direction X can be offset in the second direction Y. For example, the right edge of the second plate 72 in the first direction X can be located on one side of the right edge of the first plate 71 in the first direction X in the first direction X. The second side edge (e.g., the left edge) of the first plate 71 in the first direction X and the second side edge (e.g., the left edge) of the second plate 72 in the first direction X can be offset. For example, the left edge of the second plate in the first direction X can be located on one side of the left edge of the first plate 71 in the first direction X in the first direction X. The first side edge (e.g., right edge) of the first protrusion 72-1 in the first direction X may be misaligned with the first side edge (e.g., right edge) of the second electrode plate 72 in the first direction X in the second direction Y. For example, the right edge of the second electrode plate 72 in the first direction X may be located on one side of the right edge of the first protrusion 72-1 in the first direction X. The shape of the integrated structure formed by the second electrode plate 72 and the first protrusion 72-1 being connected to each other may be substantially T-shaped.

[0275] The rest of the structure of the first conductive layer of the display substrate of this example is substantially the same as that of the first conductive layer of the display substrate of the aforementioned embodiment, and thus will not be described again here.

[0276] (2-3) Forming a second conductive layer. In some examples, a second insulating film and a second conductive film are sequentially deposited on the substrate having the aforementioned pattern formed thereon. The second conductive film is patterned using a patterning process to form a second insulating layer covering the first conductive layer and a second conductive layer disposed on the second insulating layer, as shown in Figures 17A and 17B. Figure 17A is a schematic diagram of the display substrate after the second conductive layer is formed in Figure 15. Figure 17B is a schematic diagram of the second conductive layer in Figure 17A.

[0277] In some examples, the second conductive layer of each circuit unit in the display substrate may include at least: a first light-emitting signal line 31, a second light-emitting signal line 32, a repair line 33, a second reference signal line 35, a first shielding electrode 36, a second shielding electrode 37, a third shielding electrode 38, a third plate 73 of the first capacitor, and a fourth plate 74 of the second capacitor.

[0278] In some examples, the third plate 73 of the first capacitor can have a rectangular outline, and the corners of the rectangle can be chamfered. The third plate 73 can be located between the second reference signal line 35 and the first shielding electrode 36 of the circuit unit. A second plate connection line 73-1 can be provided on a side of the third plate 73 close to the fourth plate 74. The first end of the second plate connection line 73-1 is connected to the third plate 73, and the second end of the second plate connection line 73-1 extends toward the second reference signal line 35. The second plate connection line 73-1 can be configured to be connected to the second region of the fourth active layer (also the second region of the ninth active layer) via a subsequently formed third connection electrode, so that the second electrode of the fourth transistor T4, the second electrode of the ninth transistor T9, and the third plate 73 have the same potential.

[0279] In some examples, a first plate connecting line 74-1 may be provided on one side of the fourth plate 74 in the first direction X or in the direction opposite to the first direction X. The first end of the first plate connecting line 74-1 is connected to the fourth plate 74 of the current circuit unit, and the second end of the first plate connecting line 74-1 extends along the first direction X or in the direction opposite to the first direction X to connect to the fourth plate 74 of an adjacent circuit unit, thereby interconnecting the fourth plates 74 of adjacent circuit units in a unit row. In some examples, the length of the first plate connecting line 74-1 in the second direction Y may be less than the length of the fourth plate 74 in the second direction Y.

[0280] In some examples, a second groove K2 may be formed between the edges of two adjacent fourth plates 74 in the first direction X and the edge of the first plate connection line 74-1. The second groove K2 may be configured to accommodate the second plate connection line 73-1. The second plate connection line 73-1 on the third plate 73 extends within the second groove K2 toward the second reference signal line 35, so that the subsequently formed twelfth via hole can be moved as high as possible and as close as possible to the second region of the fourth active layer (i.e., the second region of the ninth active layer). The twelfth via hole may be configured to connect the subsequently formed third connection electrode to the second plate connection line 73-1 through the via hole. The third connection electrode can also be connected to the second region of the fourth active layer (i.e., the second region of the ninth active layer) and the second plate 72 through the via hole, so that the second electrode of the fourth transistor T4, the second electrode of the ninth transistor T9, the second plate 72, and the third plate 73 have the same potential.

[0281] In some examples, the shape of the first shielding electrode 36 can be a strip extending along the first direction X, and the first shielding electrode 36 can be located on a side of the third electrode plate 73 close to the first light-emitting signal line 31. The first shielding electrode 36 can be provided in each circuit unit. The first shielding electrode 36 can include a first shielding end and a second shielding end. The orthographic projection of the first shielding end on the substrate at least partially overlaps with the orthographic projection of the first active layer between the two gate electrodes of the first transistor T1 in the present circuit unit on the substrate, and the orthographic projection of the second shielding end on the substrate at least partially overlaps with the orthographic projection of the second active layer between the two gate electrodes of the second transistor T2 in the adjacent circuit unit on the substrate. In an exemplary embodiment, the first shielding electrode 36 can be configured to shield the influence of the data voltage jump on the first transistor T1 and the second transistor T2, thereby preventing the data voltage jump from affecting the normal operation of the pixel circuit and improving the display effect.

[0282] In some examples, the orthographic projection of the first shielding end of the first shielding electrode 36 on the substrate partially overlaps with the orthographic projection of the first region of the third active layer 13 (also the second region of the fifth active layer and the second region of the eighth active layer) of the third transistor in the circuit unit on the substrate. Since the first region of the third active layer 13 (also the second region of the fifth active layer and the second region of the eighth active layer) is a conductor layer that has been subjected to a conductorization process, and the first shielding electrode 36 is also a conductor layer, the first region of the third active layer 13 (also the second region of the fifth active layer and the second region of the eighth active layer) within a circuit unit and the first shielding end of the first shielding electrode 36 of the circuit unit can form a first voltage-stabilizing capacitor. Since the first shielding electrode 36 can subsequently be connected to the first power supply connection line to receive a constant-voltage stable first power supply signal, the first voltage-stabilizing capacitor can be configured to stabilize the potential of the second node N2, thereby preventing signal crosstalk and avoiding the impact of data voltage jumps on the second node N2, thereby ensuring the normal operation of the pixel circuit and improving the display effect.

[0283] In some examples, the orthographic projection of the second shielding end of the first shielding electrode 36 on the substrate partially overlaps with the orthographic projection of the second region of the third active layer 13 (also the first region of the sixth active layer and the second region of the second active layer) of the third transistor in the adjacent circuit unit on the substrate. Since the second region of the third active layer 13 (also the first region of the sixth active layer and the second region of the second active layer) is a conductor layer that has been subjected to a conductorization process, and the first shielding electrode 36 is also a conductor layer, the second region of the third active layer 13 (also the first region of the sixth active layer and the second region of the second active layer) within a circuit unit and the second shielding end of the first shielding electrode 36 of the adjacent circuit unit can form a second stabilizing capacitor. Since the first shielding electrode 36 can subsequently be connected to the first power supply connection line to receive a constant-voltage stable first power supply signal, the second stabilizing capacitor can be configured to stabilize the potential of the third node N3, thereby preventing signal crosstalk and avoiding the impact of data voltage jumps on the third node N3, thereby ensuring the normal operation of the pixel circuit and improving the display effect.

[0284] In some examples, the fourth plate 74 and the first shielding electrode 36 are spaced apart from each other, that is, there may be no direct connection between the fourth plate 74 and the first shielding electrode 36. Adjacent first shielding electrodes 36 may be spaced apart from each other.

[0285] Compared to the previous embodiment, this example eliminates the interconnected integral structure of the fourth plate 74 and the first shield electrode 36. This reduces the parasitic capacitance between the second node N2 and the third node N3 and the first power supply signal, thereby improving signal crosstalk. Furthermore, the shape of the fourth plate 74 can be flexibly designed to increase the distance between the first node and the fifth node, thereby increasing the space for lateral wiring.

[0286] The rest of the structure of the second conductive layer of the display substrate of this example is substantially the same as that of the second conductive layer of the display substrate of the aforementioned embodiment, and thus will not be described again here.

[0287] (2-4) Forming a third insulating layer. In some examples, a third insulating film is deposited on the substrate having the aforementioned pattern formed thereon. The third insulating film is patterned using a patterning process to form a third insulating layer. The third insulating layer of each circuit unit is provided with a plurality of vias, as shown in FIG18 . FIG18 is a schematic diagram of the display substrate after the third insulating layer is formed in FIG15 .

[0288] In some examples, the multiple vias of each circuit unit in the display substrate may include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16, a seventeenth via V17, an eighteenth via V18, a nineteenth via V19, a twentieth via V20, a twenty-first via V21, a twenty-second via V22, a twenty-third via V23, a twenty-fourth via V24, and a twenty-fifth via V25.

[0289] In some examples, the orthographic projection of the twenty-third via V23 on the substrate can be located within the range of the orthographic projection of the second electrode connecting line 73-1 of the third electrode 73 on the substrate, the third insulating layer in the twenty-third via V23 can be etched away to expose a portion of the surface of the second electrode connecting line 73-1, and the twenty-third via V23 can be configured to connect a subsequently formed third connecting electrode to the third electrode 73 through the via.

[0290] In some examples, the orthographic projection of the twenty-fourth via V24 on the substrate can be located within the range of the orthographic projection of the first shielding end of the first shielding electrode 36 of the present circuit unit on the substrate, the third insulating layer within the twenty-fourth via V24 can be etched away to expose a portion of the surface of the first shielding end of the first shielding electrode 36, and the twenty-fourth via V24 can be configured to connect the subsequently formed ninth connecting electrode to the first shielding electrode 36 of the present circuit unit through the via.

[0291] In some examples, the orthographic projection of the twenty-fifth via V25 on the substrate can be located within the range of the orthographic projection of the second shielding end of the first shielding electrode 36 of the adjacent circuit unit on the substrate, the third insulating layer within the twenty-fifth via V25 can be etched away to expose a portion of the surface of the second shielding end of the first shielding electrode 36 of the adjacent circuit unit, and the twenty-fifth via V25 can be configured to connect the subsequently formed tenth connecting electrode to the first shielding electrode 36 of the adjacent circuit unit through the via.

[0292] The rest of the structure of the third insulating layer of the display substrate of this example is substantially the same as that of the third insulating layer of the display substrate of the aforementioned embodiment, and thus will not be described again here.

[0293] (2-5) Forming a third conductive layer. In some examples, a third conductive film is deposited on the substrate having the aforementioned pattern formed thereon, and the third conductive film is patterned using a patterning process to form a third conductive layer disposed on the third insulating layer, as shown in Figures 19A and 19B. Figure 19A is a schematic diagram of the display substrate after the third conductive layer is formed in Figure 15. Figure 19B is a schematic diagram of the third conductive layer in Figure 19A. In some examples, the third conductive layer can be referred to as a first source / drain metal (SD1) layer.

[0294] In some examples, the third conductive layer of multiple circuit units in the display substrate can include: a first connecting electrode 41, a second connecting electrode 42, a third connecting electrode 43, a fourth connecting electrode 44, a fifth connecting electrode 45, a sixth connecting electrode 46, a seventh connecting electrode 47, an eighth connecting electrode 48, a ninth connecting electrode 49, a tenth connecting electrode 50, a first scanning signal line 61, a second scanning signal line 62, a third scanning signal line 63, a fifth scanning signal line 65, a first power connection line 66, a second power connection line 67, a first initial signal line 81, a second initial signal line 82 and a first reference signal line 34.

[0295] In some examples, the shape of the first power connection line 66 and the second power connection line 67 can be a straight line with a main portion extending along the first direction X. The second power connection line 67 can be located on a side of the first power connection line 66 away from the fourth electrode plate 74. The first power connection line 66 can be located on a side of the fourth electrode plate 74 close to the third electrode plate 73, and the orthographic projection of the first power connection line 66 on the substrate and the orthographic projection of the third electrode plate 73 on the substrate can partially overlap. The first power connection line 66 can be configured to be connected to the first power line formed subsequently to form a high-voltage power grid structure with a mesh-connected structure on the display substrate. The orthographic projection of the second power connection line 67 on the substrate and the orthographic projection of the third electrode plate 73 on the substrate can partially overlap. The second power connection line 67 can be configured to be connected to the second power line formed subsequently to form a low-voltage power grid structure with a mesh-connected structure on the display substrate. In this example, the fourth electrode 74 is connected to the first power connection line 66. By setting the second power connection line 67 on the side of the first power connection line 66 away from the fourth electrode 74, it is not only beneficial to realize the connection wiring between the first power connection line 66 and the fourth electrode 74, but also the first power connection line 66 can shield the interference of the second power connection line 67 on the second capacitor to ensure the performance of the second capacitor.

[0296] In some examples, a first power connection block 66-1 may be provided on a side of the first power connection line 66 away from the second power connection line 67. A first end of the first power connection block 66-1 is connected to the first power connection line 66, and a second end of the first power connection block 66-1 extends in a direction away from the second power connection line 67. The extension direction of the first power connection block 66-1 may be substantially perpendicular to the extension direction of the first power connection line 66. The first power connection line 66 may be connected to the fourth electrode plate 74 in each circuit unit through the thirteenth via V13, thereby achieving the connection between the first power connection line 66 and the fourth electrode plate 74.

[0297] In some examples, a third power connection block 67-1 may be provided on a side of the second power connection line 67 away from the first power connection line 66. The third power connection block 67-1 may be located between two adjacent circuit cells in at least one cell row. A first end of the third power connection block 67-1 is connected to the second power connection line 67, and a second end of the second power connection block 67-1 extends in a direction away from the first power connection line 66. The second power connection block 67-1 may be configured to be connected to a second power line formed subsequently.

[0298] In some examples, the shape of the third connection electrode 43 can be roughly "V"-shaped. The third connection electrode 43 can be located between the first reference signal line 34 and the first power connection line 66. The first end of the third connection electrode 43 can be connected to the second region of the fourth active layer (also the second region of the ninth active layer) through the fourth via V4, the second end of the third connection electrode 43 can be connected to the second plate connection line 73-1 of the third plate 73 through the twenty-third via V23, and the third end between the first end and the second end can be connected to the second plate 72 through the eleventh via V11. In some examples, the third connection electrode 43 can make the second electrode of the fourth transistor T4, the second electrode of the ninth transistor T9, the third plate 73 of the first capacitor (i.e., the second end of the first capacitor), and the second plate 72 of the second capacitor (i.e., the second end of the second capacitor) have the same potential, and the third connection electrode 43 can serve as the fifth node N5 of the pixel circuit.

[0299] In some examples, the ninth connection electrode 49 can be substantially rectangular in shape and can be located between the second power connection line 67 and the first scan signal line 61. The ninth connection electrode 49 can be connected to the first shielding electrode 36 of the present circuit unit through a twenty-fourth via hole V24. The ninth connection electrode 49 can be configured to be connected to a first power line connected to a pixel circuit of the present circuit unit formed subsequently.

[0300] In some examples, the tenth connection electrode 50 may be shaped substantially like a strip with a main portion extending along the second direction Y. The tenth connection electrode 50 may be located between the second power connection line 67 and the first scan signal line 61. The tenth connection electrode 50 may be connected to the first shielding electrode 36 of an adjacent circuit unit through a twenty-fifth via hole V25. The tenth connection electrode 50 may be configured to be connected to a first power line to which a pixel circuit of the subsequently formed circuit unit is connected.

[0301] The rest of the structure of the third conductive layer of the display substrate of this example is substantially the same as that of the third conductive layer of the display substrate of the aforementioned embodiment, and thus will not be described again herein.

[0302] (2-6) Forming a fourth insulating layer. In some examples, a fourth insulating film is coated on the substrate having the aforementioned pattern formed thereon, and the fourth insulating film is patterned using a patterning process to form a fourth insulating layer covering the third conductive layer. The fourth insulating layer in each circuit unit can be provided with multiple vias, as shown in FIG20 . FIG20 is a schematic diagram of the display substrate after the fourth insulating layer is formed in FIG15 .

[0303] In some examples, the multiple vias of each circuit unit in the display substrate may include at least: a thirty-first via V31, a thirty-second via V32, a thirty-third via V33, a thirty-fourth via V34, a thirty-fifth via V35, a thirty-eighth via V38, and a thirty-ninth via V39.

[0304] In some examples, the orthographic projection of the thirty-eighth via V38 on the substrate can be located within the orthographic projection range of the ninth connecting electrode 49 on the substrate, the fourth insulating layer in the thirty-eighth via V38 can be removed to expose a portion of the surface of the ninth connecting electrode 49, and the thirty-eighth via V38 can be configured to connect a subsequently formed first power line to the ninth connecting electrode 49 through the via.

[0305] In some examples, the orthographic projection of the thirty-ninth via V39 on the substrate can be located within the orthographic projection range of the tenth connecting electrode 50 on the substrate, the fourth insulating layer in the thirty-ninth via V39 can be removed to expose a portion of the surface of the tenth connecting electrode 50, and the thirty-ninth via V39 can be configured to connect a subsequently formed first power line to the tenth connecting electrode 50 through the via.

[0306] In some examples, at least one circuit unit may further include a thirty-seventh via V37. The orthographic projection of the thirty-seventh via V37 on the substrate may be located within the orthographic projection of the third power connection block 67-1 of the second power connection line 67 on the substrate. The fourth insulating layer within the thirty-seventh via V37 is removed, exposing a portion of the surface of the third power connection block 67-1. The thirty-seventh via V37 may be configured to connect a subsequently formed second power line to the third power connection block 67-1 through the via. In some examples, the thirty-seventh via V37 may be located between the first circuit unit and the second circuit unit.

[0307] The remaining structure of the fourth insulating layer of the display substrate of this example is substantially the same as that of the fourth insulating layer of the display substrate of the aforementioned embodiment, and thus will not be described again herein.

[0308] (2-7) Forming a fourth conductive layer. In some examples, a fourth conductive film is deposited on the substrate having the aforementioned pattern formed thereon, and the fourth conductive film is patterned using a patterning process to form a fourth conductive layer disposed on the fourth insulating layer, as shown in FIG21 . FIG21 is a schematic diagram of the fourth conductive layer in FIG15 .

[0309] In some examples, the fourth conductive layer of the plurality of circuit units in the display substrate may include: a data signal line 51 , a first power line 52 , a reference signal connection line 53 , and an anode connection electrode 55 .

[0310] In some examples, the first power line 52 may be shaped like a zigzag line with a main portion extending along the second direction Y. The first power line 52 may be connected to the fourth connection electrode 44 via a thirty-second via V32, and to the first power connection block 66-1 via a thirty-fifth via V35. It may also be connected to the ninth connection electrode 49 via a thirty-eighth via V38, and to the tenth connection electrode 50 via a thirty-ninth via V39. Because the fourth connection electrode 44 is connected to the first region of the fifth active layer via the vias, the first power line 52 writes the first power signal into the first electrode of the fifth transistor T5. Because the first power connection block 66-1 is connected to the first power connection line 66, the first power connection line 66 extending along the first direction X of the main portion is interconnected with the first power line 52 extending along the second direction Y of the main portion. This allows the first power line 52 and the first power connection line 66 to form a mesh structure on the display substrate for transmitting the first power signal. This not only effectively reduces the resistance of the first power line 52 and reduces the voltage drop of the first power signal, but also effectively improves the uniformity of the first power signal in the display substrate, effectively improving display uniformity, and improving display quality. Because the ninth connection electrode 49 is connected to the first shielding electrode 36 of the circuit unit through a via, the first power line 52 provides the first power signal to the first shielding electrode 36 of the circuit unit. Because the tenth connection electrode 50 is connected to the first shielding electrode 36 of the adjacent circuit unit through a via, the first power line 52 connected to the circuit unit provides the first power signal to the first shielding electrode 36 of the adjacent circuit unit.

[0311] In some examples, at least one circuit unit may further include a second power line 56. The second power line 56 may be in the form of a straight line with a main portion extending along the second direction Y. The second power line 56 may be connected to the third power connection block 67-1 via the thirty-seventh via V37. Since the third power connection block 67-1 is connected to the second power line 67, the second power line 67 extending along the first direction X and the second power line 67 extending along the second direction Y are interconnected. This allows the second power line 67 and the second power line 56 to form a mesh structure on the display substrate for transmitting the second power signal. This not only effectively reduces the resistance of the second power line 56 and the voltage drop of the second power signal, but also effectively improves the uniformity of the second power signal across the display substrate, effectively improving display uniformity and enhancing display quality. In some examples, the second power line 56 may be located between the reference signal line 53 of the first circuit unit and the data signal line 51 of the second circuit unit.

[0312] In some examples, the second power connection line 67 of the third conductive layer can be set in each unit row, and the second power line 56 of the fourth conductive layer can be set every two unit columns. Multiple second power connection lines 67 can be respectively connected to multiple second power lines 56 to form a mesh structure for transmitting the second power signal.

[0313] The rest of the structure of the fourth conductive layer of the display substrate of this example is substantially the same as that of the fourth conductive layer of the display substrate of the aforementioned embodiment, and thus will not be described again herein.

[0314] At this point, the driving circuit layer of this embodiment is prepared on the substrate. In some exemplary embodiments, after the driving circuit layer is prepared, a light emitting structure layer and an encapsulation structure layer can be sequentially prepared on the driving circuit layer, which will not be repeated here.

[0315] In this example, by arranging the first initial signal line between the first scan signal line and the second scan signal line, the distance between the first initial signal line and the channel region of the first active layer of the first transistor can be reduced. The first initial signal line can provide the first transistor with the first initial signal for initialization processing via the shortest path, which is beneficial for reducing the length of the first region of the first active layer, reducing the load on the first initial signal line, and optimizing the initialization effect. Moreover, compared with the previous embodiment, the display substrate of this example can reduce the parasitic capacitance between the second node N2 and the third node N3 and the first power supply signal by eliminating the interconnected integral structure design of the fourth electrode 74 and the first shielding electrode 36, thereby improving signal crosstalk. Moreover, the flexible design of the shape of the fourth electrode 74 can facilitate the increase of the distance between the first node and the fifth node, thereby increasing the arrangement space of the lateral wiring.

[0316] Figure 22 is a schematic planar structural diagram of another display substrate according to at least one embodiment of the present disclosure, showing the structure of pixel circuits in three circuit units (i.e., the first circuit unit, the second circuit unit, and the third circuit unit) of the display substrate.

[0317] In some examples, the first light-emitting signal line 31 and the first initial signal line 81 can be in the same layer structure, for example, both located in the third conductive layer. This example can not only reduce the resistance of the first light-emitting signal line 31, but also reduce the number of transfer vias opened in the third insulating layer, thereby optimizing wiring space.

[0318] In some examples, the second light-emitting signal line 32 and the first initial signal line 81 can be in the same layer structure, for example, both located in the third conductive layer. This example can not only reduce the resistance of the second light-emitting signal line 32, but also reduce the number of transfer vias opened in the third insulating layer, thereby optimizing wiring space.

[0319] In some examples, the preparation process of the display substrate of this example may include the following operations.

[0320] (3-1) Forming a semiconductor layer. In some examples, a semiconductor thin film is deposited on a substrate and patterned using a patterning process to form a semiconductor layer, as shown in FIG23 . FIG23 is a schematic diagram of the display substrate after the first conductive layer is formed in FIG22 . The structure of the semiconductor layer of the display substrate in this example is the same as that of the display substrate in the embodiment shown in FIG6 , and therefore will not be further described here.

[0321] (3-2) Forming a first conductive layer. In some examples, a first insulating film and a first conductive film are sequentially deposited on the substrate having the aforementioned pattern formed thereon. The first conductive film is patterned through a patterning process to form a first insulating layer covering the semiconductor layer and a first conductive layer disposed on the first insulating layer, as shown in FIG23 . The structure of the first conductive layer of the display substrate of this example is the same as that of the first conductive layer of the display substrate of the embodiment shown in FIG6 , and therefore will not be further described here.

[0322] (3-3) Forming a second conductive layer. In some examples, a second insulating film and a second conductive film are sequentially deposited on the substrate having the aforementioned pattern formed thereon. The second conductive film is patterned using a patterning process to form a second insulating layer covering the first conductive layer and a second conductive layer disposed on the second insulating layer, as shown in Figures 24A and 24B. Figure 24A is a schematic diagram of the display substrate after the second conductive layer is formed in Figure 22. Figure 24B is a schematic diagram of the second conductive layer in Figure 24A.

[0323] In some examples, the second conductive layer of each circuit unit in the display substrate may include at least: a repair line 33, a second reference signal line 35, a first shielding electrode 36, a second shielding electrode 37, a third shielding electrode 38, a third plate 73 of the first capacitor, and a fourth plate 74 of the second capacitor.

[0324] The structural description of the second conductive layer of the display substrate of this example can refer to the structural description of the second conductive layer of the display substrate of the embodiment shown in FIG6 , and thus will not be repeated here.

[0325] (3-4) Forming a third insulating layer. In some examples, a third insulating film is deposited on the substrate having the aforementioned pattern formed thereon. The third insulating film is patterned using a patterning process to form a third insulating layer. Multiple vias are provided in the third insulating layer of each circuit unit, as shown in FIG25 . FIG25 is a schematic diagram of the display substrate after the third insulating layer is formed in FIG22 .

[0326] In some examples, the multiple vias of each circuit unit in the display substrate may include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16, a seventeenth via V17, an eighteenth via V18, a nineteenth via V19, and a twenty-second via V22.

[0327] The structural description of the third insulating layer of the display substrate in this example can refer to the structural description of the third insulating layer of the display substrate in the embodiment shown in FIG6 , and thus will not be repeated here.

[0328] (3-5) Forming a third conductive layer. In some examples, a third conductive film is deposited on the substrate having the aforementioned pattern formed thereon, and the third conductive film is patterned using a patterning process to form a third conductive layer disposed on the third insulating layer, as shown in Figures 26A and 26B. Figure 26A is a schematic diagram of the display substrate after the third conductive layer is formed in Figure 22. Figure 26B is a schematic diagram of the third conductive layer in Figure 26A.

[0329] In some examples, the third conductive layer of multiple circuit units in the display substrate may include: a first connecting electrode 41, a second connecting electrode 42, a third connecting electrode 43, a fourth connecting electrode 44, a fifth connecting electrode 45, a sixth connecting electrode 46, a first scanning signal line 61, a second scanning signal line 62, a third scanning signal line 63, a fifth scanning signal line 65, a first power supply connection line 66, a first initial signal line 81, a second initial signal line 82, a first reference signal line 34, a first light-emitting signal line 31, and a second light-emitting signal line 32.

[0330] In some examples, the first lighting signal line 31 may be shaped as a straight line with a main portion extending along the first direction X, and the second lighting signal line 32 may be shaped as a zigzag line with a main portion extending along the first direction X. The first lighting signal line 31 may be located on one side of the second scan signal line 62 in the second direction Y, and the second lighting signal line 32 may be located on one side of the first lighting signal line 31 in the second direction Y. The first lighting signal line 31 may be located between the second scan signal line 62 and the second lighting signal line 32.

[0331] In some examples, the first light-emitting signal line 31 can be connected to the fifth gate electrode 25 in each circuit unit through the seventeenth via V17, thereby realizing that the first light-emitting signal line 31 is connected to the fifth gate electrode 25 of the fifth transistor T5, and the first light-emitting signal line 31 can control the conduction and disconnection of the fifth transistor T5.

[0332] In some examples, the second light-emitting signal line 32 can be connected to the sixth gate electrode 26 in each circuit unit through the eighteenth via V18, thereby realizing that the second light-emitting signal line 32 is connected to the sixth gate electrode 26 of the sixth transistor T6, and the second light-emitting signal line 32 can control the conduction and disconnection of the sixth transistor T6.

[0333] The remaining structural description of the third conductive layer of the display substrate of this example can refer to the structural description of the third conductive layer of the display substrate of the embodiment shown in FIG6 , and thus will not be repeated here.

[0334] (3-6) Forming a fourth insulating layer. In some examples, a fourth insulating film is coated on the substrate having the aforementioned pattern formed thereon, and the fourth insulating film is patterned using a patterning process to form a fourth insulating layer covering the third conductive layer. The fourth insulating layer in each circuit unit can be provided with multiple vias, as shown in FIG27 . FIG27 is a schematic diagram of the display substrate after the fourth insulating layer is formed in FIG22 .

[0335] In some examples, the plurality of vias of each circuit unit in the display substrate may include at least a thirty-first via V31 , a thirty-second via V32 , a thirty-third via V33 , a thirty-fourth via V34 , and a thirty-fifth via V35 .

[0336] In some examples, at least one circuit unit may further include a thirty-sixth via V36. The orthographic projection of the thirty-sixth via V36 on the substrate may be located within the orthographic projection of the second initial connection block 82-1 of the second initial signal line 82 on the substrate. The fourth insulating layer within the thirty-sixth via V36 is removed, exposing a portion of the surface of the second initial connection block 82-1. The thirty-sixth via V36 may be configured to connect a subsequently formed initial signal connection line to the second initial connection block 82-1 through the via. In some examples, the thirty-sixth via V36 may be located between the first circuit unit and the second circuit unit.

[0337] The remaining structural description of the fourth insulating layer of the display substrate of this example can refer to the structural description of the fourth insulating layer of the display substrate of the embodiment shown in FIG6 , and thus will not be repeated here.

[0338] (3-7) Forming a fourth conductive layer. In some examples, a fourth conductive film is deposited on the substrate having the aforementioned pattern formed thereon, and the fourth conductive film is patterned using a patterning process to form a fourth conductive layer disposed on the fourth insulating layer, as shown in FIG28 . FIG28 is a schematic diagram of the fourth conductive layer in FIG22 .

[0339] In some examples, the fourth conductive layer of the plurality of circuit units in the display substrate may include: a data signal line 51 , a first power line 52 , a reference signal connection line 53 , and an anode connection electrode 55 .

[0340] In some examples, at least one circuit unit may further include an initial signal connection line 54. The initial signal connection line 54 may be shaped as a straight line with a main portion extending along the second direction Y. The initial signal connection line 54 may be connected to the second initial connection block 82-1 via the thirty-sixth via V36. Since the second initial connection block 82-1 is connected to the second initial signal line 82, the second initial signal line 82, whose main portion extends along the first direction X, and the initial signal connection line 54, whose main portion extends along the second direction Y, are interconnected. This allows the initial signal connection line 54 and the second initial signal line 82 to form a mesh structure on the display substrate for transmitting the second initial signal. This not only effectively reduces the resistance of the second initial signal line 82 and the voltage drop of the second initial signal, but also effectively improves the uniformity of the second initial signal across the display substrate, effectively improving display uniformity and enhancing display quality. In some examples, the initial signal connection line 54 may be located between the reference signal connection line 53 of the first circuit unit and the data signal line 51 of the second circuit unit.

[0341] The remaining structural description of the fourth conductive layer of the display substrate of this example can refer to the structural description of the fourth conductive layer of the display substrate of the embodiment shown in FIG6 , and thus will not be repeated here.

[0342] At this point, the driving circuit layer of this embodiment is prepared on the substrate. In some exemplary embodiments, after the driving circuit layer is prepared, a light emitting structure layer and an encapsulation structure layer can be sequentially prepared on the driving circuit layer, which will not be repeated here.

[0343] In this example, by setting the first initial signal line between the first scanning signal line and the second scanning signal line, the distance between the first initial signal line and the channel region of the first active layer of the first transistor can be reduced. The first initial signal line can provide the first transistor with the first initial signal for initialization processing through the shortest path, which is beneficial to reducing the length of the first region of the first active layer, reducing the load of the first initial signal line, and optimizing the initialization effect. Moreover, in this embodiment, by setting the first light-emitting signal line 31 and the second light-emitting signal line 32 in the third conductive layer, the resistance of the first light-emitting signal line 31 and the second light-emitting signal line 32 can be reduced, and the transfer vias opened in the third insulating layer can be reduced, thereby optimizing the wiring space. In other examples, one of the first light-emitting signal line and the second light-emitting signal line can be set in the third conductive layer.

[0344] In other examples, the structures of the display substrates of the above embodiments may be combined with each other. For example, in the display substrate shown in FIG15 , at least one of the first light-emitting signal line and the second light-emitting signal line may be provided in the third conductive layer. This embodiment is not limited to this.

[0345] The display substrate provided in this embodiment can optimize layout and wiring by arranging the first initial signal line between the first scanning signal line and the second scanning signal line, thereby reducing the initialization path length of the first initial signal and optimizing the initialization effect.

[0346] The display substrate of this embodiment, by independently providing the fourth plate of the second capacitor and the first shielding electrode, can reduce parasitic capacitance between the second and third nodes and the first power signal, thereby improving signal crosstalk. Furthermore, the fourth plate can be flexibly designed to increase the distance between the first and fifth nodes, thereby increasing space for lateral wiring.

[0347] The display substrate provided in this embodiment is provided with a first power connection line having a main portion extending along a first direction X and a first power line having a main portion extending along a second direction Y. The first power lines are interconnected, so that the first power lines and the first power connection lines form a mesh structure on the display substrate for transmitting a first power signal. This not only effectively reduces the resistance of the first power line and reduces the voltage drop of the first power signal, but also effectively improves the uniformity of the first power signal in the display substrate, effectively improves display uniformity, and improves display quality.

[0348] The display substrate provided in this embodiment is provided with second power connection lines having a main portion extending along a first direction X and second power lines having a main portion extending along a second direction Y. The second power lines are interconnected, so that the second power connection lines form a mesh structure on the display substrate for transmitting a second power signal. This effectively reduces the resistance of the second power signal line and the voltage drop of the second power signal, and also effectively improves the uniformity of the second power signal in the display substrate, thereby effectively improving display uniformity and enhancing display quality.

[0349] The display substrate provided in this embodiment is provided with a first reference signal line extending in a first direction X in the main portion and a reference signal connection line extending in a second direction Y in the main portion. The first reference signal line and the reference signal connection line are interconnected, so that the first reference signal line and the reference signal connection line form a mesh structure on the display substrate for transmitting the first reference signal. This not only effectively reduces the resistance of the first reference signal line and reduces the voltage drop of the first reference signal, but also effectively improves the uniformity of the first reference signal in the display substrate, effectively improves display uniformity, and improves display quality.

[0350] The display substrate provided in this embodiment can shield the influence of data voltage jump on the first transistor T1 and the second transistor T2 by providing the first shielding electrode, thereby preventing the data voltage jump from affecting the normal operation of the pixel circuit and improving the display effect.

[0351] The display substrate provided in this embodiment can shield the influence of data voltage jump on the fourth transistor T4, the ninth transistor T9 and the fifth node N5 by providing the second shielding electrode and the third shielding electrode. The data voltage jump affects the normal operation of the pixel circuit and improves the display effect.

[0352] The display substrate provided in this embodiment can effectively shield the influence of other signals in the pixel circuit on the first node N1 by setting a power shielding block on the first power line, thereby preventing other signals from affecting the potential of the first node N1 of the pixel circuit and improving the display effect.

[0353] The display substrate provided in this embodiment can prevent other signals from affecting the first area of ​​the active layer of the first transistor receiving the first initial signal by setting a first power line to shield the first area of ​​the active layer of the first transistor connected to the first initial signal line, thereby ensuring the transmission accuracy of the first initial signal and ensuring the initialization effect.

[0354] The display substrate provided in this embodiment is configured such that the second power connection line is located on a side of the first power connection line away from the fourth electrode plate. This is not only beneficial for achieving connection wiring between the first power connection line and the fourth electrode plate, but also the first power connection line can shield the interference of the second power connection line on the second capacitor, thereby ensuring the performance of the second capacitor.

[0355] This embodiment further provides a method for preparing a display substrate, so as to prepare the display substrate provided by the above embodiment.

[0356] In some exemplary embodiments, a method for preparing a display substrate may include forming a driving circuit layer on a substrate. The driving circuit layer includes at least a plurality of circuit units, at least one of which includes a pixel circuit. The pixel circuit includes at least a first transistor, a second transistor, a third transistor, a fourth transistor, and a first capacitor. The gate electrode of the first transistor is electrically connected to a first scan signal line, the first electrode of the first transistor is electrically connected to a first initial signal line, and the second electrode of the first transistor is electrically connected to the gate electrode of the third transistor. The gate electrode of the second transistor is electrically connected to a second scan signal line, the first electrode of the second transistor is electrically connected to the gate electrode of the third transistor, and the second electrode of the second transistor is electrically connected to the second electrode of the third transistor. The gate electrode of the fourth transistor is electrically connected to a third scan signal line, the first electrode of the fourth transistor is electrically connected to a data signal line, and the second electrode of the fourth transistor is electrically connected to the second end of the first capacitor. The first end of the first capacitor is electrically connected to the gate electrode of the third transistor. The first initial signal line, the first scan signal line, and the second scan signal line extend in at least partially the same direction and are located on the same side of the first transistor. The first initial signal line is located between the first scan signal line and the second scan signal line.

[0357] The method for preparing the display substrate of this embodiment can be referred to the description of the aforementioned embodiment, and thus will not be described in detail here.

[0358] This embodiment also provides a display substrate, comprising: a substrate and a driving circuit layer disposed on the substrate. The driving circuit layer includes at least a plurality of circuit units, at least one of which includes a pixel circuit. The pixel circuit includes at least a first transistor, a second transistor, a third transistor, a fourth transistor, and a first capacitor. The gate electrode of the first transistor is electrically connected to a first scan signal line, the first electrode of the first transistor is electrically connected to a first initial signal line, and the second electrode of the first transistor is electrically connected to the gate electrode of the third transistor; the gate electrode of the second transistor is electrically connected to a second scan signal line, the first electrode of the second transistor is electrically connected to the gate electrode of the third transistor, and the second electrode of the second transistor is electrically connected to the second electrode of the third transistor. The gate electrode of the fourth transistor is electrically connected to a third scan signal line, the first electrode of the fourth transistor is electrically connected to a data signal line, the second electrode of the fourth transistor is electrically connected to the second end of the first capacitor; and the first end of the first capacitor is electrically connected to the gate electrode of the third transistor. The second transistor is located on one side of the first transistor in a first direction, and the third and fourth transistors are located on the same side of the first and second transistors in a second direction, with the first direction intersecting the second direction. The first initial signal line, the first scan signal line, and the second scan signal line all extend along the first direction and are located on a side of the first transistor away from the third transistor in the second direction. The first initial signal line is located between the first scan signal line and the second scan signal line.

[0359] In some example embodiments, an orthographic projection of the first scan signal line on the substrate partially overlaps with an orthographic projection of the gate electrode of the first transistor and an orthographic projection of the gate electrode of the second transistor on the substrate.

[0360] In some exemplary embodiments, the pixel circuit further includes: a second capacitor; the second capacitor includes at least: a second plate serving as a second end of the second capacitor; and a fourth plate serving as a first end of the second capacitor, wherein an orthographic projection of the second plate on the substrate at least partially overlaps with an orthographic projection of the fourth plate on the substrate. The first capacitor includes at least a first plate serving as a first end of the first capacitor; and a third plate serving as a second end of the first capacitor, wherein an orthographic projection of the first plate on the substrate at least partially overlaps with an orthographic projection of the third plate on the substrate. The fourth plate is connected to a first power line, the second plate is connected to the third plate, and the first plate serves as a gate electrode of the third transistor.

[0361] In some exemplary embodiments, a second electrode plate connecting line extending toward the fourth electrode plate is provided on the third electrode plate, and a second groove recessed away from the third electrode plate is provided on the fourth electrode plate; the second electrode plate connecting line is provided in the second groove, and the end of the second electrode plate connecting line away from the third electrode plate is connected to the second electrode plate through a via and a connecting electrode.

[0362] In some exemplary embodiments, at least one circuit unit further includes: a first shielding electrode; the first shielding electrode includes: a first shielding end and a second shielding end; an orthographic projection of the first shielding end on the substrate at least partially overlaps with an orthographic projection of a first active layer between two gate electrodes of a first transistor in the circuit unit on the substrate; the first shielding end is electrically connected to a first power line; an orthographic projection of the second shielding end on the substrate at least partially overlaps with an orthographic projection of a second active layer between two gate electrodes of a second transistor in an adjacent circuit unit on the substrate; the second shielding end is electrically connected to the first power line.

[0363] In some exemplary embodiments, the pixel circuit further includes a fifth transistor and a sixth transistor. The gate electrode of the fifth transistor is electrically connected to the first light-emitting signal line, the first electrode of the fifth transistor is electrically connected to the first power line, and the second electrode of the fifth transistor is electrically connected to the first electrode of the third transistor. The gate electrode of the sixth transistor is electrically connected to the second light-emitting signal line, the first electrode of the sixth transistor is electrically connected to the second electrode of the third transistor, and the second electrode of the sixth transistor is electrically connected to the light-emitting device. The first light-emitting signal line is located on one side of the second scan signal line in the second direction, and the second light-emitting signal line is located on one side of the first light-emitting signal line in the second direction.

[0364] In some exemplary embodiments, the first light emitting signal line, the second light emitting signal line, and the first initial signal line are in the same layer structure.

[0365] The description of the display substrate of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0366] FIG29 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. In some examples, as shown in FIG29 , this embodiment provides a display device 91 comprising a display substrate 910 according to the aforementioned embodiment. In some examples, the display substrate 910 may comprise an OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device 91 may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system. However, this embodiment is not limited thereto.

[0367] The drawings in this disclosure only relate to the structures involved in this disclosure, and other structures may refer to the general design. In the absence of conflict, the embodiments of this disclosure and the features in the embodiments may be combined with each other to obtain new embodiments. It should be understood by those skilled in the art that the technical solutions of this disclosure may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of this disclosure, and should be included in the scope of the claims of this disclosure.

Claims

1. A display substrate, comprising: A substrate and a driving circuit layer disposed on the substrate, the driving circuit layer at least comprising a plurality of circuit units, at least one of the plurality of circuit units comprising a pixel circuit, the pixel circuit at least comprising: a first transistor, a second transistor, a third transistor, a fourth transistor and a first capacitor; The gate electrode of the first transistor is electrically connected to the first scanning signal line, the first electrode of the first transistor is electrically connected to the first initial signal line, and the second electrode of the first transistor is electrically connected to the gate electrode of the third transistor; the gate electrode of the second transistor is electrically connected to the second scanning signal line, the first electrode of the second transistor is electrically connected to the gate electrode of the third transistor, and the second electrode of the second transistor is electrically connected to the second electrode of the third transistor; the gate electrode of the fourth transistor is electrically connected to the third scanning signal line, the first electrode of the fourth transistor is electrically connected to the data signal line, and the second electrode of the fourth transistor is electrically connected to the second end of the first capacitor; the first end of the first capacitor is electrically connected to the gate electrode of the third transistor; The first initial signal line, the first scanning signal line and the second scanning signal line have at least partially the same extension direction and are located on the same side of the first transistor, and the first initial signal line is located between the first scanning signal line and the second scanning signal line.

2. The display substrate according to claim 1, wherein: The first initial signal line, the first scanning signal line and the second scanning signal line are in the same layer structure.

3. The display substrate according to claim 1 or 2, wherein: The active layer of the first transistor includes: a first region, a second region, and a channel region located between the first region and the second region, and the first region of the active layer of the first transistor is connected to the first initial signal line; The driving circuit layer further includes: at least one first power line; the orthographic projection of the first power line on the substrate covers the orthographic projection of the first region of the active layer of the first transistor on the substrate.

4. The display substrate according to any one of claims 1 to 3, wherein: The pixel circuit further includes: a second capacitor; the second capacitor at least includes: a second plate as a second end of the second capacitor and a fourth plate as a first end of the second capacitor, wherein the orthographic projection of the second plate on the substrate at least partially overlaps with the orthographic projection of the fourth plate on the substrate; The first capacitor at least includes a first electrode plate as a first end of the first capacitor and a third electrode plate as a second end of the first capacitor, and an orthographic projection of the first electrode plate on the substrate at least partially overlaps with an orthographic projection of the third electrode plate on the substrate; The fourth electrode plate is connected to a first power line, the second electrode plate is connected to the third electrode plate, and the first electrode plate serves as a gate electrode of the third transistor.

5. The display substrate according to claim 4, wherein: The first electrode plate and the second electrode plate are in the same layer structure, and the third electrode plate and the fourth electrode plate are in the same layer structure.

6. The display substrate according to claim 5, wherein: The third electrode plate is provided with a second electrode plate connecting line extending toward the fourth electrode plate, and the fourth electrode plate is provided with a second groove recessed away from the third electrode plate; the second electrode plate connecting line is arranged in the second groove, and the end of the second electrode plate connecting line away from the third electrode plate is connected to the second electrode plate through a via and a connecting electrode.

7. The display substrate according to claim 6, wherein: The driving circuit layer also includes: at least one first power connection line extending along a first direction, and at least one first power line extending along a second direction, wherein the first direction intersects with the second direction; the first power lines are connected with the first power connection lines to form a mesh structure for transmitting a first power signal.

8. The display substrate according to claim 7, wherein: The driving circuit layer also includes: at least one second power connection line extending along a first direction and at least one second power connection line extending along a second direction, the first direction intersecting the second direction; the second power line and the second power connection line are connected to form a mesh structure for transmitting a second power signal; the second power connection line is located on the side of the first power connection line away from the second capacitor.

9. The display substrate according to claim 8, wherein: The first power connection line and the second power connection line are in the same layer structure, the first power line and the second power line are in the same layer structure, and the first power line is located on a side of the first power connection line away from the substrate.

10. The display substrate according to any one of claims 4 to 9, wherein: The first capacitor and the second capacitor are located on the same side of the first transistor and the second transistor, the second capacitor is located on a side of the first capacitor away from the first transistor and the second transistor, and the orthographic projection of the third transistor on the substrate at least partially overlaps with the orthographic projection of the first capacitor on the substrate.

11. The display substrate according to any one of claims 4 to 10, wherein: The fourth plates of the second capacitors of the pixel circuits of the circuit units adjacent to each other along the first direction are an integrated structure connected to each other.

12. The display substrate according to any one of claims 4 to 11, wherein: The at least one circuit unit also includes: a first shielding electrode, the first shielding electrode at least partially overlapping with the orthographic projection of the first active layer between the two gate electrodes of the first transistor in the circuit unit on the substrate, and at least partially overlapping with the orthographic projection of the second active layer between the two gate electrodes of the second transistor in the adjacent circuit unit on the substrate.

13. The display substrate according to claim 12, wherein: The first shielding electrode comprises: a first shielding end and a second shielding end; the orthographic projection of the first shielding end on the substrate at least partially overlaps with the orthographic projection of the first active layer between the two gate electrodes of the first transistor in the circuit unit on the substrate, and the first shielding end is electrically connected to the first power line; The orthographic projection of the second shielding end on the substrate at least partially overlaps with the orthographic projection of the second active layer between two gate electrodes of the second transistor in the adjacent circuit unit on the substrate, and the second shielding end is electrically connected to the first power line.

14. The display substrate according to claim 12, wherein: The first shielding electrode and the fourth electrode plate of the second capacitor are interconnected as an integral structure.

15. The display substrate according to any one of claims 4 to 14, wherein: The pixel circuit also includes: a fifth transistor, a gate electrode of the fifth transistor is electrically connected to the first light-emitting signal line, a first electrode of the fifth transistor is electrically connected to the first power line, and a second electrode of the fifth transistor is electrically connected to the first electrode of the third transistor; the first light-emitting signal line is located on a side of the second scanning signal line away from the first initial signal line.

16. The display substrate according to claim 15, wherein: The film layer where the first light-emitting signal line is located is located on a side of the film layer where the first initial signal line is located close to the substrate; or, the first light-emitting signal line and the first initial signal line are in the same layer structure.

17. The display substrate according to claim 15 or 16, wherein: The pixel circuit further includes: a sixth transistor, a gate electrode of the sixth transistor being electrically connected to the second light emitting signal line, a first electrode of the sixth transistor being electrically connected to the second electrode of the third transistor, and a second electrode of the sixth transistor being electrically connected to the light emitting device; The second light emitting signal line is located at a side of the first light emitting signal line away from the first initial signal line; The second light emitting signal line and the first light emitting signal line are in the same layer structure.

18. The display substrate according to any one of claims 4 to 17, wherein: The pixel circuit further includes: a ninth transistor; a gate electrode of the ninth transistor is electrically connected to the fifth scanning signal line, a first electrode of the ninth transistor is electrically connected to the first reference signal line, a second electrode of the ninth transistor is electrically connected to the second plate of the second capacitor and the third plate of the first capacitor; the fifth scanning signal line and the second scanning signal line output the same scanning signal; The fourth transistor and the ninth transistor are located on a side of the second capacitor away from the first capacitor; The active layer of the fourth transistor and the active layer of the ninth transistor are interconnected as an integral structure.

19. The display substrate according to claim 18, wherein: Active layers of at least two ninth transistors adjacent to each other along the first direction are connected into an integrated structure through a first active connection line.

20. The display substrate according to any one of claims 4 to 19, wherein: The pixel circuit further includes: a seventh transistor and an eighth transistor; a gate electrode of the seventh transistor is electrically connected to the fourth scanning signal line, a first electrode of the seventh transistor is electrically connected to the second initial signal line, and a second electrode of the seventh transistor is electrically connected to the light emitting device; A gate electrode of the eighth transistor is electrically connected to the fourth scanning signal line, a first electrode of the eighth transistor is electrically connected to the second reference signal line, and a second electrode of the eighth transistor is electrically connected to the first electrode of the third transistor.

21. The display substrate according to any one of claims 4 to 20, wherein: In a direction perpendicular to the display substrate, the driving circuit layer comprises: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer sequentially arranged on the base; The active layers of the first transistor, the second transistor and the third transistor are located in the semiconductor layer; The gate electrodes of the first transistor, the second transistor and the third transistor, the first electrode plate and the second electrode plate are located in the first conductive layer; The third electrode plate and the fourth electrode plate are located in the second conductive layer; The first initial signal line, the first scanning signal line and the second scanning signal line are located in the third conductive layer.

22. A display device comprising the display substrate according to any one of claims 1 to 21.

23. A method for preparing a display substrate, comprising: A driving circuit layer is formed on a substrate; wherein the driving circuit layer includes at least a plurality of circuit units, at least one of the plurality of circuit units includes a pixel circuit; the pixel circuit includes at least: a first transistor, a second transistor, a third transistor, a fourth transistor and a first capacitor; a gate electrode of the first transistor is electrically connected to a first scanning signal line, a first electrode of the first transistor is electrically connected to a first initial signal line, and a second electrode of the first transistor is electrically connected to a gate electrode of the third transistor; a gate electrode of the second transistor is electrically connected to a second scanning signal line, a first electrode of the second transistor is electrically connected to a gate electrode of the third transistor, and a second electrode of the second transistor is electrically connected to a second electrode of the third transistor; a gate electrode of the fourth transistor is electrically connected to a third scanning signal line, a first electrode of the fourth transistor is electrically connected to a data signal line, and a second electrode of the fourth transistor is electrically connected to a second end of the first capacitor; a first end of the first capacitor is electrically connected to a gate electrode of the third transistor; The first initial signal line, the first scanning signal line and the second scanning signal line have at least partially the same extension direction and are located on the same side of the first transistor, and the first initial signal line is located between the first scanning signal line and the second scanning signal line.

24. A display substrate, comprising: A substrate and a driving circuit layer disposed on the substrate, the driving circuit layer at least comprising a plurality of circuit units, at least one of the plurality of circuit units comprising a pixel circuit, the pixel circuit at least comprising: a first transistor, a second transistor, a third transistor, a fourth transistor and a first capacitor; The gate electrode of the first transistor is electrically connected to the first scanning signal line, and the first electrode of the first transistor is electrically connected to the first an initial signal line is electrically connected, a second electrode of the first transistor is electrically connected to a gate electrode of the third transistor; a gate electrode of the second transistor is electrically connected to a second scanning signal line, a first electrode of the second transistor is electrically connected to a gate electrode of the third transistor, and a second electrode of the second transistor is electrically connected to a second electrode of the third transistor; a gate electrode of the fourth transistor is electrically connected to a third scanning signal line, a first electrode of the fourth transistor is electrically connected to a data signal line, and a second electrode of the fourth transistor is electrically connected to a second end of the first capacitor; a first end of the first capacitor is electrically connected to a gate electrode of the third transistor; The second transistor is located at one side of the first transistor in a first direction, the third transistor and the fourth transistor are located at the same side of the first transistor and the second transistor in a second direction, and the first direction intersects the second direction; The first initial signal line, the first scanning signal line and the second scanning signal line all extend along the first direction and are located on a side of the first transistor away from the third transistor in the second direction; The first initial signal line is located between the first scanning signal line and the second scanning signal line.

25. The display substrate according to claim 24, wherein: An orthographic projection of the first scanning signal line on the substrate overlaps with an orthographic projection portion of the gate electrode of the first transistor and a gate electrode of the second transistor on the substrate.

26. The display substrate according to claim 24 or 25, wherein: The pixel circuit further includes: a second capacitor; the second capacitor at least includes: a second plate as a second end of the second capacitor and a fourth plate as a first end of the second capacitor, wherein the orthographic projection of the second plate on the substrate at least partially overlaps with the orthographic projection of the fourth plate on the substrate; The first capacitor at least includes a first electrode plate as a first end of the first capacitor and a third electrode plate as a second end of the first capacitor, and an orthographic projection of the first electrode plate on the substrate at least partially overlaps with an orthographic projection of the third electrode plate on the substrate; The fourth electrode plate is connected to a first power line, the second electrode plate is connected to the third electrode plate, and the first electrode plate serves as a gate electrode of the third transistor.

27. The display substrate according to claim 26, wherein: The third electrode plate is provided with a second electrode plate connecting line extending toward the fourth electrode plate, and the fourth electrode plate is provided with a second groove recessed away from the third electrode plate; the second electrode plate connecting line is arranged in the second groove, and the end of the second electrode plate connecting line away from the third electrode plate is connected to the second electrode plate through a via and a connecting electrode.

28. The display substrate according to any one of claims 24 to 27, wherein: The at least one circuit unit further comprises: a first shielding electrode; the first shielding electrode comprises: a first shielding end and a second shielding end; an orthographic projection of the first shielding end on the substrate at least partially overlaps with an orthographic projection of the first active layer between two gate electrodes of the first transistor in the circuit unit on the substrate; The orthographic projection of the second shielding end on the substrate at least partially overlaps with the orthographic projection of the second active layer between two gate electrodes of the second transistor in the adjacent circuit unit on the substrate, and the first shielding end and the second shielding end are both electrically connected to the first power line.

29. The display substrate according to any one of claims 24 to 28, wherein: The pixel circuit further includes: a fifth transistor and a sixth transistor; The gate electrode of the fifth transistor is electrically connected to the first light emitting signal line, the first electrode of the fifth transistor is electrically connected to the first power supply line, and the second electrode of the fifth transistor is electrically connected to the first electrode of the third transistor; The gate electrode of the sixth transistor is electrically connected to the second light emitting signal line, the first electrode of the sixth transistor is electrically connected to the second electrode of the third transistor, and the second electrode of the sixth transistor is electrically connected to the light emitting device; The first light emitting signal line is located at one side of the second scanning signal line in the second direction, and the second light emitting signal line is located at one side of the first light emitting signal line in the second direction.

30. The display substrate according to claim 29, wherein: The first light emitting signal line, the second light emitting signal line and the first initial signal line are in the same layer structure.

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