Semiconductor device and electronic apparatus

Abstract

According to the invention, the reliability is improved. The semiconductor device includes an island-shaped semiconductor portion having a first portion and a second portion disposed side by side with the first portion in a first direction and disposed integrally with the first portion, a width of the second portion in the same direction as a width of the first portion along a second direction intersecting the first direction is greater than a width of the first portion, each of the first and second portions having an upper surface portion and a side surface portion; an insulating layer surrounding each of the first portion and the second portion; a field effect transistor having a gate electrode spaced apart from the second portion and disposed on an upper surface portion and a side surface portion of the first portion with a gate insulating film interposed therebetween; and a dielectric portion disposed between the gate electrode and the second portion and having a relative permittivity smaller than a relative permittivity of the insulating layer.

Description

Technical Field

[0001] The present technology (technology according to the present disclosure) relates to a semiconductor device and an electronic device, and more particularly, to a technology that is effective when applied to a semiconductor device including a fin field effect transistor and an electronic device including the semiconductor device. Background Art

[0002] As a semiconductor device, for example, a solid-state imaging device called a CMOS image sensor is known. The CMOS image sensor includes a pixel circuit (reading circuit) that converts a signal charge generated by photoelectric conversion in a photoelectric conversion element into a pixel signal and outputs the pixel signal. The pixel circuit includes pixel transistors such as an amplifier transistor, a selection transistor, and a reset transistor.

[0003] On the other hand, as a field effect transistor mounted on a semiconductor device, a fin field effect transistor (Fin-FET) is known in which a gate electrode is provided in an island-shaped semiconductor (fin portion) with a gate insulating film interposed therebetween. This fin field effect transistor can improve short channel characteristics and achieve necessary operations even with a shorter gate length, which allows a reduction in planar size and is useful for high integration.

[0004] Patent Document 1 discloses a solid-state imaging device in which an amplifier transistor included in a pixel circuit is implemented by a fin field-effect transistor.

[0005] Reference List

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent Application Publication No. 2021-034435 Summary of the invention

[0008] Problems to be solved by the present invention

[0009] Meanwhile, even in such a fin field effect transistor, parasitic capacitance is added. Such parasitic capacitance becomes a factor that degrades the noise characteristics of the field effect transistor and hinders improvement in the reliability of the semiconductor device, so there is room for improvement.

[0010] Therefore, an object of the present technology is to provide a technology capable of improving reliability.

[0011] Solution to the problem

[0012] (1) A semiconductor device according to one aspect of the present technology includes:

[0013] An island-shaped semiconductor, comprising a first portion and a second portion, wherein the second portion is arranged side by side with the first portion in a first direction, and the second portion is wider than the first portion in a direction that is the same as the width of the first portion along a second direction intersecting the first direction, and the first portion and the second portion both include an upper surface and a side surface;

[0014] an insulating layer surrounding each of the first portion and the second portion;

[0015] a field effect transistor including a gate electrode separated from the second portion and disposed across an upper surface and a side surface of the first portion; and

[0016] The dielectric portion is disposed between the gate electrode and the second portion and has a relative dielectric constant smaller than that of the insulating layer.

[0017] (2) A method of manufacturing a semiconductor device according to another aspect of the present technology includes:

[0018] Forming an island-shaped semiconductor, comprising a first portion and a second portion, wherein the second portion is arranged side by side with the first portion in a first direction, and the width of the second portion in a direction which is the same as the width of the first portion along a second direction intersecting the first direction is greater than the width of the first portion, and the first portion and the second portion both comprise an upper surface and a side surface;

[0019] forming an insulating layer surrounding each of the first portion and the second portion;

[0020] forming a gate electrode separated from the second portion and facing an upper surface and a side surface of the first portion; and

[0021] In the first direction, a dielectric portion is formed between the gate electrode and the second portion, and a relative dielectric constant of the dielectric portion is smaller than that of the insulating layer.

[0022] (3) A method for manufacturing a semiconductor device according to another aspect of the present technology includes:

[0023] forming an island-shaped semiconductor, the island-shaped semiconductor comprising a first portion and a second portion, the second portion being arranged side by side with the first portion in a first direction, and the second portion having a width greater than the first portion in a direction that is the same as the width of the first portion along a second direction intersecting the first direction, the first portion and the second portion both comprising an upper surface and a side surface;

[0024] forming an insulating layer surrounding each of the first portion and the second portion;

[0025] forming a recess by selectively removing the insulating layer outside the first portion in a second direction;

[0026] forming a conductive film covering the semiconductor in a manner embedded in the recess;

[0027] forming a gate electrode by patterning a conductive film, the gate electrode including a leg portion and a head portion, the leg portion being positioned adjacent to the first portion and embedded in the recess, the head portion being integrally formed with the leg portion, overlapping the first portion, and having a smaller width than the leg portion in a first direction along the same direction as a width of the leg portion;

[0028] forming an extension region by selectively ion-implanting an impurity into a semiconductor located outside the head portion, wherein the leg portion exists outside the head portion; and

[0029] Remove the legs that are outside the head.

[0030] (4) A semiconductor device according to another aspect of the present technology includes:

[0031] A semiconductor including an upper surface and a side surface; and

[0032] A field effect transistor is provided in a semiconductor, wherein

[0033] The semiconductor includes a first region and a second region pair, the second region pair being disposed continuously with the first region on both sides of the first region in a first direction and being higher than the first region, and

[0034] The field effect transistor includes: a gate electrode provided across the upper surface and the side surface of the first region, wherein a gate insulating film is interposed between the gate electrode and the first region; and a main electrode region pair provided in the second region pair.

[0035] (5) A method of manufacturing a semiconductor device according to another aspect of the present technology includes:

[0036] forming a semiconductor including a first portion, a pair of second portions disposed continuously with the first portion on both sides of the first portion in a first direction, and an upper surface and a side surface disposed across the first portion and the second portion;

[0037] forming a gate electrode, the gate electrode facing the upper surface and the side surface of the first portion, wherein the gate insulating film is interposed between the gate electrode and the first portion in a second direction intersecting the first direction;

[0038] making each of the pair of second portions taller than the first portion by epitaxial growth; and

[0039] A pair of main electrode regions is formed in the second pair of portions.

[0040] (6) An electronic device according to another aspect of the present technology includes: a semiconductor device; an optical lens that forms an image of image light from a subject on an imaging surface of the semiconductor device; and a signal processing circuit that performs signal processing on a signal output from the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 : is a schematic plan view of a main part showing a configuration example of a semiconductor device according to a first embodiment of the present technology.

[0042] Figure 1A yes Figure 1 A plan view of a planar pattern of a semiconductor.

[0043] Figure 2 It is along Figure 1 A schematic longitudinal sectional view of the longitudinal sectional structure taken along the line a1 - a1 in FIG.

[0044] Figure 3 It is along Figure 1 A schematic longitudinal sectional view of the longitudinal sectional structure taken along line b1 - b1 in FIG.

[0045] Figure 4 It is along Figure 1 A schematic longitudinal sectional view of the longitudinal sectional structure taken along line C1-C1 in FIG.

[0046] Figure 5 It is a schematic plan view of a main part showing steps of a method of manufacturing a semiconductor device according to a first embodiment of the present technology.

[0047] Figure 6 It is along Figure 5 A schematic longitudinal sectional view of the longitudinal sectional structure taken along line a5-a5 in FIG.

[0048] Figure 7 It is along Figure 5 A schematic longitudinal sectional view of the longitudinal sectional structure taken along line b5-b5 in FIG.

[0049] Figure 8 It is along Figure 5 A schematic longitudinal sectional view of the longitudinal sectional structure taken along line c5-c5 in FIG.

[0050] Fig. 9 It means next Figure 5 A schematic plan view of the main parts of the steps.

[0051] Fig.10 It is along Fig. 9 A schematic longitudinal sectional view of the longitudinal sectional structure taken along line a9-a9 in FIG.

[0052] Fig.11 It is along Fig. 9 A schematic longitudinal sectional view of the longitudinal sectional structure taken along line b9-b9 in FIG.

[0053] Fig.12 It is along Fig. 9 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along line c9-c9 in FIG.

[0054] Fig.13 It means next Fig. 9 A schematic plan view of the main parts of the steps.

[0055] Fig.14 It is along Fig.13 A schematic longitudinal sectional view of the longitudinal sectional structure taken along line b13-b13 in FIG.

[0056] Fig.15 It is along Fig.13 A schematic longitudinal sectional view of the longitudinal sectional structure taken along line c13-c13 in FIG.

[0057] Fig.16 Yes means Fig.13 Schematic plan view of the main parts of the following steps.

[0058] Fig.17 It is along Fig.16 A schematic longitudinal sectional view of the longitudinal sectional structure taken along line a16 - a16 in FIG.

[0059] Fig.18 It is along Fig.16 A schematic longitudinal sectional view of the longitudinal sectional structure taken along line b16-b16 in FIG.

[0060] Fig.19 It is along Fig.16 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along line c16-c16 in FIG.

[0061] Fig. 20 is a schematic plan view of the main parts, showing Fig.16 The next steps.

[0062] Fig.21 It is along Fig. 20 A schematic longitudinal sectional view of the longitudinal sectional structure taken along line a20-a20 in FIG.

[0063] Fig. 22 It is along Fig. 20 A schematic longitudinal sectional view of the longitudinal sectional structure taken along line b20-b20 in FIG.

[0064] Fig.23 yes Fig. 20 Schematic longitudinal cross-sectional view of the C20-C20 line longitudinal cross-sectional structure.

[0065] Fig.24 It shows that Fig. 20A schematic plan view of the main parts of the steps.

[0066] Fig.25 It is along Fig.24 A schematic longitudinal sectional view of the longitudinal sectional structure taken along line a24 - a24 in FIG.

[0067] Fig.26 It is along Fig.24 A schematic longitudinal sectional view of the longitudinal sectional structure taken along line b24-b24 in FIG.

[0068] Fig. 27 It is along Fig.24 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along line c24-c24 in FIG.

[0069] Fig.28 is a schematic plan view of the main part, showing Fig.24 The next steps.

[0070] Fig.29 It is along Fig.28 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along line b28-b28 in FIG.

[0071] Fig.30 is a schematic plan view of the main parts, showing Fig.28 The next steps.

[0072] Fig.31 It is along Fig.30 A schematic longitudinal sectional view of the longitudinal sectional structure taken along line a30 - a30 in FIG.

[0073] Fig.32 It is along Fig.30 A schematic longitudinal sectional view of the longitudinal sectional structure taken along line b30 - b30 in FIG.

[0074] Fig.33 Yes means Fig.30 Schematic plan view of the main parts of the latter step.

[0075] Fig.34 It is along Fig.33 A schematic longitudinal sectional view of the longitudinal sectional structure taken along line a33 - a33 in FIG.

[0076] Fig.35 It is along Fig.33 A schematic longitudinal sectional view of the longitudinal sectional structure taken along line b33-b33 in FIG.

[0077] Fig.36 : is a schematic longitudinal cross-sectional view of a field effect transistor according to a first embodiment showing parasitic capacitance added to the field effect transistor.

[0078] Fig.37 is a schematic longitudinal sectional view of a field effect transistor of a comparative example, illustrating parasitic capacitance added to the field effect transistor.

[0079] Fig.38 is a schematic longitudinal cross-sectional view of a semiconductor device according to a modified example of the first embodiment of the present technology.

[0080] Fig.39 It is a schematic plan view of a semiconductor device according to a modified example of the first embodiment of the present technology.

[0081] Fig.40 is a schematic longitudinal sectional view of a configuration example of a semiconductor device according to a second embodiment of the present technology.

[0082] Fig.41 : is a schematic plan view of a main part showing a configuration example of a semiconductor device according to a third embodiment of the present technology.

[0083] Fig.42 It is along Fig.41 A schematic longitudinal sectional view of the longitudinal sectional structure taken along line a41 - a41 in FIG.

[0084] Fig.43 It is along Fig.41 A schematic longitudinal sectional view of the longitudinal sectional structure taken along line b41 - b41 in FIG.

[0085] Fig.44 It is a schematic plan view of a semiconductor device according to a modified example of the third embodiment of the present technology.

[0086] Fig.45 : is a schematic plan view of a main part showing steps of a method of manufacturing a semiconductor device according to a fourth embodiment of the present technology.

[0087] Fig.46 It is along Fig.45 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along line a45-a45 in FIG.

[0088] Fig.47 It is along Fig.45 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along line b45-b45 in FIG.

[0089] Fig.48 It is along Fig.45 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along line c45-c45 in FIG.

[0090] Fig.49 It means next Fig.45A schematic plan view of the main parts of the steps.

[0091] Fig.50 It is along Fig.49 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along line b49-b49 in FIG.

[0092] Fig.51 It is along Fig.49 Schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along line c49-c49 in FIG.

[0093] Fig.52 is a schematic plan view of the main parts, showing Fig.49 The next steps.

[0094] Fig.53 It is along Fig.52 A schematic longitudinal sectional view of the longitudinal sectional structure taken along line a52 - a52 in FIG.

[0095] Fig.54 It is along Fig.52 A schematic longitudinal sectional view of the longitudinal sectional structure taken along line b52 - b52 in FIG.

[0096] Fig.55 It is along Fig.52 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along line c52-c52 in FIG.

[0097] Fig.56 is a schematic plan view of the main parts, showing Fig.52 The next steps.

[0098] Fig.57 It is along Fig.56 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along line a56 - a56 in FIG.

[0099] Fig.58 It is along Fig.56 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along line b56-b56 in FIG.

[0100] Fig.59 It is along Fig.56 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along line c56-c56 in FIG.

[0101] Fig.60 It means next Fig.56 A schematic plan view of the main parts of the steps.

[0102] Fig.61 It is along Fig.60 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along line a60 - a60 in FIG.

[0103] Fig.62 It is along Fig.60 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along line b60 - b60 in FIG.

[0104] Fig.63 is a schematic plan view of the main parts, showing Fig.60 The next steps.

[0105] Fig.64 It is along Fig.63 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along line a63-a63 in FIG.

[0106] Fig.64A By partially enlarging Fig.64 A schematic longitudinal cross-sectional view of the portion obtained.

[0107] Fig.65 It is along Fig.63 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along line b63-b63 in FIG.

[0108] Fig.66 is a schematic plan view of the main parts, showing Fig.63 The next steps.

[0109] Fig.67 It is along Fig.66 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along line a66-a66 in FIG.

[0110] Fig.67A By partially enlarging Fig.67 A schematic longitudinal cross-sectional view of the portion obtained.

[0111] Fig.68 It is along Fig.66 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along line b66-b66 in FIG.

[0112] Fig.69 It shows that Fig.66 A schematic plan view of the main parts of the steps.

[0113] Fig.70 It is along Fig.69 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along line a69-a69 in FIG.

[0114] Fig.71 It is along Fig.69 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along line b69-b69 in FIG.

[0115] Fig.72: is a schematic plan layout diagram showing a configuration example of a solid-state imaging device according to a fifth embodiment of the present technology.

[0116] Fig.73 is a block diagram showing a configuration example of a solid-state imaging device according to a fifth embodiment of the present technology.

[0117] Fig.74 : is an equivalent circuit diagram showing a configuration example of a pixel and a pixel circuit of a solid-state imaging device according to a fifth embodiment of the present technology.

[0118] Fig.75 1 is a schematic longitudinal sectional view of a longitudinal sectional structure of a pixel array unit of a solid-state imaging device according to a fifth embodiment of the present technology.

[0119] Fig.76 : is a schematic plan view of a main part showing a configuration example of a semiconductor device according to a sixth embodiment of the present technology.

[0120] Fig.77 It is along Fig.76 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along line a76-a76 in FIG.

[0121] Fig.78 It is along Fig.76 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along line b76-b76 in FIG.

[0122] Fig.79 It is along Fig.76 Schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along line c76-c76 in FIG.

[0123] Fig.80 It is a schematic plan view of a main part showing steps of a method of manufacturing a semiconductor device according to a sixth embodiment of the present technology.

[0124] Fig.81 It is along Fig.80 A schematic longitudinal sectional view of the longitudinal sectional structure taken along line a80 - a80 in FIG.

[0125] Fig.82 It is along Fig.80 A schematic longitudinal sectional view of the longitudinal sectional structure taken along line b80 - b80 in FIG.

[0126] Fig.83 It is along Fig.80 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along line c80-c80 in FIG.

[0127] Fig.84 is a schematic plan view of the main parts, showing Fig.80 The next steps.

[0128] Fig.85 is a schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along line 84a-a84 in 84a.

[0129] Fig.86 It is along Fig.84 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along line b84-b84 in FIG.

[0130] Fig.87 It is along Fig.84 Schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along line c84-c84 in c.

[0131] Fig.88 is a schematic plan view of the main parts, showing Fig.84 The next steps.

[0132] Fig.89 It is along Fig.88 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along line a88-a88 in FIG.

[0133] Fig.90 It is along Fig.88 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along line b88-b88 in FIG.

[0134] Fig.91 It is along Fig.88 Schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along line c88-c88 in FIG.

[0135] Fig.92 is a schematic plan view of the main parts, showing Fig.88 The next steps.

[0136] Fig.93 It is along Fig.92 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along line a92-a92 in FIG.

[0137] Fig.94 It is along Fig.92 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along line b92-b92 in FIG.

[0138] Fig.95 It is along Fig.92 Schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along line c928-c92.

[0139] Fig.96 is a schematic plan view of the main parts, showing Fig.92 The next steps.

[0140] Fig.97 It is along Fig.96 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along line a96-a96 in FIG.

[0141] Fig.98 It is along Fig.96 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along line b96-b96 in FIG.

[0142] Fig.99 It is along Fig.96 Schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along line c96-c96.

[0143] Fig.100 is a schematic plan view of the main parts, showing Fig.96 The next steps.

[0144] Fig.101 It is along Fig.100 A schematic longitudinal sectional view of the longitudinal sectional structure taken along line a100 - a100 in FIG.

[0145] Fig.102 It is along Fig.100 A schematic longitudinal sectional view of the longitudinal sectional structure taken along line b100 - b100 in FIG.

[0146] Fig.103 It is along Fig.100 Schematic longitudinal sectional view of the longitudinal sectional structure taken along line c100 - c100 in FIG.

[0147] Fig.104 is a schematic plan view of the main parts, showing Fig.100 The next steps.

[0148] Fig.105 It is along Fig.104 A schematic longitudinal sectional view of the longitudinal sectional structure taken along line a104 - a104 in FIG.

[0149] Fig.106 It is along Fig.104 A schematic longitudinal sectional view of the longitudinal sectional structure taken along line b104 - b104 in FIG.

[0150] Fig.107 It is along Fig.104 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along line c104 - c104 in FIG.

[0151] Fig.108 is a schematic plan view of the main parts, showing Fig.104 The next steps.

[0152] Fig.109 It is along Fig.108 A schematic longitudinal sectional view of the longitudinal sectional structure taken along line a108 - a108 in FIG.

[0153] Fig.110 It is along Fig.108 A schematic longitudinal sectional view of the longitudinal sectional structure taken along line b108 - b108 in FIG.

[0154] Fig.111 It means next Fig.108 A schematic plan view of the main parts of the steps.

[0155] Fig.112 It is along Fig.111 A schematic longitudinal sectional view of the longitudinal sectional structure taken along line a111 - a111 in FIG.

[0156] Fig.113 It is along Fig.111 A schematic longitudinal sectional view of the longitudinal sectional structure taken along line b111 - b111 in FIG.

[0157] Fig.114 It is along Fig.111 A schematic longitudinal sectional view of the longitudinal sectional structure taken along line c111 - c111 in FIG.

[0158] Fig.115 is with Fig.111 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure at the same position of the line a111-a111 in FIG. Fig.111 The next steps.

[0159] Fig.116 is with Fig.111 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure at the same position of the line b111-b111 in FIG. Fig.115 The next steps.

[0160] Fig.117 is with Fig.111 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure at the same position of the line a111-a111 in FIG. Fig.115 The next steps.

[0161] Fig.118 is with Fig.111 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure at the same position of the line b111-b111 in FIG. Fig.115 The next steps.

[0162] Fig.119 is a schematic longitudinal sectional view of a configuration example of a semiconductor device according to a seventh embodiment of the present technology.

[0163] Fig.120 : is a schematic longitudinal cross-sectional view showing the steps of a method of manufacturing a semiconductor device according to a seventh embodiment of the present technology.

[0164] Fig.121 It is shown Fig.120 Schematic longitudinal cross-section of the following steps.

[0165] Fig.122 It is shown Fig.121 Schematic longitudinal cross-section of the following steps.

[0166] Fig.123 is a diagram illustrating a configuration example of an electronic device according to an eighth embodiment of the present technology. DETAILED DESCRIPTION

[0167] Hereinafter, embodiments of the present technology will be described in detail with reference to the accompanying drawings.

[0168] In the illustrations of the drawings mentioned in the following description, the same or similar parts are represented by the same or similar reference numerals. In addition, the drawings are schematic, and the relationship between thickness and plane size, the thickness ratio of each layer, etc. are different from the actual ones. Therefore, the specific thickness and size should be determined in consideration of the following description.

[0169] In addition, the dimensional relationships and ratios between the drawings are of course different. In addition, the effects described herein are merely embodiments and are not limited, and other effects may be provided.

[0170] In addition, the following embodiments illustrate devices and methods for embodying the technical concept of the present technology, and do not limit the configuration to the configuration described below. That is, the technical concept of the present technology can be modified in various ways within the technical scope described in the claims.

[0171] In addition, the definition of directions in the following description (such as the up and down directions) is defined only for the convenience of description and does not limit the technical concept of the present technology. For example, it goes without saying that if the object is observed while rotating 90°, then up and down are converted into left and right, and if the object is observed while rotating 180°, then up and down are reversed.

[0172] Furthermore, in the following embodiments, a case where the first conductivity type is p type and the second conductivity type is n type will be exemplarily described, but the relationship between the conductivity types may be reversed, that is, the first conductivity type may be n type and the second conductivity type may be p type.

[0173] In addition, in the following embodiments, among the three directions orthogonal to each other in space, the first direction and the second direction orthogonal to each other in the same plane are defined as the X direction and the Y direction, respectively, and the third direction orthogonal to the first direction and the second direction is defined as the Z direction. Next, in the following embodiments, the thickness direction of the semiconductor layer 2 described later is recorded as the Z direction.

[0174] [First embodiment]

[0175] In the first embodiment, an example in which the present technology is applied to a semiconductor device 1A including a semiconductor 5 in which second portions 7 are provided on both end sides of a first portion 6 in a first direction (X direction) will be described.

[0176] <<Overall Configuration of Semiconductor Device>>

[0177] First, refer to Figure 1 and Figure 1A ,as well as Figures 2 to 4 The overall configuration of the semiconductor device 1A is described. Figure 1 In order to facilitate the description, Figures 2 to 4 2 is an illustration of the insulating layer 22, the contact electrodes 22a, 22b and 22c, and the wirings 23a, 23b and 23c shown in FIG.

[0178] like Figure 1 , Figure 1A and Figures 2 to 4 As shown, the semiconductor device 1A according to the first embodiment of the present technology includes an island-shaped semiconductor 5 provided in a semiconductor layer 2 and a field effect transistor Q provided in the semiconductor 5. Furthermore, the semiconductor device 1A according to the first embodiment includes an insulating layer 11 provided outside the semiconductor 5 so as to surround the semiconductor 5.

[0179] <Semiconductor Layer>

[0180] like Figure 1 , Figure 1A and Figures 2 to 4 As shown, the semiconductor layer 2 includes a base 4 extending two-dimensionally in the X and Y directions, and an island-shaped semiconductor 5 protruding above the base 4 (in the Z direction).

[0181] The semiconductor 5 has a three-dimensional structure, which includes: a first part 6, extending in the X direction (first direction); and a second part 7, which is integrally arranged with the first part 6 in the X direction (adjacent to the first part 6), and the width W2 of the second part in the same direction as the width W1 of the first part 6 along the Y direction intersecting the X direction is greater than the width W1 of the first part 6; and wherein the first part 6 and the second part 7 have an upper surface 5a and a side surface 5b.

[0182] For example, the semiconductor 5 of the first embodiment has a three-dimensional structure including, but not limited to, two first portions 6 arranged side by side at a predetermined interval in the Y direction and two second portions 7 arranged on both end sides of each of the two first portions 6 in the X direction. The two first portions 6 and the two second portions 7 each have a rectangular planar shape in a plan view. In the X direction, each of the two first portions 6 has one end connected to one of the two second portions 7 and the other end connected to the other of the two second portions 7.

[0183] like Figure 1 , Figure 1A and Figures 2 to 4 As shown in the figure, the semiconductor 5 includes an upper surface 5a and a side surface 5b, the upper surface 5a is located on the side of the semiconductor 5 away from the base 4 and extends two-dimensionally through the two first parts 6 and the two second parts 7, and the side surface 5b extends two-dimensionally in the thickness direction (Z direction) through the two first parts 6 and the two second parts 7 of the semiconductor 5.

[0184] like Figure 1A As shown in FIG. 5 , the side surface 5b includes side surfaces 6b1 and 6b2 located on opposite sides of the first portion 6 in the Y direction, side surfaces 7b1 and 7b2 located on opposite sides of the second portion 7 in the X direction, and side surfaces 7b3 and 7b4 located on opposite sides of the second portion 7 in the Y direction. The side surface 7b1 of the second portion 7 is divided into three parts (7b1 and 7b2) by a connection portion connecting the first portion 6 and the second portion 7. 11 , 7b 12 and 7b 13 ).

[0185] The first side surface 7b1 (7b 11 ) is adjacent to the side surface 6b1 of one of the two first portions 6. The second side surface 7b1 (7b 12 ) is adjacent to the side surface 6b1 of the other of the two first portions 6. Then, the remaining third side surface 7b1 (7b 13 ) is positioned adjacent to the side surface 6b2 of each of the two first portions 6, in other words, between the two first portions 6. That is, the side surface 5b of the semiconductor 5 is composed of the side surfaces 6b1, 6b2 of the two first portions 6 and the side surfaces 7b1, 7b2, 7b3, 7b4 of the two second portions 7.

[0186] By selectively etching the semiconductor layer 2 to a depth at which the base 4 remains, a semiconductor 5 including the first portion 6 and the second portion 7 can be formed. The semiconductor layer 2 can be, but is not limited to, a semiconductor substrate including, for example, silicon (Si) as a semiconductor material, for example, single crystal as crystallinity, and for example, p-type conductivity type as conductivity type.

[0187] like Figures 2 to 4 As shown, the semiconductor layer 2 has a P-type well region 3, which is, for example, a P-type semiconductor region. The P-type well region 3 is arranged throughout the semiconductor 5 and is arranged throughout the surface layer of the base 4 adjacent to the semiconductor 5. Then, the p-type well region 3 is separated from the rear surface of the base 4 away from the semiconductor 5.

[0188] <Insulation layer>

[0189] like Figures 2 to 4 As shown, the insulating layer 11 is provided on the side of the base 4 of the semiconductor layer 2 adjacent to the semiconductor 5 so as to surround the semiconductor 5. The insulating layer 11 has a surface layer away from the base 4 of the flattened semiconductor layer 2, and has a film thickness almost equal to the height (protrusion) of the semiconductor 5 except for recesses 12a and 12b described later. The insulating layer 11 includes, for example, a silicon oxide (SiO2) film.

[0190] like Figures 2 to 4 As shown, on the side of the insulating layer 11 away from the base 4, the insulating layer 22 is provided to cover the gate electrode 15 of the field effect transistor Q described later and the head 15a of the semiconductor 5. The insulating layer 22 also includes, for example, a silicon oxide (SiO2) film.

[0191] A first wiring layer including wirings 23a, 23b and 23c is provided on the side of the insulating layer 22 away from the semiconductor 5. The wirings 23a, 23b and 23c of the first wiring layer include, for example, a metal film of aluminum (Al), copper (Cu) or the like or an alloy film mainly containing Al or Cu.

[0192] <Field Effect Transistor>

[0193] Figure 1 The field effect transistor Q shown in is but not limited to an n-channel conductivity type. Then, the field effect transistor Q includes a metal oxide semiconductor field effect transistor (MOSFET), wherein the gate insulating film includes a silicon oxide (SiO2) film. On the contrary, the field effect transistor Q may be a p-channel conductivity type. Alternatively, the field effect transistor Q may include a metal insulator semiconductor FET (MISFET), wherein the gate insulating film includes a silicon nitride film or a multilayer film (composite film) including a silicon nitride (Si3N4) film and a silicon oxide film.

[0194] like Figure 1 and Figures 2 to 4 As shown, the field effect transistor Q is arranged in the semiconductor 5 of the semiconductor layer 2 .

[0195] The field effect transistor Q includes: a channel forming portion 9, which is arranged in the first portion 6 of the semiconductor 5; and a gate electrode 15, which is separated from the second portion 7 of the semiconductor 5 and is arranged across the upper surface 5a and side surfaces 6b1 and 6b2 of the first portion 6 of the semiconductor 5, with a gate insulating film 13 interposed therebetween.

[0196] In addition, the field effect transistor Q includes: a side surface spacer 19, which is arranged on the side surface of the gate electrode 15 so as to surround the gate electrode 15; and a main electrode region pair 21a and 21b, which are arranged in the semiconductor 5 on both sides of the gate electrode 15 in the gate length direction (X direction) and serve as a source region and a drain region.

[0197] <Gate Electrode>

[0198] like Figures 2 to 4 As shown, the gate electrode 15 includes: a head 15a, which is arranged on the upper surface 5a of the first part 6 of the semiconductor 5, with the gate insulating film 13 interposed therebetween; and a leg 15b, which is integrally formed with the head 15 and is arranged outside each of the two side surfaces 6b1 and 6b2 located on opposite sides of the first part 6 of the semiconductor 5, with the gate insulating film 13 interposed therebetween.

[0199] Here, the gate electrode 15 is preferably configured so that the first portion 6 of the semiconductor 5 is sandwiched between the legs 15b in the width direction (Y direction). Therefore, when the number of the first portions 6 is represented by "n", the number of the legs 15b of the gate electrode 15 is generally "n+1". In the first embodiment, since two first portions 6 are provided, the gate electrode 15 includes three legs 15b.

[0200] The head 15a of the gate electrode 15 protrudes above the insulating layer 11. Then, each of the three legs 15b of the gate electrode 15 is provided in the insulating layer 11 together with the semiconductor 5. The gate electrode 15 including the head 15a and the leg 15b includes, for example, a polysilicon (doped polysilicon) film doped with impurities for reducing the resistance value.

[0201] The head 15a has a rectangular shape in a top view and has a three-dimensional structure including an upper surface and four side surfaces. Each of the three legs 15b has a three-dimensional structure that extends in the thickness direction (Z direction) of the semiconductor layer 2 and in the height direction of the semiconductor 5 and includes a lower surface and four side surfaces.

[0202] like Figure 3As shown, the gate electrode 15 has two side surfaces 15a1 and 15a2 of the head 15a in the X direction (gate length direction) and two side surfaces 15b1 and 5b2 of the leg 15b in the X direction (gate length direction) in the cross-sectional view, and the two side surfaces are flush with each other. That is, the side surface 15a1 of the head 15a and the side surface 15b1 of the leg 15b form a plane that extends continuously in the thickness direction (Z direction) of the semiconductor layer 2, and the side surface 15a2 of the head 15a and the side surface 15b2 of the leg 15b form a plane that extends continuously in the thickness direction (Z direction) of the semiconductor layer 2.

[0203] Here, the plan view refers to the case where the semiconductor layer 2 is observed from a direction along the thickness direction (Z direction) of the semiconductor layer 2. In addition, the cross-sectional view refers to the case where a longitudinal section along the thickness direction (Z direction) of the semiconductor layer 2 is viewed from a direction (X direction or Y direction) orthogonal to the thickness direction (Z direction) of the semiconductor layer 2.

[0204] <Gate Insulating Film>

[0205] like Figure 4 As shown, the gate insulating film 13 is provided between the first portion 6 of the semiconductor 5 and the gate electrode 15 across the upper surface 5a of the first portion 6 and the two side surfaces 6b1 and 6b2 of the first portion 6. In the first embodiment, since the semiconductor 5 includes two first portions 6, the gate insulating film 13 is provided across the upper surface 5a and the two side surfaces 6b1 and 6b2 of each of the two first portions 6. The gate insulating film 13 includes, for example, a silicon oxide film.

[0206] <Side Surface Spacer>

[0207] like Figure 1 and 2 As shown in FIGS. 4A to 4B , the side surface spacer 19 is provided on the side surface of the head portion 15a of the gate electrode 15 so as to surround the head portion 15a. That is, the side surface spacer 19 extends across the first portion 6 located outside the gate electrode 15 in the gate length direction (X direction) and the dielectric portion 17 to be described later in the plan view to cover the first portion 6 and the dielectric portion 17 located outside the gate electrode 15 in the gate length direction (X direction).

[0208] The side surface spacer 19 is arranged to be aligned with the head 15a of the gate electrode 15. In other words, the side surface spacer 19 is formed in a self-aligned manner with respect to the head 15a of the gate electrode 15. For example, the side surface spacer 19 can be formed by forming an insulating film on the side of the insulating layer 11 away from the base 4 by a chemical vapor deposition (CVD) method to cover the gate electrode 15, and then performing anisotropic trunk etching such as reactive ion etching (RIE) on the insulating film. The side surface spacer 19 includes, for example, a silicon oxide film.

[0209] <Main Electrode Area>

[0210] like Figure 2 As shown, each of the main electrode region pairs 21a and 21b includes an n-type extension region 18 and an n-type contact region 20, the n-type extension region 18 including an n-type semiconductor region arranged in the semiconductor 5 aligned with the gate electrode 15, and the n-type contact region 20 including an n-type semiconductor region arranged in the semiconductor 5 aligned with the side surface spacer 19 located on the side surface of the gate electrode 15. That is, each of the main electrode region pairs 21a and 21b including the n-type extension region 18 and the n-type contact region 20 is arranged in the semiconductor 5 aligned with the gate electrode 15. Most of the n-type extension region 18 is arranged in the first portion 6 of the semiconductor 5. Most of the n-type contact region 20 is arranged in the second portion 7 of the semiconductor 5.

[0211] like Figure 1A As shown in FIG. 1 , in a plan view, the n-type contact region 20 is provided throughout the second portion 7 of the semiconductor 5 and is in contact with the side surface 7b1 (7b 11 , 7b 12 , 7b 13 The n-type contact region 20 and the n-type extension region 18 are in contact with each other in the first portion 6 of the semiconductor 5 .

[0212] like Figure 3 As shown, both the n-type extension region 18 and the n-type contact region 20 have thicknesses in the thickness direction (Z direction) of the semiconductor layer 2 and in the height direction of the semiconductor 5. Then, the n-type contact region 20 is formed deeper than the n-type extension region 18, in other words, formed thicker.

[0213] like Figure 2 and Figure 4 As shown in , the field effect transistor Q of the first embodiment is configured as a so-called fin type in which a gate electrode 15 is provided in an island-shaped semiconductor 5 as a fin portion with a gate insulating film 13 interposed therebetween.

[0214] In this fin field effect transistor Q, the length between the main electrode region pair 21a and 21b is the channel length L (≈gate length Lg), and the value obtained by multiplying the length of the width W1 of the first part 6 on the upper surface 5a side and the height of the two side surfaces 6b1 and 6b2 of the first part 6 in the area where the gate electrode 15 of the semiconductor 5 and the first part 6 overlap each other three-dimensionally (the length of the outline of the semiconductor 5) by the number of first parts 6 is the channel width W (≈gate width).

[0215] Therefore, the fin field effect transistor Q can increase the channel width W by increasing the width W1 of the first portion 6 of the semiconductor 5 and the height of the first portion 6, thereby allowing the channel area (channel length L×channel width W) to be increased. Then, the fin field effect transistor Q can increase the channel area (channel length L×channel width W) by increasing the number of first portions 6.

[0216] For example, the field effect transistor Q is an enhancement type (normally off type) in which a drain current flows when a gate voltage higher than or equal to a threshold voltage is applied to the gate electrode 15, or a suppression type (normally off type) in which a drain current flows even when no voltage is applied to the gate electrode 15. For example, the first embodiment adopts but is not limited to the enhancement type. In the case of the enhancement type, in the field effect transistor Q, a channel (inversion layer) electrically connecting the main electrode region pair 21a and 21b is formed (induced) in the channel forming portion 9 by the voltage applied to the gate electrode 15, and a current (drain current) flows from the drain region side (for example, the main electrode region 21b side) to the source region side (for example, the main electrode region 21a side) through the channel of the channel forming portion 9.

[0217] <Contact Electrode and Wiring>

[0218] like Figure 2 As shown, the gate electrode 15 is electrically connected to the wiring 23c located on the insulating layer 22 via the contact electrode 22c provided in the insulating layer 22. In addition, the main electrode region 21a of one of the main electrode region pair 21a and 21b is electrically connected to the wiring 23a located on the insulating layer 22 via the contact electrode 22a provided in the insulating layer 22. Moreover, the main electrode region 21b of the other of the main electrode region pair 21a and 21b is electrically connected to the wiring 23b located on the insulating layer 22 via the contact electrode 22b provided in the insulating layer 22. As the material of the contact electrodes 22a, 22b and 22c, for example, a high melting point metal film such as titanium (Ti) or tungsten (W) can be used.

[0219] <Dielectric Part>

[0220] like Figure 1 and Figure 3 As shown in , the semiconductor device 1A according to the first embodiment further includes a dielectric portion (isolation region) 17 which is provided between the gate electrode 15 of the semiconductor 5 and the second portion 7 in the X direction (first direction) and has a relative dielectric constant smaller than that of the insulating layer 11. Specifically, the dielectric portion 17 is provided between the side surface 7b1 of the second portion 7 and the leg portion 15b of the gate electrode 15.

[0221] In the first embodiment, since the semiconductor 5 includes two second portions 7, the dielectric portion 17 is provided between one of the two second portions 7 and the leg portion 15b of the gate electrode 15 and between the other of the two second portions 7 and the leg portion 15b of the gate electrode 15. That is, in the first embodiment, the dielectric portion 17 is provided on either side of the gate electrode 15 in the gate length direction (X direction).

[0222] Furthermore, in the first embodiment, since the semiconductor 5 includes two first portions 6, the dielectric portion 17 is provided on three side surfaces 7b1 (7b 11 , 7b 12 , 7b 13 ) between each of the legs 15b of the gate electrode 15.

[0223] That is, in the first embodiment, the three dielectric portions 17 separated from each other by the two first portions 6 are arranged between the side surface portion 7b1 of one of the two second portions 7 and the leg portion 15b of the gate electrode 15, and the three dielectric portions 17 separated from each other by the two first portions 6 are further arranged between the side surface portion 7b1 of the other of the two second portions 7 and the leg portion 15b of the gate electrode 15.

[0224] In other words, the dielectric portion 17 is provided on both sides of the first portion 6 in the width direction (Y direction) between the side surface 7b1 of one second portion 7 and the leg portion 15b of the gate electrode 15 so as to sandwich the first portion 6. Then, also on the other second portion 7 side, the dielectric portion 17 is provided on both sides of the first portion 6 in the width direction (Y direction) between the side surface 7b1 of the other second portion 7 and the leg portion 15b of the gate electrode 15 so as to sandwich the first portion 6.

[0225] like Figure 3 As shown, the side surface 7b of the second portion 7 11 The dielectric portion 17 between the second portion 7 and the leg portion 15b of the gate electrode 15 extends from the upper surface 5a of the second portion 7 toward the base 4 (in the depth direction (Z direction) of the semiconductor layer 2), and is connected to the insulating layer 11a provided on the bottom surface of the leg portion 15b of the gate electrode 15. The dielectric portion 17 electrically isolates the second portion 7 of the semiconductor 5 from the leg portion 15b of the gate electrode 15, and electrically isolates the first portion 6 from the leg portion 15b of the gate electrode 15 between the second portion 7 and the leg portion 15a of the gate electrode 15.

[0226] Here, in the manufacturing process of the semiconductor device 1A, the insulating layer 11 between the two second portions 7 of the semiconductor 5 is selectively etched to form the recessed portions 12a and 12b having a smaller height (thickness) than the semiconductor 5 (see FIG. Figures 13 to 15 ), so that the insulating layer 11 remains on the bottom surface of each of the recesses 12a and 12b, to obtain Figure 3 The insulating layer 11a is shown in FIG.

[0227] In the first embodiment, the insulating layer 11 a is provided, but the insulating layer 11 a need not be provided. In this case, the gate insulating film is interposed between the bottom surface of the leg 15 b of the gate electrode 15 and the base 4 of the semiconductor layer 2 .

[0228] It should be noted that Figure 3 , the side surface 7b of the second portion 7 is shown 11 The dielectric portion 17 between the leg portion 15b of the gate electrode 15 is used as an example, but the side surface 7b of the second portion 7 12 The dielectric portion 17 between the leg portion 15 b of the gate electrode 15 and the side surface 7 b of the second portion 7 13 The dielectric portion 17 between the leg portion 15b of the gate electrode 15 also has a dielectric Figure 3 The dielectric portion 17 shown in FIG. 1 is the same configuration as that shown in FIG. Figure 3 Description of the side surface 7b of the second portion 7 12 The dielectric portion 17 between the leg portion 15 b of the gate electrode 15 and the side surface 7 b of the second portion 7 13 The dielectric portion 17 is formed between the leg portion 15 b of the gate electrode 15 .

[0229] As in Figure 1 and Figure 3 As shown in FIG. 1 , in a plan view, the side surface 7b of the second portion 7 11 The dielectric portion 17 between the leg portion 15b of the gate electrode 15 is surrounded on all sides by the first portion 6, the second portion 7, the leg portion 15b of the gate electrode 15, and the insulating layer 11. Similarly, in a plan view, the side surface 7b of the second portion 7 12 The dielectric portion 17 between the leg 15 b of the gate electrode 15 is also surrounded by the first portion 6 , the second portion 7 , the leg 15 b of the gate electrode 15 , and the insulating layer 11 on all sides.

[0230] On the other hand, in a plan view, the side surface 7b of the second portion 7 13 The dielectric portion 17 between the leg 15 b of the gate electrode 15 is surrounded on all sides by the two first portions 6 , the second portion 7 , and the leg 15 b of the gate electrode 15 .

[0231] The dielectric portion 7 is not limited to such a structure, and for example, a dielectric film (Low-k film) having a relative dielectric constant lower than that of the insulating layer 11 can be used. As such a dielectric film, for example, a carbon-doped silicon oxide (SiOC) film obtained by doping silicon oxide (SiO) with carbon (C) can be used. The relative dielectric constant of the SiOC film is lower than that of the silicon oxide film. For example, the relative dielectric constant of the SiOC film is about 1.5 to 2, the relative dielectric constant of the silicon oxide film is about 4 to 4.2, and the relative dielectric constant of the air is about 1.

[0232] In addition, it is preferable that the relative dielectric constant of the dielectric portion 7 is lower than the dielectric constant of the gate insulating film 13. In addition, the width W3 of the dielectric portion 7 along the X direction (see Figure 3 ) is preferably greater than the film thickness W4 of the gate insulating film 11 (see Figure 4 ).

[0233] <<Method of Manufacturing Semiconductor Device>>

[0234] Next, we will refer to Figures 5 to 35 A method for manufacturing the semiconductor device 1A is described.

[0235] In the first embodiment, a description will be given focusing on the formation of the field effect transistor Q and the dielectric portion 17 included in the method for manufacturing the semiconductor device 1A.

[0236] First, if Figure 5 (Schematic plan view of main parts), Figure 6 (Along Figure 5 Schematic cross-sectional view taken along line a5-a5 in FIG. Figure 7 (Along Figure 5 Schematic cross-sectional view taken along line b5-b5 in FIG. Figure 8 (Along Figure 5 As shown in the schematic cross-sectional view taken along line c5-c5 in FIG. 1 , an island-shaped semiconductor 5 protruding above the base 4 is formed.

[0237] The semiconductor 5 is formed into a three-dimensional structure, which includes: a first portion 6 extending in the X direction (first direction); and a second portion 7, which is integrally provided with the first portion 6 in the X direction, and the width W2 of the second portion in the same direction as the width W1 of the first portion 6 along the Y direction (second direction) intersecting the X direction is greater than the width W1 of the first portion 6; and wherein the first portion 6 and the second portion 7 have an upper surface 5a and a side surface 5b. The side surface 5b includes side surfaces 6b1 and 6b2 of the first portion 6 and side surfaces 7b1, 7b2, 7b3 and 7b4 of the second portion 7.

[0238] In the first embodiment, for example, the semiconductor 5 is formed to include but is not limited to a three-dimensional structure including two first portions 6 arranged side by side at a predetermined interval in the Y direction and two second portions 7 arranged on both end sides of each of the two first portions 6 in the X direction. In this case, the side surface 5b includes three side surfaces 7b1 obtained by dividing the side surface 7b1 with a connecting portion connecting the first portion 6 and the second portion 7. 11 , 7b 12 and 7b 13 As the side surface 7b1.

[0239] By selectively etching the semiconductor layer 2 to a depth where the base 4 remains, a semiconductor 5 including the first portion 6 and the second portion 7 can be formed. The semiconductor layer 2 can be, but is not limited to, a semiconductor substrate including, for example, silicon (Si) as a semiconductor material, for example, single crystal as crystallinity, and for example, p-type conductivity type as conductivity type.

[0240] Note that, in the semiconductor layer 2 , the p-type well region 3 which is a p-type semiconductor region is formed before the semiconductor 5 is formed.

[0241] Next, if Fig. 9 (Schematic plan view of main parts), Fig.10 (Along Fig. 9 Schematic cross-sectional view taken along line a9-a9 in FIG. Fig.11 (Along Fig. 9 Schematic cross-sectional view taken along line b9-b9 in FIG. Fig.12 (Along Fig. 9 As shown in the schematic cross-sectional view taken along the line c9-c9 in FIG, in a plan view, an insulating layer 11 surrounding the first portion 6 and the second portion 7 of the semiconductor 5 is formed outside the semiconductor 5. For example, the insulating layer 11 can be formed by forming a silicon oxide film on the entire surface of the base 4 of the semiconductor layer 2 and the semiconductor 5 by a known film forming method, and then selectively removing the silicon oxide film on the semiconductor 5 by a CMP method.

[0242] In this step, the surface layer of the insulating layer 11 away from the base 4 is flattened, and the surface layer of the insulating layer 11 and the upper surface 5a of the semiconductor 5 become almost flush with each other. Then, the insulating layer 11 is formed with a film thickness almost equal to the height (protrusion) of the semiconductor 5.

[0243] Furthermore, in this step, the insulating layer 11 flush with the upper surface 5 a of the semiconductor 5 is also formed in the region surrounded by the two first portions 6 and the two second portions 7 .

[0244] Next, the insulating layer 11 located outside the second portion 6 of the semiconductor 5 in the width direction (Y direction) is selectively removed to form recesses 12a, 12a, 12b. Fig.13 As shown in (schematic plan view of main part), the side surfaces 6b1 and 6b2 of the first part 6 and the side surface 7b1 of each of the two second parts 7 are exposed on the outside in the width direction (Y direction) of the first part 6 of the semiconductor 5, Fig.14 (Along Fig.13 Schematic cross-sectional view taken along line b13-b13 in FIG. Fig.15 (Along Fig.13 Schematic cross-sectional view taken along line c13-c13 in FIG.

[0245] One of the two recesses 12a and 12a is formed on a side away from the other of the two first portions 6 to expose the side surface 6b1 of the one first portion 6 and the side surface 7b1 (7b2) of each of the two second portions 7. 11 ).

[0246] Furthermore, the other of the two recesses 12a and 12a is formed on a side of the other of the two first portions 6 away from one of the two first portions 6 to expose the side surface 6b1 of the other first portion 6 and the side surface 7b1 (7b2) of each of the two second portions 7. 12 ).

[0247] Then, a recess 12b is formed between the two first portions 6 to expose the side surface 6b2 of each of the two first portions 6 and the side surface 7b1 (7b 13 ).

[0248] In this step, the recessed portions 12 a and 12 b are formed to a depth such that a portion of the insulating layer 11 remains on the bottom surface as the insulating layer 11 a , for example, but not limited thereto.

[0249] Next, if Fig.16 (Schematic plan view of main parts), Fig.17 (Along Fig.16 Schematic cross-sectional view taken along line a16-a16 in FIG. Fig.18 (Along Fig.16 A schematic cross-sectional view taken along line b16-b16 in FIG. Fig.19 (Along Fig.16As shown in the schematic cross-sectional view taken along the line c16-c16 in FIG. 1 , a gate insulating film 13 is formed on the upper surface 5a of each of the two first portions 6 of the semiconductor 5 and the side surfaces 6b1 and 6b2 of each of the two first portions 6. For example, the gate insulating film 13 may be formed by forming a silicon oxide film on the upper surface 5a and the side surfaces 6b1 and 6b2 of each of the two first portions 6 by a thermal oxidation method or a deposition method.

[0250] In this step, the upper surface 5a and the side surface 7b1 (7b 11 , 7b 12 and 7b 13 ) is further formed on a gate insulating film 13.

[0251] Then, if Fig. 20 (Schematic plan view of main parts), Fig.21 (Along Fig. 20 Schematic cross-sectional view taken along line a20-a20 in FIG. Fig. 22 (Along Fig. 20 Schematic cross-sectional view taken along line b20-b20 in FIG. Fig.23 (Along Fig. 20 As shown in the schematic cross-sectional view taken along the line c20-c20 in FIG. 1 , a conductive film 14 is formed on the semiconductor layer 2 including the inner side of the recesses 12a and 12b, the upper surface 5a of the semiconductor 5, and the insulating layer 11. As the conductive film 14, for example, a polysilicon (doped polysilicon) film doped with impurities for reducing the resistance value during or after film formation can be used. At the portion where the gate insulating film 13 is formed on the semiconductor 5, the gate insulating film 13 is interposed between the semiconductor 5 and the conductive film 14.

[0252] Next, the conductive film 14 is patterned using known photolithography and dry etching techniques, and the conductive film 14 is patterned as shown in FIG. Fig.24 (Schematic plan view of main parts), Fig.25 (Along Fig.24 As shown in the schematic cross-sectional view taken along the line a24-a24 in FIG. Fig.26 (Along Fig.24 A schematic cross-sectional view taken along line b24-b24 in FIG. Fig. 27 (Along Fig.24 A schematic cross-sectional view taken along line c24-c24 in FIG. 1 ) forms a gate electrode 15 separated from each of the two second portions 7 of the semiconductor 5 and facing the upper surface 5a and side surfaces 6b1 and 6b2 of each of the two first portions 6, with the gate insulating film 13 interposed therebetween.

[0253] The gate electrode 15 includes: a head 15a, which is arranged on the upper surface 5a of the first part 6 of the semiconductor 5, with the gate insulating film 13 interposed therebetween; and a leg 15b, which is integrally formed with the head 15 and is arranged outside each of the two side surfaces 6b1 and 6b2 located on opposite sides of the first part 6 of the semiconductor 5, with the gate insulating film 13 interposed therebetween.

[0254] The head portion 15 a intersects the recess 12 a , the first portion 6 , the recess 12 b , the first portion 6 , and the recess 12 a in this order in the width direction (Y direction) of the first portion 6 of the semiconductor 5 .

[0255] The leg portion 15b is formed in each of the three recesses 12a, 12b, and 12a, and has one end connected to the head portion 15a.

[0256] In this step, if Fig.26 As shown in , the gate electrode 15 is formed so that the two side surfaces 15a1 and 15a2 of the head 15a in the X direction (gate length direction) and the two side surfaces 15b1 and 5b2 of the leg 15b in the X direction (gate length direction) are flush with each other in the cross-sectional view. That is, one side surface 15a1 of the head 15a and one side surface 15b1 of the leg 15b form a plane extending continuously in the thickness direction (Z direction) of the semiconductor layer 2, and the other side surface 15a2 of the head 15a and the other side surface 15b2 of the leg 15b form a plane extending continuously in the thickness direction (Z direction) of the semiconductor layer 2.

[0257] In addition, in this step, Fig.24 and Fig.26 As shown in FIG. 1 , the gap 16 is formed on the side surface 7b1 (7b 11 , 7b 12 , 7b 13 ) and the leg portion 15b of the gate electrode 15. Fig.26 In the embodiment, the side surface 7b of the second portion 7 11 The gap 16 between the side surfaces 15 b 1 and 15 b 2 of the leg portion 15 b of the gate electrode 15 is shown as an example.

[0258] In the first embodiment, since the semiconductor 5 includes two first portions 6 and two second portions 7 , the space 16 includes three spaces formed on each of both sides (sides adjacent to the two second portions 7 ) of the gate electrode 15 in the gate length direction in plan view.

[0259] Furthermore, in this step, when the conductive film 14 is patterned, the gate insulating film 13 on the upper surface 5 a and the side surface 7 b 1 of the second portion 7 is removed by side etching and over etching.

[0260] Next, if Fig.28 (Schematic plan view of main parts) and Fig.29 (Along Fig.28 As shown in the schematic cross-sectional view taken along line b28-b28 in FIG. 1 , a dielectric portion 17 having a lower relative dielectric constant of the insulating layer 11 is formed in each gap 16.

[0261] For example, but not limited to, a SiOC film having a relative dielectric constant lower than that of the silicon oxide film is formed between the semiconductor layer 2, the semiconductor 5 and the insulating layer 11 including in the gap 16, and then the SiOC film on the semiconductor 5 and the insulating layer 11 is selectively removed to form the dielectric portion 17.

[0262] Through this step, the dielectric portion 17 having a relative dielectric constant smaller than that of the insulating layer 11 can be selectively formed on the side surface 7b1 (7b 11 , 7b 12 and 7b 13 ) and the leg portion 15b of the gate electrode 15.

[0263] Next, if Fig.30 (Schematic plan view of main parts), Fig.31 (Along Fig.30 A schematic cross-sectional view taken along line a30-a30 in FIG. Fig.32 (Along Fig.30 As shown in the schematic cross-sectional view taken along line b30-b30 in FIG. 1 , a pair of n-type extension regions 18 each including an n-type semiconductor region is formed in each semiconductor 5 located on both sides of the gate electrode 15 in the X direction. By using the gate electrode 15, the dielectric portion 17, and the insulating layer 11 as a mask for impurity introduction, arsenic ions (As + ) or phosphorus ion (P + ) is implanted into each semiconductor 5 located on both sides of the gate electrode 15 in the gate length direction (X direction), and then the semiconductor 5 is subjected to heat treatment for activating the impurities to form the extension region 18.

[0264] In this step, each of a pair of n-type extension regions 18 is formed in the first portion 6 and the second portion 7 of the semiconductor 5 in alignment with the gate electrode 15 .

[0265] Furthermore, in this step, the dielectric portion 17 functions as a protective layer and thus can suppress the phenomenon that impurity ions are injected into the semiconductor 5 and the base 4 through between the second portion 7 of the semiconductor 5 and the leg 15 b of the gate electrode 15 .

[0266] Then, if Fig.33 (Schematic plan view of main parts), Fig.34 (Along Fig.33 A schematic cross-sectional view taken along line a33-a33 in FIG. Fig.35 (Along Fig.33 As shown in the schematic cross-sectional view taken along the line b33-b33 in FIG, the side surface spacer 19 is formed on the side surface including the side surfaces 15a1 and 15a2 of the head 15a of the gate electrode 15 protruding from the insulating layer 11. The side surface spacer 19 can be formed by forming an insulating film on the insulating layer 11 by a CVD method to cover the semiconductor 5 and the head 15a of the gate electrode 15, and then performing anisotropic dry etching such as RIE on the insulating film. As the insulating film, for example, a silicon oxide film can be used.

[0267] The side surface spacer 19 is formed on the side surface of the head portion 15a of the gate electrode 15 so as to surround the head portion 15a of the gate electrode 15, and the side surface spacer 19 is formed in a self-aligned manner with respect to the gate electrode 15. The side surface spacer 19 extends across the first portion 6 and the dielectric portion 17 located outside the gate electrode 15 in the gate length direction to cover the first portion 6 and the dielectric portion 17.

[0268] Then, if Fig.33 (Schematic plan view of main parts), Fig.34 (Along Fig.33 A schematic cross-sectional view taken along line a33-a33 in FIG. Fig.35 (Along Fig.33 As shown in the schematic cross-sectional view taken along line b33-b33 in FIG. 1 , a pair of n-type contact regions 20 each including an n-type semiconductor region is formed in each semiconductor 5 located at both end sides of the gate electrode 15 in the gate length direction (X direction). By using the insulating layer 11, the gate electrode 15 and the side surface spacer 19 as a mask for impurity introduction, arsenic ions (As + ) or phosphorus ion (P + ) is ion-implanted into the semiconductor 5 (second portion 7) in a plan view between the insulating layer 11 and the side surface spacer 19, and then the semiconductor 5 (second portion 7) is heat-treated to activate the impurities to form a pair of n-type contact regions 20. The pair of n-type contact regions 20 are formed across the second portion 7 and the first portion 6 in a self-aligned manner relative to the side surface spacer 19.

[0269] In this step, n type extension region 18 and n type contact region 20 are in contact with each other at first portion 6 .

[0270] Furthermore, in this step, a pair of main electrode regions 21 a and 21 b each including an n-type extension region 18 and an n-type contact region 20 are formed in the semiconductor 5 .

[0271] Through this step, Figures 1 to 4 The field effect transistor Q shown in FIG. 1 becomes almost completed.

[0272] Note that the n-type contact region 20 can be selectively formed in the second portion 6 (only the second portion 6 ) by controlling the width of the side surface spacer 19 in the planar direction.

[0273] <<Main Effects of First Embodiment>>

[0274] Next, we will refer to Fig.36 and Fig.37 The main effects of the first embodiment are described.

[0275] Fig.36 is a schematic longitudinal sectional view of the field effect transistor Q of the first embodiment, showing parasitic capacitance added to the field effect transistor Q.

[0276] Fig.37 It is a longitudinal cross-sectional view showing the parasitic capacitance of the field effect transistor Qz of the comparative example.

[0277] like Fig.37 As shown in , in the semiconductor device of the comparative example, the insulating layer 11 surrounding the semiconductor 5 is also provided between the second portion 7 of the semiconductor 5 and the leg portion 15b of the gate electrode 15. Therefore, a parasitic amount 26 of the insulating layer 11 having the second portion 7 as one electrode, the leg portion 15b of the gate electrode 15 as the second electrode, and the second portion 7 of the semiconductor 5 and the leg portion 15b of the gate electrode 15 as a dielectric is added to the field effect transistor Qz. This parasitic capacitance 26 becomes a factor that reduces the noise characteristics of the field effect transistor Qz and reduces the reliability of the semiconductor device.

[0278] On the other hand, Fig.36 As shown in FIG. 1 , in the semiconductor device 1A of the first embodiment, the dielectric portion 17 is provided between the second portion 7 of the semiconductor 5 and the leg portion 15 b of the gate electrode 15. Therefore, even in the first embodiment, a parasitic amount 25 having the second portion 7 as one electrode, the leg portion 15 a of the gate electrode 15 as the second electrode, and the dielectric portion 17 between the second portion 7 and the leg portion 15 b of the gate electrode 15 as a dielectric is added to the field effect transistor Q.

[0279] However, the relative dielectric constant of the dielectric portion 17 is smaller than that of the insulating layer 11. Therefore, the parasitic capacitance 25 added to the field effect transistor Q can be made smaller than the parasitic capacitance 26 added to the field effect transistor Qz of the comparative example.

[0280] Furthermore, the parasitic capacitance added to the field effect transistor Q includes not only the parasitic capacitance 25 but also other parasitic capacitances, and the parasitic capacitance 25 can be reduced, thereby suppressing degradation of noise characteristics of the field effect transistor Q and improving the reliability of the semiconductor device 1A.

[0281] In addition, in the step of forming the gate electrode 15 of the method for manufacturing the semiconductor device 1A according to the first embodiment, the gate electrode 15 including the head 15a and the leg 15b is formed at one time by processing the conductive film 14, so that in the cross-sectional view, the two side surfaces 15a1 and 15a2 of the head 15a in the X direction (gate length direction) and the two side surfaces 15b1 and 15b2 of the leg 15b in the X direction (gate length direction) can be formed to be flush with each other.

[0282] In addition, based on the description using reference numerals in the first embodiment, in the conventional manufacturing process, the head 15a and the leg 15b of the gate electrode 15 are formed in separate processing steps. Therefore, due to the misalignment or size change of the mask, a step is formed between the head 15a and the leg 15b, and further, the step height changes. Due to the change in the step height, the parasitic capacitance Cgd between the gate electrode and the drain region also changes, and the noise characteristics of the field effect transistor are also reduced.

[0283] On the other hand, in the method of manufacturing the semiconductor device 1A of the first embodiment, the side surfaces 15a1 and 15a2 of the head 15a and the side surfaces 15b1 and 5b2 of the leg 15b can be made flush with each other in a cross-sectional view so that the parasitic capacitance Cgd between the gate electrode 15 and the drain region (for example, the main electrode region 21b) is not affected by the process variation in the prior art. Therefore, according to the method of manufacturing the semiconductor device 1A of the first embodiment, the degradation of the noise characteristics of the field effect transistor Q can be suppressed.

[0284] Furthermore, according to the method of manufacturing the semiconductor device 1A of the first embodiment, a dielectric portion 17 having a relative dielectric constant lower than that of the insulating layer 11 surrounding the semiconductor 5 can be formed between the second portion 7 of the semiconductor 5 and the leg portion 15 b of the gate electrode 15, thereby further suppressing the degradation of the noise characteristics of the field effect transistor Q. Therefore, the reliability of the semiconductor device 1A can be further improved.

[0285] <<Modification of First Embodiment>>

[0286] Note that, although the case where the dielectric portion 17 is provided on either side of the gate electrode 15 in the gate length direction has been described in the above-mentioned first embodiment, Fig.38As shown, the dielectric portion 17 may be provided on either side of the gate electrode 15 in the gate length direction (X direction). That is, the dielectric portion 17 may be provided on at least either side of the gate electrode 15 in the gate length direction. It should be noted that, in consideration of the degradation of the noise characteristics of the field effect transistor Q, it is preferred that the dielectric portion 17 be provided on both sides of the gate electrode 15 in the gate length direction, as in the above-described first embodiment.

[0287] Furthermore, although the semiconductor 5 including the two first portions 6 arranged side by side in the Y direction has been described in the above-mentioned first embodiment, the present technology can also be applied to a semiconductor device such as Fig.39 The semiconductor 5 shown in FIG. 1 includes one first portion 6. Even in this case, it is only necessary to provide the dielectric portion 17 on at least either side of the gate electrode 15 in the gate length direction. Fig.39 A configuration in which the dielectric portions 17 are provided on both sides of the gate electrode 15 in the gate length direction is shown as an embodiment.

[0288] Furthermore, the present technology is also applicable to the semiconductor 5 including three or more first portions 6 arranged side by side in the Y direction.

[0289] Furthermore, although the semiconductor 5 including the second portion 7 provided on both sides of the first portion 6 in the X direction has been described in the above embodiment, the present technology is also applicable to the semiconductor 5 including the second portion 7 provided on at least either side of the first portion 6 in the X direction.

[0290] Furthermore, although the case where the field effect transistor Q is of n-channel conductivity type has been described in the above-mentioned first embodiment, the present technology can also be applied to the case where the field effect transistor Q is of p-channel conductivity type.

[0291] Furthermore, although the case where the field effect transistor Q is of the enhancement type has been described in the above-mentioned first embodiment, the present technology can also be applied to the case where the field effect transistor Q is of the inhibition type.

[0292] Furthermore, although the case where one field effect transistor Q is provided in the first portion 6 of the semiconductor 5 has been described in the above-mentioned first embodiment, the present technology can also be applied to the case where a plurality of field effect transistors Q are provided in the first portion 6 .

[0293] [Second embodiment]

[0294] The semiconductor device 1B according to the second embodiment of the present technology has a configuration basically similar to that of the semiconductor device 1A according to the above-described first embodiment, and is different in the following configuration.

[0295] That is, Fig.40As shown, the semiconductor device 1B according to the second embodiment of the present technology includes a dielectric portion 17B instead of the dielectric portion 17B of the first embodiment described above. Figure 3 The dielectric portion 17B shown in FIG. 1 includes a cavity 17b1 having a lower relative dielectric constant than the insulating layer 11. During the manufacturing process of the semiconductor device 1B, the gap 16 (see FIG. 1B ) between the second portion 7 of the semiconductor 5 and the leg portion 15b of the gate electrode 15 is formed. Fig.24 and Fig.26 ) is formed with a low coverage insulating film 17b2, and the cavity 17b1 can be formed in a simple manner. The other configurations are substantially the same as those of the first embodiment.

[0296] The semiconductor device 1B according to the second embodiment can also produce effects similar to those produced by the semiconductor device 1A according to the above-described first embodiment.

[0297] In addition, the insulating film 17b2 extending from the upper surface 5a of the semiconductor 5 to the cavity 17b1 and the insulating film 17b2 extending from the cavity 17b1 to the insulating layer 11a are preferably formed to a film thickness that prevents the penetration of ion-implanted impurities in the step of forming the extension region. In the second embodiment, the insulating layer 11a remains as in the first embodiment, but when the insulating layer 11a does not remain, it is necessary to control the film thickness of the insulating film 17b2.

[0298] In addition, as the insulating film 17 b 2 , an insulating film having a lower dielectric constant than the insulating layer 11 can be used.

[0299] [Third Embodiment]

[0300] In the third embodiment, a case where two field effect transistors are provided in one semiconductor will be described.

[0301] The semiconductor device 1C according to the third embodiment of the present technology is basically similar in configuration to the semiconductor device 1A according to the above-described first embodiment, and is different in the following configuration.

[0302] That is, Figures 41 to 43 As shown, a semiconductor device 1C according to a third embodiment of the present technology includes an island-shaped semiconductor 5 provided in a semiconductor layer 2 and two field effect transistors Q1 and Q2 provided in the semiconductor 5. In addition, similar to the above-mentioned first embodiment, the semiconductor device 1C according to the third embodiment includes an insulating layer 11 provided outside the semiconductor 5 to surround the semiconductor 5.

[0303] The semiconductor layer 2 includes a base 4 extending two-dimensionally in the X and Y directions and an island-shaped semiconductor 5 protruding above the base 4 (in the Z direction).

[0304] The semiconductor 5 of the third embodiment has a three-dimensional structure including two first portions 6 arranged side by side at a predetermined interval in the Y direction, two second portions 7 arranged on both end sides in the X direction of each of the two first portions 6, and a third portion 28 arranged at a middle portion in the X direction between the two first portions 6, and wherein the first portion 6, the second portion 7, and the third portion 28 have an upper surface 5a and a side surface 5b. The semiconductor 5 of the third embodiment is substantially similar in configuration to the semiconductor 5 of the first embodiment described above, and differs in that the third portion 28 is included.

[0305] The third portion 28 is substantially similar to the configuration of the second portion 7. In a manner similar to the second portion 7, the third portion 28 has a width W5 wider than the width W1 of the first portion 6 in the same direction as the width W1 of the first portion 6. The third portion 28 includes side surfaces 28b1 and 28b2 located at opposite sides in the X direction and side surfaces 28b3 and 28b4 located at opposite sides in the Y direction. Then, each of the side surfaces 28b1 and 28b2 is divided into three parts by a connection portion connected to the third portion 28 by the first portion 6.

[0306] That is, the side surface 5b of the semiconductor 5 of the third embodiment includes side surfaces 6b1 and 6b2 of each of the two first portions 6, side surfaces 7b1, 7b2, 7b3 and 7b4 of each of the two second portions 7, and side surfaces 28b1, 28b2, 28b3 and 28b4 of the third portion 28.

[0307] The field effect transistor Q1 is provided in the first portion 6 between one of the two second portions 7 and the third portion 28. The field effect transistor Q2 is provided in the first portion 6 between the other of the two second portions 7 and the third portion 28. Then, each of the field effect transistors Q1 and Q2 is similar in configuration to the field effect transistor Q of the above-described first embodiment.

[0308] The semiconductor device 1C of the third embodiment includes, in a manner similar to the above-described first embodiment, a dielectric portion 17 having a lower relative permittivity of the insulating layer 11 surrounding the semiconductor 5 between one of the two second portions 7 of the semiconductor 5 and the leg portion 15b of the gate electrode 15 of the field effect transistor Q1. Furthermore, the semiconductor device 1C of the third embodiment includes, in a manner similar to the above-described first embodiment, a dielectric portion 17 having a relative permittivity smaller than that of the insulating layer 11 surrounding the semiconductor 5 between the other of the two second portions 7 of the semiconductor 5 and the leg portion 15b of the gate electrode 15 of the field effect transistor Q2. Then, the semiconductor device 1C of the third embodiment further includes a dielectric portion 17 having a relative permittivity smaller than that of the insulating layer 11 surrounding the semiconductor 5 between the third portion 28 of the semiconductor 5 and the leg portion 15b of the gate electrode 15 of the field effect transistor Q1 and between the third portion 28 of the semiconductor 5 and the leg portion 15b of the gate electrode 15 of the field effect transistor Q2.

[0309] like Fig.42 As shown, field effect transistors Q1 and Q2 share main electrode region 21b which is the other of the pair of main electrode regions 21a and 21b of field effect transistor Q1 and main electrode region 21a which is one of the pair of main electrode regions 21a and 21b of field effect transistor Q2.

[0310] The semiconductor device 1C according to the third embodiment can also produce effects similar to those produced by the semiconductor device 1A according to the above-described first embodiment.

[0311] <<Modification of the Third Embodiment>>

[0312] It should be noted that although the case where the two field effect transistors Q1 and Q2 are provided in the semiconductor 5 including the third portion 28 provided in the middle portion between the first portions 6 in the X direction has been described in the above third embodiment, Fig.44 As shown in FIG. 1 , the present technique is also applicable to two field effect transistors Q1 and Q2 arranged in a manner not including Fig.41 The situation in the semiconductor 5 of the third portion 28 is shown in .

[0313] [Fourth Embodiment]

[0314] Will see Figures 45 to 69 A method of manufacturing a semiconductor device according to a fourth embodiment of the present technology is described.

[0315] In the fourth embodiment, a description will be given focusing on the formation of the field effect transistor Q and the dielectric portion 17 included in the method for manufacturing the semiconductor device.

[0316] Furthermore, in the fourth embodiment, a case where the gate electrode 15 is formed by processing the conductive film 14 twice will be described.

[0317] First, if Fig.45 (Schematic plan view of main parts), Fig.46 (Along Fig.45 Schematic cross-sectional view taken along line a45-a45 in FIG. Fig.47 (Along Fig.45 A schematic cross-sectional view taken along line b45-b45 in FIG. Fig.48 (Along Fig.45 As shown in the schematic cross-sectional view taken along line c45-c45 in FIG. 1 , an island-shaped semiconductor 5 protruding above the base 4 is formed.

[0318] The semiconductor 5 is formed into a three-dimensional structure, which includes: a first portion 6 extending in the X direction (first direction); and a second portion 7, which is integrally provided with the first portion 6 in the X direction, and the width W2 of the second portion in the same direction as the width W1 of the first portion 6 along the Y direction (second direction) intersecting the X direction is greater than the width W1 of the first portion 6; and wherein the first portion 6 and the second portion 7 have an upper surface 5a and a side surface 5b. The side surface 5b includes side surfaces 6b1 and 6b2 of the first portion 6 and side surfaces 7b1, 7b2, 7b3 and 7b4 of the second portion 7. In the fourth embodiment, the semiconductor 5 is formed into a three-dimensional structure including one first portion 6 and two second portions 7 provided on both end sides of one first portion 6 in the X direction.

[0319] By selectively etching the semiconductor layer 2 to a depth where the base 4 remains, a semiconductor 5 including the first portion 6 and the second portion 7 can be formed. The semiconductor layer 2 can be, but is not limited to, a semiconductor substrate including, for example, silicon (Si) as a semiconductor material, for example, single crystal as crystallinity, and for example, p-type conductivity type as conductivity type.

[0320] Note that, in the semiconductor layer 2 , the p-type well region 3 which is a p-type semiconductor region is formed before the semiconductor 5 is formed.

[0321] Next, the insulating layer 11 surrounding the semiconductor 5 is formed by a method similar to that of the above-described first embodiment.

[0322] Then, after forming the insulating layer 11, the insulating layer 11 located outside the second portion 6 of the semiconductor 5 in the width direction (Y direction) is selectively removed to form recesses 12a and 12a, which expose the side surfaces 6b1 and 6b2 of the first portion 6 and the side surface 7b1 of the second portion 7 outside the first portion 6 of the semiconductor 5 in the width direction (Y direction), as shown in FIG. Fig.49 As shown in (schematic plan view of main parts), Fig.50 (Along Fig.49 A schematic cross-sectional view taken along line b49-b49 in FIG. Fig.51 (Along Fig.49 Schematic cross-sectional view taken along line c49-c49 in FIG. 1 ).

[0323] The recessed portion 12a as one of the two recessed portions 12a and 12a is formed on the side surface 6b1 of the first portion 6 to expose the side surface 6b1 of the first portion 6 and the side surface 7b1 (7b 11 ).

[0324] Furthermore, the recess 12a as the other of the two recesses 12a and 12a is formed on the side of the side surface 6b2 of the first portion 6 to expose the side surface 6b2 of the first portion 6 and the side surface 7b1 (7b2) of each of the two second portions 7. 12 ).

[0325] In this step, for example, unlike the above-described first embodiment, the recessed portions 12 a and 12 a are formed to a depth reaching the base portion 4 of the semiconductor layer 2 , but not limited to.

[0326] Next, gate insulating film 13 is formed on upper surface 5a and side surfaces 6b1 and 6b2 of first portion 6 of semiconductor 5. Gate insulating film 13 can be formed by forming a silicon oxide film on upper surface 5a and side surfaces 6b1 and 6b2 of first portion 6 by, for example, thermal oxidation method or deposition method.

[0327] In this step, the upper surface 5a and the side surface 7b1 (7b 11 and 7b 12 ) and on the front surface of the base 4 of the semiconductor layer 2, a gate insulating film 13 is further formed.

[0328] Next, after forming the gate insulating film 13, as shown in FIG. Fig.52 (Schematic plan view of main parts), Fig.53 (Along Fig.52 Schematic cross-sectional view taken along line a52-a52 in FIG. Fig.54 (Along Fig.52 Schematic cross-sectional view taken along line b52-b52 in FIG. Fig.55 (Along Fig.52As shown in the schematic cross-sectional view taken along the line c52-c52 in FIG. 1 , a conductive film 14 (gate electrode material) covering the semiconductor layer 2 and the insulating layer 11 is formed to fill the inside of each of the two recesses 12a. As the conductive film 14, for example, a polysilicon (doped polysilicon) film doped with impurities for reducing the resistance value during or after film formation can be used. At the portion where the gate insulating film 13 is formed on the semiconductor 5, the gate insulating film 13 is interposed between the semiconductor 5 and the conductive film 14.

[0329] Next, the conductive film 14 is patterned using known photolithography and dry etching techniques, and the conductive film 14 is patterned as shown in FIG. Fig.56 (Schematic plan view of main parts), Fig.57 (Along Fig.56 As shown in the schematic cross-sectional view taken along the line a56-a56 in FIG. Fig.58 (Along Fig.56 A schematic cross-sectional view taken along line b56-b56 in FIG. Fig.59 (Along Fig.56 ), the gate electrode 15 includes a leg 7 embedded in each of two recesses 12a adjacent to the first portion 6, and forms a head 15 that is integral with the leg 15b, overlaps the first portion 6, and has a width W6 that is smaller than the width W7 of the leg 15b in the same direction as the width W7 of the leg 15b along the first direction (X direction).

[0330] In this step, the head 15a of the gate electrode 15 is disposed on the upper surface of the first portion 6 of the semiconductor 5, with the gate insulating film 13 interposed therebetween, and intersects with the first portion 6 in the Y direction. The leg 15b of the gate electrode 15 is formed in each of the two recesses 12a, and has one end connected to the head 15a. Then, one of the two leg portions 15b is disposed on the outside of the side surface 6b1 of the first portion 6 of the semiconductor 5, with the gate insulating film 13 interposed therebetween. Then, the other of the two leg portions 15b is disposed on the outside of the side surface 6b2 of the first portion 6 of the semiconductor 5, with the gate insulating film 13 interposed therebetween.

[0331] Furthermore, in this step, when the conductive film 14 is patterned, the gate insulating film 13 on the upper surface 5 a of the semiconductor 5 located outside the head portion 15 a in the X direction is removed by side etching and over etching.

[0332] Note that in this embodiment, the conductive film 14 is subjected to, but not limited to, a process of making the leg portion 15 b located outside the head portion 15 a almost flush with the upper surface 5 a of the semiconductor 5 .

[0333] Next, if Fig.60 (Schematic plan view of main parts), Fig.61 (Along Fig.60 A schematic cross-sectional view taken along line a60-a60 in FIG. Fig.62 (Along Fig.60 As shown in the schematic cross-sectional view taken along the line b60-b60 in FIG. 1 , a pair of n-type extension regions 18 each including an n-type semiconductor region is formed in each semiconductor 5 located on both sides of the gate electrode 15 in the gate length direction (X direction). By using the head 15a of the gate electrode 15, the leg 5b located outside the head 15a, and the insulating layer 11 as masks for impurity introduction, arsenic ions (As ) are introduced. + ) or phosphorus ion (P + ) is implanted into the semiconductor 5 located on both sides of the gate electrode 15 in the gate length direction (X direction), and then the semiconductor 5 is subjected to a heat treatment for activating the impurities, thereby forming an extension region 18.

[0334] In this step, each of a pair of n-type extension regions 18 is formed in the first portion 6 and the second portion 7 of the semiconductor 5 in alignment with the head portion 15 a of the gate electrode 15 .

[0335] In addition, in this step, the leg 15b located outside the head 15a serves as a protective layer (impurity introduction suppression layer), and thus can suppress the phenomenon that impurity ions are injected into the semiconductor 5 and the base 4 through between the second part 7 of the semiconductor 5 and the leg 15b of the gate electrode 15.

[0336] Next, if Fig.63 (Schematic plan view of main parts), Fig.64 (Along Fig.63 A schematic cross-sectional view taken along line a63-a63 in FIG. 1 ), and Fig.65 (Along Fig.63 As shown in the schematic cross-sectional view taken along line a63-a63 in FIG, the leg portion 15b located outside the head portion 15a is selectively removed.

[0337] The leg portion 15b located outside the head portion 15a is removed using known photolithography and dry etching techniques.

[0338] Furthermore, removal of the leg portion 15b located outside the head portion 15a is performed by etching the head portion 15a and the leg portion 15b together in the height direction of the semiconductor 5 so that the side surfaces 15a1 and 15a2 on both sides of the head portion 15a in the X direction are recessed inward.

[0339] In addition, the etching is performed near the bottom of the recessed portion 12a. That is, the etching is performed to a depth that completely removes the leg portion 15b located outside the head portion 15a, in other words, to a depth that does not leave the leg portion 15b located outside the leg portion 15b.

[0340] In this step, the side surface 7b1 (7b 11 and 7b 12 ) and the leg portion 15 b of the gate electrode 15 form a gap 16.

[0341] Furthermore, in this step, the two side surfaces 15a1 and 15a2 of the head 15a in the X direction (gate length direction) and the two side surfaces 15b1 and 15b2 of the leg 15b in the X direction (gate length direction) are formed to be flush with each other in a cross-sectional view. That is, one side surface 15a1 of the head 15a and one side surface 15b1 of the leg 15b form a plane extending continuously in the thickness direction (Z direction) of the semiconductor layer 2, and the other side surface 15a2 of the head 15a and the other side surface 15b2 of the leg 15b form a plane extending continuously in the thickness direction (Z direction) of the semiconductor layer 2. That is, the X-direction width W6 of the head 15a and the X-direction width W7 of the leg 15b have the same design value.

[0342] In addition, in this step, Fig.64A As shown, due to the inward concavity of the side surfaces 15a1 and 15a2 on both sides of the head 15a in the X direction, a stepped portion 5a1 is formed on the upper surface 5a of the first portion 6 of the semiconductor 5.

[0343] Next, if Fig.66 (Schematic plan view of main parts), Fig.67 (Along Fig.66 A schematic cross-sectional view taken along line b66-b66 in FIG. Fig.68 (Along Fig.66 As shown in the schematic cross-sectional view taken along the line b66-b66 in FIG. 1 , the side surface spacer 19 is formed on the side surface of the gate electrode 15 to cover the side surfaces 15a1 and 15a2 of the head 15a and the side surfaces 15b1 and 15b2 of the leg 15b. An insulating film is formed on the insulating layer 11 by a CVD method to fill the insulating film. Fig.65 The gap 16 shown in the figure is formed to cover the semiconductor 5 and the head 15a of the gate electrode 15, and then the insulating film is anisotropically dry-etched such as RIE to form the side surface spacer 19. As the insulating film, for example, a silicon oxide film can be used.

[0344] The side surface spacer 19 is formed on the side surface of the head portion 15a of the gate electrode 15 so as to surround the head portion 15a of the gate electrode 15, and the side surface spacer 19 is formed in a self-aligned manner with respect to the gate electrode 15. The side surface spacer 19 intersects with the first portion 6 located outside the gate electrode 15 in the gate length direction in the Y direction.

[0345] In this step, if Fig.67A As shown, the step portion 5a1 of the first portion 6 of the semiconductor 5 is covered with the side spacer 19. That is, the step portion 5a1 is arranged at a position overlapping with the side spacer 19 in a plan view.

[0346] Next, if Fig.69 (Schematic plan view of main parts), Fig.70 (Along Fig.69 A schematic cross-sectional view taken along line a69-a69 in FIG. Fig.71 (Along Fig.69 As shown in the schematic cross-sectional view taken along the line b69-b69 in FIG. 1 , a pair of n-type contact regions 20 each including an n-type semiconductor region is formed in each semiconductor 5 located on both end sides of the gate electrode 15 in the gate length direction (X direction). By using the insulating layer 11, the gate electrode 15 and the side surface spacer 19 as a mask for impurity introduction, arsenic ions (As + ) or phosphorus ion (P + ) is ion-implanted into the semiconductor 5 (second portion 7) in a plan view between the insulating layer 11 and the side surface spacer 19, and then the semiconductor 5 (second portion 7) is heat-treated to activate the impurities to form a pair of n-type contact regions 20. The pair of n-type contact regions 20 are formed across the second portion 7 and the first portion 6 in a self-aligned manner relative to the side surface spacer 19.

[0347] In this step, n type extension region 18 and n type contact region 20 are in contact with each other at first portion 6 .

[0348] Furthermore, in this step, a pair of main electrode regions 21 a and 21 b each including an n-type extension region 18 and an n-type contact region 20 are formed in the semiconductor 5 .

[0349] Through this step, the field effect transistor Q including: the channel forming portion 9 arranged in the first portion 5a of the semiconductor 5, the gate electrode 15 arranged across the upper surface 5a and the side surfaces 6b1 and 6b2 of the first portion 6 of the semiconductor 5, the gate insulating film 13 interposed therebetween, the side surface spacer 19 arranged on the side surface of the gate electrode 15 across the head portion 15a and the leg portion 15b, and the main electrode region pair 21a and 21b each arranged in the semiconductor 5 becomes almost completed, and the semiconductor 5 is located on both sides of the gate electrode 15 in the channel length direction (X direction).

[0350] Note that the n-type contact region 20 of each of the pair of main electrode regions 21 a and 21 b can be selectively formed in the second portion 6 (only the second portion 6 ) by controlling the width of the side surface spacer 19 in the planar direction.

[0351] <<Main Effects of the Fourth Embodiment>>

[0352] In the method of manufacturing a semiconductor device according to the fourth embodiment, in a plan view, impurities are selectively ion-implanted into the semiconductor 5 located outside the head portion 15a, and the leg portion 15b remains between the head portion 15a of the gate electrode 15 and the second portion 6 of the semiconductor 5 to form the extension region 18. Therefore, the leg portion 15b located outside the head portion 15a serves as a protective layer (impurity introduction suppression layer), and thus a phenomenon in which impurity ions are injected into the semiconductor 5 and the base 4 through between the second portion 7 of the semiconductor 5 and the leg portion 15b of the gate electrode 15 can be suppressed.

[0353] Furthermore, since the phenomenon that impurity ions are injected into the semiconductor 5 or the base 4 through the gap between the second portion 7 of the semiconductor 5 and the leg portion 15b of the gate electrode 15 can be suppressed, the white spot phenomenon caused by the injection of impurity ions can be suppressed. Therefore, a semiconductor device with further improved reliability can be manufactured.

[0354] In addition, in the method of manufacturing a semiconductor device according to the fourth embodiment, the head 15a and the leg 15b are etched together in the height direction of the semiconductor 5 (the thickness direction of the semiconductor layer 2) so that the side surfaces 15a1 and 15a2 of the head 15a are recessed inward in the gate length direction (X direction), and the leg 15b located outside the head 15a in a plan view is removed.

[0355] Therefore, both side surfaces 15a1 and 15a2 of the head 15a in the X direction (gate length direction) and both side surfaces 15b1 and 5b2 of the leg 15b in the X direction (gate length direction) can be formed flush with each other in a cross-sectional view.

[0356] In addition, the side surfaces 15a1 and 15a2 of the head 15a and the side surfaces 15b1 and 5b2 of the leg 15b can be flush with each other in a cross-sectional view, so that the parasitic capacitance Cgd between the gate electrode 15 and the drain region (for example, the main electrode region 21b) is not affected by process variations as in the prior art, in a manner similar to the above-mentioned manufacturing method of the first embodiment. Therefore, according to the method of manufacturing a semiconductor device of the fourth embodiment, it is also possible to suppress the degradation of the noise characteristics of the field effect transistor Q.

[0357] In addition, according to the method of manufacturing a semiconductor device of the fourth embodiment, the step portion 5a1 formed on the upper surface 5a of the first portion 6 of the semiconductor 5 due to the inward concavity of the side surfaces 15a1 and 15a2 on both sides of the head 15a in the X direction is covered by the side surface spacer 19.

[0358] In addition, the side surface spacer 19 may also be composed of an insulating film having a lower relative dielectric constant than the insulating layer 11, similarly to the dielectric portion 17 of the first embodiment described above. In this case, since the parasitic capacitance 25 added to the field effect transistor Q can be reduced, the degradation of the noise characteristics of the field effect transistor Q can be suppressed and the reliability of the semiconductor device can be improved in a manner similar to the first embodiment described above.

[0359] [Fifth Embodiment]

[0360] In this fifth embodiment, reference will be made to Figure 72 to Figure 75 An embodiment in which the present technology is applied to a solid-state imaging device called a back-illuminated complementary metal oxide semiconductor (CMOS) image sensor is described as a photodetector included in the semiconductor device.

[0361] <<Overall Configuration of Solid-State Imaging Device>>

[0362] First, the overall configuration of the solid-state imaging device 1D will be described.

[0363] like Fig.72 As shown, the solid-state imaging device 1D according to the fifth embodiment of the present technology mainly includes a semiconductor chip 102 having a rectangular two-dimensional planar shape in a plan view. That is, the solid-state imaging device 1D is mounted on the semiconductor chip 102, and the semiconductor chip 102 can be regarded as the solid-state imaging device 1D. Fig.123 As shown in the figure, the solid-state imaging device 1D (201) receives image light (incident light 206) from an object through an optical lens 202, converts the amount of incident light 206 formed as an image on an imaging surface into an electrical signal for each pixel, and outputs the electrical signal as a pixel signal (image signal).

[0364] like Fig.72 As shown in , the semiconductor chip 102 on which the solid-state imaging device 1D is mounted includes a rectangular pixel array unit 102A arranged in the center part and a peripheral part 102B arranged outside the pixel array unit 102A to surround the pixel array unit 102A in a two-dimensional plane including the X direction and the Y direction orthogonal to each other. In the manufacturing process, a semiconductor wafer including a semiconductor layer 2, 130 described later is cut into small pieces per chip formation area, thereby forming the semiconductor chip 102. Therefore, even in the wafer state before the semiconductor wafer is cut into small pieces, the configuration of the solid-state imaging device 102 to be described below is basically similar. That is, the present technology can be applied to both semiconductor chips and semiconductor wafers.

[0365] The pixel array unit 102A receives, for example, Fig.123The optical lens (optical system) 202 shown in FIG. Then, a plurality of pixels 103 are arranged in a matrix in a two-dimensional plane including an X direction and a Y direction in the pixel array unit 102A. In other words, the pixels 103 are repeatedly arranged in the X direction and the Y direction orthogonal to each other in the two-dimensional plane.

[0366] like Fig.72 As shown, a plurality of bonding pads 114 are arranged in the peripheral portion 102B. Each of the plurality of bonding pads 114 is arranged, for example, in a two-dimensional plane along each of the four sides of the semiconductor chip 102. Each of the plurality of bonding pads 114 serves as an input / output terminal for electrically connecting the semiconductor chip 102 to an external device.

[0367] <Logic Circuit>

[0368] The semiconductor chip 102 includes Fig.73 The logic circuit 113 shown in FIG. Fig.73 As shown in , the logic circuit 113 includes a vertical drive circuit 104, a column signal processing circuit 105, a horizontal drive circuit 106, an output circuit 107, a control circuit 108, etc. The logic circuit 113 includes, for example, a complementary MOS (CMOS) circuit including an n-channel conductive metal oxide semiconductor field effect transistor (MOSFET) and a p-channel conductive MOSFET as field effect transistors.

[0369] The vertical drive circuit 104 includes, for example, a shift register. The vertical drive circuit 104 sequentially selects a desired pixel drive line 110, supplies a pulse for driving the pixel 103 to the selected pixel drive line 110, and drives each pixel 103 on a row-by-row basis. That is, the vertical drive circuit 104 sequentially selectively scans each pixel 103 in the pixel array unit 102A in the vertical direction on a row-by-row basis, and supplies a pixel signal from each pixel 103 to the column signal processing circuit 105 through the vertical signal line 111 based on a signal charge generated according to the amount of light received by the photoelectric converter (photoelectric conversion element) of the pixel 103.

[0370] The column signal processing circuit 105 is arranged, for example, for each column of the pixels 103, and performs signal processing such as noise removal on the signals output from the pixels 103 of one row for each pixel column. For example, the column signal processing circuit 105 performs signal processing such as correlated double sampling (CDS) and analog-to-digital (AD) conversion for removing pixel-specific fixed pattern noise.

[0371] The horizontal drive circuit 106 includes, for example, a shift register. The horizontal drive circuit 106 sequentially outputs horizontal scanning pulses to the column signal processing circuits 105 to sequentially select each of the column signal processing circuits 105 and cause the column signal processing circuits 105 to output pixel signals obtained as a result of signal processing to the horizontal signal line 112.

[0372] The output circuit 107 performs signal processing on pixel signals sequentially supplied from the column signal processing circuit 105 through the horizontal signal line 112 and outputs the processed signals. As the signal processing, for example, buffering, black level adjustment, column variation correction, various types of digital signal processing, etc. can be used.

[0373] The control circuit 108 generates a clock signal or a control signal based on the vertical synchronization signal, the horizontal synchronization signal, and the main clock signal, and the vertical drive circuit 104, the column signal processing circuit 105, the horizontal drive circuit 106, etc. operate according to the clock signal or the control signal. The control circuit 108 then outputs the generated clock signal or the control signal to the vertical drive circuit 104, the column signal processing circuit 105, the horizontal drive circuit 106, etc.

[0374] <Circuit Configuration of Pixel>

[0375] like Fig.74 As shown, each of the plurality of pixels 103 includes a photoelectric conversion region 121 and a pixel circuit (reading circuit) 115. The photoelectric conversion region 121 includes a photoelectric converter 124, a transfer transistor TR, and a charge holding region (floating diffusion) FD. The pixel circuit 115 is electrically connected to the charge holding region FD of the photoelectric conversion region 121. For example, the third embodiment adopts a circuit configuration in which one pixel circuit 115 is used exclusively by one pixel 103, but the circuit configuration is not limited thereto, and a circuit configuration in which one pixel circuit 115 is shared by a plurality of pixels 103 may be adopted. For example, a circuit configuration may be adopted in which one pixel circuit 115 is shared by four pixels 103 (one pixel block) arranged in a two-by-two layout, that is, two pixels 103 are arranged in the X direction and two pixels 103 are arranged in the Y direction.

[0376] Fig.74 The photoelectric converter 124 shown in FIG. 1 is, for example, a pn junction photodiode (PD) and generates signal charge according to the amount of light received. The photoelectric converter 124 has a cathode side electrically connected to the source region of the transfer transistor TR and an anode side electrically connected to a reference potential line (eg, ground).

[0377] Fig.74The transfer transistor TR shown transfers the signal charge generated as a result of the photoelectric conversion in the photoelectric converter 124 to the charge holding region FD. The transfer transistor TR has a source region electrically connected to the cathode side of the photoelectric converter 124 and a drain region electrically connected to the charge holding region FD. Then, the transfer transistor TR has a gate electrode electrically connected to a transfer transistor driving line among the pixel driving lines 110 (see Fig.76 ).

[0378] Fig.74 The charge holding region FD shown temporarily holds (accumulates) the signal charge transferred from the photoelectric converter 124 via the transfer transistor TR.

[0379] The photoelectric conversion region 121 including the photoelectric converter 124, the transfer transistor TR, and the charge holding region FD is provided in the semiconductor layer 130 (see Fig.75 ) as a second semiconductor layer to be described later.

[0380] Fig.74 The pixel circuit 115 shown in reads the signal charge held in the charge holding region FD, converts the read signal charge into a pixel signal, and outputs the pixel signal. In other words, the pixel circuit 115 converts the signal charge generated as a result of the photoelectric conversion in the photoelectric conversion element PD into a pixel signal based on the signal charge and outputs the pixel signal. For example, the pixel circuit 115 includes, but is not limited to, an amplifier transistor AMP, a selection transistor SEL, a reset transistor RST, and a switch transistor FDG as pixel transistors. For example, such pixel transistors (AMP, SEL, RST, and FDG) and the above-mentioned transfer transistor TR all include MOSFETs as field effect transistors. Alternatively, these transistors may include MISFETs.

[0381] Among the pixel transistors included in the pixel circuit 115, the selection transistor SEL, the reset transistor RST, and the switching transistor FDG each function as a switching element, and the amplifier transistor AMP functions as an amplification element. That is, the pixel circuit 115 includes field effect transistors for different purposes.

[0382] It should be noted that the selection transistor SEL and the switching transistor FDG may be omitted as necessary.

[0383] like Fig.74 As shown in , the amplifier transistor AMP has a source region electrically connected to the drain region of the selection transistor SEL and a drain region electrically connected to the power supply line Vdd and the drain region of the reset transistor RST. Then, the amplifier transistor AMP has a gate electrode electrically connected to the charge holding region FD and the source region of the switching transistor FDG.

[0384] The selection transistor SEL has a source electrode electrically connected to a corresponding one of the vertical signal lines 111 (VSL) and a drain region electrically connected to the source region of the amplifier transistor AMP. Then, the selection transistor SEL has a gate electrode electrically connected to a selection transistor driving line among the pixel driving lines 110 (see Fig.73 ).

[0385] The source region of the reset transistor RST is electrically connected to the drain region of the switching transistor FDG, and the drain region of the reset transistor RST is electrically connected to the power supply line Vdd and the drain region of the amplifier transistor AMP. Then, the reset transistor RST has a gate electrode electrically connected to the reset transistor driving line among the pixel driving lines 110 (see Fig.73 ).

[0386] The switching transistor FDG has a source region electrically connected to the charge holding region FD and the gate electrode of the amplifying transistor AMP and a drain region electrically connected to the power supply line Vdd and the drain region of the amplifying transistor AMP. Then, the gate electrode of the switching transistor FDG is electrically connected to a switching transistor driving line in the pixel driving line 110 (see Fig.73 ).

[0387] Note that when the selection transistor SEL is omitted, the source region of the amplifier transistor AMP is electrically connected to a corresponding one of the vertical signal lines (VSL) 111. Furthermore, when the switching transistor FDG is omitted, the source region of the reset transistor RST is electrically connected to the gate electrode of the amplifier transistor AMP and the charge holding region FD.

[0388] When turned on, the transfer transistor TR transfers the signal charge generated by the photoelectric converter 124 to the charge holding region FD.

[0389] When turned on, the reset transistor RST resets the potential (signal charge) of the charge holding region FD to the potential of the power supply line Vdd. The selection transistor SEL controls the output timing of the pixel signal from the pixel circuit 115.

[0390] The amplifier transistor AMP generates a signal of a voltage corresponding to the level of the signal charge held in the charge holding region FD as a pixel signal. The amplifier transistor AMP constitutes a source follower amplifier and outputs a pixel signal of a voltage corresponding to the level of the signal charge generated by the photoelectric converter 124. When the selection transistor SEL is turned on, the amplifier transistor AMP amplifies the potential of the charge holding region FD and outputs a voltage corresponding to the potential to the column signal processing circuit 105 via a corresponding one of the vertical signal lines (VSL) 111.

[0391] The switching transistor FDG controls charge retention by the charge retention region FD, and adjusts a voltage multiplication factor according to the potential amplified by the amplification transistor AMP.

[0392] When the solid-state imaging device 1D according to the fifth embodiment operates, the signal charge generated by the photoelectric converter 124 of the pixel 103 is held (accumulated) in the charge holding region FD via the transfer transistor TR of the pixel 103. Then, the signal charge held in the charge holding region FD is read by the pixel circuit 115 and applied to the gate electrode of the amplifier transistor AMP of the pixel circuit 115. The vertical shift register supplies the horizontal line selection control signal to the gate electrode of the selection transistor SEL of the pixel circuit 115. Then, the selection control signal is set to a high (H) level to turn on the selection transistor SEL to allow a current corresponding to the potential of the charge holding region FD amplified by the amplifier transistor AMP to flow to the vertical signal line 111. In addition, the reset control signal applied to the gate electrode of the reset transistor RST of the pixel circuit 115 is set to a high (H) level to turn on the reset transistor RST to reset the signal charge accumulated in the charge holding region FD.

[0393] <<Longitudinal Cross-Sectional Structure of Solid-State Imaging Device>>

[0394] Next, we will refer to Fig.75 A longitudinal cross-sectional structure of the semiconductor chip 102 (solid-state imaging device 1C) is described. Fig.75 yes Fig.72 A schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure of the pixel array unit in FIG. Fig.72 It is inverted to make the figure easier to see.

[0395] <Semiconductor Chip>

[0396] like Fig.75 As shown, the semiconductor chip 102 includes: a semiconductor layer 130 having a first surface S1 and a second surface S2 located on opposite sides in the thickness direction (Z direction); an insulating layer 131 arranged on the first surface S1 side of the semiconductor layer 130; and a semiconductor layer 2 arranged on the side of the insulating layer 131 away from the semiconductor layer 130.

[0397] On the second surface S2 side of the semiconductor layer 130 , the semiconductor chip 102 further includes a planarization layer 141 , a color filter layer 142 , a lens layer 143 , and the like, which are sequentially stacked from the second surface S2 side.

[0398] For example, the semiconductor layer 130 includes single crystal silicon.

[0399] The planarization layer 141 includes, for example, a silicon oxide film. Then, the planarization layer 141 covers the entire second surface S2 (light incident surface) side of the semiconductor layer 130 in the pixel array unit 102A to make the second surface S2 side of the semiconductor layer 130 flat without unevenness.

[0400] In the color filter layer 142 , a color filter such as red (R), green (G), or blue (B) is provided for each pixel 103 , and incident light incident from the light incident surface side of the semiconductor chip 102 is color-separated.

[0401] In the lens layer 143 , a microlens that condenses the irradiated light and allows the condensed light to efficiently enter the photoelectric conversion region 121 is provided for each pixel 103 .

[0402] like Fig.75 As shown, the semiconductor layer 2 according to the fifth embodiment is configured similarly to the semiconductor layer 2 according to the above embodiment. Figure 2 and Figure 3 The semiconductor layer 2 of the first embodiment shown is similar, and the field effect transistor Q is provided in the semiconductor 5 of the semiconductor layer 2. Next, on the base 4 of the semiconductor layer 2, an insulating layer 11 is provided in a manner surrounding the semiconductor 5. The configuration of the field effect transistor Q of the fifth embodiment is similar to that of the field effect transistor Q according to the above-described first embodiment.

[0403] The semiconductor layer 130 is arranged to overlap with the semiconductor 5 of the semiconductor layer 2. That is, the semiconductor chip 102 has a two-layer structure in which the semiconductor layer 130 and the semiconductor layer 2 are stacked in their respective thickness directions (Z directions).

[0404] In the fifth embodiment, although not shown in detail, Fig.74 The photoelectric converter 124, the transfer transistor TR and the charge holding region FD shown are respectively arranged Fig.75 In the semiconductor layer 130 shown.

[0405] on the other hand, Fig.74 The pixel transistors (AMP, SEL, RST and FDG) included in the pixel circuit 115 are all set Fig.75 Then, the pixel transistors (AMP, SEL, RST and FDG) included in the pixel circuit 115 each include Fig.75 The field effect transistor Q shown in FIG. Fig.75 An amplifier transistor AMP including a field effect transistor Q is shown as an example.

[0406] <<Main Effects of the Fifth Embodiment>>

[0407] In the solid-state imaging device 1D according to the fifth embodiment, the pixel transistors (AMP, SEL, RST, and FDG) included in the pixel circuit 115 each include a field effect transistor Q. Therefore, the solid-state imaging device 1D according to the fifth embodiment can also produce effects similar to those produced by the semiconductor device 1A according to the above-described first embodiment.

[0408] Here, it is important to suppress the degradation of the resistance to noise such as 1 / f noise or RTS noise compared to the pixel transistors (SEL, RST, and FDG) used as switching elements in the amplifier transistor AMP. Therefore, the present technology is particularly useful when applied to the amplifier transistor AMP included in the pixel circuit (in other words, the amplifier transistor AMP includes the field effect transistor Q).

[0409] In addition, since the pixel transistors (AMP, SEL, RST and FDG) included in the pixel circuit 115 are arranged in the semiconductor layer 2 different from the semiconductor layer 130 in which the photoelectric converter 124 is arranged, the transfer transistor TR and the charge holding region FD, the freedom of arrangement of the pixel transistors (AMP, SEL, RST and FDG) included in the pixel circuit 115 can be increased, and compared with the case where the photoelectric converter 124, the transfer transistor TR, the charge holding region FD, and the pixel transistors are arranged in the same semiconductor layer, high integration and improvement in noise resistance can be achieved.

[0410] <<Modification of the Fifth Embodiment>>

[0411] It should be noted that at least one of the pixel transistors (AMP, SEL, RST, and FDG) included in the pixel circuit 115 may include a field effect transistor Q.

[0412] In addition, if Figure 41 to Figure 43 As shown, two pixel transistors among the pixel transistors (AMP, SEL, RST, and FDG) included in the pixel circuit 115 may include two field effect transistors Q provided in one semiconductor 5. In this case, in order to improve the arrangement efficiency of the pixel transistors, preferably, the amplification transistor AMP and the selection transistor SEL include two field effect transistors Q provided in one semiconductor 5, and the reset transistor RST and the switch transistor FDG include two field effect transistors Q provided in one semiconductor 5.

[0413] Furthermore, at least one of the pixel transistors (AMP, SEL, RST, and FDG) included in the pixel circuit 115 may include a field effect transistor Q6 provided in a semiconductor 35 of a sixth embodiment described later.

[0414] [Sixth Embodiment]

[0415] In the sixth embodiment, if Fig.77 As shown, a semiconductor device 1E including a semiconductor 35 in which a thickness He2 of a second region 38B is greater than a height He1 of a first region 38A and a field effect transistor Q6 provided in the semiconductor 35 will be described.

[0416] <<Overall Configuration of Semiconductor Device>>

[0417] First, refer to Figure 76 to Figure 79 The overall configuration of the semiconductor device 1E is described.

[0418] Note that for ease of description, Figure 77 to Figure 77 The insulating layer 55 shown in FIG. Fig.76 In addition, Figure 77 to Figure 77 9, neither the contact electrodes provided in the insulating layer 55 nor the wiring and the insulating layer located above the insulating layer 55 are shown.

[0419] like Figure 76 to Figure 79 As shown, the semiconductor device 1E according to the sixth embodiment of the present technology includes an island-shaped semiconductor 35 provided in a semiconductor layer 32 and a field effect transistor Q6 provided in the semiconductor 35. In addition, the semiconductor device 1E according to the sixth embodiment includes an insulating layer 41 provided outside the semiconductor 35 so as to surround the semiconductor 35.

[0420] <Semiconductor Layer>

[0421] like Figure 76 to Figure 79 As shown, the semiconductor layer 32 includes a base portion 34 extending two-dimensionally in the X and Y directions, and an island-shaped semiconductor 35 protruding above the base portion 34 (in the Z direction).

[0422] <Semiconductors>

[0423] like Figure 76 to Figure 79 As shown in the figure, the semiconductor 35 has a three-dimensional structure, which includes a first part 36 and a second part 37 extending in the X direction (first direction), the second part is integrally arranged with the first part 36 in the X direction (adjacent to the first part 36) and the width W2 of the second part in the same direction as the width W1 of the first part 36 along the Y direction intersecting the X direction is greater than the width W1 of the first part 36, and wherein the first part 36 and the second part 37 have an upper surface 35a and a side surface 5b.

[0424] For example, the semiconductor 35 of the sixth embodiment has a three-dimensional structure including, but not limited to, one first portion 36 extending in the X direction and two second portions 37 each provided on either end side of the one first portion 36 in the X direction. The one first portion 36 and the two second portions 37 each have a rectangular planar shape in a plan view. In the X direction, one end of the first portion 36 is connected to one of the two second portions 37, and the other end of the first portion 36 is connected to the other of the two second portions 37.

[0425] In addition, if Figure 76 to Figure 79 As shown in , the semiconductor 35 further includes a first region 38A and a second region pair 38B, which is integrally provided beside the first region 38A (adjacent to the first region 38A) on both sides of the first region 38A in the X direction (first direction) and has a height (thickness) He2 in the Z direction, which is greater than the height (thickness) He1 of the first region 38A in the Z direction. The first region 38A is provided in the first portion 36. One of the second region pair 38B is provided on one of the two second portions 37 and the first portion 36. Then, the other of the second region pair 38B is provided on the other of the two second portions 37 and the first portion 36.

[0426] like Fig.77 and Fig.78 As described above, the first region 38A includes the semiconductor layer 32. Then, unlike the first region 38A, the second region 38B includes the semiconductor layer 32 and an n-type growth layer 48 selectively formed on the upper surface of the semiconductor layer 32 by epitaxial growth. The growth layer 48 is formed in alignment with the insulating film 47 provided on the side surface of the gate electrode 45 described later.

[0427] Here, epitaxial growth can form an n-type, p-type, or i-type single crystal layer by inheriting the crystallinity of the semiconductor layer 32 as the bottom layer. However, the single crystal layer formed by epitaxial growth is covalently bonded to the semiconductor layer 32, so that the bottom layer and the growth layer cannot be distinguished from each other under normal conditions when they are of the same type and have the same conductivity type or i-type. In the sixth embodiment, for ease of description, the semiconductor layer 32 and the growth layer 48 will be described separately, but are not limited to this. In the case where the conductivity type between the bottom layer and the growth layer is different, the depletion layer can make the bottom layer and the growth layer distinguishable.

[0428] Note that in the first region 38A, the surface layer of the semiconductor layer 32 becomes the upper surface 35a, and in the second region 38B, the surface layer of the growth layer 48 becomes the upper surface 35a. Therefore, in the semiconductor 35 of the sixth embodiment, a step is formed on the upper surface 35a between the first region 38A and the second region 38B.

[0429] like Figure 76 to Figure 79 As shown in the figure, the semiconductor 35 includes an upper surface 35a and a side surface 35b, wherein the upper surface 35a is located on a side of the semiconductor 35 away from the base 34 and extends two-dimensionally through the first part 36 and the two second parts 37, and the side surface 35b extends two-dimensionally through the first part 36 and the two second parts 37 in the thickness direction (Z direction) of the semiconductor 35.

[0430] like Figure 76 to Figure 79 As shown, the side surface 35b includes side surfaces 36b1 and 36b2 located at opposite sides in the Y direction of the first portion 36, side surfaces 37b1 and 37b2 located at opposite sides in the X direction of each second portion 37, and side surfaces 37b3 and 37b4 located at opposite sides in the Y direction of each second portion 37. The side surface 37b1 of the second portion 37 is divided into two parts by a connecting portion connecting the first portion 36 and the second portion 37.

[0431] That is, the side surface 5 b of the semiconductor 35 includes the side surfaces 36 b 1 and 36 b 2 of the first portion 36 and the side surfaces 37 b 1 , 37 b 2 , 37 b 3 , and 37 b 4 of each of the two second portions 37 .

[0432] The semiconductor 35 including the first portion 36 and the second portion 37 can be formed by selectively etching the semiconductor layer 32 to a depth that the base 34 remains. On the other hand, by selectively forming a growth layer 48 on the semiconductor layer 32 of the second region 38B through epitaxial growth, a height difference can be generated between the first region 38A and the second region 38B of the semiconductor 35. The semiconductor layer 32 can be, but is not limited to, a semiconductor substrate including, for example, silicon (Si) as a semiconductor material, for example, single crystal as crystallinity, and, for example, p-type conductivity type as conductivity type. The growth layer 48 includes, for example, a single crystal silicon layer doped with n-type impurities.

[0433] Here, the height He1 of the first region 38A is defined as the protrusion from the base 34 to the upper surface 35a of the first region 38A. In addition, the height He2 of the first region 38B is defined as the protrusion from the base 34 to the upper surface 35a of the second region 38A.

[0434] like Figure 77 to Figure 79 As shown, the semiconductor layer 32 is provided with a P-type well region 33, which is, for example, a P-type semiconductor region. The P-type well region 33 is provided in the entire semiconductor 35 and in the entire surface layer of the base 34 adjacent to the semiconductor 35. Then, the p-type well region 33 is separated from the rear surface of the base 34 away from the semiconductor 35.

[0435] <Insulation layer>

[0436] like Figure 77 to Figure 79 As shown, an insulating layer 41 is provided.

[0437] On the semiconductor 35 side of the semiconductor layer 32 so as to surround the semiconductor 35. The insulating layer 41 has a surface layer away from the base 34 of the planarized semiconductor layer 32, and has a plurality of concave portions 42 and 42 (see FIG. 1 ) to be described later. Fig.84 , Fig.86 and Fig.87 ) and has a film thickness substantially equal to the height He1 of the first region 38A of the semiconductor 35. The insulating layer 41 includes, for example, a silicon oxide (SiO 2 ) film.

[0438] like Figure 77 to Figure 79 As shown, on the side of the insulating layer 41 away from the base 34, an insulating layer 55 is provided to cover the head 45a of the gate electrode 45 of the field effect transistor Q6 to be described later and the semiconductor 35. The insulating layer 55 also includes, for example, a silicon oxide (SiO2) film.

[0439] <Field Effect Transistor>

[0440] Fig.76 The field effect transistor Q6 shown in is, but not limited to, an n-channel conductive type. Then, the field effect transistor Q6 includes a MOSFET, and the MOSFET includes silicon oxide (SiO2) as a gate insulating film. On the contrary, the field effect transistor Q6 can be a p-channel conductive type. In addition, the field effect transistor Q6 includes a MISFET, and the MISFET includes a silicon nitride film or a multilayer film (composite film) including a silicon nitride (Si3N4) film and a silicon oxide film as a gate insulating film.

[0441] like Figure 76 to Figure 79 As shown, the field effect transistor Q6 is disposed in the semiconductor 35 of the semiconductor layer 32 .

[0442] The field effect transistor Q6 includes a channel forming portion 39 provided in the first portion 36 of the semiconductor 35 and a gate electrode 45 provided between the upper surface 5 a and the side surfaces 36 b 1 and 36 b 2 of the first region 38A of the semiconductor 35 via a gate insulating film 43 .

[0443] In addition, the field effect transistor Q6 includes an insulating film (isolation insulating film) 47 and a side surface spacer 50 arranged on the side surface of the gate electrode 45 to surround the gate electrode 45, and a main electrode region pair 54a and 54b arranged in the second region pair 38B of the semiconductor 35 and serving as a source region and a drain region.

[0444] Here, for convenience of description, the main electrode region 54a as one of the pair of main electrode regions 54a and 54b may be referred to as a source region 54a, and the other main electrode region 54b may be referred to as a drain region 54b.

[0445] <Gate Electrode>

[0446] like Figure 77 to Figure 79 As shown in the figure, the gate electrode 45 includes: a head 45a, which is arranged on the upper surface 35a of the first part 36 (first region 38A) of the semiconductor 35, with the gate insulating film 43 interposed therebetween; and two leg parts 45b, which are integral with the head 45a and are arranged on the outside of each of the two side surfaces 36b1 and 36b2 located on opposite sides of the first part 36 (first region 38A) of the semiconductor 35, with the gate insulating film 43 interposed therebetween.

[0447] Here, the gate electrode 45 is preferably configured so that the first portion 36 of the semiconductor 35 is sandwiched between the legs 45b in the lateral direction (Y direction). Therefore, when the number of the first portions 36 is represented by "n", the number of the legs 45b of the gate electrode 45 is generally "n+1". In the sixth embodiment, since one first portion 36 is provided, the gate electrode 45 includes two legs 45b.

[0448] The head 45a of the gate electrode 45 protrudes above the insulating layer 41. Then, each of the two leg portions 45b of the gate electrode 45 is provided in the insulating layer 41 together with the semiconductor 35. The gate electrode 45 including the head 45a and the leg portion 45b includes, for example, a polysilicon (doped polysilicon) film doped with an impurity for reducing a resistance value.

[0449] The head 45a has a rectangular shape when viewed from above and has a three-dimensional structure including an upper surface and four side surfaces. Each of the two legs 45b has a three-dimensional structure extending from the head 45a in the thickness direction (Z direction) of the semiconductor layer 32 and in the height direction of the semiconductor 35 and including a lower surface and four side surfaces.

[0450] like Fig.78 As shown, the gate electrode 45 has two side surfaces 45a1 and 45a2 of the head 45a in the X direction (gate length direction) and two side surfaces 45b1 and 45b2 of the leg 45b in the X direction (gate length direction) in the cross-sectional view, which are flush with each other. That is, the side surface 45a1 of the head 45a and the side surface 45b1 of the leg 45b form a plane extending continuously in the thickness direction (Z direction) of the semiconductor layer 32, and the side surface 45a2 of the head 45a and the side surface 45b2 of the leg 45b form a plane extending continuously in the thickness direction (Z direction) of the semiconductor layer 32.

[0451] Here, the plan view refers to a situation where the semiconductor layer 32 is viewed from a direction along the thickness direction (Z direction) of the semiconductor layer 32. In addition, the cross-sectional view refers to a situation where a longitudinal section along the thickness direction (Z direction) of the semiconductor layer 32 is viewed from a direction (X direction or Y direction) orthogonal to the thickness direction (Z direction) of the semiconductor layer 32.

[0452] Note that Fig.76 and Fig.77 As shown, the first region 38A of the semiconductor 35 has a width W11 in the same direction as the gate length direction (X direction, first direction) of the gate electrode 45 that is larger than a width W12 of the gate electrode 45 in the gate length direction.

[0453] <Gate Insulating Film>

[0454] like Fig.79 As shown, the gate insulating film 43 is provided between the first portion 36 (first region 38A) of the semiconductor 35 and the gate electrode 45 across the upper surface 35a of the first portion 36 (first region 38A) and the two side surfaces 36b1 and 36b2 of the first portion 36 (first region 38A). In the sixth embodiment, since the semiconductor 35 includes one first portion 36, the gate insulating film 43 is provided across the upper surface 35a and the two side surfaces 36b1 and 36b2 of the one first portion 36. The gate insulating film 43 is composed of, for example, a silicon oxide film.

[0455] <Insulating Film and Side Surface Spacer>

[0456] like Figures 76 to 79 As shown, the insulating film 47 is provided on the side surface of the head 45a of the gate electrode 45 so as to surround the head 45a. The insulating film 47 is provided to electrically isolate the growth layer 48 of the second region 38B of the semiconductor 35 from the gate electrode 45. Therefore, the insulating film 47 can be referred to as an isolation insulating film 47.

[0457] The insulating film 47 is arranged to be aligned with the head 45a of the gate electrode 45. In other words, the insulating film 47 is formed in a self-aligned manner with respect to the head 45a of the gate electrode 45. For example, a thin silicon oxide film may be formed on the side of the insulating layer 41 away from the base 34 by a chemical vapor deposition (CVD) method to cover the gate electrode 45, and then the silicon oxide film may be subjected to anisotropic dry etching such as reactive ion etching (RIE) to selectively remove the silicon oxide film on the head 45a of the gate electrode 45 and the silicon oxide film outside the head 45a of the gate electrode 45 to form the insulating film 47. The insulating film 47 is preferably formed with a film thickness of, for example, about 2 nm to 10 nm.

[0458] Note that Fig.78As shown, the insulating film 47 is also provided on the side surface 37 b 1 of the second portion 37 of the semiconductor 35 .

[0459] like Figure 76 to Figure 79 As shown, the side surface spacer 50 is provided on the side surface of the head 45a of the gate electrode 45 so as to surround the head 45a of the gate electrode 45, and the insulating film 47 is interposed between the side surface spacer 50 and the head 45a. That is, the insulating film 47 is formed with a film thickness along the upper surface and the side surface of the gate electrode 45.

[0460] The side surface spacer 50 is arranged to be aligned with the gate electrode 45 and the insulating film 47. In other words, the side surface spacer 50 is formed in a self-aligned manner with respect to the gate electrode 45 and the insulating film 47. For example, the side surface spacer 50 can be formed by forming an insulating film by a CVD method to cover the gate electrode 45 and the insulating film 47 on the side of the insulating layer 41 away from the base 34, and then performing anisotropic trunk etching such as RIE on the insulating film. The side surface spacer 50 includes, for example, a silicon nitride film.

[0461] like Fig.76 As shown in FIG. 1 , the side spacer 50 is provided on the semiconductor 35 and the insulating layer 41 so as to intersect the semiconductor 35. Furthermore, the portion of the side spacer 50 located on the semiconductor 35 is adjacent to the head 45a of the gate electrode 45, and the portion located between the side surface 37b1 of the second portion 37 of the semiconductor 35 and the gate electrode 45 in a plan view is adjacent to the head 45a and the leg 45b of the gate electrode 45. That is, in the side spacer 50 of the sixth embodiment, the portion located between the side surface 37b1 of the second portion 37 of the semiconductor 35 and the gate electrode 45 in a plan view is adjacent to the head 45a and the leg 45b of the gate electrode 45. Fig.77 The portion on the semiconductor 35 shown and the portion between the side surface 37b1 of the second portion 37 of the semiconductor 35 and the gate electrode 45 (see FIG. Fig.78 ) along the height direction (Z direction) of the semiconductor 35 is different, Fig.78 The portion shown is Fig.77 Portion shown is length.

[0462] like Fig.77 As shown, in the second region 38B of the first portion 36 of the semiconductor 35, the side surface spacer 50 is formed on the growth layer 48 located outside the insulating film 47, aligned with the insulating film 47 located on the side surface of the gate electrode 45. That is, in the second region 38B of the first portion 36 of the semiconductor 35, the side surface spacer 50 is formed outside the side surface of the gate electrode 45, aligned with the insulating film 47, and overlaps with the growth layer 48 in a plan view.

[0463] <Main Electrode Area>

[0464] like Fig.77As shown, each of the main electrode region pair 54a and 54b includes an n-type semiconductor region 53 that is aligned with the side surface spacer 50 and formed across the growth layer 48 and the semiconductor layer 32. The n-type semiconductor region 53 is separated from the insulating film 47 located on the side surface of the gate electrode 45. Then, the n-type semiconductor region 53 is in contact with the n-type growth layer 48a that remains between the n-type semiconductor region 53 and the insulating film 47 in the second region 38B of the first portion 36 of the semiconductor 35 as a part of the n-type growth layer 48, and has an impurity concentration higher than that of the n-type growth layer 48a. The n-type growth layer 48a overlaps with the side surface spacer 50 in a plan view.

[0465] The n-type growth layer 48 a and the n-type semiconductor region 53 are in contact with the p-type well region 33 to form a pn junction.

[0466] The n-type semiconductor region 53 has thickness in the thickness direction (Z direction) of the semiconductor layer 32 and in the height direction of the semiconductor 35. Then, the n-type semiconductor region 53 is formed deeper than the n-type growth layer 48a (in other words, thicker than the n-type growth layer 48a).

[0467] As described above, in second region 38B of semiconductor 35, n-type semiconductor region 53 is formed across growth layer 48 and semiconductor layer 32. That is, each of main electrode region pair 54a and 54b has a structure protruding above first region 38A, in other words, protruding upward.

[0468] like Fig.77 and Fig.79 As shown in , the field effect transistor Q6 of the sixth embodiment is configured as a so-called fin type in which a gate electrode 45 is provided in an island-shaped semiconductor 35 as a fin portion with a gate insulating film 43 interposed therebetween.

[0469] In this fin field effect transistor Q6, the length between the main electrode region pair 54a and 54b is the channel length L (≈gate length Lg), and the value obtained by multiplying the width W1 of the first portion 36 on the upper surface 35a side included in the lateral direction (Y direction) and the length of the height of the two side surfaces 6b1 and 6b2 of the first portion 36 in the area where the gate electrode 45 of the semiconductor 35 and the first portion 36 overlap each other three-dimensionally (the length of the outline of the semiconductor 35) by the number of first portions 36 is the channel width W (≈gate width).

[0470] Therefore, the fin field effect transistor Q6 can increase the channel width W by increasing the width W1 of the first portion 36 of the semiconductor 35 and the height of the first portion 36 in the Z direction, thereby allowing an increase in the effective channel area (channel length L×channel width W). Then, the fin field effect transistor Q6 can increase the channel area (channel length L×channel width W) by increasing the number of first portions 36. Although the case where the field effect transistor Q6 is provided in one semiconductor 35 has been described in the sixth embodiment, the field effect transistor Q6 may be provided in a plurality of semiconductors 35 arranged in parallel.

[0471] In addition, the effective channel area of ​​the FinFET Q6 can be increased without increasing the occupied area (footprint) of the FinFET Q6 .

[0472] For example, the field effect transistor Q6 is an enhancement type (normally off type) in which a drain current flows when a gate voltage higher than or equal to a threshold voltage is applied to the gate electrode 45, or a suppression type (normally off type) in which a drain current flows even when no voltage is applied to the gate electrode 45. For example, the first embodiment adopts but is not limited to the enhancement type. In the case of the enhancement type, in the field effect transistor Q6, a channel (inversion layer) electrically connecting the main electrode region pair 54a and 54b is formed (induced) in the channel forming portion 39 by the voltage applied to the gate electrode 45, and a current (drain current) flows from the drain region side (for example, the main electrode region 54b side) to the source region side (for example, the main electrode region 54a side) through the channel of the channel forming portion 39.

[0473] <Contact Electrode and Wiring>

[0474] Although in Figure 76 to Figure 79 Although not shown in the figure, the gate electrode 4 is electrically connected to the wiring provided in the wiring layer located on the insulating layer 55 via the contact electrode provided in the insulating layer 55 in a manner similar to the above-mentioned first embodiment. In addition, the main electrode region 54a as one of the main electrode region pairs 54a and 54b is electrically connected to the wiring provided in the wiring layer located on the insulating layer 55 via the contact electrode provided in the insulating layer 55. Then, on the other hand, the main electrode region 54b as the other of the main electrode region pairs 54a and 54b is electrically connected to the wiring provided in the wiring layer located on the insulating layer 55 via the contact electrode provided in the insulating layer 55. As a material for the contact electrode, for example, tungsten (W) which is a high melting point metal can be used. In addition, as a material for the wiring, for example, a metal material such as aluminum (Al) or copper (Cu), an alloy material mainly containing Al or Cu, or the like can be used.

[0475] <<Method of Manufacturing Semiconductor Device>>

[0476] Next, we will refer to Figures 80 to 118 A method of manufacturing the semiconductor device 1E according to the sixth embodiment is described.

[0477] Furthermore, in the sixth embodiment, a description will be given focusing on the formation of the semiconductor 35 and the charge effect transistor Q6 included in the method for manufacturing the semiconductor device 1E.

[0478] First, if Fig.80 (Schematic plan view of main parts), Fig.81 (Along Fig.80 Schematic cross-sectional view taken along line a80-a80 in FIG. Fig.82 (Along Fig.80 A schematic cross-sectional view taken along line b80-b480 in FIG. Fig.82 (Along Fig.80 As shown in the schematic cross-sectional view taken along line c80-c80 in FIG. 1 , an island-shaped semiconductor 35 protruding above the base 34 is formed.

[0479] The semiconductor 35 is formed into a three-dimensional structure, which includes: a first portion 36 extending in the X direction (first direction); and a second portion 37, which is integrally arranged with the first portion 36 in the X direction, and the width W2 of the second portion 37 in the same direction as the width W1 of the first portion 36 along the Y direction (second direction) intersecting the X direction is greater than the width W1 of the first portion 36; and wherein the first portion 36 and the second portion 37 have an upper surface 35a and a side surface 35b. The side surface 35b includes side surfaces 36b1 and 36b2 of the first portion 36 and side surfaces 37b1, 37b2, 37b3 and 37b4 of the second portion 37. In the sixth embodiment, the semiconductor 35 is formed into a three-dimensional structure including one first portion 36 and two second portions 37, each of which is arranged on either end side of one first portion 36 in the X direction.

[0480] In addition, the semiconductor 35 further includes a first region 38A and a second region pair 38B and 38B, in which a gate electrode 45 described later is formed (see Fig.96 ), the second region pair 38B and 38B are provided continuously with the first region 38A on both sides of the first region 38A in the X direction and an n-type growth layer 48 described later is formed therein. The first region 38A is provided in the first portion 36. One of the second region pair 38B is provided on one of the two second portions 37 and the first portion 36. Then, the other of the second region pair 38B is provided on the other of the two second portions 37 and the first portion 36.

[0481] A semiconductor 35 including a first portion 36 and a second portion 37 and including a first region 38A and a second region 38B can be formed by selectively etching the semiconductor layer 32 to a depth at which the base 34 remains. The semiconductor layer 32 may be, but is not limited to, a semiconductor substrate including, for example, silicon (Si) as a semiconductor material, for example, single crystal as crystallinity, and for example, p-type conductivity as conductivity type.

[0482] In this step, due to the processing of the semiconductor layer 32, the side surfaces 35b (36b1, 36b2, and 37b1 to 37b4) of the semiconductor 35 are damaged.

[0483] Note that in the semiconductor layer 32 , the p-type well region 33 which is a p-type semiconductor region is formed before the semiconductor 35 is formed.

[0484] Next, by comparing with the first embodiment described above, Fig. 9 The insulating layer 41 surrounding the semiconductor 35 is formed by a method similar to the formation of the insulating layer 11 shown in FIG.

[0485] Then, after forming the insulating layer 41, the insulating layer 41 located outside the second portion 36 of the semiconductor 35 in the lateral direction (Y direction) is selectively removed to form two recessed portions 42a that expose the side surfaces 36b1 and 36b2 of the first portion 36 and the side surface 37b1 of the second portion 37 to the outside of the first portion 36 of the semiconductor 35 in the lateral direction (Y direction), as shown in FIG. Fig.84 (Schematic plan view of main parts), Fig.85 (Along Fig.84 Schematic cross-sectional view taken along line a84-a84 in FIG. Fig.86 (Along Fig.84 A schematic cross-sectional view taken along line b84-b84 in FIG. 1 ), and Fig.87 (Along Fig.84 Schematic cross-sectional view taken along line c84-c84 in FIG. 1 ).

[0486] One of the two recesses 42 , 42 is formed on the side surface 36 b 1 of the first portion 36 to expose the side surface 36 b 1 of the first portion 36 and the side surfaces 37 b 1 of the two second portions 37 adjacent to the side surface 36 b 1 .

[0487] The other of the two recesses 42 , 42 is formed on the side surface 36 b 2 of the first portion 36 to expose the side surface 36 b 2 of the first portion 36 and the side surfaces 37 b 1 of the two second portions 37 adjacent to the side surface 36 b 2 .

[0488] In this step, for example, unlike the above-described first embodiment, the recessed portions 42 and 42 are formed to a depth that reaches the base portion 34 of the semiconductor layer 32 , but is not limited thereto.

[0489] Next, if Fig.88 (Schematic plan view of main parts), Fig.89 (Along Fig.88 Schematic cross-sectional view taken along line a88-a88 in FIG. Fig.90 (Along Fig.88 A schematic cross-sectional view taken along line b88-b88 in FIG. Fig.91 (Along Fig.88 As shown in the schematic cross-sectional view taken along line c88-c88 in FIG, a gate insulating film 43 is formed on the upper surface 35a of the first portion 36 of the semiconductor 35 and both side surfaces 36b1 and 36b2 of the first portion 36. For example, the gate insulating film 43 can be formed by forming a silicon oxide film by a thermal oxidation method or a deposition method.

[0490] In this step, a gate insulating film 43 is further formed on the upper surface 35 a and the side surface 37 b 1 of the second portion 37 of the semiconductor 35 and on the front surface of the base 34 of the semiconductor layer 32 .

[0491] Next, after forming the gate insulating film 43, as shown in FIG. Fig.92 (Schematic plan view of main parts), Fig.93 (Along Fig.92 Schematic cross-sectional view taken along line a92-a92 in FIG. Fig.94 (Along Fig.92 A schematic cross-sectional view taken along line b92-b92 in FIG. Fig.95 (Along Fig.92 As shown in the schematic cross-sectional view taken along the line c92-c92 in FIG. 1 , a conductive film 44 (gate electrode material) covering the semiconductor 35 and the insulating layer 41 is formed to fill the inside of each of the two recesses 42 and 42. As the conductive film 44, for example, a polysilicon (doped polysilicon) film doped with impurities for reducing the resistance value during or after film formation can be used. A portion of the gate insulating film 43 is formed on the semiconductor 35, and the gate insulating film 43 is interposed between the semiconductor 35 and the conductive film 44.

[0492] Next, the conductive film 44 is patterned using known photolithography and dry etching techniques, and the conductive film 44 is patterned as shown in FIG. Fig.96 (Schematic plan view of main parts), Fig.97 (Along Fig.96 As shown in the schematic cross-sectional view taken along the line a96-a96 in FIG. Fig.98 (Along Fig.96 A schematic cross-sectional view taken along line b96-b96 in FIG. Fig.99 (Along Fig.96 A schematic cross-sectional view taken along line c96-c96 in the figure) forms a gate electrode 45 separated from each of the two second portions 37 of the semiconductor 35 and facing the upper surface 5a and side surfaces 36b1 and 36b2 of the first portion 36 (first region 38A) with the gate insulating film 43 interposed therebetween.

[0493] The gate electrode 45 includes: a head 45a, which is arranged on the upper surface 35a of the first part 36 of the semiconductor 35 through the gate insulating film 43; and a leg 45b, which is formed as a whole with the head 45 and is arranged on the outside of two side surfaces 36b1 and 36b2 on the opposite sides of the first part 36 of the semiconductor 35 through the gate insulating film 43.

[0494] The head portion 45 a intersects one of the recesses 42 , the first portion 36 , and the other recess 42 in sequence in the lateral direction (Y direction) of the first portion 36 of the semiconductor 35 .

[0495] Each of the two leg portions 45 b is formed in a corresponding one of the two recesses 42 , and has one end connected to the head portion 45 a .

[0496] In this step, if Fig.98 As shown, the gate electrode 45 is formed so that the two side surfaces 45a1 and 45a2 of the head 45a in the X direction (gate length direction) and the two side surfaces 45b1 and 45b2 of the leg 45b in the X direction (gate length direction) are flush with each other in the cross-sectional view. That is, one side surface 45a1 of the head 45a and one side surface 45b1 of the leg 45b form a plane extending continuously in the height direction (Z direction) of the semiconductor 35, and the other side surface 45a2 of the head 45a and the other side surface 45b2 of the leg 45b form a plane extending continuously in the height direction (Z direction) of the semiconductor 35.

[0497] In addition, in this step, Fig.96 and Fig.98 As shown, a gap (space) 46 is formed between the side surface 7b1 of the second portion 37 of the semiconductor 35 and the leg portion 45b of the gate electrode 45. Fig.98 , as an example, the gap 46 on the side of the side surface 36b1 of the first portion 36 is shown.

[0498] In the first embodiment, because the semiconductor 35 includes one first portion 36 and two second portions 37, the gap 46 includes two gaps formed on either side of the gate electrode 45 (sides adjacent to each of the two second portions 37) in the gate length direction in a plan view.

[0499] Furthermore, in this step, when the conductive film 44 is patterned, the gate insulating film 43 on the upper surface 35 a and the side surface 37 b 1 of the second portion 37 of the semiconductor 35 is removed by side etching and over etching.

[0500] In addition, in this step, Figures 96 to 98 As shown, the gate electrode 45 facing the upper surface 35 a and the side surface 35 b of the first region 38A of the semiconductor 35 with the gate insulating film 43 interposed therebetween is formed in the first region 38A.

[0501] Then, if Fig.100 (Schematic plan view of main parts), Fig.101 (Along Fig.100 Schematic cross-sectional view taken along line a100-a100 in FIG. Fig.102 (Along Fig.100 Schematic cross-sectional view taken along line b100-b100 in FIG. Fig.103 (Along Fig.100 As shown in the schematic cross-sectional view taken along the line c100-c100 in FIG. 1 , the insulating film 47 is formed across the semiconductor 35, the gate electrode 45, and the insulating layer 41 so as to cover the side surface of the gate electrode 45. For example, the insulating film 47 can be formed by forming a silicon oxide film by a CVD method. The insulating film 47 is provided to electrically insulate the gate electrode 45 from the growth layer 48 described later (see FIG. 1 ). Fig.109 and 110 ), preferably formed as a thin film with a film thickness of about 2 nm to 10 nm. That is, the insulating film 47 is formed with a film thickness along the upper surface and side surface of the gate electrode 45.

[0502] In this step, if Fig.102 As shown, the insulating film 47 is formed across the side surfaces 45a1 and 45a2 of the head 45a and the side surfaces 45b1 and 45b2 of the leg 45b of the gate electrode 45. In addition, the insulating film 47 is further formed on the side surface 37b1 of the second portion 37 of the semiconductor 35.

[0503] Next, the insulating film 47 located above the gate electrode 45 and outside the gate electrode 45 is selectively removed so that the insulating film 47 remains on the side surface of the gate electrode 45, and Fig.104 (Schematic plan view of main parts), Fig.105 (Along Fig.104 Schematic cross-sectional view taken along line a104-a104 in FIG. Fig.106 (Along Fig.104 As shown in the schematic cross-sectional view taken along the line b104-b104 in FIG. Fig.107 (Along Fig.1044 ), an insulating film 47 is formed on the side surface of the gate electrode 45 to cover the side surface of the gate electrode 45. The selective removal of the insulating film 47 can be performed by a known anisotropic dry etching such as RIE. In addition, the selective removal of the insulating film 47 can also be performed by patterning the insulating film 47 using an etching mask.

[0504] Next, in the semiconductor 35, a growth layer 48 is selectively formed by epitaxial growth on the upper surface 35a of each of the second region pair 38B and 38B located on both sides of the first region 38A in the X direction where the gate electrode 45 is formed, and Fig.108 (Schematic plan view of main parts), Fig.109 (Along Fig.108 A schematic cross-sectional view taken along line a108-a108 in FIG. Fig.110 (Along Fig.108 As shown in the schematic cross-sectional view taken along the line b108-b108 in FIG. 1 , the height (thickness) He2 of the second region pair 38B, 38B in the Z direction is greater (thicker) than the height (thickness) He1 of the first region 38A in the Z direction. The growth layer 48 is formed by inheriting the crystallinity of the semiconductor layer 32 as the base, so that the growth layer 48 is formed as, for example, a single crystal silicon layer doped with n-type impurities.

[0505] In this step, the growth layer 48 is formed in alignment with the gate electrode 45 and the insulating film 47. Then, the growth layer 48 is formed so as to be isolated from the gate electrode 45 by the insulating film 47.

[0506] Furthermore, in this step, since the side surface 37 b 1 of the second portion 37 of the semiconductor 35 is covered with the insulating film 47 , the growth layer 48 is generally not formed on the side surface 37 b 1 of the second portion 37 .

[0507] Furthermore, in this step, first region 38A of semiconductor 35 includes semiconductor layer 32, and the surface layer of semiconductor layer 32 becomes upper surface 35a. On the other hand, second region 38B of semiconductor 35 includes semiconductor layer 32 and growth layer 48, and the front surface of growth layer 48 becomes upper surface 35a.

[0508] Next, if Fig.111 (Schematic plan view of main parts), Fig.112 (Along Fig.111 Schematic cross-sectional view taken along line a111-a111 in FIG. Fig.113 (Along Fig.111 ), and Fig.114 (Along Fig.111As shown in the schematic cross-sectional view taken along the line c111-c111 in FIG. 1 , a side surface spacer 50 covering the side surfaces 45a1 and 45a2 of the head portion 45a and the side surfaces 45b1 and 45b2 of the leg portion 45b is formed on the side surface of the gate electrode 45. An insulating film is formed on the insulating layer 41 by a CVD method to fill the insulating film. Fig.110 The gap 46 shown covers the semiconductor 35 and the head 45a of the gate electrode 45, and then anisotropic dry etching such as RIE is performed to form a side surface spacer 50. As the insulating film, for example, a silicon oxide film can be used.

[0509] In this step, the side surface spacer 50 is formed on the side surface of the head portion 45a of the gate electrode 45 via the insulating film 47, and is formed in a self-aligned manner to surround the head portion 45a of the gate electrode 45. The side surface spacer 50 intersects with the first portion 36 located outside the gate electrode 45 in the gate length direction in the Y direction.

[0510] In addition, in this step, Fig.112 and 113 As shown, the side surface spacer 50 is formed to overlap with the growth layer 48 of the second region 38B of the semiconductor 35 in a plan view.

[0511] Next, using the gate electrode 45, the insulating film 47, and the side surface spacer 50 as a mask for impurity introduction, as shown in FIG. Fig.115 (Along Fig.111 A schematic longitudinal cross-sectional view taken along line a111-a111 in FIG. Fig.116 (Along Fig.111 As shown in the schematic longitudinal cross-sectional view taken along line b111-b111 in FIG. + ) is selectively implanted as an n-type impurity into the second region pair 38B of the semiconductor 35. As the n-type impurity, phosphorus ions (P + ).

[0512] Then, if Fig.117 (Along Fig.111 A schematic longitudinal cross-sectional view taken along line a111-a111 in FIG. Fig.118 (Along Fig.111 As shown in the schematic longitudinal cross-sectional view taken along the line b111-b111 in FIG. 1 , a process for activating the impurities (arsenic ions As) implanted into the second region 38B of the semiconductor 35 is performed. +) is performed to form a pair of n-type semiconductor regions 53 and 53 in the second region pair 38B and 38B of the semiconductor 35. Each of the pair of n-type semiconductor regions 53 is aligned with the side surface spacer 50 and is formed across the growth layer 48 and the semiconductor layer 32. Then, each of the pair of n-type semiconductor regions 53 is in contact with the n-type growth layer 48a remaining between the n-type semiconductor region 53 and the insulating film 47 in the second region 38B of the semiconductor 35 as a part of the n-type growth layer 48, and is formed to have a higher impurity concentration than the n-type growth layer 48a. The n-type growth layer 48a overlaps with the side surface spacer 50 in a plan view.

[0513] In this step, the pair of main electrode regions 54 a and 54 b each including the n-type semiconductor region 53 is formed in the second pair of regions 38B of the semiconductor 35 .

[0514] Furthermore, in this step, the channel forming portion 39 is formed in the semiconductor 35 between the pair of main electrode regions 54 a and 54 b .

[0515] Furthermore, in this step, a field effect transistor Q6 including the gate insulating film 43 , the gate electrode 45 , the pair of main electrode regions 54 a and 54 b , the channel forming portion 39 , and the like is formed in the semiconductor 35 .

[0516] Furthermore, in this step, each of the pair of main electrode regions 54 a and 54 b is formed into a structure that protrudes above the first region 38A (a structure that protrudes upward).

[0517] Next, an insulating layer 55 covering the semiconductor 35 and the field effect transistor Q6 is formed on the insulating layer 41, and the surface layer of the insulating layer 55 away from the semiconductor 35 is flattened, which results in Figure 76 to Figure 79 Status shown.

[0518] <<Main Effects of the Sixth Embodiment>>

[0519] The semiconductor device 1E according to the sixth embodiment includes a semiconductor 35 and a field effect transistor Q6 provided in the semiconductor 35. Then, the semiconductor 35 includes a first region 38A and a second region pair 38B and 38B provided to be adjacent to the first region 38A on both sides of the first region 38A in the X direction (first direction) and having a height He2 greater than a height He1 of the first region 38A. Then, the field effect transistor Q6 includes a gate electrode 45 (with a gate insulating film 43 interposed therebetween) provided on the upper surface 35a and side surfaces 35b1 and 35b2 of the first region 38A and a main electrode region pair 54a and 54b provided in the second region pair 38B and 38B.

[0520] Therefore, the semiconductor device 1E according to the sixth embodiment has a structure in which the main electrode region pair 54a and 54b protrudes above the first region 38A of the semiconductor 35, which increases the effective channel length compared to the conventional structure in which the first region 38A and the second region 38B of the semiconductor 35 are flat, so that the short channel effect can be suppressed. Therefore, the reliability of the semiconductor device 1E can be improved.

[0521] In addition, in the step of forming the gate electrode 45 of the method for manufacturing the semiconductor device 1E of the sixth embodiment, the gate electrode 45 including the head 45a and the leg 45b is formed by processing the conductive film 44 once, so that the two side surfaces 45a1 and 45a2 of the head 45a in the X direction (gate length direction) can be made flush with the two side surfaces 45b1 and 45b2 of the leg 45b in the X direction (gate length direction) in the cross-sectional view.

[0522] In addition, in the method of manufacturing the semiconductor device 1E of the sixth embodiment, by making the side surfaces 45a1 and 45a2 of the head 45a and the side surfaces 45b1 and 45b2 of the leg 45b the same plane in the cross-sectional view, the parasitic capacitance Cgd between the gate electrode 45 and the drain region (for example, the main electrode region 54b) is not affected by the conventional process variation, as in the first embodiment described above. Therefore, according to the method of manufacturing the semiconductor device 1E of the sixth embodiment, the degradation of the noise characteristics of the field effect transistor Q6 can be suppressed in a manner similar to the first embodiment described above.

[0523] Furthermore, in the method of manufacturing the semiconductor device 1E according to the sixth embodiment, since the main electrode region pair 54a and 54b are formed in the second region pair 48B and 48B having a height He2 greater than the height He1 of the first region 48A of the semiconductor 35, a structure in which the main electrode region pair 54a and 54b protrudes onto the first region 38A of the semiconductor 35 can be formed. Therefore, compared with a conventional structure in which the first region 38A and the second region 38B of the semiconductor 35 are flat, the effective channel length of the field effect transistor Q6 can be increased and the short channel effect can be suppressed. Therefore, according to the method of manufacturing the semiconductor device 1E of the sixth embodiment, the semiconductor device 1E can be manufactured with higher reliability.

[0524] In addition, in the sixth embodiment described above, the case where the growth layer 48 is selectively formed by epitaxial growth in a state where the side surface 37b1 of the second portion 37 (second region 38B) of the semiconductor 35 is covered by the insulating film 47 is described, but the side surface 37b1 of the second portion 37 (second region 38B) of the semiconductor 35 may not be covered by the insulating film. That is, when the semiconductor layer 32 is processed to form the semiconductor 35, the side surface 35b of the semiconductor 35 is etched damaged due to the processing of the semiconductor layer 32. In the case where the etching damage remains in the side surface 37b1 of the second portion 37 (second region 38B) of the semiconductor 35, the single crystal layer formed by epitaxial growth is not formed in the side surface 37b1 of the second portion 37 (second region 38B). Therefore, even if the side surface 37b1 of the second portion 37 (second region 38B) is not covered by the insulating film, the growth layer 48 can be selectively formed on the upper surface of the second region 38B of the semiconductor 35 by epitaxial growth.

[0525] Furthermore, unlike the polycrystalline growth layer 48 , even if a polycrystalline or amorphous growth layer is formed on the side surface 37 b 1 of the second portion 37 (second region 38B), these growth layers can be selectively removed.

[0526] [Seventh Embodiment]

[0527] The configuration of a semiconductor device 1F according to the seventh embodiment of the present technology is basically similar to the semiconductor device 1E according to the above-described sixth embodiment, and the configuration of the semiconductor is different.

[0528] That is, Fig.77 As shown, the semiconductor 35 of the sixth embodiment described above has a configuration in which one growth layer 48 is provided in the second region 38B.

[0529] On the other hand, Fig.119 As shown, the semiconductor 35 of the seventh embodiment has a configuration in which two growth layers 48 and 51 are provided in the second region 38B. In the manufacturing process of the semiconductor device 1F, after forming the side surface spacer 50, the growth layer 51 is selectively formed on the growth layer 48 by epitaxial growth, thereby obtaining the two growth layers 48, 51.

[0530] Specifically, Fig.120 As shown, steps similar to those in the above-described sixth embodiment are performed to form the spacers 50 up to the side surfaces.

[0531] Next, if Fig.121As shown, in the second region pair 38B and 38B of the semiconductor 35, a growth layer 51 is selectively formed by epitaxial growth on the upper surface of each growth layer 48. The growth layer 51 is formed by inheriting the crystallinity of the growth layer 48 as a base, so that the growth layer 51 can be formed as a single crystal silicon layer doped with n-type impurities, for example.

[0532] In this step, the growth layer 51 is formed in alignment with the side surface spacer 50. Then, the growth layer 51 is formed to be isolated from the gate electrode 45 by the side surface spacer 50 and the insulating film 47.

[0533] Furthermore, in this step, each of the second region pair 38B and 38B of the semiconductor 35 includes the semiconductor layer 32 and the growth layers 48 and 51, and the surface layer of the growth layer 51 becomes the upper surface 35a. Moreover, the height (thickness) He2 in the Z direction of the second region pair 38B, 38B can be made larger (thicker) than the height (thickness) He1 in the Z direction of the first region 38A.

[0534] Next, the gate electrode 45, the insulating film 47, and the side surface spacer 50 are used as a mask for the introduction of impurities, for example, arsenic ions (As + ) is selectively implanted as an n-type impurity into each of the second region pair 38B and 38B of the semiconductor 35. As the n-type impurity, phosphorus ions (P + ).

[0535] Next, a process for activating the impurities (arsenic ions As) in the second region pair 38B and 38B of the implanted semiconductor 35 is performed. + ) to form the pair of n-type semiconductor regions 53 and 53 in the second region pair 38B and 38B of the semiconductor 35, as shown in FIG. Fig.122 As shown. Each of a pair of n-type semiconductor regions 53 is aligned with the side surface spacer 50 and is formed across the growth layer 51, the growth layer 48, and the semiconductor layer 32. Then, each of the pair of n-type semiconductor regions 53 is in contact with the n-type growth layer 48a remaining between the n-type semiconductor region 53 and the insulating film 47 in the second region 38B of the semiconductor 35 as a part of the n-type growth layer 48, and is formed to have a higher impurity concentration than the n-type growth layer 48a. The n-type growth layer 48a overlaps with the side surface spacer 50 in a plan view.

[0536] In this step, the pair of main electrode regions 54 a and 54 b each including the n-type semiconductor region 53 is formed in the pair of second regions 38B and 38B of the semiconductor 35 .

[0537] Furthermore, in this step, the channel forming portion 39 is formed in the semiconductor 35 between the pair of main electrode regions 54 a and 54 b .

[0538] Furthermore, in this step, a field effect transistor Q6 including the gate insulating film 43 , the gate electrode 45 , the pair of main electrode regions 54 a and 54 b , the channel forming portion 39 , and the like is formed in the semiconductor 35 .

[0539] Furthermore, in this step, the pair of main electrode regions 54 a and 54 b are formed into a structure protruding above the first region 38A of the semiconductor 35 (a structure protruding upward).

[0540] Next, an insulating layer 55 covering the semiconductor 35 and the field effect transistor Q6 is formed on the insulating layer 41, and the surface layer of the insulating layer 55 away from the semiconductor 35 is flattened, which results in Fig.119 Status shown.

[0541] The semiconductor device 1F and the manufacturing method thereof according to the seventh embodiment can also produce effects similar to those produced by the semiconductor device 1E and the manufacturing method thereof according to the above-described sixth embodiment.

[0542] [Eighth Embodiment]

[0543] <<Embodiment applied to electronic equipment>>

[0544] For example, the present technology (technology of the present disclosure) can be applied to various electronic devices such as an imaging apparatus such as a digital still camera or a digital video camera, a mobile phone with an imaging function, or other devices with an imaging function.

[0545] Fig.123 : is a diagram illustrating a schematic configuration of an electronic device (for example, a camera) according to a sixth embodiment of the present technology.

[0546] like Fig.123 As shown, the electronic device 200 includes a solid-state imaging device 201, an optical lens 202, a shutter device 203, a drive circuit 204, and a signal processing circuit 205. The electronic device 200 is an embodiment in which the solid-state imaging device 1D according to the fifth embodiment of the present technology is used as the solid-state imaging device 201 in an electronic device (e.g., a camera).

[0547] The optical lens 202 forms an image of the image light (incident light 206) from the object on the imaging surface of the solid-state imaging device 201. Therefore, the signal charge is accumulated in the solid-state imaging device 201 within a specific time period. The shutter device 203 controls the light irradiation period and the light shielding period of the solid-state imaging device 201. The drive circuit 204 provides a drive signal for controlling the transmission operation of the solid-state imaging device 201 and the shutter operation of the shutter device 203. According to the drive signal (timing signal) provided from the drive circuit 204, the signal of the solid-state imaging device 201 is transmitted. The signal processing circuit 205 performs various types of signal processing on the signal (pixel signal (image signal)) output from the solid-state imaging device 201. The image signal after signal processing is stored in a storage medium such as a memory, or is output to a monitor.

[0548] With this configuration, since improvement in reliability is achieved in the solid-state imaging device 201 , improvement in reliability can also be achieved in the electronic device 200 of the eighth embodiment.

[0549] Note that the electronic device 200 to which the solid-state imaging device according to one of the above-described embodiments can be applied is not limited to a camera, and the solid-state imaging device can also be applied to other electronic devices. For example, the solid-state imaging device can be applied to an imaging device such as a camera module for a mobile device such as a mobile phone or a tablet terminal.

[0550] In addition, the present technology can be applied to any photodetector including not only the above-mentioned solid-state imaging device as an image sensor but also a distance measuring sensor, which is also called a time-of-flight (ToF) sensor and measures distance, etc. The distance measuring sensor is a sensor that emits irradiation light toward an object, detects reflected light as the irradiation light reflected from the surface of the object, and calculates the distance to the object based on the flight time from the emission of the irradiation light to the reception of the reflected light. As the structure of the element isolation region of the distance measuring sensor, the structure of the above-mentioned element isolation region can be adopted.

[0551] [Other embodiments]

[0552] In the above-described embodiment, description has been given of the case where the field effect transistor is provided in the rectangular parallelepiped semiconductor 5 extending in the X direction. However, the present technology is not limited to the rectangular parallelepiped semiconductor 5 .

[0553] For example, the present technology can also be applied to a field effect transistor in which a channel forming portion and a gate electrode are provided at a corner of a semiconductor having an L-shaped planar shape.

[0554] Furthermore, in the above-described first to fifth embodiments, the island-shaped semiconductor 5 integrated with the base 4 of the semiconductor layer 2 is described as a semiconductor. However, the present technology is not limited to the island-shaped semiconductor 5 integrated with the base 4 .

[0555] For example, the present technology can also be applied to a so-called silicon-on-insulator (SOI) structure in which a semiconductor is provided on an insulating layer. In this case, the semiconductor has a bottom surface in contact with the insulating layer on the side opposite to the upper surface.

[0556] Furthermore, the present technology can also be applied to semiconductor devices including fin field effect transistors and planar field effect transistors.

[0557] It should be noted that the present technology may also have the following configurations. (1)

[0559] A semiconductor device comprising:

[0560] An island-shaped semiconductor, comprising a first portion and a second portion, wherein the second portion is integrally arranged side by side with the first portion in a first direction, and the second portion has a width greater than the first portion in a direction that is the same as the width of the first portion along a second direction intersecting the first direction, and the first portion and the second portion both include an upper surface and a side surface;

[0561] an insulating layer surrounding each of the first portion and the second portion;

[0562] a field effect transistor including a gate electrode separated from the second portion and disposed across an upper surface and a side surface of the first portion; and

[0563] The dielectric portion is disposed between the gate electrode and the second portion and has a relative dielectric constant smaller than that of the insulating layer. (2)

[0565] The semiconductor device according to (1) above, wherein:

[0566] The dielectric portion includes a dielectric film having a relative dielectric constant smaller than that of the insulating layer. (3)

[0568] The semiconductor device according to (1) above, wherein:

[0569] The dielectric portion includes a cavity having a relative dielectric constant smaller than that of the insulating layer. (4)

[0571] The semiconductor device according to any one of (1) to (3) above, wherein:

[0572] The field effect transistor further includes a gate insulating film interposed between the first portion and the gate electrode, and

[0573] The relative dielectric constant of the dielectric portion is smaller than the relative dielectric constant of the gate insulating film. (5)

[0575] The semiconductor device according to any one of (1) to (4) above, wherein:

[0576] A width of the dielectric portion along the first direction is greater than a film thickness of the gate insulating film. (6)

[0578] The semiconductor device according to any one of (1) to (5) above, wherein:

[0579] The gate electrode includes a head portion protruding above the insulating layer and a leg portion formed integrally with the head portion and disposed in the insulating layer, and

[0580] A side surface of the head portion in the first direction and a side surface of the leg portion in the first direction are flush with each other in a cross-sectional view. (7)

[0582] The semiconductor device according to any one of (1) to (6) above, wherein:

[0583] The gate electrode includes a head portion protruding above the insulating layer and a leg portion formed integrally with the head portion and disposed in the insulating layer, and

[0584] In a plan view, the dielectric portion is surrounded on all sides by the first portion, the second portion, the leg portions, and the insulating layer. (8)

[0586] The semiconductor device according to any one of (1) to (7) above, wherein:

[0587] The field effect transistor further includes a pair of main electrode regions disposed in the semiconductor, the semiconductor being located on both sides of the gate electrode in the gate length direction. (9)

[0589] The semiconductor device according to (8) above, wherein:

[0590] The field effect transistor further includes a side surface spacer disposed on a side surface of the gate electrode, and

[0591] Each of the pair of main electrode regions includes an extension region disposed in the semiconductor and aligned with the gate electrode, and a contact region disposed in the semiconductor and aligned with the side surface spacer and having a higher impurity concentration than the extension region. (10)

[0593] The semiconductor device according to any one of (1) to (9) above, further comprising:

[0594] Opto-electrical converter; and

[0595] A pixel circuit converts a signal charge generated as a result of photoelectric conversion in the photoelectric converter into a pixel signal, wherein

[0596] At least one of a plurality of pixel transistors included in the pixel circuit includes a field effect transistor. (11)

[0598] The semiconductor device according to the above (10), further including: a semiconductor layer arranged to overlap with the semiconductor in a plan view and provided with a photoelectric converter. (12)

[0600] A method for manufacturing a semiconductor device, comprising:

[0601] forming an island-shaped semiconductor, the island-shaped semiconductor comprising a first portion and a second portion, the second portion being arranged side by side with the first portion in a first direction, and the second portion having a width greater than the first portion in a direction that is the same as the width of the first portion along a second direction intersecting the first direction, the first portion and the second portion both comprising an upper surface and a side surface;

[0602] forming an insulating layer surrounding each of the first portion and the second portion;

[0603] forming a gate electrode separated from the second portion and facing an upper surface and a side surface of the first portion; and

[0604] A dielectric portion is formed between the gate electrode and the second portion, the dielectric portion having a relative dielectric constant smaller than that of the insulating layer. (13)

[0606] The method of manufacturing a semiconductor device according to (12) above further includes: forming an extension region by implanting impurity ions into the semiconductor located outside the gate electrode using the gate electrode and the dielectric portion as masks. (14)

[0608] A method for manufacturing a semiconductor device, the method comprising:

[0609] forming an island-shaped semiconductor, the island-shaped semiconductor comprising a first portion and a second portion, the second portion being arranged side by side with the first portion in a first direction, and the second portion having a width greater than the first portion in a direction that is the same as the width of the first portion along a second direction intersecting the first direction, the first portion and the second portion both comprising an upper surface and a side surface;

[0610] forming an insulating layer surrounding each of the first portion and the second portion;

[0611] forming a recess by selectively removing the insulating layer outside the first portion in a second direction;

[0612] forming a conductive film covering the semiconductor in a manner embedded in the recess;

[0613] forming a gate electrode by patterning a conductive film, the gate electrode including a leg portion and a head portion, the leg portion being positioned adjacent to the first portion and embedded in the recess, the head portion being integrally formed with the leg portion, overlapping the first portion, and having a smaller width than the leg portion in a first direction along the same direction as a width of the leg portion;

[0614] forming an extension region by selectively ion-implanting an impurity into the semiconductor outside the head portion in a plan view, wherein the leg portion remains between the head portion and the second portion; and

[0615] Remove the legs that are outside the head. (15)

[0617] The method for manufacturing a semiconductor device according to (14) above, wherein:

[0618] Removal of the leg portion located outside the head portion is performed by etching the head portion and the leg portion collectively in the height direction of the semiconductor so that the side surface of the head portion is recessed inwardly. (16)

[0620] The method for manufacturing a semiconductor device according to (15) above, wherein:

[0621] Etching is performed to a depth near the bottom of the recessed portion. (17)

[0623] The method for manufacturing a semiconductor device according to any one of (14) to (16) above further includes: forming a side surface spacer on the side surface of the gate electrode after removing the leg portion located outside the head portion, the side surface spacer covering the corresponding side surfaces of the head portion and the leg portion. (18)

[0625] The method for manufacturing a semiconductor device according to (17) above, wherein:

[0626] The relative dielectric constant of the side surface spacer is smaller than that of the insulating film of the insulating layer. (19)

[0628] A semiconductor device comprising:

[0629] A semiconductor including an upper surface and a side surface; and

[0630] A field effect transistor is provided in a semiconductor, wherein

[0631] The semiconductor includes a first region and a second region pair, the second region pair being disposed continuously with the first region on both sides of the first region in a first direction and being higher than the first region, and

[0632] The field effect transistor includes: a gate electrode provided across the upper surface and the side surface of the first region, wherein a gate insulating film is interposed between the gate electrode and the first region; and a main electrode region pair provided in the second region pair. (20)

[0634] A semiconductor device according to (19) above, wherein:

[0635] The width of the first region in the same direction as a gate length direction of the gate electrode is greater than the width of the gate electrode in the gate length direction. (twenty one)

[0637] A semiconductor device according to (19) or (20) above, wherein:

[0638] The field effect transistor further includes an insulating film provided on a side surface of the gate electrode, and

[0639] Each of the pair of second regions is located outside the insulating film. (twenty two)

[0641] The semiconductor device according to any one of (19) to (21) above, wherein:

[0642] The first semiconductor region includes a semiconductor layer,

[0643] The second regions of the semiconductor each include a semiconductor layer and a growth layer formed on the semiconductor layer by epitaxial growth and aligned with the insulating film,

[0644] The field effect transistor further includes a side surface spacer formed on the growth layer located outside the insulating film and aligned with the insulating film; and

[0645] Each of the pair of main electrode regions includes a semiconductor region aligned with the side surface spacers and formed across the growth layer and the semiconductor layer of a corresponding one of the second regions. (twenty three)

[0647] The semiconductor device according to any one of (19) to (22) above, further comprising:

[0648] Opto-electrical converter; and

[0649] A pixel circuit converts a signal charge generated as a result of photoelectric conversion in the photoelectric converter into a pixel signal, wherein

[0650] At least one of a plurality of pixel transistors included in the pixel circuit includes a field effect transistor. (twenty four)

[0652] The semiconductor device according to the above (23), further including: a semiconductor layer arranged to overlap with the semiconductor in a plan view and provided with a photoelectric converter. (25)

[0654] A method for manufacturing a semiconductor device, the method comprising:

[0655] forming a semiconductor including a first region, a pair of second regions disposed continuously with the first region on both sides of the first region in a first direction, and an upper surface and a side surface disposed across the first region and the second region;

[0656] forming a gate electrode, the gate electrode facing the upper surface and the side surface of the first region, wherein the gate insulating film is interposed between the gate electrode and the first region in a second direction intersecting the first direction;

[0657] Each of the pair of second regions is made higher in height than the first region by epitaxial growth; and

[0658] A main electrode region pair is formed in the second region pair. (26)

[0660] An electronic device, comprising:

[0661] Semiconductor devices;

[0662] an optical lens that forms an image of image light from a subject on an imaging surface of the semiconductor device; and

[0663] A signal processing circuit performs signal processing on a signal output from the semiconductor layer, wherein

[0664] Semiconductor devices include:

[0665] An island-shaped semiconductor, comprising a first portion and a second portion, wherein the second portion is integrally arranged side by side with the first portion in a first direction, and the second portion has a width greater than the first portion in a direction that is the same as the width of the first portion along a second direction intersecting the first direction, and the first portion and the second portion both include an upper surface and a side surface;

[0666] an insulating layer surrounding each of the first portion and the second portion;

[0667] a field effect transistor including a gate electrode separated from the second portion and disposed across an upper surface and a side surface of the first portion; and

[0668] The dielectric portion is disposed between the gate electrode and the second portion and has a relative dielectric constant smaller than that of the insulating layer.

[0669] The scope of the present technology is not limited to the exemplary embodiments shown in the drawings and described above, but includes all embodiments that produce effects equivalent to the effects that the present technology is intended to produce. In addition, the scope of the present technology is not limited to the combination of the features of the present invention defined by the claims, and may be defined by any desired combination of specific features among all the features disclosed.

[0670] Reference Symbols List

[0671] 1A, 1B, 1C, 1E, 1F semiconductor devices

[0672] 1D solid-state imaging device

[0673] 2 Semiconductor layer

[0674] 3-well region

[0675] 4 Base

[0676] 5 Semiconductors

[0677] 5a Upper surface

[0678] 5a1 step section

[0679] 5b Side surface

[0680] 6 Part 1

[0681] 6b1, 6b2 side surface

[0682] 7 Part 2

[0683] 7b1, 7b2, 7b3, 7b4 side surfaces

[0684] 9 Channel formation part

[0685] 11 Insulation layer

[0686] 12a, 12b Recess (gate electrode recess)

[0687] 13Gate insulating film

[0688] 14Conductive film (gate electrode material)

[0689] 15. Gate electrode

[0690] 15a Head

[0691] 15a1, 15a2 side surface

[0692] 15b Legs

[0693] 15b1, 15b2 side surface

[0694] 16 Gap (opening)

[0695] 17, 17B Dielectric part

[0696] 17b1 Cavity

[0697] 17b2 insulation film

[0698] 18 Extended Area

[0699] 19 Side surface spacer

[0700] 20 Contact area

[0701] 21a, 21b Main electrode area

[0702] 22 Insulation layer

[0703] 22a, 22b, 22c contact electrodes

[0704] 23a, 23b, 23c wires

[0705] 25, 26 Parasitic capacitance

[0706] 28 Part 3

[0707] 32 Semiconductor layer

[0708] 33 p-type well region

[0709] 34 base

[0710] 35 Semiconductors

[0711] 35a Upper surface

[0712] 35b Side surface

[0713] 36 Part 1

[0714] 36b1, 6b2 side surface

[0715] 37 Part 2

[0716] 37b1, 37b2, 37b3, 37b4 side surfaces

[0717] 38A First Area

[0718] 38B Second Area

[0719] 39 Channel formation part

[0720] 41 Insulation layer

[0721] 42a, 42b concave portions (gate electrode concave portions)

[0722] 43Gate insulation film

[0723] 44 Conductive film (gate electrode material)

[0724] 45 Gate electrode

[0725] 45a Head

[0726] 45a1, 15a2 side surface

[0727] 45b Legs

[0728] 45b1, 15b2 side surface

[0729] 46 Gap (opening)

[0730] 47 Insulation film (isolation insulation film)

[0731] 48 Growth layer (epitaxial layer)

[0732] 50 side surface spacer

[0733] 51 Growth layer (epitaxial layer)

[0734] 53n-type semiconductor region

[0735] 54a, 54b main electrode area

[0736] 55 Insulation layer

[0737] 102 Semiconductor Chip

[0738] 102A pixel array unit

[0739] 102B Peripheral part

[0740] 103 pixels

[0741] 104 Vertical drive circuit

[0742] 105 columns signal processing circuit

[0743] 106 Horizontal drive circuit

[0744] 107 Output Circuit

[0745] 108 Control Circuit

[0746] 110 pixel drive lines

[0747] 111 vertical signal line

[0748] 113 Logic Circuits

[0749] 114 Bonding pad

[0750] 115 Reading Circuit

[0751] 130 semiconductor layer (second semiconductor layer)

[0752] 131 Wiring Layer

[0753] 141 planarization layer

[0754] 142 filter layer

[0755] 143 Lens Layer

[0756] 200 Electronic equipment

[0757] 201 Solid-state imaging device

[0758] 202 Optical lens

[0759] 203 Shutter device

[0760] 204 drive circuit

[0761] 205 Signal Processing Circuit

[0762] 206 Incident Light

[0763] AMP Amplifier Transistor

[0764] FDG Switching Transistor

[0765] RST Reset transistor

[0766] SEL select transistor

[0767] S1 First Surface

[0768] S2 Second Surface

[0769] TR Pass Transistor

[0770] Q, Q1, Q2 field effect transistors.

Claims

1. A semiconductor device comprising: An island-shaped semiconductor, comprising a first portion and a second portion, wherein the second portion is arranged side by side with the first portion in a first direction, and the second portion has a width greater than the first portion in a direction that is the same as the width of the first portion along a second direction intersecting the first direction, and the first portion and the second portion each include an upper surface and a side surface; an insulating layer surrounding each of the first portion and the second portion; a field effect transistor including a gate electrode separated from the second portion and disposed across the upper surface and the side surface of the first portion; as well as A dielectric portion is disposed between the gate electrode and the second portion and has a relative dielectric constant smaller than that of the insulating layer.

2. The semiconductor device according to claim 1, wherein The dielectric portion includes a dielectric film having a relative dielectric constant smaller than that of the insulating layer.

3. The semiconductor device according to claim 1, wherein The dielectric portion includes a cavity having a relative dielectric constant smaller than that of the insulating layer.

4. The semiconductor device according to claim 1, wherein The field effect transistor further includes a gate insulating film interposed between the first portion and the gate electrode, and A relative dielectric constant of the dielectric portion is smaller than a relative dielectric constant of the gate insulating film.

5. The semiconductor device according to claim 4, wherein: A width of the dielectric portion along the first direction is greater than a film thickness of the gate insulating film.

6. The semiconductor device according to claim 4, wherein: The gate electrode includes a head portion protruding above the insulating layer and a leg portion formed integrally with the head portion and disposed in the insulating layer, and A side surface of the head portion in the first direction and a side surface of the leg portion in the first direction are flush with each other in a cross-sectional view.

7. The semiconductor device according to claim 1, wherein The gate electrode includes a head portion protruding above the insulating layer and a leg portion formed integrally with the head portion and disposed in the insulating layer, and In a plan view, the dielectric portion is surrounded on all sides by the first portion, the second portion, the leg portions, and the insulating layer.

8. The semiconductor device according to claim 1, wherein The field effect transistor further includes a pair of main electrode regions disposed in the semiconductor, the semiconductor being located on both sides of the gate electrode in a gate length direction.

9. The semiconductor device according to claim 8, wherein: The field effect transistor further includes a side surface spacer disposed on a side surface of the gate electrode, and Each of the pair of main electrode regions includes an extension region provided in the semiconductor and aligned with the gate electrode, and a contact region provided in the semiconductor and aligned with the side surface spacer and having a higher impurity concentration than the extension region.

10. The semiconductor device according to claim 1, further comprising: Photoelectric converter; as well as a pixel circuit that converts a signal charge generated as a result of photoelectric conversion in the photoelectric converter into a pixel signal, wherein At least one of a plurality of pixel transistors included in the pixel circuit includes the field effect transistor.

11. The semiconductor device according to claim 10, further comprising: A semiconductor layer is arranged to overlap with the semiconductor in a plan view and is provided with the photoelectric converter.

12. A method for manufacturing a semiconductor device, the method comprising: forming an island-shaped semiconductor, the island-shaped semiconductor comprising a first portion and a second portion, the second portion being arranged side by side with the first portion in a first direction, and the second portion having a width greater than the first portion in a direction that is the same as the width of the first portion along a second direction intersecting the first direction, the first portion and the second portion each comprising an upper surface and a side surface; forming an insulating layer surrounding each of the first portion and the second portion; forming a gate electrode separated from the second portion and facing an upper surface and a side surface of the first portion; as well as A dielectric portion is formed between the gate electrode and the second portion, the dielectric portion having a relative dielectric constant smaller than that of the insulating layer.

13. The method for manufacturing a semiconductor device according to claim 12, further comprising: An extension region is formed by implanting impurity ions into the semiconductor located outside the gate electrode using the gate electrode and the dielectric portion as masks.

14. A method for manufacturing a semiconductor device, the method comprising: forming an island-shaped semiconductor, the island-shaped semiconductor comprising a first portion and a second portion, the second portion being arranged side by side with the first portion in a first direction, and the second portion having a width greater than the first portion in a direction that is the same as the width of the first portion along a second direction intersecting the first direction, the first portion and the second portion each comprising an upper surface and a side surface; forming an insulating layer surrounding each of the first portion and the second portion; forming a recess by selectively removing the insulating layer outside the first portion in the second direction; forming a conductive film covering the semiconductor in a manner embedded in the recess; forming a gate electrode by patterning the conductive film, the gate electrode including a leg portion and a head portion, the leg portion being positioned adjacent to the first portion and embedded in the recess, the head portion being integrally formed with the leg portion, overlapping the first portion, and having a smaller width than the leg portion in the first direction along the same direction as the width of the leg portion; forming an extension region by selectively ion-implanting an impurity into the semiconductor outside the head in a plan view, wherein the leg portion remains between the head and the second portion; as well as The legs located outside the head are removed.

15. The method for manufacturing a semiconductor device according to claim 14, wherein: The removal of the leg portion located outside the head portion is performed by etching the head portion and the leg portion collectively in the height direction of the semiconductor so that the side surface of the head portion is recessed inwardly.

16. The method for manufacturing a semiconductor device according to claim 15, wherein: Etching is performed to a depth near the bottom of the recessed portion.

17. The method for manufacturing a semiconductor device according to claim 14, further comprising: A side surface spacer is formed on a side surface of the gate electrode after removing the leg portion located outside the head portion, the side surface spacer covering corresponding side surfaces of the head portion and the leg portion.

18. The method for manufacturing a semiconductor device according to claim 17, wherein: The relative dielectric constant of the side surface spacer is smaller than that of the insulating film of the insulating layer.

19. A semiconductor device comprising: A semiconductor, including an upper surface and a side surface; as well as A field effect transistor is provided in the semiconductor, wherein The semiconductor includes a first region and a second region pair, the second region pair being disposed continuously with the first region on both sides of the first region in a first direction and having a height higher than the first region, and The field effect transistor includes: a gate electrode provided across the upper surface and the side surface of the first region, wherein a gate insulating film is interposed between the gate electrode and the first region; and a main electrode region pair provided in the second region pair.

20. The semiconductor device according to claim 19, wherein A width of the first region in a direction that is the same as a gate length direction of the gate electrode is greater than a width of the gate electrode in the gate length direction.

21. The semiconductor device according to claim 19, wherein The field effect transistor further includes an insulating film provided on a side surface of the gate electrode, and Each of the second pair of regions is located outside the insulating film.

22. The semiconductor device according to claim 21, wherein The first region of the semiconductor includes a semiconductor layer, The second regions of the semiconductor each include the semiconductor layer and a growth layer formed on the semiconductor layer by epitaxial growth and aligned with the insulating film, The field effect transistor further includes a side surface spacer formed on the growth layer outside the insulating film and aligned with the insulating film; and Each of the pair of main electrode regions includes a semiconductor region aligned with the side surface spacer and formed across the growth layer and the semiconductor layer of a corresponding one of the second regions.

23. A method for manufacturing a semiconductor device, the method comprising: forming a semiconductor including a first region, a pair of second regions disposed continuously with the first region on both sides of the first region in a first direction, and an upper surface and a side surface disposed across the first region and the second region; forming a gate electrode facing the upper surface and the side surface of the first region, wherein a gate insulating film is interposed between the gate electrode and the first region in a second direction intersecting the first direction; Each of the second region pair is made higher than the first region by epitaxial growth; and A main electrode region pair is formed in the second region pair.

24. An electronic device comprising: Semiconductor devices; an optical lens that forms an image of image light from a subject on an imaging surface of the semiconductor device; as well as A signal processing circuit performs signal processing on a signal output from the semiconductor layer, wherein: The semiconductor device comprises: An island-shaped semiconductor, comprising a first portion and a second portion, wherein the second portion is arranged side by side with the first portion in a first direction, and the second portion has a width greater than the first portion in a direction that is the same as the width of the first portion along a second direction intersecting the first direction, and the first portion and the second portion each include an upper surface and a side surface; an insulating layer surrounding each of the first portion and the second portion; a field effect transistor including a gate electrode separated from the second portion and disposed across the upper surface and the side surface of the first portion; and A dielectric portion is disposed between the gate electrode and the second portion and has a relative dielectric constant smaller than that of the insulating layer.

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