Array substrate and display device

Abstract

An array substrate includes a plurality of signal lines. Each signal line of the plurality of signal lines includes a plurality of first signal line portions, a plurality of second signal line portions, and a plurality of third signal line portions. The plurality of first signal line portions and the plurality of second signal line portions are in two different layers. The plurality of first signal line portions and the plurality of third signal line portions are in two different layers. Two separate first signal line portions, a separate second signal line portion, and a separate third signal line portion form a loop that substantially surrounds an area of a transistor and a capacitor of a pixel driving circuit having a sub-pixel. The two separate first signal line portions are connected by the separate second signal line portion and are connected by the separate third signal line portion.

Description

Technical Field

[0001] This invention relates to display technology, and more particularly to an array substrate and a display device. Background Technology

[0002] Organic light-emitting diode (OLED) displays are currently a hot topic in flat panel display research. Unlike thin-film transistor liquid crystal displays (TFT-LCDs), which use a stable voltage to control brightness, OLEDs are driven by a driving current that needs to be kept constant to control illuminance. An OLED display panel includes multiple pixel units configured with pixel driving circuits arranged in multiple rows and columns. Each pixel driving circuit includes a driving transistor having a gate terminal connected to a gate signal line in each row and a drain terminal connected to a data line in each column. When the row in which the pixel unit is selected is turned on, a switching transistor connected to the driving transistor is turned on, and a data voltage is applied from the data line through the switching transistor to the driving transistor, causing the driving transistor to output a current corresponding to the data voltage to the OLED device. This drives the OLED device to emit light of a corresponding brightness. Summary of the Invention

[0003] On one hand, this disclosure provides an array substrate including a plurality of signal lines; wherein each of the plurality of signal lines includes a plurality of first signal line portions, a plurality of second signal line portions, and a plurality of third signal line portions; the plurality of first signal line portions and the plurality of second signal line portions are located in two different layers; the plurality of first signal line portions and the plurality of third signal line portions are located in two different layers; each of the plurality of second signal line portions is respectively connected to two adjacent first signal line portions; each of the plurality of third signal line portions is respectively connected to two adjacent first signal line portions; two separate first signal line portions, a separate second signal line portion, and a separate third signal line portion form a loop, the loop substantially surrounding a region of a transistor and capacitor of a pixel driving circuit having sub-pixels; and the two separate first signal line portions are connected through the separate second signal line portions and through the separate third signal line portions.

[0004] Optionally, the array substrate includes a plurality of rings arranged in a row; wherein the plurality of rings substantially surround the region of the pixel driving circuit of the sub-pixel of the same color; and each of the plurality of rings substantially surrounds the region of the pixel driving circuit of the sub-pixel of the same color.

[0005] Optionally, the array substrate includes a plurality of rings arranged in a row; wherein the plurality of rings substantially surround the region of the anode of a sub-pixel having the same color; and each of the plurality of rings substantially surrounds the region of the anode of the sub-pixel having the same color.

[0006] Optionally, the sub-pixels are arranged in multiple rows and columns; in the m-th row of sub-pixels, the array substrate includes a row of first sub-pixels of a first color; in the (m+1)-th row of sub-pixels, the array substrate includes a row of third sub-pixels of a third color; in the (m+2)-th row of sub-pixels, the array substrate includes a row of second sub-pixels of a second color; in the n-th column of sub-pixels, the array substrate includes a column of third sub-pixels of the third color; in the (n-1)-th column of sub-pixels, the array substrate includes a column of alternating first sub-pixels of the first color and second sub-pixels of the second color; in the (n+1)-th column of sub-pixels, the... The array substrate includes a column of alternately arranged first sub-pixels of the first color and second sub-pixels of the second color; the first signal line portion of the plurality of first signal line portions is connected to one or more transistors in the pixel driving circuit of the third sub-pixel in the nth column of sub-pixels and the (m+1)th row of sub-pixels, connected to one or more transistors in the pixel driving circuit of the first sub-pixel in the (n-1)th column of sub-pixels and the mth row of sub-pixels, and connected to one or more transistors in the pixel driving circuit of the second sub-pixel in the (n+1)th column of sub-pixels and the (m+2)th row of sub-pixels.

[0007] Optionally, one of the plurality of second signal line portions connects the first signal line portion to a first adjacent first signal line portion, and the first adjacent first signal line portion is connected to one or more transistors in the pixel driving circuit of the second sub-pixel in the (n-1)th column sub-pixel and the (m+2)th row sub-pixel.

[0008] Optionally, a third signal line portion of the plurality of third signal line portions connects the first signal line portion to a second adjacent first signal line portion, and the second adjacent first signal line portion is connected to one or more transistors in the pixel driving circuit of the first sub-pixel in the (n+1)th column sub-pixel and the first sub-pixel in the mth row sub-pixel.

[0009] Optionally, the array substrate further includes a plurality of light-transmitting regions; wherein, in the nth column of sub-pixels, each of the plurality of light-transmitting regions separates two adjacent third sub-pixels.

[0010] Optionally, the plurality of signal lines includes a plurality of initialization signal lines; the plurality of first signal line portions includes a plurality of first initialization signal line portions; the plurality of second signal line portions includes a plurality of second initialization signal line portions; and the plurality of third signal line portions includes a plurality of third initialization signal line portions.

[0011] Optionally, the plurality of signal lines include a plurality of gate signal lines; the plurality of first signal line portions include a plurality of first gate signal line portions; the plurality of second signal line portions include a plurality of second gate signal line portions; and the plurality of third signal line portions include a plurality of third gate signal line portions.

[0012] Optionally, the plurality of signal lines include a plurality of reset control signal lines; the plurality of first signal line portions include a plurality of first reset control signal line portions; the plurality of second signal line portions include a plurality of second reset control signal line portions; and the plurality of third signal line portions include a plurality of third reset control signal line portions.

[0013] Optionally, the plurality of signal lines include a plurality of light emission control signal lines; the plurality of first signal line portions include a plurality of first light emission control signal line portions; the plurality of second signal line portions include a plurality of second light emission control signal line portions; and the plurality of third signal line portions include a plurality of third light emission control signal line portions.

[0014] Optionally, the array substrate further includes multiple light-transmitting areas; wherein the array substrate includes a first conductive layer, a second conductive layer, a first signal line layer, a third signal line layer, and an anode layer; and signal lines and electrodes of the first conductive layer, the second conductive layer, the first signal line layer, the third signal line layer, and the anode layer are not present in the multiple light-transmitting areas.

[0015] Optionally, the array substrate further includes a second signal line layer; wherein the signal lines located in the second signal line layer comprise a substantially transparent conductive material; and the signal lines of the second signal line layer are present in the plurality of light-transmitting regions.

[0016] Optionally, the plurality of second signal line portions and the plurality of third signal line portions are located in the second signal line layer; and the plurality of first signal line portions are located in the first conductive layer or the second conductive layer.

[0017] Optionally, the array substrate further includes a plurality of voltage supply lines and a plurality of voltage connection bridges located in two different layers; the plurality of voltage connection bridges are arranged in an array of multiple rows and columns; two adjacent voltage connection bridges in the same pixel row are connected to the same voltage supply line in the plurality of voltage supply lines; and voltage connection bridges in the same pixel column are connected to the same adjacent voltage supply lines in the plurality of voltage supply lines.

[0018] Optionally, the plurality of voltage supply lines include a first adjacent voltage supply line, a second adjacent voltage supply line, and a third adjacent voltage supply line; the first adjacent voltage supply line is configured to provide a voltage supply signal to a first pixel driving circuit in a corresponding first sub-pixel, the second adjacent voltage supply line is configured to provide a voltage supply signal to a second pixel driving circuit in a corresponding second sub-pixel, and the third adjacent voltage supply line is configured to provide a voltage supply signal to a third pixel driving circuit in a corresponding third sub-pixel; and each of the plurality of voltage connection bridges is respectively connected to the first adjacent voltage supply line, the second adjacent voltage supply line, and the third adjacent voltage supply line.

[0019] Optionally, each of the first adjacent voltage supply line, the second adjacent voltage supply line, and the third adjacent voltage supply line includes a plurality of alternating first voltage supply line portions and a plurality of second voltage supply line portions; each of the plurality of voltage connection bridges is respectively connected to the first adjacent voltage supply line portion and the second adjacent voltage supply line portion of the first adjacent voltage supply line, respectively connected to the first adjacent voltage supply line portion and the second adjacent voltage supply line portion of the second adjacent voltage supply line, and respectively connected to the first adjacent voltage supply line portion and the second adjacent voltage supply line portion of the third adjacent voltage supply line.

[0020] Optionally, the plurality of voltage supply lines includes a first adjacent voltage supply line and a second adjacent voltage supply line; each of the plurality of voltage supply lines is connected to a voltage connection bridge in two adjacent columns of the plurality of voltage connection bridges; and each of the plurality of voltage connection bridges is connected to the first adjacent voltage supply line and to the second adjacent voltage supply line.

[0021] Optionally, each of the plurality of voltage connection bridges includes a second capacitor electrode of a plurality of pixel driving circuits.

[0022] On the other hand, this disclosure provides a display device including the array substrate described herein, and one or more integrated circuits connected to the array substrate.

[0023] On the other hand, this disclosure provides an array substrate including a plurality of voltage supply lines and a plurality of voltage connection bridges located in two different layers; wherein the plurality of voltage connection bridges are arranged in an array of multiple rows and columns; two adjacent voltage connection bridges in the same pixel row are connected to the same voltage supply line in the plurality of voltage supply lines; and voltage connection bridges in the same pixel column are connected to the same adjacent voltage supply lines in the plurality of voltage supply lines.

[0024] Optionally, the plurality of voltage supply lines include a first adjacent voltage supply line, a second adjacent voltage supply line, and a third adjacent voltage supply line; the first adjacent voltage supply line is configured to provide a voltage supply signal to a first pixel driving circuit in a corresponding first sub-pixel, the second adjacent voltage supply line is configured to provide a voltage supply signal to a second pixel driving circuit in a corresponding second sub-pixel, and the third adjacent voltage supply line is configured to provide a voltage supply signal to a third pixel driving circuit in a corresponding third sub-pixel; and each of the plurality of voltage connection bridges is respectively connected to the first adjacent voltage supply line, the second adjacent voltage supply line, and the third adjacent voltage supply line.

[0025] Optionally, each of the first adjacent voltage supply line, the second adjacent voltage supply line, and the third adjacent voltage supply line includes a plurality of alternating first voltage supply line portions and a plurality of second voltage supply line portions; each of the plurality of voltage connection bridges is respectively connected to the first adjacent voltage supply line portion and the second adjacent voltage supply line portion of the first adjacent voltage supply line, respectively connected to the first adjacent voltage supply line portion and the second adjacent voltage supply line portion of the second adjacent voltage supply line, and respectively connected to the first adjacent voltage supply line portion and the second adjacent voltage supply line portion of the third adjacent voltage supply line.

[0026] Optionally, the plurality of voltage supply lines includes a first adjacent voltage supply line and a second adjacent voltage supply line; each of the plurality of voltage supply lines is connected to a voltage connection bridge in two adjacent columns of the plurality of voltage connection bridges; and each of the plurality of voltage connection bridges is connected to the first adjacent voltage supply line and to the second adjacent voltage supply line.

[0027] Optionally, each of the plurality of voltage connection bridges includes a second capacitor electrode of a plurality of pixel driving circuits.

[0028] Optionally, the array substrate further includes a plurality of signal lines; wherein each of the plurality of signal lines includes a plurality of first signal line portions, a plurality of second signal line portions, and a plurality of third signal line portions; the plurality of first signal line portions and the plurality of second signal line portions are located in two different layers; the plurality of first signal line portions and the plurality of third signal line portions are located in two different layers; each of the plurality of second signal line portions is respectively connected to two adjacent first signal line portions; each of the plurality of third signal line portions is respectively connected to two adjacent first signal line portions; two separate first signal line portions, a separate second signal line portion, and a separate third signal line portion form a loop, the loop substantially surrounding the region of the transistor and capacitor of the pixel driving circuit having sub-pixels; and the two separate first signal line portions are connected through the separate second signal line portions and through the separate third signal line portions.

[0029] Optionally, the array substrate includes a plurality of rings arranged in a row; wherein the plurality of rings substantially surround the region of the pixel driving circuit of the sub-pixel of the same color; and each of the plurality of rings substantially surrounds the region of the pixel driving circuit of the sub-pixel of the same color.

[0030] Optionally, the array substrate includes a plurality of rings arranged in a row; wherein the plurality of rings substantially surround the region of the anode of a sub-pixel having the same color; and each of the plurality of rings substantially surrounds the region of the anode of the sub-pixel having the same color.

[0031] Optionally, the sub-pixels are arranged in multiple rows and columns; in the m-th row of sub-pixels, the array substrate includes a row of first sub-pixels of a first color; in the (m+1)-th row of sub-pixels, the array substrate includes a row of third sub-pixels of a third color; in the (m+2)-th row of sub-pixels, the array substrate includes a row of second sub-pixels of a second color; in the n-th column of sub-pixels, the array substrate includes a column of third sub-pixels of the third color; in the (n-1)-th column of sub-pixels, the array substrate includes a column of alternating first sub-pixels of the first color and second sub-pixels of the second color; in the (n+1)-th column of sub-pixels, the... The array substrate includes a column of alternately arranged first sub-pixels of the first color and second sub-pixels of the second color; the first signal line portion of the plurality of first signal line portions is connected to one or more transistors in the pixel driving circuit of the third sub-pixel in the nth column of sub-pixels and the (m+1)th row of sub-pixels, connected to one or more transistors in the pixel driving circuit of the first sub-pixel in the (n-1)th column of sub-pixels and the mth row of sub-pixels, and connected to one or more transistors in the pixel driving circuit of the second sub-pixel in the (n+1)th column of sub-pixels and the (m+2)th row of sub-pixels.

[0032] Optionally, one of the plurality of second signal line portions connects the first signal line portion to a first adjacent first signal line portion, and the first adjacent first signal line portion is connected to one or more transistors in the pixel driving circuit of the second sub-pixel in the (n-1)th column sub-pixel and the (m+2)th row sub-pixel.

[0033] Optionally, a third signal line portion of the plurality of third signal line portions connects the first signal line portion to a second adjacent first signal line portion, and the second adjacent first signal line portion is connected to one or more transistors in the pixel driving circuit of the first sub-pixel in the (n+1)th column sub-pixel and the first sub-pixel in the mth row sub-pixel.

[0034] Optionally, the array substrate further includes a plurality of light-transmitting regions; wherein, in the nth column of sub-pixels, each of the plurality of light-transmitting regions separates two adjacent third sub-pixels.

[0035] Optionally, the plurality of signal lines includes a plurality of initialization signal lines; the plurality of first signal line portions includes a plurality of first initialization signal line portions; the plurality of second signal line portions includes a plurality of second initialization signal line portions; and the plurality of third signal line portions includes a plurality of third initialization signal line portions.

[0036] Optionally, the plurality of signal lines include a plurality of gate signal lines; the plurality of first signal line portions include a plurality of first gate signal line portions; the plurality of second signal line portions include a plurality of second gate signal line portions; and the plurality of third signal line portions include a plurality of third gate signal line portions.

[0037] Optionally, the plurality of signal lines include a plurality of reset control signal lines; the plurality of first signal line portions include a plurality of first reset control signal line portions; the plurality of second signal line portions include a plurality of second reset control signal line portions; and the plurality of third signal line portions include a plurality of third reset control signal line portions.

[0038] Optionally, the plurality of signal lines include a plurality of light emission control signal lines; the plurality of first signal line portions include a plurality of first light emission control signal line portions; the plurality of second signal line portions include a plurality of second light emission control signal line portions; and the plurality of third signal line portions include a plurality of third light emission control signal line portions.

[0039] Optionally, the array substrate further includes multiple light-transmitting regions; wherein the array substrate includes a first conductive layer, a second conductive layer, a first signal line layer, a third signal line layer, and an anode layer; and signal lines and electrodes of the first conductive layer, the second conductive layer, the first signal line layer, the third signal line layer, and the anode layer are not present in the multiple light-transmitting regions.

[0040] Optionally, the array substrate further includes a second signal line layer; wherein the signal lines located in the second signal line layer comprise a substantially transparent conductive material; and the signal lines of the second signal line layer are present in the plurality of light-transmitting regions.

[0041] Optionally, the plurality of second signal line portions and the plurality of third signal line portions are located in the second signal line layer; and the plurality of first signal line portions are located in the first conductive layer or the second conductive layer.

[0042] On the other hand, this disclosure provides a display device including the array substrate described herein, and one or more integrated circuits connected to the array substrate. Attached Figure Description

[0043] The following figures are merely illustrative examples based on various disclosed embodiments and are not intended to limit the scope of the invention.

[0044] Figure 1 This is a plan view of an array substrate according to some embodiments of the present disclosure.

[0045] Figure 2AThis is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0046] Figure 2B This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0047] Figure 2C This is a timing diagram illustrating the operation of a pixel driving circuit according to some embodiments of the present disclosure.

[0048] Figure 3A This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure.

[0049] Figure 3B It is shown Figure 3A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate.

[0050] Figure 3C It is shown Figure 3A A schematic diagram of the structure of the first conductive layer in a portion of the array substrate depicted in the figure.

[0051] Figure 3D It is shown Figure 3A A schematic diagram of the structure of the second conductive layer in a portion of the array substrate depicted in the figure.

[0052] Figure 3E It is shown Figure 3A A schematic diagram of the structure of the interlayer dielectric layer in a portion of the array substrate depicted in the figure.

[0053] Figure 3F It is shown Figure 3A A schematic diagram of the structure of the first signal line layer in a portion of the array substrate depicted in the figure.

[0054] Figure 3G It is shown Figure 3A A schematic diagram of the structure of the passivation layer in a portion of the array substrate depicted in the figure.

[0055] Figure 3H It is shown Figure 3A A schematic diagram of the structure of the second signal line layer in a portion of the array substrate depicted in the figure.

[0056] Figure 3I It is shown Figure 3A A schematic diagram of the structure of the first planarization layer in a portion of the array substrate depicted in the figure.

[0057] Figure 3J It is shown Figure 3A A schematic diagram of the structure of the third signal line layer in a portion of the array substrate depicted in the figure.

[0058] Figure 3K It is shown Figure 3A A schematic diagram of the structure of the second planarization layer in a portion of the array substrate depicted in the figure.

[0059] Figure 3L It is shown Figure 3A A schematic diagram of the structure of the anode layer in a portion of the array substrate depicted in the diagram.

[0060] Figure 3M It is shown Figure 3A A schematic diagram of the structure of the pixel-defining layer in a portion of the array substrate depicted in the figure.

[0061] Figure 4 It is along Figure 3A A cross-sectional view of line A-A' in the diagram.

[0062] Figure 5A This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure.

[0063] Figure 5B It is shown Figure 5A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate.

[0064] Figure 5C It is shown Figure 5A A schematic diagram of the structure of the first conductive layer in a portion of the array substrate depicted in the figure.

[0065] Figure 5D It is shown Figure 5A A schematic diagram of the structure of the second conductive layer in a portion of the array substrate depicted in the figure.

[0066] Figure 5E It is shown Figure 5A A schematic diagram of the structure of the interlayer dielectric layer in a portion of the array substrate depicted in the figure.

[0067] Figure 5F It is shown Figure 5A A schematic diagram of the structure of the first signal line layer in a portion of the array substrate depicted in the figure.

[0068] Figure 5G It is shown Figure 5A A schematic diagram of the structure of the passivation layer in a portion of the array substrate depicted in the figure.

[0069] Figure 5H It is shown Figure 5A A schematic diagram of the structure of the second signal line layer in a portion of the array substrate depicted in the figure.

[0070] Figure 5I It is shown Figure 5AA schematic diagram of the structure of the first planarization layer in a portion of the array substrate depicted in the figure.

[0071] Figure 5J It is shown Figure 5A A schematic diagram of the structure of the third signal line layer in a portion of the array substrate depicted in the figure.

[0072] Figure 5K It is shown Figure 5A A schematic diagram of the structure of the second planarization layer in a portion of the array substrate depicted in the figure.

[0073] Figure 5L It is shown Figure 5A A schematic diagram of the structure of the anode layer in a portion of the array substrate depicted in the diagram.

[0074] Figure 5M It is shown Figure 5A A schematic diagram of the structure of the pixel-defining layer in a portion of the array substrate depicted in the figure.

[0075] Figure 6 This is a schematic diagram illustrating a voltage supply network in a portion of an array substrate according to some embodiments of the present disclosure.

[0076] Figure 7 This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure.

[0077] Figure 8 This is a schematic diagram illustrating a reset signal network in a portion of an array substrate according to some embodiments of the present disclosure.

[0078] Figure 9 This is a schematic diagram illustrating a reset signal network in a portion of an array substrate according to some embodiments of the present disclosure.

[0079] Figure 10 This is a schematic diagram illustrating a gate scan signal network in a portion of an array substrate according to some embodiments of the present disclosure.

[0080] Figure 11 This is a schematic diagram illustrating a gate scan signal network in a portion of an array substrate according to some embodiments of the present disclosure.

[0081] Figure 12 This is a schematic diagram illustrating a reset control signal network in a portion of an array substrate according to some embodiments of the present disclosure.

[0082] Figure 13 This is a schematic diagram illustrating a reset control signal network in a portion of an array substrate according to some embodiments of the present disclosure.

[0083] Figure 14 This is a schematic diagram illustrating a light-emitting control signal network in a portion of an array substrate according to some embodiments of the present disclosure.

[0084] Figure 15 This is a schematic diagram illustrating a light-emitting control signal network in a portion of an array substrate according to some embodiments of the present disclosure.

[0085] Figure 16A This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure.

[0086] Figure 16B It is shown Figure 16A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate.

[0087] Figure 16C It is shown Figure 16A A schematic diagram of the structure of the first conductive layer in a portion of the array substrate depicted in the figure.

[0088] Figure 16D It is shown Figure 16A A schematic diagram of the structure of the second conductive layer in a portion of the array substrate depicted in the figure.

[0089] Figure 16E It is shown Figure 16A A schematic diagram of the structure of the interlayer dielectric layer in a portion of the array substrate depicted in the figure.

[0090] Figure 16F It is shown Figure 16A A schematic diagram of the structure of the first signal line layer in a portion of the array substrate depicted in the figure.

[0091] Figure 16G It is shown Figure 16A A schematic diagram of the structure of the passivation layer in a portion of the array substrate depicted in the figure.

[0092] Figure 16H It is shown Figure 16A A schematic diagram of the structure of the second signal line layer in a portion of the array substrate depicted in the figure.

[0093] Figure 16I It is shown Figure 16A A schematic diagram of the structure of the first planarization layer in a portion of the array substrate depicted in the figure.

[0094] Figure 16J It is shown Figure 16A A schematic diagram of the structure of the third signal line layer in a portion of the array substrate described herein.

[0095] Figure 16K It is shown Figure 16AA schematic diagram of the structure of the second planarization layer in a portion of the array substrate depicted in the figure.

[0096] Figure 16L It is shown Figure 16A A schematic diagram of the structure of the anode layer in a portion of the array substrate depicted in the diagram.

[0097] Figure 16M It is shown Figure 16A A schematic diagram of the structure of the pixel-defining layer in a portion of the array substrate depicted in the figure.

[0098] Figure 17A This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure.

[0099] Figure 17B It is shown Figure 17A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate.

[0100] Figure 17C It is shown Figure 17A A schematic diagram of the structure of the first conductive layer in a portion of the array substrate depicted in the figure.

[0101] Figure 17D It is shown Figure 17A A schematic diagram of the structure of the second conductive layer in a portion of the array substrate depicted in the figure.

[0102] Figure 17E It is shown Figure 17A A schematic diagram of the structure of the interlayer dielectric layer in a portion of the array substrate depicted in the figure.

[0103] Figure 17F It is shown Figure 17A A schematic diagram of the structure of the first signal line layer in a portion of the array substrate depicted in the figure.

[0104] Figure 17G It is shown Figure 17A A schematic diagram of the structure of the passivation layer in a portion of the array substrate depicted in the figure.

[0105] Figure 17H It is shown Figure 17A A schematic diagram of the structure of the second signal line layer in a portion of the array substrate depicted in the figure.

[0106] Figure 17I It is shown Figure 17A A schematic diagram of the structure of the first planarization layer in a portion of the array substrate depicted in the figure.

[0107] Figure 17J It is shown Figure 17AA schematic diagram of the structure of the third signal line layer in a portion of the array substrate depicted in the figure.

[0108] Figure 17K It is shown Figure 17A A schematic diagram of the structure of the second planarization layer in a portion of the array substrate depicted in the figure.

[0109] Figure 17L It is shown Figure 17A A schematic diagram of the structure of the anode layer in a portion of the array substrate depicted in the diagram.

[0110] Figure 17M It is shown Figure 17A A schematic diagram of the structure of the pixel-defining layer in a portion of the array substrate depicted in the figure.

[0111] Figure 18 This is a schematic diagram illustrating a voltage supply network in a portion of an array substrate according to some embodiments of the present disclosure.

[0112] Figure 19 This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure.

[0113] Figure 20 This is a schematic diagram illustrating a reset signal network in a portion of an array substrate according to some embodiments of the present disclosure.

[0114] Figure 21 This is a schematic diagram illustrating a reset signal network in a portion of an array substrate according to some embodiments of the present disclosure.

[0115] Figure 22 This is a schematic diagram illustrating a gate scan signal network in a portion of an array substrate according to some embodiments of the present disclosure.

[0116] Figure 23 This is a schematic diagram illustrating a gate scan signal network in a portion of an array substrate according to some embodiments of the present disclosure.

[0117] Figure 24 This is a schematic diagram illustrating a reset control signal network in a portion of an array substrate according to some embodiments of the present disclosure.

[0118] Figure 25 This is a schematic diagram illustrating a reset control signal network in a portion of an array substrate according to some embodiments of the present disclosure.

[0119] Figure 26 This is a schematic diagram illustrating a light-emitting control signal network in a portion of an array substrate according to some embodiments of the present disclosure.

[0120] Figure 27This is a schematic diagram illustrating a light-emitting control signal network in a portion of an array substrate according to some embodiments of the present disclosure.

[0121] Figure 28A This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure.

[0122] Figure 28B It is shown Figure 28A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate.

[0123] Figure 28C It is shown Figure 28A A schematic diagram of the structure of the first conductive layer in a portion of the array substrate depicted in the figure.

[0124] Figure 28D It is shown Figure 28A A schematic diagram of the structure of the second conductive layer in a portion of the array substrate depicted in the figure.

[0125] Figure 28E It is shown Figure 28A A schematic diagram of the structure of the interlayer dielectric layer in a portion of the array substrate depicted in the figure.

[0126] Figure 28F It is shown Figure 28A A schematic diagram of the structure of the first signal line layer in a portion of the array substrate depicted in the figure.

[0127] Figure 28G It is shown Figure 28A A schematic diagram of the structure of the passivation layer in a portion of the array substrate depicted in the figure.

[0128] Figure 28H It is shown Figure 28A A schematic diagram of the structure of the first planarization layer in a portion of the array substrate depicted in the figure.

[0129] Figure 28I It is shown Figure 28A A schematic diagram of the structure of the third signal line layer in a portion of the array substrate depicted in the figure.

[0130] Figure 28J It is shown Figure 28A A schematic diagram of the structure of the second planarization layer in a portion of the array substrate described herein.

[0131] Figure 28K It is shown Figure 28A A schematic diagram of the structure of the anode layer in a portion of the array substrate depicted in the diagram.

[0132] Figure 28L It is shown Figure 28AA schematic diagram of the structure of the pixel-defining layer in a portion of the array substrate depicted in the figure.

[0133] Figure 29 It is along Figure 28A A cross-sectional view of line B-B' in the diagram.

[0134] Figure 30A This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure.

[0135] Figure 30B It is shown Figure 30A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate.

[0136] Figure 30C It is shown Figure 30A A schematic diagram of the structure of the first conductive layer in a portion of the array substrate depicted in the figure.

[0137] Figure 30D It is shown Figure 30A A schematic diagram of the structure of the second conductive layer in a portion of the array substrate depicted in the figure.

[0138] Figure 30E It is shown Figure 30A A schematic diagram of the structure of the interlayer dielectric layer in a portion of the array substrate depicted in the figure.

[0139] Figure 30F It is shown Figure 30A A schematic diagram of the structure of the first signal line layer in a portion of the array substrate depicted in the figure.

[0140] Figure 30G It is shown Figure 30A A schematic diagram of the structure of the passivation layer in a portion of the array substrate depicted in the figure.

[0141] Figure 30H It is shown Figure 30A A schematic diagram of the structure of the first planarization layer in a portion of the array substrate depicted in the figure.

[0142] Figure 30I It is shown Figure 30A A schematic diagram of the structure of the third signal line layer in a portion of the array substrate depicted in the figure.

[0143] Figure 30J It is shown Figure 30A A schematic diagram of the structure of the second planarization layer in a portion of the array substrate described herein.

[0144] Figure 30K It is shown Figure 30A A schematic diagram of the structure of the anode layer in a portion of the array substrate depicted in the diagram.

[0145] Figure 30L It is shown Figure 30A A schematic diagram of the structure of the pixel-defining layer in a portion of the array substrate depicted in the figure.

[0146] Figure 31 This is a schematic diagram illustrating a voltage supply network in a portion of an array substrate according to some embodiments of the present disclosure.

[0147] Figure 32 This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure.

[0148] Figure 33 This is a schematic diagram illustrating a reset signal network in a portion of an array substrate according to some embodiments of the present disclosure.

[0149] Figure 34 This is a schematic diagram illustrating a reset signal network in a portion of an array substrate according to some embodiments of the present disclosure.

[0150] Figure 35 This is a schematic diagram illustrating a gate scan signal network in a portion of an array substrate according to some embodiments of the present disclosure.

[0151] Figure 36 This is a schematic diagram illustrating a gate scan signal network in a portion of an array substrate according to some embodiments of the present disclosure.

[0152] Figure 37 This is a schematic diagram illustrating a reset control signal network in a portion of an array substrate according to some embodiments of the present disclosure.

[0153] Figure 38 This is a schematic diagram illustrating a reset control signal network in a portion of an array substrate according to some embodiments of the present disclosure.

[0154] Figure 39 This is a schematic diagram illustrating a light-emitting control signal network in a portion of an array substrate according to some embodiments of the present disclosure.

[0155] Figure 40 This is a schematic diagram illustrating a light-emitting control signal network in a portion of an array substrate according to some embodiments of the present disclosure. Detailed Implementation

[0156] This disclosure will now be described in more detail with reference to the following embodiments. It should be noted that the following description of some embodiments presented herein is for illustrative and descriptive purposes only. It is not exhaustive or limited to the precise forms disclosed.

[0157] This disclosure provides, in particular, an array substrate and a display device that substantially overcomes one or more problems caused by the limitations and disadvantages of the prior art. In one aspect, this disclosure provides an array substrate. In some embodiments, the array substrate includes a plurality of signal lines. Optionally, each of the plurality of signal lines includes a plurality of first signal line portions, a plurality of second signal line portions, and a plurality of third signal line portions. Optionally, the plurality of first signal line portions and the plurality of second signal line portions are located in two different layers. Optionally, the plurality of first signal line portions and the plurality of third signal line portions are located in two different layers. Optionally, each of the plurality of second signal line portions is respectively connected to two adjacent first signal line portions. Optionally, each of the plurality of third signal line portions is respectively connected to two adjacent first signal line portions. Optionally, two separate first signal line portions, a separate second signal line portion, and a separate third signal line portion form a loop that substantially surrounds a region of transistors and capacitors of a pixel driving circuit having sub-pixels. Optionally, the two separate first signal line portions are connected via a separate second signal line portion and via a separate third signal line portion.

[0158] Various suitable pixel driving circuits can be used in the array substrate described in this disclosure. Examples of suitable driving circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C, and 8T2C. In some embodiments, each pixel driving circuit in a plurality of pixel driving circuits is a 7T1C driving circuit. Various suitable light-emitting elements can be used in the array substrate described in this disclosure. Examples of suitable light-emitting elements include organic light-emitting diodes (OLEDs), quantum dot OLEDs, and micro-LEDs. Optionally, the light-emitting element is a micro-LED. Optionally, the light-emitting element is an organic light-emitting diode including an organic light-emitting layer.

[0159] Figure 1 This is a plan view of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 1The array substrate comprises an array of subpixels Sp. Each subpixel includes electronic components, such as a light-emitting element. In one example, the light-emitting element is driven by a corresponding pixel driving circuit PDC. The array substrate includes multiple gate signal lines GL, multiple data lines DL, and multiple voltage supply lines Vdd (e.g., multiple first voltage supply lines and / or multiple second voltage supply lines). Each subpixel Sp is driven to emit light by a corresponding pixel driving circuit PDC. In one example, a high voltage signal (e.g., a VDD signal) is input to the corresponding pixel driving circuit PDC connected to the anode of the light-emitting element through each of the multiple voltage supply lines Vdd; a low voltage signal (e.g., a VSS signal) is input to the cathode of the light-emitting element through a low voltage supply line. The voltage difference between the high voltage signal (e.g., the VDD signal) and the low voltage signal (e.g., the VSS signal) is the driving voltage ΔV, which drives the light-emitting element to emit light.

[0160] Figure 2A This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figure 2AIn some embodiments, the pixel driving circuit includes: a driving transistor Td; a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a first transistor T1 having a gate connected to a corresponding reset control signal line among a plurality of reset control signal lines rst, a first electrode connected to a corresponding initialization signal line among a plurality of initialization signal lines Vint, and a second electrode connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate of the driving transistor Td; a second transistor T2 having a gate connected to a corresponding gate signal line among a plurality of gate signal lines GL, a first electrode connected to a corresponding data line among a plurality of data lines DL, and a second electrode connected to the first electrode of the driving transistor Td; and a third transistor T3 having a gate connected to a corresponding gate signal line, a first capacitor electrode Ce1 of the storage capacitor Cst, and the gate of the driving transistor Td. The first electrode of the transistor T1 is connected to the first electrode of the driving transistor T2; the second electrode of the third transistor T4 is connected to the second electrode of the driving transistor T2; the third transistor T5 is connected to the second electrode of the driving transistor T2 and the second electrode of the second transistor T3; the fourth transistor T6 is connected to the second electrode of the driving transistor T4 and the second electrode of the second transistor T2; the fifth transistor T5 is connected to the gate of the corresponding light-emitting control signal line, the first electrode of the driving transistor T3 and the second electrode of the third transistor T3, and the second electrode of the second transistor T6 is connected to the anode of the light-emitting element LE; and the sixth transistor T6 is connected to the gate of the corresponding gate signal line of the multiple gate signal lines GL, the first electrode of the corresponding initialization signal line of the multiple initialization signal lines Vint, and the second electrode of the fifth transistor and the anode of the light-emitting element LE. The second capacitor electrode Ce2 is connected to the corresponding voltage supply line and the first electrode of the fourth transistor T4.

[0161] In some embodiments, the pixel driving circuit includes a driving transistor Td, a data writing transistor (e.g., a second transistor T2), a compensation transistor (e.g., a third transistor T3), two light-emitting control transistors (e.g., a fourth transistor T4 and a fifth transistor T5), and two reset transistors (e.g., a first transistor T1 and a sixth transistor T6).

[0162] Figure 2B This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figure 2BIn some embodiments, the third transistor T3 is a "dual-gate" transistor, and the first transistor T1 is a "dual-gate" transistor. Optionally, in the "dual-gate" first transistor, the active layer of the first transistor crosses the corresponding reset control signal line twice (alternatively, the corresponding reset control signal line crosses the active layer of the first transistor T1 twice). Similarly, in the "dual-gate" third transistor, the active layer of the third transistor T3 crosses the corresponding first gate signal line of a plurality of first gate signal lines GL1 twice (alternatively, the corresponding gate signal line crosses the active layer of the third transistor T3 twice). The gate of the first transistor T1 is... Figure 3C The designation is "G1", where the first transistor T1 is a "dual-gate" transistor. The gate of the third transistor T3 is... Figure 3C The designation is "G3", where the third transistor, T3, is a "dual-gate" transistor.

[0163] The pixel driving circuit also includes a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the gate of the driving transistor Td, the first capacitor electrode Ce1, and the first electrode of the third transistor T3. The second node N2 is connected to the second electrode of the fourth transistor T4, the second electrode of the second transistor T2, and the first electrode of the driving transistor Td. The third node N3 is connected to the second electrode of the driving transistor Td, the second electrode of the third transistor T3, and the first electrode of the fifth transistor T5. The fourth node N4 is connected to the second electrode of the fifth transistor T5, the second electrode of the sixth transistor T6, and the anode of the light-emitting element LE.

[0164] As used herein, a first electrode or a second electrode refers to one of a first terminal and a second terminal of a transistor, both of which are connected to the active layer of the transistor. The direction of current flowing through the transistor can be configured to be from the first electrode to the second electrode, or from the second electrode to the first electrode. Thus, depending on the direction of current flowing through the transistor, in one example, the first electrode is configured to receive an input signal and the second electrode is configured to output an output signal; in another example, the second electrode is configured to receive an input signal and the first electrode is configured to output an output signal.

[0165] Figure 2C This is a timing diagram illustrating the operation of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figures 2A to 2CDuring one frame of an image, the operation of the pixel driving circuit includes a reset sub-stage t1, a data writing sub-stage t2, and a light emission sub-stage t3. In the initial sub-stage t0, a cutoff reset control signal is provided to the gate of the first transistor T1 via the corresponding reset control signal line in the plurality of reset control signal lines rst, causing the first transistor T1 to turn off. In the initial sub-stage t0, a cutoff signal is provided to the corresponding gate signal line in the plurality of gate signal lines GL, thus turning off the second transistor T2 and the third transistor T3.

[0166] In reset phase t1, a reset control signal is provided to the gate of the first transistor T1 via a corresponding reset control signal line among multiple reset control signal lines rst, to turn on the first transistor T1. This allows the initialization voltage signal from the corresponding initialization signal line among multiple initialization signal lines Vint to be transmitted from the first electrode of the first transistor T1 to the second electrode of the first transistor T1, and further to the first capacitor electrode Ce1 and the gate of the driving transistor Td. The gate of the driving transistor Td is initialized. The second capacitor electrode Ce2 receives a high voltage signal from the corresponding second voltage supply line among multiple second voltage supply lines Vdd2. Due to the increased voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2, the first capacitor electrode Ce1 is charged in reset phase t1. In reset phase t1, a cutoff signal is provided to the corresponding gate signal line among multiple gate signal lines GL, thus turning off the second transistor T2 and the third transistor T3. A high voltage signal is provided to the corresponding light emission control signal line among multiple light emission control signal lines em to turn off the fourth transistor T4 and the fifth transistor T5.

[0167] During the data write sub-stage t2, a cutoff reset control signal is again provided to the gate of the first transistor T1 via the corresponding reset control signal line in the multiple reset control signal lines rst, thus turning off the first transistor T1. The corresponding gate signal line in the multiple gate signal lines GL is provided with a conduction signal, therefore the second transistor T2 and the third transistor T3 are turned on. The second electrode of the driving transistor Td is connected to the second electrode of the third transistor T3. The gate of the driving transistor Td is electrically connected to the first electrode of the third transistor T3. Since the third transistor T3 is turned on during the data write sub-stage t2, the gate and second electrode of the driving transistor Td are connected and short-circuited, so only the PN junction between the gate and the first electrode of the driving transistor Td is effective, thus making the driving transistor Td a diode-connected mode. The second transistor T2 is turned on during the data write sub-stage t2. The data voltage signal transmitted via the corresponding data line in the multiple data lines DL is received by the first electrode of the second transistor T2 and then transmitted to the first electrode of the driving transistor Td, which is connected to the second electrode of the second transistor T2. The node N2 connected to the first electrode of the driving transistor Td has the voltage level of the data voltage signal. Since only the PN junction between the gate of the driving transistor Td and the first electrode is active, during the data write sub-stage t2, the voltage level at node N1 gradually rises to (Vdata + Vth), where Vdata is the voltage level of the data voltage signal and Vth is the voltage level of the threshold voltage Th of the PN junction. Because the voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2 decreases to a relatively small value, the storage capacitor Cst discharges. The corresponding light-emitting control signal lines in the plurality of light-emitting control signal lines em are provided with high-voltage signals to cut off the fourth transistor T4 and the fifth transistor T5.

[0168] During the data writing sub-stage t2, a turn-on reset control signal is provided to the gate of the sixth transistor T6 via the corresponding gate signal line among the multiple gate signal lines GL, so as to turn on the sixth transistor T6; to allow the initialization voltage signal from the corresponding initialization signal line among the multiple initialization signal lines Vint to be transmitted from the first electrode of the sixth transistor T6 to the second electrode of the sixth transistor T6; and further to node N4. The anode of the light-emitting element LE is initialized.

[0169] In the light-emitting phase t3, a cutoff reset control signal is again provided to the gate of the first transistor T1 through the corresponding reset control signal line in the plurality of reset control signal lines rst, thus turning off the first transistor T1. The corresponding gate signal lines in the plurality of gate signal lines GL are provided with cutoff signals, turning off the second transistor T2 and the third transistor T3. The corresponding light-emitting control signal lines in the plurality of light-emitting control signal lines em are provided with low voltage signals to turn on the fourth transistor T4 and the fifth transistor T5. In the light-emitting phase t3, the voltage level at node N1 is maintained at (Vdata + Vth), and the driving transistor Td is turned on by this voltage level, operating in the saturation region. A path is formed through the fourth transistor T4, the driving transistor Td, and the fifth transistor T5 to the light-emitting element LE. The driving transistor Td generates a driving current to drive the light-emitting element LE to emit light. The voltage level at node N3, connected to the second electrode of the driving transistor Td, is equal to the emission voltage of the light-emitting element LE.

[0170] In some embodiments, the array substrate includes a plurality of sub-pixels. In some embodiments, the plurality of sub-pixels includes a first sub-pixel, a second sub-pixel, and a third sub-pixel. Optionally, each pixel of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. The plurality of sub-pixels in the array substrate are arranged in an array. In one example, the array of the plurality of sub-pixels includes a repeating array in the format S1-S2-S3, wherein S1 represents a corresponding first sub-pixel, S2 represents a corresponding second sub-pixel, and S3 represents a corresponding third sub-pixel. In another example, the S1-S2-S3 format is a C1-C2-C3 format, wherein C1 represents a corresponding first sub-pixel of a first color, C2 represents a corresponding second sub-pixel of a second color, and C3 represents a corresponding third sub-pixel of a third color. In another example, the C1-C2-C3 format is an RGB format, wherein the corresponding first sub-pixel is a red sub-pixel, the corresponding second sub-pixel is a green sub-pixel, and the corresponding third sub-pixel is a blue sub-pixel.

[0171] In another example, the array of multiple subpixels includes a repeating array in the format S1-S2-S3-S4, where S1 represents the corresponding first subpixel, S2 represents the corresponding second subpixel, S3 represents the corresponding third subpixel, and S4 represents the corresponding fourth subpixel. In another example, the S1-S2-S3-S4 format is C1-C2-C3-C4, where C1 represents the corresponding first subpixel of the first color, C2 represents the corresponding second subpixel of the second color, C3 represents the corresponding third subpixel of the third color, and C4 represents the corresponding fourth subpixel of the fourth color. In yet another example, the S1-S2-S3-S4 format is C1-C2-C3-C2', where C1 represents the corresponding first subpixel of the first color, C2 represents the corresponding second subpixel of the second color, C3 represents the corresponding third subpixel of the third color, and C2' represents the corresponding fourth subpixel of the second color. In another example, the C1-C2-C3-C2' format is RGBG format, where the corresponding first subpixel is a red subpixel, the corresponding second subpixel is a green subpixel, the corresponding third subpixel is a blue subpixel, and the corresponding fourth subpixel is a green subpixel.

[0172] In some embodiments, the smallest repeating unit of the plurality of sub-pixels of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. Optionally, each of the corresponding first sub-pixel, the corresponding second sub-pixel, and the corresponding third sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a driving transistor Td, and a storage capacitor Cst.

[0173] In an alternative embodiment, the smallest repeating unit of the plurality of sub-pixels of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, a corresponding third sub-pixel, and a corresponding fourth sub-pixel. Optionally, each of the corresponding first sub-pixel, the corresponding second sub-pixel, the corresponding third sub-pixel, and the corresponding fourth sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a driving transistor Td, and a storage capacitor Cst.

[0174] Figure 3A This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure. Figure 3B It is shown Figure 3A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate. Figure 3C It is shown Figure 3A A schematic diagram of the structure of the first conductive layer in a portion of the array substrate depicted in the figure. Figure 3D It is shown Figure 3A A schematic diagram of the structure of the second conductive layer in a portion of the array substrate depicted in the figure. Figure 3E It is shown Figure 3A A schematic diagram of the structure of the interlayer dielectric layer in a portion of the array substrate depicted in the figure. Figure 3F It is shown Figure 3A A schematic diagram of the structure of the first signal line layer in a portion of the array substrate depicted in the figure. Figure 3G It is shown Figure 3A A schematic diagram of the structure of the passivation layer in a portion of the array substrate depicted in the figure. Figure 3H It is shown Figure 3A A schematic diagram of the structure of the second signal line layer in a portion of the array substrate depicted in the figure. Figure 3I It is shown Figure 3A A schematic diagram of the structure of the first planarization layer in a portion of the array substrate depicted in the figure. Figure 3J It is shown Figure 3A A schematic diagram of the structure of the third signal line layer in a portion of the array substrate depicted in the figure. Figure 3K It is shown Figure 3A A schematic diagram of the structure of the second planarization layer in a portion of the array substrate depicted in the figure. Figure 3L It is shown Figure 3A A schematic diagram of the structure of the anode layer in a portion of the array substrate depicted in the diagram. Figure 3M It is shown Figure 3A A schematic diagram of the structure of the pixel-defining layer in a portion of the array substrate depicted in the figure. Figure 4 It is along Figure 3A A cross-sectional view of line A-A' in the diagram.

[0175] Reference Figures 3A to 3M and Figure 4In some embodiments, the array substrate includes: a substrate BS; a semiconductor material layer SML located on the substrate BS; a gate insulating layer GI located on the side of the semiconductor material layer SML away from the substrate BS; a first conductive layer CT1 located on the side of the gate insulating layer GI away from the semiconductor material layer SML; an insulating layer IN located on the side of the first conductive layer CT1 away from the gate insulating layer GI; a second conductive layer CT2 located on the side of the insulating layer IN away from the first conductive layer CT1; an interlayer dielectric layer ILD located on the side of the second conductive layer CT2 away from the insulating layer IN; a first signal line layer SL1 located on the side of the interlayer dielectric layer ILD away from the second conductive layer CT2; and a passivation layer PVX. It is located on the side of the first signal line SL1 away from the interlayer dielectric layer ILD; the second signal line layer SL2 is located on the side of the passivation layer PVX away from the first signal line layer SL1; the first planarization layer PLN1 is located on the side of the second signal line layer SL2 away from the passivation layer PVX; the third signal line layer SL3 is located on the side of the first planarization layer PLN1 away from the second signal line layer SL2; the second planarization layer PLN2 is located on the side of the third signal line layer SL3 away from the first planarization layer PLN1; the anode layer ADL is located on the side of the second planarization layer PLN2 away from the third signal line layer SL3; and the pixel defining layer PDL is located on the side of the anode layer ADL away from the second planarization layer PLN2.

[0176] Reference Figure 2A , Figure 2B , Figure 3A and Figure 3BThe corresponding pixel driving circuits are labeled with numbers, which represent regions corresponding to multiple transistors (including first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, and driving transistor Td) in the corresponding pixel driving circuit. The corresponding pixel driving circuits are also labeled with numbers representing components of each of the multiple transistors in the pixel driving circuit. For example, first transistor T1 includes an active layer ACT1, a first electrode S1, and a second electrode D1. Second transistor T2 includes an active layer ACT2, a first electrode S2, and a second electrode D2. Third transistor T3 includes an active layer ACT3, a first electrode S3, and a second electrode D3. Fourth transistor T4 includes an active layer ACT4, a first electrode S4, and a second electrode D4. Fifth transistor T5 includes an active layer ACT5, a first electrode S5, and a second electrode D5. Sixth transistor T6 includes an active layer ACT6, a first electrode S6, and a second electrode D6. Driving transistor Td includes an active layer ACTd, a first electrode Sd, and a second electrode Dd. In one example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) in the corresponding pixel driving circuit are part of the overall structure. In another example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd), the first electrode (S1, S2, S3, S4, S5, S6, and Sd), and the second electrode (D1, D2, D3, D4, D5, D6, and Dd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) in the corresponding pixel driving circuit are part of the overall structure. In yet another example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) are located in the same layer. In another example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd), the first electrodes (S1, S2, S3, S4, S5, S6, and Sd), and the second electrodes (D1, D2, D3, D4, D5, D6, and Dd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) are located in the same layer.

[0177] As used herein, an active layer refers to a portion of a transistor comprising a semiconductor material layer, the orthographic projection of which onto the substrate overlaps with the orthographic projection of the gate onto the substrate. A first electrode refers to a portion of the transistor connected to one side of the active layer, and a second electrode refers to a portion of the transistor connected to the other side of the active layer. In the context of a dual-gate transistor (e.g., a third transistor T3), an active layer refers to a portion of the transistor comprising a first portion of a semiconductor material layer, a second portion of a semiconductor material layer, and a third portion located between the first and second portions, wherein the orthographic projection of the first portion of the semiconductor material layer onto the substrate overlaps with the orthographic projection of the first gate onto the substrate, and the orthographic projection of the second portion of the semiconductor material layer onto the substrate overlaps with the orthographic projection of the second gate onto the substrate. In the context of a dual-gate transistor, a first electrode refers to a portion of the transistor connected to the side of the first portion away from the third portion, and a second electrode refers to a portion of the transistor connected to the side of the second portion away from the third portion.

[0178] Reference Figure 2A , Figure 2B , Figure 3A and Figure 3C In some embodiments, the first conductive layer includes a plurality of reset control signal lines rst, a plurality of light emission control signal lines em, a plurality of gate signal lines GL, and a first capacitor electrode Ce1 of the storage capacitor Cst. Various suitable electrode materials and various suitable manufacturing methods can be used to fabricate the first conductive layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, the plurality of reset control signal lines rst, the plurality of light emission control signal lines em, the plurality of gate signal lines GL, and the first capacitor electrode Ce1 of the storage capacitor Cst are located in the same layer.

[0179] As used herein, the term "same layer" refers to a relationship between layers formed simultaneously in the same step. In one example, multiple gate signal lines GL and a first capacitor electrode Ce1 are located in the same layer when they are formed by one or more steps of the same patterning process performed in the same material layer. In another example, multiple gate signal lines GL and a first capacitor electrode Ce1 can be formed in the same layer by simultaneously performing the steps of forming multiple gate signal lines GL and forming the first capacitor electrode Ce1. The term "same layer" does not always mean that the layer thickness or layer height is the same in a cross-sectional view.

[0180] Reference Figure 2A , Figure 2B , Figure 3A and Figure 3D In some embodiments, the second conductive layer includes a plurality of initialization signal lines Vint and a second capacitor electrode Ce2 for a storage capacitor Cst. Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the second conductive layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the second conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, the plurality of initialization signal lines Vint and the second capacitor electrode Ce2 for the storage capacitor Cst are located in the same layer.

[0181] Figure 3E The image depicts vias extending through the interlayer dielectric layer (ILD).

[0182] Reference Figure 2A , Figure 2B , Figure 3A and Figure 3F In some embodiments, the first signal line layer includes node connection lines Cln, voltage connection pads VCP, data signal connection pads DCP, electrode connection lines Cle, and reset signal connection lines Cli. Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the first signal line layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first signal line layer include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. In some embodiments, the first signal line layer includes multiple sublayers stacked together. In one example, the first signal line layer includes a stacked titanium / aluminum / titanium multilayer structure. In another example, the first signal line layer includes a stacked molybdenum / aluminum / molybdenum multilayer structure. Optionally, the node connection lines Cln, voltage connection pads VCP, data signal connection pads DCP, electrode connection lines Cle, and reset signal connection lines Cli are located in the same layer.

[0183] Node connection line Cln is connected to the first capacitor electrode Ce1, and also to the second electrode of the third transistor T3 and / or the second electrode of the first transistor T1 in the corresponding pixel driving circuit. Data signal connection pad DCP connects the corresponding data line among multiple data lines to the first electrode of the second transistor T2. Reset signal connection line Cli connects the corresponding initialization signal line among multiple initialization signal lines to the first electrodes of the first transistor T1 and the sixth transistor T6. Voltage connection pad VCP connects the corresponding voltage supply line among multiple voltage supply lines to the first electrode of the fourth transistor T4, and also to the second capacitor electrode of the storage capacitor. Electrode connection line Cle is connected to the second electrodes of the fifth transistor T5 and the sixth transistor T6, respectively.

[0184] Figure 3G The image depicts vias extending through the passivation layer PVX.

[0185] Reference Figure 2A , Figure 2B , Figure 3A and Figure 3H In some embodiments, the second signal line layer includes a plurality of voltage supply lines Vdd and a plurality of data lines DL. Each of the plurality of voltage supply lines Vdd includes a plurality of alternating first voltage supply line portions Vdd-1 and a plurality of second voltage supply line portions Vdd-2. Each first voltage supply line portion in the plurality of first voltage supply line portions Vdd-1 and a corresponding second voltage supply line portion in the plurality of second voltage supply line portions Vdd-2 are connected by a voltage connection bridge located in the third signal line layer. Each of the plurality of data lines is electrically connected to the first electrode of the second transistor T2 via a data signal connection pad located in the first signal line layer.

[0186] Various suitable conductive materials and various suitable fabrication methods can be used to fabricate the second signal line layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the second signal line layer include, but are not limited to, substantially transparent conductive materials, such as metal oxide conductive materials. In one example, the second signal line layer comprises indium tin oxide. Optionally, multiple voltage supply lines Vdd and multiple data lines DL are located in the same layer. As used herein, the term "substantially transparent" means that at least 50% (e.g., at least 60%, at least 70%, at least 80%, at least 90%, and at least 95%) of incident light in the visible wavelength range is transmitted through it.

[0187] Figure 3I The image depicts vias extending through the first planarization layer PLN1.

[0188] Reference Figure 2A , Figure 2B , Figure 3A and Figure 3J In some embodiments, the third signal line layer includes a voltage connection bridge (VCB) and an anode connection pad (ACP). The VCB connects a first voltage supply line portion located in the second signal line layer and a second voltage supply line portion located in the second signal line layer. The anode connection pad (ACP) is connected to the fourth node N4 and the corresponding anode in the corresponding sub-pixel, respectively. The anode connection pad (ACP) is connected to the second electrodes of the fifth transistor T5 and the sixth transistor T6, and the corresponding anode in the corresponding sub-pixel is connected to the anode connection pad (ACP).

[0189] Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the third signal line layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the third signal line layer include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. In some embodiments, the second signal line layer comprises multiple sublayers stacked together. In one example, the second signal line layer comprises a stacked titanium / aluminum / titanium multilayer structure. In another example, the second signal line layer comprises a stacked molybdenum / aluminum / molybdenum multilayer structure. Optionally, the voltage connection bridge VCB and the anode connection pad ACP are located in the same layer.

[0190] Figure 3K The image depicts vias extending through the second planarization layer PLN2.

[0191] Reference Figure 2A , Figure 2B , Figure 3A and Figure 3L In some embodiments, the anode layer includes the anode of the corresponding light-emitting element. The anode is connected to an anode connection pad located in the third signal line layer, and the anode connection pad is connected to the second electrode of the fifth transistor T5 and the sixth transistor T6.

[0192] Figure 3M The image depicts a via extending through the pixel-defined layer (PDL). (See reference...) Figure 3M The array substrate includes sub-pixel openings SA configured to accommodate light-emitting material.

[0193] Reference Figure 2A , Figure 2B , Figures 3A to 3M and Figure 4In some embodiments, the first capacitor electrode Ce1 is located on the side of the gate insulating layer GI away from the substrate BS. In some embodiments, the array substrate further includes a first via v1 and a second via v2. The first via v1 extends through the interlayer dielectric layer ILD and the insulating layer IN. The second via v2 extends through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. Optionally, the node connection line Cln is connected to the first capacitor electrode Ce1 through the first via v1, and the node connection line Cln is connected to the semiconductor material layer SML through the second via v2. Optionally, the node connection line Cln is connected to the second electrode D3 of the third transistor and / or the second electrode D1 of the first transistor, such as... Figure 4 The description.

[0194] In some embodiments, the array substrate further includes a third via v3 and a fourth via v4. The voltage connection bridge VCB is connected via the third via v3 to a corresponding first voltage supply line portion of a plurality of first voltage supply line portions Vdd-1, and via the fourth via v4 to a corresponding second voltage supply line portion of a plurality of second voltage supply line portions Vdd-2. In one example, the third via v3 extends through the first planarization layer PLN1. In another example, the fourth via v4 extends through the first planarization layer PLN1.

[0195] In some embodiments, the array substrate further includes a fifth via v5. A corresponding voltage supply line (e.g., a corresponding second voltage supply line portion of a plurality of second voltage supply line portions Vdd-2) is connected to a voltage connection pad VCP via the fifth via v5. In one example, the fifth via v5 extends through the passivation layer PVX.

[0196] In some embodiments, the array substrate further includes a sixth via v6. A voltage connection pad VCP is connected to the first electrode S4 of the fourth transistor T4 via the sixth via v6, thereby providing a voltage supply signal to the first electrode S4 of the fourth transistor T4. In one example, the sixth via v6 extends through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI.

[0197] Figure 5A This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure. Figure 5B It is shown Figure 5A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate. Figure 5C It is shown Figure 5A A schematic diagram of the structure of the first conductive layer in a portion of the array substrate depicted in the figure. Figure 5D It is shown Figure 5A A schematic diagram of the structure of the second conductive layer in a portion of the array substrate depicted in the figure. Figure 5E It is shown Figure 5A A schematic diagram of the structure of the interlayer dielectric layer in a portion of the array substrate depicted in the figure. Figure 5F It is shown Figure 3A A schematic diagram of the structure of the first signal line layer in a portion of the array substrate. Figure 5G It is shown Figure 5A A schematic diagram of the structure of the passivation layer in a portion of the array substrate depicted in the figure. Figure 5H It is shown Figure 5A A schematic diagram of the structure of the second signal line layer in a portion of the array substrate depicted in the figure. Figure 5I It is shown Figure 5A A schematic diagram of the structure of the first planarization layer in a portion of the array substrate depicted in the figure. Figure 5J It is shown Figure 5A A schematic diagram of the structure of the third signal line layer in a portion of the array substrate depicted in the figure. Figure 5K It is shown Figure 5A A schematic diagram of the structure of the second planarization layer in a portion of the array substrate depicted in the figure. Figure 5L It is shown Figure 5A A schematic diagram of the structure of the anode layer in a portion of the array substrate depicted in the diagram. Figure 5M It is shown Figure 5A A schematic diagram of the structure of the pixel-defining layer in a portion of the array substrate depicted in the figure.

[0198] In some embodiments, refer to Figure 5A The smallest repeating unit of multiple sub-pixels of the array substrate includes a corresponding first sub-pixel sp1, a corresponding second sub-pixel sp2, and a corresponding third sub-pixel sp3. Figure 3A A portion of the array substrate depicted corresponds to Figure 5A A portion of the corresponding third sub-pixel sp3 depicted in the image.

[0199] In some embodiments, each of the corresponding first sub-pixel sp1, the corresponding second sub-pixel sp2, and the corresponding third sub-pixel sp3 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a driving transistor Td, and a storage capacitor Cst.

[0200] In some embodiments, the corresponding first sub-pixel sp1 is a sub-pixel of a first color (e.g., red), the corresponding second sub-pixel sp2 is a sub-pixel of a second color (e.g., green), and the corresponding third sub-pixel sp3 is a sub-pixel of a third color (e.g., blue). In some embodiments, the corresponding first sub-pixel sp1, the corresponding second sub-pixel sp2, and the corresponding third sub-pixel sp3 are three sub-pixels of a pixel in an array substrate.

[0201] Reference Figure 5A , Figure 5H and Figure 5J In some embodiments, each of the plurality of voltage supply lines Vdd includes a plurality of first voltage supply line portions Vdd-1 and a plurality of second voltage supply line portions Vdd-2 arranged alternately in a second signal line layer. The respective first voltage supply line portions in the plurality of first voltage supply line portions Vdd-1 and the corresponding second voltage supply line portions in the plurality of second voltage supply lines Vdd-2 are connected via a voltage connection bridge VCB in a third signal line layer.

[0202] Figure 6 This is a schematic diagram illustrating a voltage supply network in a portion of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 5A , Figure 5H , Figure 5J and Figure 6 In some embodiments, the array substrate includes multiple voltage connection bridges (VCBS). Optionally, the multiple VCBS are arranged in a multi-row and multi-column array. Multiple voltage supply lines Vdd include a first adjacent voltage supply line AVdd1, a second adjacent voltage supply line AVdd2, and a third adjacent voltage supply line AVdd3. Optionally, the first adjacent voltage supply line AVdd1 is configured to provide a voltage supply signal to a first pixel driving circuit PDC1 in a corresponding first sub-pixel Sp1, the second adjacent voltage supply line AVdd2 is configured to provide a voltage supply signal to a second pixel driving circuit PDC2 in a corresponding second sub-pixel Sp2, and the third adjacent voltage supply line AVdd3 is configured to provide a voltage supply signal to a third pixel driving circuit PDC3 in a corresponding third sub-pixel Sp3.

[0203] In some embodiments, each voltage bridge in the plurality of voltage bridges VCBS is connected to a first adjacent voltage supply line AVdd1, a second adjacent voltage supply line AVdd2, and a third adjacent voltage supply line AVdd3, respectively.

[0204] In some embodiments, each of the first adjacent voltage supply line AVdd1, the second adjacent voltage supply line AVdd2, and the third adjacent voltage supply line AVdd3 includes a plurality of first voltage supply line portions Vdd-1 and a plurality of second voltage supply line portions Vdd-2 alternately arranged in the second signal line layer. In some embodiments, each voltage connection bridge in the plurality of voltage connection bridges VCBS is respectively connected to the first adjacent voltage supply line portion AVdd-1 and the second adjacent voltage supply line portion AVdd-2 of the first adjacent voltage supply line AVdd1, respectively connected to the first adjacent voltage supply line portion AVdd-1 and the second adjacent voltage supply line portion AVdd-2 of the second adjacent voltage supply line AVdd2, and respectively connected to the first adjacent voltage supply line portion AVdd-1 and the second adjacent voltage supply line portion AVdd-2 of the third adjacent voltage supply line AVdd3.

[0205] In some embodiments, multiple voltage supply lines (including a first adjacent voltage supply line AVdd1, a second adjacent voltage supply line AVdd2, and a third adjacent voltage supply line AVdd3) are located on a second signal line layer, and multiple voltage connection bridges VCBS are located on a third signal line layer.

[0206] In some embodiments, the signal lines located in the second signal line layer are made of a substantially transparent conductive material, thereby allowing multiple light-transmitting areas to exist in the array substrate. Figure 7 This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 7 In some embodiments, the array substrate includes multiple light-transmitting regions TR that allow light to pass through. Within the multiple light-transmitting regions TR, signal lines of a second signal line layer (e.g., multiple data lines, multiple first voltage supply line portions, and multiple second voltage supply line portions) are present, while signal lines and electrodes of the first conductive layer, second conductive layer, first signal line layer, third signal line layer, and anode layer are absent. Because the signal lines of the second signal line layer are made of a substantially transparent conductive material, light can pass through the multiple light-transmitting regions TR.

[0207] In some embodiments, two adjacent voltage connection bridges in a plurality of voltage connection bridges in the same pixel row VCBS are connected to the same voltage supply line in a plurality of voltage supply lines, such as Figure 6 As depicted. Reference Figure 9 In some embodiments, a pixel row includes a row m sub-pixel Rm, a row (m+1) sub-pixel R(m+1), and a row (m+2) sub-pixel R(m+2).

[0208] In some embodiments, the voltage connection bridges in the VCBS of multiple voltage connection bridges in the same pixel column are connected to the same three adjacent voltage supply lines of multiple voltage supply lines. (See reference...) Figure 9 In some embodiments, the pixel column includes the nth column sub-pixel Cn, the (n-1)th column sub-pixel C(n-1), and the (n+1)th column sub-pixel C(n+1).

[0209] In some embodiments, the array substrate is a full display with camera (FDC) array substrate, wherein the array substrate further includes photoelectric sensors located in a plurality of light-transmitting regions TR configured to detect light.

[0210] Figure 8 This is a schematic diagram illustrating a reset signal network in a portion of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 5A , Figure 5D , Figure 5H and Figure 8 Each of the multiple initialization signal lines includes multiple first initialization signal line portions Vint-1 and multiple second initialization signal line portions Vint-2. The multiple first initialization signal line portions Vint-1 and the multiple second initialization signal line portions Vint-2 are located in two different layers. In one example, the multiple first initialization signal line portions Vint-1 are located in a second conductive layer, while the multiple second initialization signal line portions Vint-2 are located in a second signal line layer. Each second initialization signal line portion in the multiple second initialization signal line portions Vint-2 is connected to two adjacent first initialization signal line portions in the multiple first initialization signal line portions Vint-1. Two adjacent first initialization signal line portions in the multiple first initialization signal line portions Vint-1 are connected through individual second initialization signal line portions in the multiple second initialization signal line portions Vint-2.

[0211] In some embodiments, each of the plurality of initialization signal lines includes a plurality of first initialization signal line portions Vint-1 and a plurality of third initialization signal line portions Vint-3. The plurality of first initialization signal line portions Vint-1 and the plurality of third initialization signal line portions Vint-3 are located in two different layers. In one example, the plurality of first initialization signal line portions Vint-1 are located in a second conductive layer, while the plurality of third initialization signal line portions Vint-3 are located in a second signal line layer. Each third initialization signal line portion in the plurality of third initialization signal line portions Vint-3 is respectively connected to two adjacent first initialization signal line portions in the plurality of first initialization signal line portions Vint-1 in the same row. Two adjacent first initialization signal line portions in the plurality of first initialization signal line portions Vint-1 are connected through individual third initialization signal line portions in the plurality of third initialization signal line portions Vint-3.

[0212] In some embodiments, each of the plurality of initialization signal lines includes a plurality of first initialization signal line portions Vint-1, a plurality of second initialization signal line portions Vint-2, and a plurality of third initialization signal line portions Vint-3. The plurality of first initialization signal line portions Vint-1 and the plurality of second initialization signal line portions Vint-2 are located in two different layers; and the plurality of first initialization signal line portions Vint-1 and the plurality of third initialization signal line portions Vint-3 are located in two different layers. Optionally, the plurality of second initialization signal line portions Vint-2 and the plurality of third initialization signal line portions Vint-3 are located in the same layer. In one example, the plurality of first initialization signal line portions Vint-1 are located in a second conductive layer, the plurality of second initialization signal line portions Vint-2 are located in a second signal line layer, and the plurality of third initialization signal line portions Vint-3 are located in a second signal line layer. In some embodiments, the signal lines located in the second signal line layer are made of a substantially transparent conductive material. Within multiple light-transmitting regions TR, there are signal lines of a second signal line layer (e.g., multiple data lines, multiple first voltage supply line portions, multiple second voltage supply line portions, multiple second initialization signal line portions Vint-2, and multiple third initialization signal line portions Vint-3), but no signal lines or electrodes of the first conductive layer, second conductive layer, first signal line layer, third signal line layer, and anode layer. Since the signal lines of the second signal line layer are made of a substantially transparent conductive material, light can pass through the multiple light-transmitting regions TR.

[0213] In some embodiments, each of the plurality of second initialization signal line portions Vint-2 is connected to two adjacent first initialization signal line portions Vint-1. Each of the plurality of third initialization signal line portions Vint-3 is connected to two adjacent first initialization signal line portions Vint-1. The two adjacent first initialization signal line portions in Vint-1 are connected via individual second initialization signal line portions in Vint-2 and via individual third initialization signal line portions in Vint-3. The two adjacent first initialization signal line portions in Vint-1, the individual second initialization signal line portions in Vint-2, and the individual third initialization signal line portions in Vint-3 form a first ring that substantially surrounds the region of the transistor and capacitor of the pixel driving circuit having a sub-pixel. In one example, the first ring substantially surrounds the region of the transistor and capacitor having a corresponding first sub-pixel. In another example, the first ring substantially surrounds the region of transistors and capacitors having a subpixel of the first color. In another example, the first ring substantially surrounds the region of transistors and capacitors having a red subpixel. As used herein, the term "substantially surrounds" means at least 50% surround, such as at least 55% surround, at least 60% surround, at least 65% surround, at least 70% surround, at least 75% surround, at least 80% surround, at least 85% surround, at least 90% surround, at least 95% surround, at least 99% surround, or 100% surround.

[0214] In some embodiments, the array substrate includes a plurality of first rings LPS1 arranged in a row. Optionally, the plurality of first rings LPS1 respectively substantially surround the region of the pixel driving circuit of a sub-pixel of the same color. Each of the plurality of first rings LPS1 substantially surrounds the region of the pixel driving circuit of a sub-pixel of the same color. In one example, the plurality of first rings LPS1 substantially surround the region of the pixel driving circuit of a red sub-pixel.

[0215] In some embodiments, a plurality of first rings LPS1 substantially surround the region of the anode of a sub-pixel having the same color. Each of the plurality of first rings LPS1 substantially surrounds the region of the anode of a sub-pixel having the same color. In one example, the plurality of first rings LPS1 substantially surround the region of the anode having a red sub-pixel.

[0216] Figure 9This is a schematic diagram illustrating a reset signal network in a portion of an array substrate according to some embodiments of the present disclosure. In some embodiments, reference is made to... Figure 9 The subpixels in the array substrate are arranged in multiple rows and columns. In the m-th row of subpixels Rm, the array substrate includes a row of first subpixels. In the (m+1)-th row of subpixels R(m+1), the array substrate includes a row of third subpixels. In the (m+2)-th row of subpixels R(m+2), the array substrate includes a row of second subpixels. Optionally, a row of first subpixels is a row of subpixels of a first color, a row of second subpixels is a row of subpixels of a second color, and a row of third subpixels is a row of subpixels of a third color. Figure 9 The text represents the corresponding first sub-pixel sp1, the corresponding second sub-pixel sp2, and the corresponding third sub-pixel sp3.

[0217] In some embodiments, in the nth column of sub-pixels Cn, the array substrate includes a column of third sub-pixels. In the (n-1)th column of sub-pixels C(n-1), the array substrate includes a column of alternating first and second sub-pixels. In the (n+1)th column of sub-pixels C(n+1), the array substrate includes a column of alternating first and second sub-pixels. Optionally, the column of third sub-pixels is a column of sub-pixels of a third color, and the column of alternating first and second sub-pixels is a column of alternating first and second color sub-pixels. Optionally, in the nth column of sub-pixels Cn, each of the plurality of light-transmitting regions TR separates two adjacent third sub-pixels.

[0218] Reference Figure 2A , Figure 2B , Figures 3A to 3M , Figures 5A to 5M and Figure 9 In some embodiments, the first initialization signal line portion of the plurality of first initialization signal line portions Vint-1 is connected to the first electrode of one or more reset transistors in the pixel driving circuit of the third sub-pixel in the nth column sub-pixel Cn and the (m+1)th row sub-pixel R(m+1), connected to the first electrode of one or more reset transistors in the pixel driving circuit of the first sub-pixel in the (n-1)th column sub-pixel C(n-1) and the mth row sub-pixel Rm, and connected to the first electrode of one or more reset transistors in the pixel driving circuit of the second sub-pixel in the (n+1)th column sub-pixel C(n+1) and the (m+2)th row sub-pixel R(m+2).

[0219] In some embodiments, the second initialization signal line portion of the plurality of second initialization signal line portions Vint-2 connects the first initialization signal line portion to a first adjacent first initialization signal line portion, and the first adjacent first initialization signal line portion is connected to the first electrode of one or more reset transistors in the pixel driving circuit of the second sub-pixel in the (n-1)th column sub-pixel C(n-1) and the (m+2)th row sub-pixel R(m+2).

[0220] In some embodiments, the third initialization signal line portion of the plurality of third initialization signal line portions Vint-3 connects the first initialization signal line portion to the second adjacent first initialization signal line portion, and the second adjacent first initialization signal line portion is connected to the first electrode of one or more reset transistors in the pixel driving circuit of the first sub-pixel in the (n+1)th column sub-pixel C(n+1) and the first sub-pixel in the mth row sub-pixel Rm.

[0221] Figure 10 This is a schematic diagram illustrating a gate scan signal network in a portion of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 5A , Figure 5C , Figure 5H and Figure 10 Each of the plurality of gate signal lines includes a plurality of first gate signal line portions GL-1 and a plurality of second gate signal line portions GL-2. The plurality of first gate signal line portions GL-1 and the plurality of second gate signal line portions GL-2 are located in two different layers. In one example, the plurality of first gate signal line portions GL-1 are located in a first conductive layer, and the plurality of second gate signal line portions GL-2 are located in a second signal line layer. Each second gate signal line portion in the plurality of second gate signal line portions GL-2 is connected to two adjacent first gate signal line portions in the plurality of first gate signal line portions GL-1. Two adjacent first gate signal line portions in the plurality of first gate signal line portions GL-1 are connected through individual second gate signal line portions in the plurality of second gate signal line portions GL-2.

[0222] In some embodiments, each of the plurality of gate signal lines includes a plurality of first gate signal line portions GL-1 and a plurality of third gate signal line portions GL-3. The plurality of first gate signal line portions GL-1 and the plurality of third gate signal line portions GL-3 are located in two different layers. In one example, the plurality of first gate signal line portions GL-1 are located in a first conductive layer, and the plurality of third gate signal line portions GL-3 are located in a second signal line layer. Each third gate signal line portion in the plurality of third gate signal line portions GL-3 is respectively connected to two adjacent first gate signal line portions in the plurality of first gate signal line portions GL-1 in the same row. Two adjacent first gate signal line portions in the plurality of first gate signal line portions GL-1 are connected through separate third gate signal line portions in the plurality of third gate signal line portions GL-3.

[0223] In some embodiments, each of the plurality of gate signal lines includes a plurality of first gate signal line portions GL-1, a plurality of second gate signal line portions GL-2, and a plurality of third gate signal line portions GL-3. The plurality of first gate signal line portions GL-1 and the plurality of second gate signal line portions GL-2 are located in two different layers; and the plurality of first gate signal line portions GL-1 and the plurality of third gate signal line portions GL-3 are located in two different layers. Optionally, the plurality of second gate signal line portions GL-2 and the plurality of third gate signal line portions GL-3 are located in the same layer. In one example, the plurality of first gate signal line portions GL-1 are located in a first conductive layer, the plurality of second gate signal line portions GL-2 are located in a second signal line layer, and the plurality of third gate signal line portions GL-3 are located in a second signal line layer. In some embodiments, the signal lines located in the second signal line layer are made of a substantially transparent conductive material. Within multiple light-transmitting regions TR, there are signal lines of a second signal line layer (e.g., multiple data lines, multiple first voltage supply line portions, multiple second voltage supply line portions, multiple second gate signal line portions GL-2, and multiple third gate signal line portions GL-3), but no signal lines or electrodes of the first conductive layer, second conductive layer, first signal line layer, third signal line layer, and anode layer. Since the signal lines of the second signal line layer are made of a substantially transparent conductive material, light can pass through the multiple light-transmitting regions TR.

[0224] In some embodiments, each of the plurality of second gate signal line portions GL-2 is connected to two adjacent first gate signal line portions GL-1. Each of the plurality of third gate signal line portions GL-3 is connected to two adjacent first gate signal line portions GL-1. Two adjacent first gate signal line portions in GL-1 are connected via individual second gate signal line portions in GL-2 and via individual third gate signal line portions in GL-3. Two adjacent first gate signal line portions in GL-1, individual second gate signal line portions in GL-2, and individual third gate signal line portions in GL-3 form a second ring that substantially surrounds the region of the transistor and capacitor of the pixel driving circuit having a sub-pixel. In one example, the second ring substantially surrounds the region of the transistor and capacitor having a corresponding first sub-pixel. In another example, the second ring substantially surrounds the region of the transistor and capacitor having a sub-pixel of a first color. In another example, the second ring essentially surrounds the area containing transistors and capacitors with red subpixels.

[0225] In some embodiments, the array substrate includes a plurality of second rings LPS2 arranged in a row. Optionally, the plurality of second rings LPS2 respectively substantially surround the region of the pixel driving circuitry of a sub-pixel of the same color. Each of the plurality of second rings LPS2 substantially surrounds the region of the pixel driving circuitry of a sub-pixel of the same color. In one example, the plurality of second rings LPS2 substantially surround the region of the pixel driving circuitry of a red sub-pixel.

[0226] In some embodiments, a plurality of second rings LPS2 substantially surround the region of the anode of a sub-pixel having the same color. Each of the plurality of second rings LPS2 substantially surrounds the region of the anode of a sub-pixel having the same color. In one example, the plurality of second rings LPS2 substantially surround the region of the anode having a red sub-pixel.

[0227] Figure 11 This is a schematic diagram illustrating a gate scan signal network in a portion of an array substrate according to some embodiments of the present disclosure. In some embodiments, reference is made to... Figure 11The subpixels in the array substrate are arranged in multiple rows and columns. In the m-th row of subpixels Rm, the array substrate includes a row of first subpixels. In the (m+1)-th row of subpixels R(m+1), the array substrate includes a row of third subpixels. In the (m+2)-th row of subpixels R(m+2), the array substrate includes a row of second subpixels. Optionally, a row of first subpixels is a row of subpixels of a first color, a row of second subpixels is a row of subpixels of a second color, and a row of third subpixels is a row of subpixels of a third color. Figure 11 The text represents the corresponding first sub-pixel sp1, the corresponding second sub-pixel sp2, and the corresponding third sub-pixel sp3.

[0228] In some embodiments, in the nth column of sub-pixels Cn, the array substrate includes a column of third sub-pixels. In the (n-1)th column of sub-pixels C(n-1), the array substrate includes a column of alternating first and second sub-pixels. In the (n+1)th column of sub-pixels C(n+1), the array substrate includes a column of alternating first and second sub-pixels. Optionally, the column of third sub-pixels is a column of sub-pixels of a third color, and the column of alternating first and second sub-pixels is a column of alternating first and second color sub-pixels. Optionally, in the nth column of sub-pixels Cn, each of the plurality of light-transmitting regions TR separates two adjacent third sub-pixels.

[0229] Reference Figure 2A , Figure 2B , Figures 3A to 3M , Figures 5A to 5M and Figure 11 In some embodiments, the first gate signal line portion of the plurality of first gate signal line portions GL-1 is connected to the gate of one or more data write transistors in the pixel driving circuit of the third sub-pixel in the nth column sub-pixel Cn and the (m+1)th row sub-pixel R(m+1), connected to the gate of one or more data write transistors in the pixel driving circuit of the first sub-pixel in the (n-1)th column sub-pixel C(n-1) and the mth row sub-pixel Rm, and connected to the gate of one or more data write transistors in the pixel driving circuit of the second sub-pixel in the (n+1)th column sub-pixel C(n+1) and the (m+2)th row sub-pixel R(m+2).

[0230] In some embodiments, the second gate signal line portion GL-2 of the plurality of second gate signal line portions GL-2 connects the first gate signal line portion to a first adjacent first gate signal line portion, and the first adjacent first gate signal line portion is connected to the gate of one or more data writing transistors in the pixel driving circuit of the second sub-pixel in the (n-1)th column sub-pixel C(n-1) and the (m+2)th row sub-pixel R(m+2).

[0231] In some embodiments, the third gate signal line portion GL-3 of the plurality of third gate signal line portions GL-3 connects the first gate signal line portion to the second adjacent first gate signal line portion, and the second adjacent first gate signal line portion is connected to the gate of one or more data writing transistors in the pixel driving circuit of the first sub-pixel in the (n+1)th column sub-pixel C(n+1) and the mth row sub-pixel Rm.

[0232] Figure 12 This is a schematic diagram illustrating a reset control signal network in a portion of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 5A , Figure 5C , Figure 5H and Figure 12 Each of the plurality of reset control signal lines includes a plurality of first reset control signal line portions rst-1 and a plurality of second reset control signal line portions rst-2. The plurality of first reset control signal line portions rst-1 and the plurality of second reset control signal line portions rst-2 are located in two different layers. In one example, the plurality of first reset control signal line portions rst-1 are located in a first conductive layer, and the plurality of second reset control signal line portions rst-2 are located in a second signal line layer. Each second reset control signal line portion in the plurality of second reset control signal line portions rst-2 is respectively connected to two adjacent first reset control signal line portions in the plurality of first reset control signal line portions rst-1. Two adjacent first reset control signal line portions in the plurality of first reset control signal line portions rst-1 are connected through individual second reset control signal line portions in the plurality of second reset control signal line portions rst-2.

[0233] In some embodiments, each of the plurality of reset control signal lines includes a plurality of first reset control signal line portions rst-1 and a plurality of third reset control signal line portions rst-3. The plurality of first reset control signal line portions rst-1 and the plurality of third reset control signal line portions rst-3 are located in two different layers. In one example, the plurality of first reset control signal line portions rst-1 are located in a first conductive layer, and the plurality of third reset control signal line portions rst-3 are located in a second signal line layer. Each third reset control signal line portion in the plurality of third reset control signal line portions rst-3 is respectively connected to two adjacent first reset control signal line portions rst-1 in the same row. Two adjacent first reset control signal line portions rst-1 are connected through individual third reset control signal line portions rst-3.

[0234] In some embodiments, each of the plurality of reset control signal lines includes a plurality of first reset control signal line portions rst-1, a plurality of second reset control signal line portions rst-2, and a plurality of third reset control signal line portions rst-3. The plurality of first reset control signal line portions rst-1 and the plurality of second reset control signal line portions rst-2 are located in two different layers; and the plurality of first reset control signal line portions rst-1 and the plurality of third reset control signal line portions rst-3 are located in two different layers. Optionally, the plurality of second reset control signal line portions rst-2 and the plurality of third reset control signal line portions rst-3 are located in the same layer. In one example, the plurality of first reset control signal line portions rst-1 are located in a first conductive layer, the plurality of second reset control signal line portions rst-2 are located in a second signal line layer, and the plurality of third reset control signal line portions rst-3 are located in a second signal line layer. In some embodiments, the signal lines located in the second signal line layer are made of a substantially transparent conductive material. Within multiple light-transmitting regions TR, there are signal lines of a second signal line layer (e.g., multiple data lines, multiple first voltage supply line portions, multiple second voltage supply line portions, multiple second reset control signal line portions rst-2, and multiple third reset control signal line portions rst-3), but no signal lines or electrodes of the first conductive layer, second conductive layer, first signal line layer, third signal line layer, and anode layer. Because the signal lines of the second signal line layer are made of a substantially transparent conductive material, light can pass through the multiple light-transmitting regions TR.

[0235] In some embodiments, each of the plurality of second reset control signal line portions rst-2 is connected to two adjacent first reset control signal line portions rst-1. Each of the plurality of third reset control signal line portions rst-3 is connected to two adjacent first reset control signal line portions rst-1. Two adjacent first reset control signal line portions rst-1 are connected via individual second reset control signal line portions rst-2 and via individual third reset control signal line portions rst-3. The two adjacent first reset control signal line portions rst-1, the individual second reset control signal line portions rst-2, and the individual third reset control signal line portions rst-3 form a third ring, which substantially surrounds the region of the transistor and capacitor of the pixel driving circuit having sub-pixels. In one example, the third ring essentially surrounds the region with the transistor and capacitor corresponding to the first sub-pixel. In another example, the third ring essentially surrounds the region with the transistor and capacitor of the first color sub-pixel. In yet another example, the third ring essentially surrounds the region with the transistor and capacitor of the red sub-pixel.

[0236] In some embodiments, the array substrate includes a plurality of third rings LPS3 arranged in a row. Optionally, the plurality of third rings LPS3 respectively surround the region of the pixel driving circuit of a sub-pixel of the same color. Each of the plurality of third rings LPS3 surrounds the region of the pixel driving circuit of a sub-pixel of the same color. In one example, the plurality of third rings LPS3 surround the region of the pixel driving circuit of a red sub-pixel.

[0237] In some embodiments, the plurality of third rings LPS3 substantially surround the region of the anode of the sub-pixel having the same color. Each of the plurality of third rings LPS3 substantially surrounds the region of the anode of the sub-pixel having the same color. In one example, the plurality of third rings LPS3 substantially surround the region of the anode having a red sub-pixel.

[0238] Figure 13 This is a schematic diagram illustrating a reset control signal network in a portion of an array substrate according to some embodiments of the present disclosure. In some embodiments, reference is made to... Figure 13The subpixels in the array substrate are arranged in multiple rows and columns. In the m-th row of subpixels Rm, the array substrate includes a row of first subpixels. In the (m+1)-th row of subpixels R(m+1), the array substrate includes a row of third subpixels. In the (m+2)-th row of subpixels R(m+2), the array substrate includes a row of second subpixels. Optionally, a row of first subpixels is a row of subpixels of a first color, a row of second subpixels is a row of subpixels of a second color, and a row of third subpixels is a row of subpixels of a third color. Figure 13 The text represents the corresponding first sub-pixel sp1, the corresponding second sub-pixel sp2, and the corresponding third sub-pixel sp3.

[0239] In some embodiments, in the nth column of sub-pixels Cn, the array substrate includes a column of third sub-pixels. In the (n-1)th column of sub-pixels C(n-1), the array substrate includes a column of alternating first and second sub-pixels. In the (n+1)th column of sub-pixels C(n+1), the array substrate includes a column of alternating first and second sub-pixels. Optionally, the column of third sub-pixels is a column of sub-pixels of a third color, and the column of alternating first and second sub-pixels is a column of alternating first and second color sub-pixels. Optionally, in the nth column of sub-pixels Cn, each of the plurality of light-transmitting regions TR separates two adjacent third sub-pixels.

[0240] Reference Figure 2A , Figure 2B , Figures 3A to 3M , Figures 5A to 5M and Figure 13 In some embodiments, the first reset control signal line portion of the plurality of first reset control signal line portions rst-1 is connected to the gate of one or more reset control transistors in the pixel driving circuit of the third sub-pixel in the nth column sub-pixel Cn and the (m+1)th row sub-pixel R(m+1), connected to the gate of one or more reset control transistors in the pixel driving circuit of the first sub-pixel in the (n-1)th column sub-pixel C(n-1) and the mth row sub-pixel Rm, and connected to the gate of one or more reset control transistors in the pixel driving circuit of the second sub-pixel in the (n+1)th column sub-pixel C(n+1) and the (m+2)th row sub-pixel R(m+2).

[0241] In some embodiments, the second reset control signal line portion in the plurality of second reset control signal line portions rst-2 connects the first reset control signal line portion to the first adjacent first reset control signal line portion, and the first adjacent first reset control signal line portion is connected to the gate of one or more reset control transistors in the pixel driving circuit of the second sub-pixel in the (n-1)th column sub-pixel C(n-1) and the (m+2)th row sub-pixel R(m+2).

[0242] In some embodiments, the third reset control signal line portion of the plurality of third reset control signal line portions rst-3 connects the first reset control signal line portion to the second adjacent first reset control signal line portion, and the second adjacent first reset control signal line portion is connected to the gate of one or more reset control transistors in the pixel driving circuit of the first sub-pixel in the (n+1)th column sub-pixel C(n+1) and the mth row sub-pixel Rm.

[0243] Figure 14 This is a schematic diagram illustrating a light-emitting control signal network in a portion of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 5A , Figure 5C , Figure 5H and Figure 14 Each of the plurality of light-emitting control signal lines includes a plurality of first light-emitting control signal line portions em-1 and a plurality of second light-emitting control signal line portions em-2. The plurality of first light-emitting control signal line portions em-1 and the plurality of second light-emitting control signal line portions em-2 are located in two different layers. In one example, the plurality of first light-emitting control signal line portions em-1 are located in a first conductive layer, and the plurality of second light-emitting control signal line portions em-2 are located in a second signal line layer. Each second light-emitting control signal line portion in the plurality of second light-emitting control signal line portions em-2 is respectively connected to two adjacent first light-emitting control signal line portions in the plurality of first light-emitting control signal line portions em-1. Two adjacent first light-emitting control signal line portions in the plurality of first light-emitting control signal line portions em-1 are connected through individual second light-emitting control signal line portions in the plurality of second light-emitting control signal line portions em-2.

[0244] In some embodiments, each of the plurality of light-emitting control signal lines includes a plurality of first light-emitting control signal line portions em-1 and a plurality of third light-emitting control signal line portions em-3. The plurality of first light-emitting control signal line portions em-1 and the plurality of third light-emitting control signal line portions em-3 are located in two different layers. In one example, the plurality of first light-emitting control signal line portions em-1 are located in a first conductive layer, and the plurality of third light-emitting control signal line portions em-3 are located in a second signal line layer. Each third light-emitting control signal line portion em-3 is respectively connected to two adjacent first light-emitting control signal line portions em-1 in the same row. Two adjacent first light-emitting control signal line portions em-1 are connected through individual third light-emitting control signal line portions em-3.

[0245] In some embodiments, each of the plurality of light-emitting control signal lines includes a plurality of first light-emitting control signal line portions em-1, a plurality of second light-emitting control signal line portions em-2, and a plurality of third light-emitting control signal line portions em-3. The plurality of first light-emitting control signal line portions em-1 and the plurality of second light-emitting control signal line portions em-2 are located in two different layers; and the plurality of first light-emitting control signal line portions em-1 and the plurality of third light-emitting control signal line portions em-3 are located in two different layers. Optionally, the plurality of second light-emitting control signal line portions em-2 and the plurality of third light-emitting control signal line portions em-3 are located in the same layer. In one example, the plurality of first light-emitting control signal line portions em-1 are located in a first conductive layer, the plurality of second light-emitting control signal line portions em-2 are located in a second signal line layer, and the plurality of third light-emitting control signal line portions em-3 are located in a second signal line layer. In some embodiments, the signal lines located in the second signal line layer are made of a substantially transparent conductive material. Within multiple light-transmitting regions TR, there are signal lines of a second signal line layer (e.g., multiple data lines, multiple first voltage supply line portions, multiple second voltage supply line portions, multiple second light emission control signal line portions em-2, and multiple third light emission control signal line portions em-3), but no signal lines or electrodes of the first conductive layer, second conductive layer, first signal line layer, third signal line layer, and anode layer. Since the signal lines of the second signal line layer are made of a substantially transparent conductive material, light can pass through the multiple light-transmitting regions TR.

[0246] In some embodiments, each of the plurality of second light-emitting control signal line portions em-2 is connected to two adjacent first light-emitting control signal line portions em-1. Each of the plurality of third light-emitting control signal line portions em-3 is connected to two adjacent first light-emitting control signal line portions em-1. Two adjacent first light-emitting control signal line portions em-1 are connected via individual second light-emitting control signal line portions em-2 and via individual third light-emitting control signal line portions em-3. The two adjacent first light-emitting control signal line portions em-1, the individual second light-emitting control signal line portions em-2, and the individual third light-emitting control signal line portions em-3 form a fourth ring, which substantially surrounds the region of the transistor and capacitor of the pixel driving circuit having a sub-pixel. In one example, the fourth ring substantially surrounds the region of the transistor and capacitor having a corresponding first sub-pixel. In another example, the fourth ring essentially surrounds the area of ​​transistors and capacitors with the first color subpixel. In yet another example, the fourth ring essentially surrounds the area of ​​transistors and capacitors with the red subpixel.

[0247] In some embodiments, the array substrate includes a plurality of fourth rings LPS4 arranged in a row. Optionally, the plurality of fourth rings LPS4 respectively substantially surround the region of the pixel driving circuit of a sub-pixel of the same color. Each of the plurality of fourth rings LPS4 substantially surrounds the region of the pixel driving circuit of a sub-pixel of the same color. In one example, the plurality of fourth rings LPS4 substantially surround the region of the pixel driving circuit of a red sub-pixel.

[0248] In some embodiments, a plurality of fourth rings LPS4 substantially surround the region of the anode of a sub-pixel having the same color. Each of the plurality of fourth rings LPS4 substantially surrounds the region of the anode of a sub-pixel having the same color. In one example, the plurality of fourth rings LPS4 substantially surround the region of the anode having a red sub-pixel.

[0249] Figure 15 This is a schematic diagram illustrating a light-emitting control signal network in a portion of an array substrate according to some embodiments of the present disclosure. In some embodiments, reference is made to... Figure 15The subpixels in the array substrate are arranged in multiple rows and columns. In the m-th row of subpixels Rm, the array substrate includes a row of first subpixels. In the (m+1)-th row of subpixels R(m+1), the array substrate includes a row of third subpixels. In the (m+2)-th row of subpixels R(m+2), the array substrate includes a row of second subpixels. Optionally, a row of first subpixels is a row of subpixels of a first color, a row of second subpixels is a row of subpixels of a second color, and a row of third subpixels is a row of subpixels of a third color. Figure 15 The text represents the corresponding first sub-pixel sp1, the corresponding second sub-pixel sp2, and the corresponding third sub-pixel sp3.

[0250] In some embodiments, in the nth column of sub-pixels Cn, the array substrate includes a column of third sub-pixels. In the (n-1)th column of sub-pixels C(n-1), the array substrate includes a column of alternating first and second sub-pixels. In the (n+1)th column of sub-pixels C(n+1), the array substrate includes a column of alternating first and second sub-pixels. Optionally, the column of third sub-pixels is a column of sub-pixels of a third color, and the column of alternating first and second sub-pixels is a column of alternating first and second color sub-pixels. Optionally, in the nth column of sub-pixels Cn, each of the plurality of light-transmitting regions TR separates two adjacent third sub-pixels.

[0251] Reference Figure 2A , Figure 2B , Figures 3A to 3M , Figures 5A to 5M and Figure 15 In some embodiments, the first light emission control signal line portion em-1 of the plurality of first light emission control signal line portions is connected to the gate of one or more light emission control transistors in the pixel driving circuit of the third sub-pixel in the nth column sub-pixel Cn and the (m+1)th row sub-pixel R(m+1), connected to the gate of one or more light emission control transistors in the pixel driving circuit of the first sub-pixel in the (n-1)th column sub-pixel C(n-1) and the mth row sub-pixel Rm, and connected to the gate of one or more light emission control transistors in the pixel driving circuit of the second sub-pixel in the (n+1)th column sub-pixel C(n+1) and the (m+2)th row sub-pixel.

[0252] In some embodiments, the second light emission control signal line portion in the plurality of second light emission control signal line portions em-2 connects the first light emission control signal line portion to the first adjacent first light emission control signal line portion, and the first adjacent first light emission control signal line portion is connected to the gate of one or more light emission control transistors in the pixel driving circuit of the second sub-pixel in the (n-1)th column sub-pixel C(n-1) and the (m+2)th row sub-pixel R(m+2).

[0253] In some embodiments, the third light emission control signal line portion of the plurality of third light emission control signal line portions em-3 connects the first light emission control signal line portion to the second adjacent first light emission control signal line portion, and the second adjacent first light emission control signal line portion is connected to the gate of one or more light emission control transistors in the pixel driving circuit of the first sub-pixel in the (n+1)th column sub-pixel C(n+1) and the mth row sub-pixel Rm.

[0254] Reference Figure 5A , Figure 5C , Figure 5H as well as Figures 8 to 15 In some embodiments, the array substrate includes a plurality of signal lines, each of which includes a plurality of first signal line portions and a plurality of second signal line portions. The plurality of first signal line portions and the plurality of second signal line portions are located in two different layers. In one example, the plurality of first signal line portions are located in a first conductive layer, and the plurality of second signal line portions are located in a second signal line layer. In another example, the plurality of first signal line portions are located in a second conductive layer, and the plurality of second signal line portions are located in a second signal line layer. Each of the plurality of second signal line portions is respectively connected to two adjacent first signal line portions. Two adjacent first signal line portions are connected through individual second signal line portions.

[0255] In some embodiments, each of the plurality of signal lines includes a plurality of first signal line portions and a plurality of third signal line portions. The plurality of first signal line portions and the plurality of third signal line portions are located in two different layers. In one example, the plurality of first signal line portions are located in a first conductive layer, and the plurality of third signal line portions are located in a second signal line layer. In another example, the plurality of first signal line portions are located in a second conductive layer, and the plurality of third signal line portions are located in a second signal line layer. Each of the plurality of third signal line portions is respectively connected to two adjacent first signal line portions in the same row. Two adjacent first signal line portions are connected through a separate third signal line portion.

[0256] In some embodiments, each of the plurality of signal lines includes a plurality of first signal line portions, a plurality of second signal line portions, and a plurality of third signal line portions. The plurality of first signal line portions and the plurality of second signal line portions are located in two different layers; and the plurality of first signal line portions and the plurality of third signal line portions are located in two different layers. Optionally, the plurality of second signal line portions and the plurality of third signal line portions are located in the same layer. In one example, the plurality of first signal line portions are located in a first conductive layer, the plurality of second signal line portions are located in a second signal line layer, and the plurality of third signal line portions are located in a second signal line layer. In one example, the plurality of first signal line portions are located in a second conductive layer, the plurality of second signal line portions are located in a second signal line layer, and the plurality of third signal line portions are located in a second signal line layer. In some embodiments, the signal lines located in the second signal line layer are made of a substantially transparent conductive material. In the plurality of light-transmitting regions TR, signal lines of the second signal line layer are present, while signal lines and electrodes of the first conductive layer, the second conductive layer, the first signal line layer, the third signal line layer, and the anode layer are absent. Because the signal lines of the second signal line layer are made of a substantially transparent conductive material, light can pass through multiple light-transmitting areas TR.

[0257] In some embodiments, each of the plurality of second signal line portions is connected to two adjacent first signal line portions of the plurality of first signal line portions. Each of the plurality of third signal line portions is connected to two adjacent first signal line portions of the plurality of first signal line portions. Two adjacent first signal line portions of the plurality of first signal line portions are connected via individual second signal line portions of the plurality of second signal line portions and via individual third signal line portions of the plurality of third signal line portions. Two adjacent first signal line portions of the plurality of first signal line portions, individual second signal line portions of the plurality of second signal line portions, and individual third signal line portions of the plurality of third signal line portions form a loop that substantially surrounds the region of the transistor and capacitor of the pixel driving circuit having a sub-pixel. In one example, the loop substantially surrounds the region of the transistor and capacitor having a corresponding first sub-pixel. In another example, the loop substantially surrounds the region of the transistor and capacitor having a sub-pixel of a first color. In yet another example, the loop substantially surrounds the region of the transistor and capacitor having a red sub-pixel.

[0258] In some embodiments, the array substrate includes a plurality of rings arranged in a row. Optionally, the plurality of rings respectively surround a region of pixel driving circuitry for a sub-pixel of the same color. Each ring in the plurality of rings surrounds a region of pixel driving circuitry for a sub-pixel of the same color. In one example, the plurality of rings surround a region of pixel driving circuitry for a red sub-pixel.

[0259] In some embodiments, the plurality of rings substantially surround the region of the anode of a sub-pixel having the same color. Each of the plurality of rings substantially surrounds the region of the anode of a sub-pixel having the same color. In one example, the plurality of rings substantially surround the region of the anode having a red sub-pixel.

[0260] In some embodiments, the subpixels in the array substrate are arranged in multiple rows and columns. In the m-th row of subpixels Rm, the array substrate includes a row of first subpixels. In the (m+1)-th row of subpixels R(m+1), the array substrate includes a row of third subpixels. In the (m+2)-th row of subpixels R(m+2), the array substrate includes a row of second subpixels. Optionally, a row of first subpixels is a row of subpixels of a first color, a row of second subpixels is a row of subpixels of a second color, and a row of third subpixels is a row of subpixels of a third color. The first color, the second color, and the third color are three different colors. In one example, the first color is red, the second color is green, and the third color is blue.

[0261] In some embodiments, in the nth column of sub-pixels Cn, the array substrate includes a column of third sub-pixels. In the (n-1)th column of sub-pixels C(n-1), the array substrate includes a column of alternating first and second sub-pixels. In the (n+1)th column of sub-pixels C(n+1), the array substrate includes a column of alternating first and second sub-pixels. Optionally, the column of third sub-pixels is a column of sub-pixels of a third color, and the column of alternating first and second sub-pixels is a column of alternating first and second color sub-pixels. Optionally, in the nth column of sub-pixels Cn, each of the plurality of light-transmitting regions TR separates two adjacent third sub-pixels.

[0262] Reference Figure 2A , Figure 2B , Figures 3A to 3M , Figures 5A to 5M as well as Figures 8 to 15 In some embodiments, a first signal line portion of a plurality of first signal line portions is connected to one or more transistors in the pixel driving circuit of the third sub-pixel in the nth column sub-pixel Cn and the (m+1)th row sub-pixel R(m+1), connected to one or more transistors in the pixel driving circuit of the first sub-pixel in the (n-1)th column sub-pixel C(n-1) and the mth row sub-pixel Rm, and connected to one or more transistors in the pixel driving circuit of the second sub-pixel in the (n+1)th column sub-pixel C(n+1) and the (m+2)th row sub-pixel R(m+2).

[0263] In some embodiments, a second signal line portion of a plurality of second signal line portions connects a first signal line portion to a first adjacent first signal line portion, and the first adjacent first signal line portion is connected to one or more transistors in the pixel driving circuit of the second sub-pixel in the (n-1)th column sub-pixel C(n-1) and the (m+2)th row sub-pixel R(m+2).

[0264] In some embodiments, a third signal line portion of a plurality of third signal line portions is connected to a first signal line portion and a second adjacent first signal line portion, and the second adjacent first signal line portion is connected to one or more transistors in the pixel driving circuit of the first sub-pixel in the (n+1)th column sub-pixel C(n+1) and the mth row sub-pixel Rm.

[0265] Figure 16A This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure. Figure 16B It is shown Figure 16A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate. Figure 16C It is shown Figure 16A A schematic diagram of the structure of the first conductive layer in a portion of the array substrate depicted in the figure. Figure 16D It is shown Figure 16A A schematic diagram of the structure of the second conductive layer in a portion of the array substrate depicted in the figure. Figure 16E It is shown Figure 16A A schematic diagram of the structure of the interlayer dielectric layer in a portion of the array substrate depicted in the figure. Figure 16F It is shown Figure 16A A schematic diagram of the structure of the first signal line layer in a portion of the array substrate depicted in the figure. Figure 16G It is shown Figure 16A A schematic diagram of the structure of the passivation layer in a portion of the array substrate depicted in the figure. Figure 16H It is shown Figure 16A A schematic diagram of the structure of the second signal line layer in a portion of the array substrate depicted in the figure. Figure 16I It is shown Figure 16A A schematic diagram of the structure of the first planarization layer in a portion of the array substrate depicted in the figure. Figure 16J It is shown Figure 16A A schematic diagram of the structure of the third signal line layer in a portion of the array substrate described herein. Figure 16K It is shown Figure 16A A schematic diagram of the structure of the second planarization layer in a portion of the array substrate depicted in the figure. Figure 16L It is shown Figure 16A A schematic diagram of the structure of the anode layer in a portion of the array substrate depicted in the diagram. Figure 16M It is shown Figure 16AA schematic diagram of the structure of the pixel-defining layer in a portion of the array substrate.

[0266] Figure 17A This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure. Figure 17B It is shown Figure 17A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate. Figure 17C It is shown Figure 17A A schematic diagram of the structure of the first conductive layer in a portion of the array substrate depicted in the figure. Figure 17D It is shown Figure 17A A schematic diagram of the structure of the second conductive layer in a portion of the array substrate depicted in the figure. Figure 17E It is shown Figure 17A A schematic diagram of the structure of the interlayer dielectric layer in a portion of the array substrate depicted in the figure. Figure 17F It is shown Figure 17A A schematic diagram of the structure of the first signal line layer in a portion of the array substrate depicted in the figure. Figure 17G It is shown Figure 17A A schematic diagram of the structure of the passivation layer in a portion of the array substrate depicted in the figure. Figure 17H It is shown Figure 17A A schematic diagram of the structure of the second signal line layer in a portion of the array substrate depicted in the figure. Figure 17I It is shown Figure 17A A schematic diagram of the structure of the first planarization layer in a portion of the array substrate depicted in the figure. Figure 17J It is shown Figure 17A A schematic diagram of the structure of the third signal line layer in a portion of the array substrate depicted in the figure. Figure 17K It is shown Figure 17A A schematic diagram of the structure of the second planarization layer in a portion of the array substrate depicted in the figure. Figure 17L It is shown Figure 17A A schematic diagram of the structure of the anode layer in a portion of the array substrate depicted in the diagram. Figure 17M It is shown Figure 17A A schematic diagram of the structure of the pixel-defining layer in a portion of the array substrate depicted in the figure.

[0267] Figures 16A to 16M and Figures 17A to 17M The array substrate depicted in the image and Figures 3A to 3M and Figures 5A to 5M The difference between the array substrates depicted in the text is that... Figures 16A to 16M and Figures 17A to 17M The extension directions of the multiple initialization signal lines, multiple reset control signal lines, multiple gate signal lines, and multiple light emission control signal lines in the array substrate depicted are similar to those of the array substrate. Figures 3A to 3M and Figures 5A to 5MThe multiple initialization signal lines, multiple reset control signal lines, multiple gate signal lines, and multiple light emission control signal lines in the array substrate depicted in the figure extend in different directions.

[0268] Reference Figure 2A , Figure 2B , Figure 16A and Figure 16B The corresponding pixel driving circuits are labeled with numbers, which represent regions corresponding to multiple transistors (including first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, and driving transistor Td) in the corresponding pixel driving circuit. The corresponding pixel driving circuits are also labeled with numbers representing components of each of the multiple transistors in the pixel driving circuit. For example, first transistor T1 includes an active layer ACT1, a first electrode S1, and a second electrode D1. Second transistor T2 includes an active layer ACT2, a first electrode S2, and a second electrode D2. Third transistor T3 includes an active layer ACT3, a first electrode S3, and a second electrode D3. Fourth transistor T4 includes an active layer ACT4, a first electrode S4, and a second electrode D4. Fifth transistor T5 includes an active layer ACT5, a first electrode S5, and a second electrode D5. Sixth transistor T6 includes an active layer ACT6, a first electrode S6, and a second electrode D6. Driving transistor Td includes an active layer ACTd, a first electrode Sd, and a second electrode Dd.

[0269] Reference Figure 2A , Figure 2B , Figure 16A and Figure 16C In some embodiments, the first conductive layer includes a plurality of reset control signal lines rst, a plurality of light emission control signal lines em, a plurality of gate signal lines GL, and a first capacitor electrode Ce1 of the storage capacitor Cst.

[0270] Reference Figure 2A , Figure 2B , Figure 16A and Figure 16D In some embodiments, the second conductive layer includes a plurality of initialization signal lines Vint and a second capacitor electrode Ce2 for storing capacitor Cst.

[0271] Figure 16E The image depicts vias extending through the interlayer dielectric layer (ILD).

[0272] Reference Figure 2A , Figure 2B , Figure 16A and Figure 16F In some embodiments, the first signal line layer includes node connection line Cln, voltage connection pad VCP, data signal connection pad DCP, electrode connection line Cle, and reset signal connection line Cli.

[0273] Node connection line Cln connects the first capacitor electrode Ce1 to the second electrode of the third transistor T3 and / or the second electrode of the first transistor T1 in the corresponding pixel driving circuit. Data signal connection pad DCP connects the corresponding data line among the multiple data lines to the first electrode of the second transistor T2. Reset signal connection line Cli connects the corresponding initialization signal line among the multiple initialization signal lines to the first electrodes of the first transistor T1 and the sixth transistor T6. Voltage connection pad VCP connects the corresponding voltage supply line among the multiple voltage supply lines to the first electrode of the fourth transistor T4, and also connects the corresponding voltage supply line among the multiple voltage supply lines to the second capacitor electrode of the storage capacitor. Electrode connection line Cle connects to the second electrodes of the fifth transistor T5 and the sixth transistor T6, respectively.

[0274] Figure 16G The image depicts vias extending through the passivation layer PVX.

[0275] Reference Figure 2A , Figure 2B , Figure 16A and Figure 16H In some embodiments, the second signal line layer includes a plurality of voltage supply lines Vdd and a plurality of data lines DL. Each of the plurality of voltage supply lines Vdd includes a plurality of alternating first voltage supply line portions Vdd-1 and a plurality of second voltage supply line portions Vdd-2. Each first voltage supply line portion in the plurality of first voltage supply line portions Vdd-1 and a corresponding second voltage supply line portion in the plurality of second voltage supply line portions Vdd-2 are connected by a voltage connection bridge located in the third signal line layer. Each of the plurality of data lines is electrically connected to the first electrode of the second transistor T2 via a data signal connection pad located in the first signal line layer.

[0276] Figure 16I The image depicts vias extending through the first planarization layer PLN1.

[0277] Reference Figure 2A , Figure 2B , Figure 16A and Figure 16J In some embodiments, the third signal line layer includes a voltage connection bridge (VCB) and an anode connection pad (ACP). The VCB connects a first voltage supply line portion located in the second signal line layer and a second voltage supply line portion located in the second signal line layer. The anode connection pad (ACP) is connected to the fourth node N4 and the corresponding anode in the corresponding sub-pixel, respectively. The anode connection pad (ACP) is connected to the second electrodes of the fifth transistor T5 and the sixth transistor T6, and the corresponding anode in the corresponding sub-pixel is connected to the anode connection pad (ACP).

[0278] Figure 16K The image depicts vias extending through the second planarization layer PLN2.

[0279] Reference Figure 2A , Figure 2B , Figure 16A and Figure 16L In some embodiments, the anode layer includes the anode of the corresponding light-emitting element. The anode is connected to an anode connection pad in the third signal line layer, and the anode connection pad is connected to the second electrode of the fifth transistor T5 and the sixth transistor T6.

[0280] Figure 16M The image depicts a via extending through the pixel-defined layer (PDL). (See reference...) Figure 16M The array substrate includes sub-pixel openings SA configured to accommodate light-emitting material.

[0281] In some embodiments, refer to Figure 17A The smallest repeating unit of multiple sub-pixels of the array substrate includes a corresponding first sub-pixel sp1, a corresponding second sub-pixel sp2, and a corresponding third sub-pixel sp3. Figure 16A A portion of the array substrate depicted corresponds to Figure 17A A portion of the corresponding third sub-pixel sp3 depicted in the image.

[0282] In some embodiments, each of the corresponding first sub-pixel sp1, the corresponding second sub-pixel sp2, and the corresponding third sub-pixel sp3 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a driving transistor Td, and a storage capacitor Cst.

[0283] In some embodiments, the corresponding first sub-pixel sp1 is a sub-pixel of a first color (e.g., red), the corresponding second sub-pixel sp2 is a sub-pixel of a second color (e.g., green), and the corresponding third sub-pixel sp3 is a sub-pixel of a third color (e.g., blue). In some embodiments, the corresponding first sub-pixel sp1, the corresponding second sub-pixel sp2, and the corresponding third sub-pixel sp3 are three sub-pixels of a pixel in an array substrate.

[0284] Reference Figure 17A , Figure 17H and Figure 17J In some embodiments, each of the plurality of voltage supply lines Vdd includes a plurality of first voltage supply line portions Vdd-1 and a plurality of second voltage supply line portions Vdd-2 arranged alternately in a second signal line layer. The respective first voltage supply line portions in the plurality of first voltage supply line portions Vdd-1 and the corresponding second voltage supply line portions in the plurality of second voltage supply lines Vdd-2 are connected via a voltage connection bridge VCB in a third signal line layer.

[0285] Figure 18 This is a schematic diagram illustrating a voltage supply network in a portion of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 17A , Figure 17H , Figure 17J and Figure 18 In some embodiments, the array substrate includes multiple voltage connection bridges (VCBS). Optionally, the multiple VCBS are arranged in a multi-row and multi-column array. Multiple voltage supply lines Vdd include a first adjacent voltage supply line AVdd1, a second adjacent voltage supply line AVdd2, and a third adjacent voltage supply line AVdd3. Optionally, the first adjacent voltage supply line AVdd1 is configured to provide a voltage supply signal to a first pixel driving circuit in a corresponding first sub-pixel Sp1, the second adjacent voltage supply line AVdd2 is configured to provide a voltage supply signal to a second pixel driving circuit in a corresponding second sub-pixel Sp2, and the third adjacent voltage supply line AVdd3 is configured to provide a voltage supply signal to a third pixel driving circuit in a corresponding third sub-pixel Sp3.

[0286] In some embodiments, each voltage bridge in the plurality of voltage bridges VCBS is connected to a first adjacent voltage supply line AVdd1, a second adjacent voltage supply line AVdd2, and a third adjacent voltage supply line AVdd3, respectively.

[0287] In some embodiments, each of the first adjacent voltage supply line AVdd1, the second adjacent voltage supply line AVdd2, and the third adjacent voltage supply line AVdd3 includes a plurality of first voltage supply line portions Vdd-1 and a plurality of second voltage supply line portions Vdd-2 alternately arranged in the second signal line layer. In some embodiments, each voltage connection bridge in the plurality of voltage connection bridges VCBS is respectively connected to the first adjacent voltage supply line portion AVdd-1 and the second adjacent voltage supply line portion AVdd-2 of the first adjacent voltage supply line AVdd1, respectively connected to the first adjacent voltage supply line portion AVdd-1 and the second adjacent voltage supply line portion AVdd-2 of the second adjacent voltage supply line AVdd2, and respectively connected to the first adjacent voltage supply line portion AVdd-1 and the second adjacent voltage supply line portion AVdd-2 of the third adjacent voltage supply line AVdd3.

[0288] In some embodiments, multiple voltage supply lines (including a first adjacent voltage supply line AVdd1, a second adjacent voltage supply line AVdd2, and a third adjacent voltage supply line AVdd3) are located in a second signal line layer, and multiple voltage connection bridges VCBS are located in a third signal line layer.

[0289] In some embodiments, the signal lines located in the second signal line layer are made of a substantially transparent conductive material, thereby allowing multiple light-transmitting areas to exist in the array substrate. Figure 19 This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 19 In some embodiments, the array substrate includes multiple light-transmitting regions TR that allow light to pass through. Within the multiple light-transmitting regions TR, signal lines of a second signal line layer (e.g., multiple data lines, multiple first voltage supply line portions, and multiple second voltage supply line portions) are present, while signal lines and electrodes of the first conductive layer, second conductive layer, first signal line layer, third signal line layer, and anode layer are absent. Because the signal lines of the second signal line layer are made of a substantially transparent conductive material, light can pass through the multiple light-transmitting regions TR.

[0290] In some embodiments, two adjacent voltage connection bridges in a plurality of voltage connection bridges in the same pixel row VCBS are connected to the same voltage supply line in a plurality of voltage supply lines, such as Figure 18 As depicted. Reference Figure 9 In some embodiments, a pixel row includes a row m sub-pixel Rm, a row (m+1) sub-pixel R(m+1), and a row (m+2) sub-pixel R(m+2).

[0291] In some embodiments, the voltage connection bridges in the VCBS of multiple voltage connection bridges in the same pixel column are connected to the same three adjacent voltage supply lines of multiple voltage supply lines. (See reference...) Figure 9 In some embodiments, the pixel column includes the nth column sub-pixel Cn, the (n-1)th column sub-pixel C(n-1), and the (n+1)th column sub-pixel C(n+1).

[0292] In some embodiments, the array substrate is a full-display (FDC) array substrate with a camera, wherein the array substrate further includes photoelectric sensors located in a plurality of light-transmitting regions TR configured to detect light.

[0293] Figure 20 This is a schematic diagram illustrating a reset signal network in a portion of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 17A , Figure 17D , Figure 17H and Figure 20Each of the multiple initialization signal lines includes multiple first initialization signal line portions Vint-1 and multiple second initialization signal line portions Vint-2. The multiple first initialization signal line portions Vint-1 and the multiple second initialization signal line portions Vint-2 are located in two different layers. In one example, the multiple first initialization signal line portions Vint-1 are located in a second conductive layer, while the multiple second initialization signal line portions Vint-2 are located in a second signal line layer. Each second initialization signal line portion in the multiple second initialization signal line portions Vint-2 is connected to two adjacent first initialization signal line portions in the multiple first initialization signal line portions Vint-1. Two adjacent first initialization signal line portions in the multiple first initialization signal line portions Vint-1 are connected through individual second initialization signal line portions in the multiple second initialization signal line portions Vint-2.

[0294] In some embodiments, each of the plurality of initialization signal lines includes a plurality of first initialization signal line portions Vint-1 and a plurality of third initialization signal line portions Vint-3. The plurality of first initialization signal line portions Vint-1 and the plurality of third initialization signal line portions Vint-3 are located in two different layers. In one example, the plurality of first initialization signal line portions Vint-1 are located in a second conductive layer, while the plurality of third initialization signal line portions Vint-3 are located in a second signal line layer. Each third initialization signal line portion in the plurality of third initialization signal line portions Vint-3 is respectively connected to two adjacent first initialization signal line portions in the plurality of first initialization signal line portions Vint-1 in the same row. Two adjacent first initialization signal line portions in the plurality of first initialization signal line portions Vint-1 are connected through individual third initialization signal line portions in the plurality of third initialization signal line portions Vint-3.

[0295] In some embodiments, each of the plurality of initialization signal lines includes a plurality of first initialization signal line portions Vint-1, a plurality of second initialization signal line portions Vint-2, and a plurality of third initialization signal line portions Vint-3. The plurality of first initialization signal line portions Vint-1 and the plurality of second initialization signal line portions Vint-2 are located in two different layers; and the plurality of first initialization signal line portions Vint-1 and the plurality of third initialization signal line portions Vint-3 are located in two different layers. Optionally, the plurality of second initialization signal line portions Vint-2 and the plurality of third initialization signal line portions Vint-3 are located in the same layer. In one example, the plurality of first initialization signal line portions Vint-1 are located in a second conductive layer, the plurality of second initialization signal line portions Vint-2 are located in a second signal line layer, and the plurality of third initialization signal line portions Vint-3 are located in a second signal line layer. In some embodiments, the signal lines located in the second signal line layer are made of a substantially transparent conductive material. Within multiple light-transmitting regions TR, there are signal lines of a second signal line layer (e.g., multiple data lines, multiple first voltage supply line portions, multiple second voltage supply line portions, multiple second initialization signal line portions Vint-2, and multiple third initialization signal line portions Vint-3), but no signal lines or electrodes of the first conductive layer, second conductive layer, first signal line layer, third signal line layer, and anode layer. Since the signal lines of the second signal line layer are made of a substantially transparent conductive material, light can pass through the multiple light-transmitting regions TR.

[0296] In some embodiments, each of the plurality of second initialization signal line portions Vint-2 is connected to two adjacent first initialization signal line portions Vint-1. Each of the plurality of third initialization signal line portions Vint-3 is connected to two adjacent first initialization signal line portions Vint-1. Two adjacent first initialization signal line portions in Vint-1 are connected via individual second initialization signal line portions in Vint-2 and via individual third initialization signal line portions in Vint-3. The two adjacent first initialization signal line portions in Vint-1, the individual second initialization signal line portions in Vint-2, and the individual third initialization signal line portions in Vint-3 form a first ring that substantially surrounds the region of the transistor and capacitor of the pixel driving circuit having a sub-pixel. In one example, the first ring substantially surrounds the region of the transistor and capacitor having a corresponding first sub-pixel. In another example, the first ring essentially surrounds the region of transistors and capacitors with subpixels of the first color. In yet another example, the first ring essentially surrounds the region of transistors and capacitors with red subpixels.

[0297] In some embodiments, the array substrate includes a plurality of first rings LPS1 arranged in a row. Optionally, the plurality of first rings LPS1 respectively substantially surround the region of the pixel driving circuit of a sub-pixel of the same color. Each of the plurality of first rings LPS1 substantially surrounds the region of the pixel driving circuit of a sub-pixel of the same color. In one example, the plurality of first rings LPS1 substantially surround the region of the pixel driving circuit of a red sub-pixel.

[0298] In some embodiments, a plurality of first rings LPS1 substantially surround the region of the anode of a sub-pixel having the same color. Each of the plurality of first rings LPS1 substantially surrounds the region of the anode of a sub-pixel having the same color. In one example, the plurality of first rings LPS1 substantially surround the region of the anode having a red sub-pixel.

[0299] Figure 21 This is a schematic diagram illustrating a reset signal network in a portion of an array substrate according to some embodiments of the present disclosure. In some embodiments, reference is made to... Figure 21The subpixels in the array substrate are arranged in multiple rows and columns. In the m-th row of subpixels Rm, the array substrate includes a row of first subpixels. In the (m+1)-th row of subpixels R(m+1), the array substrate includes a row of third subpixels. In the (m+2)-th row of subpixels R(m+2), the array substrate includes a row of second subpixels. Optionally, a row of first subpixels is a row of subpixels of a first color, a row of second subpixels is a row of subpixels of a second color, and a row of third subpixels is a row of subpixels of a third color. Figure 21 The text represents the corresponding first sub-pixel sp1, the corresponding second sub-pixel sp2, and the corresponding third sub-pixel sp3.

[0300] In some embodiments, in the nth column of sub-pixels Cn, the array substrate includes a column of third sub-pixels. In the (n-1)th column of sub-pixels C(n-1), the array substrate includes a column of alternating first and second sub-pixels. In the (n+1)th column of sub-pixels C(n+1), the array substrate includes a column of alternating first and second sub-pixels. Optionally, the column of third sub-pixels is a column of sub-pixels of a third color, and the column of alternating first and second sub-pixels is a column of alternating first and second color sub-pixels. Optionally, in the nth column of sub-pixels Cn, each of the plurality of light-transmitting regions TR separates two adjacent third sub-pixels.

[0301] Reference Figure 2A , Figure 2B , Figures 16A to 16M , Figures 17A to 17M and Figure 21 In some embodiments, the first initialization signal line portion of the plurality of first initialization signal line portions Vint-1 is connected to the first electrode of one or more reset transistors in the pixel driving circuit of the third sub-pixel in the nth column sub-pixel Cn and the (m+1)th row sub-pixel R(m+1), connected to the first electrode of one or more reset transistors in the pixel driving circuit of the second sub-pixel in the (n-1)th column sub-pixel C(n-1) and the (m+2)th row sub-pixel R(m+2), and connected to the first electrode of one or more reset transistors in the pixel driving circuit of the first sub-pixel in the (n+1)th column sub-pixel C(n+1) and the mth row sub-pixel Rm.

[0302] In some embodiments, the second initialization signal line portion of the plurality of second initialization signal line portions Vint-2 connects the first initialization signal line portion to the first adjacent first initialization signal line portion, and the first adjacent first initialization signal line portion is connected to the first electrode of one or more reset transistors in the pixel driving circuit of the first sub-pixel in the (n-1)th column sub-pixel C(n-1) and the first sub-pixel in the mth row sub-pixel Rm.

[0303] In some embodiments, the third initialization signal line portion of the plurality of third initialization signal line portions Vint-3 connects the first initialization signal line portion to the second adjacent first initialization signal line portion, and the second adjacent first initialization signal line portion is connected to the first electrode of one or more reset transistors in the pixel driving circuit of the second sub-pixel in the (n+1)th column sub-pixel C(n+1) and the (m+2)th row sub-pixel R(m+2).

[0304] Figure 22 This is a schematic diagram illustrating a gate scan signal network in a portion of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 17A , Figure 17C , Figure 17H and Figure 22 Each of the plurality of gate signal lines includes a plurality of first gate signal line portions GL-1 and a plurality of second gate signal line portions GL-2. The plurality of first gate signal line portions GL-1 and the plurality of second gate signal line portions GL-2 are located in two different layers. In one example, the plurality of first gate signal line portions GL-1 are located in a first conductive layer, and the plurality of second gate signal line portions GL-2 are located in a second signal line layer. Each second gate signal line portion in the plurality of second gate signal line portions GL-2 is connected to two adjacent first gate signal line portions in the plurality of first gate signal line portions GL-1. Two adjacent first gate signal line portions in the plurality of first gate signal line portions GL-1 are connected through individual second gate signal line portions in the plurality of second gate signal line portions GL-2.

[0305] In some embodiments, each of the plurality of gate signal lines includes a plurality of first gate signal line portions GL-1 and a plurality of third gate signal line portions GL-3. The plurality of first gate signal line portions GL-1 and the plurality of third gate signal line portions GL-3 are located in two different layers. In one example, the plurality of first gate signal line portions GL-1 are located in a first conductive layer, and the plurality of third gate signal line portions GL-3 are located in a second signal line layer. Each third gate signal line portion in the plurality of third gate signal line portions GL-3 is respectively connected to two adjacent first gate signal line portions in the plurality of first gate signal line portions GL-1 in the same row. Two adjacent first gate signal line portions in the plurality of first gate signal line portions GL-1 are connected through separate third gate signal line portions in the plurality of third gate signal line portions GL-3.

[0306] In some embodiments, each of the plurality of gate signal lines includes a plurality of first gate signal line portions GL-1, a plurality of second gate signal line portions GL-2, and a plurality of third gate signal line portions GL-3. The plurality of first gate signal line portions GL-1 and the plurality of second gate signal line portions GL-2 are located in two different layers; and the plurality of first gate signal line portions GL-1 and the plurality of third gate signal line portions GL-3 are located in two different layers. Optionally, the plurality of second gate signal line portions GL-2 and the plurality of third gate signal line portions GL-3 are located in the same layer. In one example, the plurality of first gate signal line portions GL-1 are located in a first conductive layer, the plurality of second gate signal line portions GL-2 are located in a second signal line layer, and the plurality of third gate signal line portions GL-3 are located in a second signal line layer. In some embodiments, the signal lines located in the second signal line layer are made of a substantially transparent conductive material. Within multiple light-transmitting regions TR, there are signal lines of a second signal line layer (e.g., multiple data lines, multiple first voltage supply line portions, multiple second voltage supply line portions, multiple second gate signal line portions GL-2, and multiple third gate signal line portions GL-3), but no signal lines or electrodes of the first conductive layer, second conductive layer, first signal line layer, third signal line layer, and anode layer. Since the signal lines of the second signal line layer are made of a substantially transparent conductive material, light can pass through the multiple light-transmitting regions TR.

[0307] In some embodiments, each of the plurality of second gate signal line portions GL-2 is connected to two adjacent first gate signal line portions GL-1. Each of the plurality of third gate signal line portions GL-3 is connected to two adjacent first gate signal line portions GL-1. Two adjacent first gate signal line portions in GL-1 are connected via individual second gate signal line portions in GL-2 and via individual third gate signal line portions in GL-3. Two adjacent first gate signal line portions in GL-1, individual second gate signal line portions in GL-2, and individual third gate signal line portions in GL-3 form a second ring that substantially surrounds the region of the transistor and capacitor of the pixel driving circuit having a sub-pixel. In one example, the second ring substantially surrounds the region of the transistor and capacitor having a corresponding first sub-pixel. In another example, the second ring substantially surrounds the region of the transistor and capacitor having a sub-pixel of a first color. In another example, the second ring essentially surrounds the area containing transistors and capacitors with red subpixels.

[0308] In some embodiments, the array substrate includes a plurality of second rings LPS2 arranged in a row. Optionally, the plurality of second rings LPS2 respectively substantially surround the region of the pixel driving circuitry of a sub-pixel of the same color. Each of the plurality of second rings LPS2 substantially surrounds the region of the pixel driving circuitry of a sub-pixel of the same color. In one example, the plurality of second rings LPS2 substantially surround the region of the pixel driving circuitry of a red sub-pixel.

[0309] In some embodiments, a plurality of second rings LPS2 substantially surround the region of the anode of a sub-pixel having the same color. Each of the plurality of second rings LPS2 substantially surrounds the region of the anode of a sub-pixel having the same color. In one example, the plurality of second rings LPS2 substantially surround the region of the anode having a red sub-pixel.

[0310] Figure 23 This is a schematic diagram illustrating a gate scan signal network in a portion of an array substrate according to some embodiments of the present disclosure. In some embodiments, reference is made to... Figure 23 The subpixels in the array substrate are arranged in multiple rows and columns. In the m-th row of subpixels Rm, the array substrate includes a row of first subpixels. In the (m+1)-th row of subpixels R(m+1), the array substrate includes a row of third subpixels. In the (m+2)-th row of subpixels R(m+2), the array substrate includes a row of second subpixels. Optionally, a row of first subpixels is a row of subpixels of a first color, a row of second subpixels is a row of subpixels of a second color, and a row of third subpixels is a row of subpixels of a third color. Figure 23 The text represents the corresponding first sub-pixel sp1, the corresponding second sub-pixel sp2, and the corresponding third sub-pixel sp3.

[0311] In some embodiments, in the nth column of sub-pixels Cn, the array substrate includes a column of third sub-pixels. In the (n-1)th column of sub-pixels C(n-1), the array substrate includes a column of alternating first and second sub-pixels. In the (n+1)th column of sub-pixels C(n+1), the array substrate includes a column of alternating first and second sub-pixels. Optionally, the column of third sub-pixels is a column of sub-pixels of a third color, and the column of alternating first and second sub-pixels is a column of alternating first and second color sub-pixels. Optionally, in the nth column of sub-pixels Cn, each of the plurality of light-transmitting regions TR separates two adjacent third sub-pixels.

[0312] Reference Figure 2A , Figure 2B , Figures 16A to 16M , Figures 17A to 17M and Figure 23In some embodiments, the first gate signal line portion of the plurality of first gate signal line portions GL-1 is connected to the gate of one or more data write transistors in the pixel driving circuit of the third sub-pixel in the nth column sub-pixel Cn and the (m+1)th row sub-pixel R(m+1), connected to the gate of one or more data write transistors in the pixel driving circuit of the second sub-pixel in the (n-1)th column sub-pixel C(n-1) and the (m+2)th row sub-pixel R(m+2), and connected to the gate of one or more data write transistors in the pixel driving circuit of the first sub-pixel in the (n+1)th column sub-pixel C(n+1) and the mth row sub-pixel Rm.

[0313] In some embodiments, the second gate signal line portion GL-2 of the plurality of second gate signal line portions GL-2 connects the first gate signal line portion to the first adjacent first gate signal line portion, and the first adjacent first gate signal line portion is connected to the gate of one or more data writing transistors in the pixel driving circuit of the first sub-pixel in the (n-1)th column sub-pixel C(n-1) and the first sub-pixel in the mth row sub-pixel Rm.

[0314] In some embodiments, the third gate signal line portion GL-3 of the plurality of third gate signal line portions GL-3 connects the first gate signal line portion and the second adjacent first gate signal line portion, and the second adjacent first gate signal line portion is connected to the gate of one or more data writing transistors in the pixel driving circuit of the second sub-pixel in the (n+1)th column sub-pixel C(n+1) and the (m+2)th row sub-pixel R(m+2).

[0315] Figure 24 This is a schematic diagram illustrating a reset control signal network in a portion of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 17A , Figure 17C , Figure 17H and Figure 24Each of the plurality of reset control signal lines includes a plurality of first reset control signal line portions rst-1 and a plurality of second reset control signal line portions rst-2. The plurality of first reset control signal line portions rst-1 and the plurality of second reset control signal line portions rst-2 are located in two different layers. In one example, the plurality of first reset control signal line portions rst-1 are located in a first conductive layer, and the plurality of second reset control signal line portions rst-2 are located in a second signal line layer. Each second reset control signal line portion in the plurality of second reset control signal line portions rst-2 is respectively connected to two adjacent first reset control signal line portions in the plurality of first reset control signal line portions rst-1. Two adjacent first reset control signal line portions in the plurality of first reset control signal line portions rst-1 are connected through individual second reset control signal line portions in the plurality of second reset control signal line portions rst-2.

[0316] In some embodiments, each of the plurality of reset control signal lines includes a plurality of first reset control signal line portions rst-1 and a plurality of third reset control signal line portions rst-3. The plurality of first reset control signal line portions rst-1 and the plurality of third reset control signal line portions rst-3 are located in two different layers. In one example, the plurality of first reset control signal line portions rst-1 are located in a first conductive layer, and the plurality of third reset control signal line portions rst-3 are located in a second signal line layer. Each third reset control signal line portion in the plurality of third reset control signal line portions rst-3 is respectively connected to two adjacent first reset control signal line portions rst-1 in the same row. Two adjacent first reset control signal line portions rst-1 are connected through individual third reset control signal line portions rst-3.

[0317] In some embodiments, each of the plurality of reset control signal lines includes a plurality of first reset control signal line portions rst-1, a plurality of second reset control signal line portions rst-2, and a plurality of third reset control signal line portions rst-3. The plurality of first reset control signal line portions rst-1 and the plurality of second reset control signal line portions rst-2 are located in two different layers; and the plurality of first reset control signal line portions rst-1 and the plurality of third reset control signal line portions rst-3 are located in two different layers. Optionally, the plurality of second reset control signal line portions rst-2 and the plurality of third reset control signal line portions rst-3 are located in the same layer. In one example, the plurality of first reset control signal line portions rst-1 are located in a first conductive layer, the plurality of second reset control signal line portions rst-2 are located in a second signal line layer, and the plurality of third reset control signal line portions rst-3 are located in a second signal line layer. In some embodiments, the signal lines located in the second signal line layer are made of a substantially transparent conductive material. Within multiple light-transmitting regions TR, there are signal lines of a second signal line layer (e.g., multiple data lines, multiple first voltage supply line portions, multiple second voltage supply line portions, multiple second reset control signal line portions rst-2, and multiple third reset control signal line portions rst-3), but no signal lines or electrodes of the first conductive layer, second conductive layer, first signal line layer, third signal line layer, and anode layer. Because the signal lines of the second signal line layer are made of a substantially transparent conductive material, light can pass through the multiple light-transmitting regions TR.

[0318] In some embodiments, each of the plurality of second reset control signal line portions rst-2 is connected to two adjacent first reset control signal line portions rst-1. Each of the plurality of third reset control signal line portions rst-3 is connected to two adjacent first reset control signal line portions rst-1. Two adjacent first reset control signal line portions rst-1 are connected via individual second reset control signal line portions rst-2 and via individual third reset control signal line portions rst-3. The two adjacent first reset control signal line portions rst-1, the individual second reset control signal line portions rst-2, and the individual third reset control signal line portions rst-3 form a third ring, which substantially surrounds the region of the transistor and capacitor of the pixel driving circuit having sub-pixels. In one example, the third ring essentially surrounds the region with the transistor and capacitor corresponding to the first sub-pixel. In another example, the third ring essentially surrounds the region with the transistor and capacitor of the first color sub-pixel. In yet another example, the third ring essentially surrounds the region with the transistor and capacitor of the red sub-pixel.

[0319] In some embodiments, the array substrate includes a plurality of third rings LPS3 arranged in a row. Optionally, the plurality of third rings LPS3 respectively surround the region of the pixel driving circuit of a sub-pixel of the same color. Each of the plurality of third rings LPS3 surrounds the region of the pixel driving circuit of a sub-pixel of the same color. In one example, the plurality of third rings LPS3 surround the region of the pixel driving circuit of a red sub-pixel.

[0320] In some embodiments, the plurality of third rings LPS3 substantially surround the region of the anode of the sub-pixel having the same color. Each of the plurality of third rings LPS3 substantially surrounds the region of the anode of the sub-pixel having the same color. In one example, the plurality of third rings LPS3 substantially surround the region of the anode having a red sub-pixel.

[0321] Figure 25 This is a schematic diagram illustrating a reset control signal network in a portion of an array substrate according to some embodiments of the present disclosure. In some embodiments, reference is made to... Figure 25The subpixels in the array substrate are arranged in multiple rows and columns. In the m-th row of subpixels Rm, the array substrate includes a row of first subpixels. In the (m+1)-th row of subpixels R(m+1), the array substrate includes a row of third subpixels. In the (m+2)-th row of subpixels R(m+2), the array substrate includes a row of second subpixels. Optionally, a row of first subpixels is a row of subpixels of a first color, a row of second subpixels is a row of subpixels of a second color, and a row of third subpixels is a row of subpixels of a third color. Figure 25 The text represents the corresponding first sub-pixel sp1, the corresponding second sub-pixel sp2, and the corresponding third sub-pixel sp3.

[0322] In some embodiments, in the nth column of sub-pixels Cn, the array substrate includes a column of third sub-pixels. In the (n-1)th column of sub-pixels C(n-1), the array substrate includes a column of alternating first and second sub-pixels. In the (n+1)th column of sub-pixels C(n+1), the array substrate includes a column of alternating first and second sub-pixels. Optionally, the column of third sub-pixels is a column of sub-pixels of a third color, and the column of alternating first and second sub-pixels is a column of alternating first and second color sub-pixels. Optionally, in the nth column of sub-pixels Cn, each of the plurality of light-transmitting regions TR separates two adjacent third sub-pixels.

[0323] Reference Figure 2A , Figure 2B , Figures 16A to 16M , Figures 17A to 17M and Figure 25 In some embodiments, the first reset control signal line portion of the plurality of first reset control signal line portions rst-1 is connected to the gate of one or more reset control transistors in the pixel driving circuit of the third sub-pixel in the nth column sub-pixel Cn and the (m+1)th row sub-pixel R(m+1), connected to the gate of one or more reset control transistors in the pixel driving circuit of the second sub-pixel in the (n-1)th column sub-pixel C(n-1) and the (m+2)th row sub-pixel R(m+2), and connected to the gate of one or more reset control transistors in the pixel driving circuit of the first sub-pixel in the (n+1)th column sub-pixel C(n+1) and the mth row sub-pixel Rm.

[0324] In some embodiments, the second reset control signal line portion in the plurality of second reset control signal line portions rst-2 connects the first reset control signal line portion to the first adjacent first reset control signal line portion, and the first adjacent first reset control signal line portion is connected to the gate of one or more reset control transistors in the pixel driving circuit of the first sub-pixel in the (n-1)th column sub-pixel C(n-1) and the first sub-pixel in the mth row sub-pixel Rm.

[0325] In some embodiments, the third reset control signal line portion of the plurality of third reset control signal line portions rst-3 connects the first reset control signal line portion to the second adjacent first reset control signal line portion, and the second adjacent first reset control signal line portion is connected to the gate of one or more reset control transistors in the pixel driving circuit of the second sub-pixel in the (n+1)th column sub-pixel C(n+1) and the (m+2)th row sub-pixel R(m+2).

[0326] Figure 26 This is a schematic diagram illustrating a light-emitting control signal network in a portion of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 17A , Figure 17C , Figure 17H and Figure 26 Each of the plurality of light-emitting control signal lines includes a plurality of first light-emitting control signal line portions em-1 and a plurality of second light-emitting control signal line portions em-2. The plurality of first light-emitting control signal line portions em-1 and the plurality of second light-emitting control signal line portions em-2 are located in two different layers. In one example, the plurality of first light-emitting control signal line portions em-1 are located in a first conductive layer, and the plurality of second light-emitting control signal line portions em-2 are located in a second signal line layer. Each second light-emitting control signal line portion in the plurality of second light-emitting control signal line portions em-2 is respectively connected to two adjacent first light-emitting control signal line portions in the plurality of first light-emitting control signal line portions em-1. Two adjacent first light-emitting control signal line portions in the plurality of first light-emitting control signal line portions em-1 are connected through individual second light-emitting control signal line portions in the plurality of second light-emitting control signal line portions em-2.

[0327] In some embodiments, each of the plurality of light-emitting control signal lines includes a plurality of first light-emitting control signal line portions em-1 and a plurality of third light-emitting control signal line portions em-3. The plurality of first light-emitting control signal line portions em-1 and the plurality of third light-emitting control signal line portions em-3 are located in two different layers. In one example, the plurality of first light-emitting control signal line portions em-1 are located in a first conductive layer, and the plurality of third light-emitting control signal line portions em-3 are located in a second signal line layer. Each third light-emitting control signal line portion em-3 is respectively connected to two adjacent first light-emitting control signal line portions em-1 in the same row. Two adjacent first light-emitting control signal line portions em-1 are connected through individual third light-emitting control signal line portions em-3.

[0328] In some embodiments, each of the plurality of light-emitting control signal lines includes a plurality of first light-emitting control signal line portions em-1, a plurality of second light-emitting control signal line portions em-2, and a plurality of third light-emitting control signal line portions em-3. The plurality of first light-emitting control signal line portions em-1 and the plurality of second light-emitting control signal line portions em-2 are located in two different layers; and the plurality of first light-emitting control signal line portions em-1 and the plurality of third light-emitting control signal line portions em-3 are located in two different layers. Optionally, the plurality of second light-emitting control signal line portions em-2 and the plurality of third light-emitting control signal line portions em-3 are located in the same layer. In one example, the plurality of first light-emitting control signal line portions em-1 are located in a first conductive layer, the plurality of second light-emitting control signal line portions em-2 are located in a second signal line layer, and the plurality of third light-emitting control signal line portions em-3 are located in a second signal line layer. In some embodiments, the signal lines located in the second signal line layer are made of a substantially transparent conductive material. Within multiple light-transmitting regions TR, there are signal lines of a second signal line layer (e.g., multiple data lines, multiple first voltage supply line portions, multiple second voltage supply line portions, multiple second light emission control signal line portions em-2, and multiple third light emission control signal line portions em-3), but no signal lines or electrodes of the first conductive layer, second conductive layer, first signal line layer, third signal line layer, and anode layer. Since the signal lines of the second signal line layer are made of a substantially transparent conductive material, light can pass through the multiple light-transmitting regions TR.

[0329] In some embodiments, each of the plurality of second light-emitting control signal line portions em-2 is connected to two adjacent first light-emitting control signal line portions em-1. Each of the plurality of third light-emitting control signal line portions em-3 is connected to two adjacent first light-emitting control signal line portions em-1. Two adjacent first light-emitting control signal line portions em-1 are connected via individual second light-emitting control signal line portions em-2 and via individual third light-emitting control signal line portions em-3. The two adjacent first light-emitting control signal line portions em-1, the individual second light-emitting control signal line portions em-2, and the individual third light-emitting control signal line portions em-3 form a fourth ring, which substantially surrounds the region of the transistor and capacitor of the pixel driving circuit having a sub-pixel. In one example, the fourth ring substantially surrounds the region of the transistor and capacitor having a corresponding first sub-pixel. In another example, the fourth ring essentially surrounds the area of ​​transistors and capacitors with the first color subpixel. In yet another example, the fourth ring essentially surrounds the area of ​​transistors and capacitors with the red subpixel.

[0330] In some embodiments, the array substrate includes a plurality of fourth rings LPS4 arranged in a row. Optionally, the plurality of fourth rings LPS4 respectively substantially surround the region of the pixel driving circuit of a sub-pixel of the same color. Each of the plurality of fourth rings LPS4 substantially surrounds the region of the pixel driving circuit of a sub-pixel of the same color. In one example, the plurality of fourth rings LPS4 substantially surround the region of the pixel driving circuit of a red sub-pixel.

[0331] In some embodiments, a plurality of fourth rings LPS4 substantially surround the region of the anode of a sub-pixel having the same color. Each of the plurality of fourth rings LPS4 substantially surrounds the region of the anode of a sub-pixel having the same color. In one example, the plurality of fourth rings LPS4 substantially surround the region of the anode having a red sub-pixel.

[0332] Figure 27 This is a schematic diagram illustrating a light-emitting control signal network in a portion of an array substrate according to some embodiments of the present disclosure. In some embodiments, reference is made to... Figure 27The subpixels in the array substrate are arranged in multiple rows and columns. In the m-th row of subpixels Rm, the array substrate includes a row of first subpixels. In the (m+1)-th row of subpixels R(m+1), the array substrate includes a row of third subpixels. In the (m+2)-th row of subpixels R(m+2), the array substrate includes a row of second subpixels. Optionally, a row of first subpixels is a row of subpixels of a first color, a row of second subpixels is a row of subpixels of a second color, and a row of third subpixels is a row of subpixels of a third color. Figure 27 The text represents the corresponding first sub-pixel sp1, the corresponding second sub-pixel sp2, and the corresponding third sub-pixel sp3.

[0333] In some embodiments, in the nth column of sub-pixels Cn, the array substrate includes a column of third sub-pixels. In the (n-1)th column of sub-pixels C(n-1), the array substrate includes a column of alternating first and second sub-pixels. In the (n+1)th column of sub-pixels C(n+1), the array substrate includes a column of alternating first and second sub-pixels. Optionally, the column of third sub-pixels is a column of sub-pixels of a third color, and the column of alternating first and second sub-pixels is a column of alternating first and second color sub-pixels. Optionally, in the nth column of sub-pixels Cn, each of the plurality of light-transmitting regions TR separates two adjacent third sub-pixels.

[0334] Reference Figure 2A , Figure 2B , Figures 16A to 16M , Figures 17A to 17M and Figure 27 In some embodiments, the first light emission control signal line portion em-1 of the plurality of first light emission control signal line portions is connected to the gate of one or more light emission control transistors in the pixel driving circuit of the third sub-pixel in the nth column sub-pixel Cn and the (m+1)th row sub-pixel R(m+1), connected to the gate of one or more light emission control transistors in the pixel driving circuit of the second sub-pixel in the (n-1)th column sub-pixel C(n-1) and the (m+2)th row sub-pixel R(m+2), and connected to the gate of one or more light emission control transistors in the pixel driving circuit of the first sub-pixel in the (n+1)th column sub-pixel C(n+1) and the mth row sub-pixel Rm.

[0335] In some embodiments, the second light emission control signal line portion in the plurality of second light emission control signal line portions em-2 connects the first light emission control signal line portion to the first adjacent first light emission control signal line portion, and the first adjacent first light emission control signal line portion is connected to the gate of one or more light emission control transistors in the pixel driving circuit of the first sub-pixel in the (n-1)th column sub-pixel C(n-1) and the first sub-pixel in the mth row sub-pixel Rm.

[0336] In some embodiments, the third light emission control signal line portion in the plurality of third light emission control signal line portions em-3 connects the first light emission control signal line portion to the second adjacent first light emission control signal line portion, and the second adjacent first light emission control signal line portion is connected to the gate of one or more light emission control transistors in the pixel driving circuit of the second sub-pixel in the (n+1)th column sub-pixel C(n+1) and the (m+2)th row sub-pixel R(m+2).

[0337] Reference Figure 17A , Figure 17C , Figure 17H and Figures 20 to 27 In some embodiments, the array substrate includes a plurality of signal lines, each of which includes a plurality of first signal line portions and a plurality of second signal line portions. The plurality of first signal line portions and the plurality of second signal line portions are located in two different layers. In one example, the plurality of first signal line portions are located in a first conductive layer, and the plurality of second signal line portions are located in a second signal line layer. In another example, the plurality of first signal line portions are located in a second conductive layer, and the plurality of second signal line portions are located in a second signal line layer. Each of the plurality of second signal line portions is respectively connected to two adjacent first signal line portions. Two adjacent first signal line portions are connected through individual second signal line portions.

[0338] In some embodiments, each of the plurality of signal lines includes a plurality of first signal line portions and a plurality of third signal line portions. The plurality of first signal line portions and the plurality of third signal line portions are located in two different layers. In one example, the plurality of first signal line portions are located in a first conductive layer, and the plurality of third signal line portions are located in a second signal line layer. In another example, the plurality of first signal line portions are located in a second conductive layer, and the plurality of third signal line portions are located in a second signal line layer. Each of the plurality of third signal line portions is respectively connected to two adjacent first signal line portions in the same row. Two adjacent first signal line portions are connected through a separate third signal line portion.

[0339] In some embodiments, each of the plurality of signal lines includes a plurality of first signal line portions, a plurality of second signal line portions, and a plurality of third signal line portions. The plurality of first signal line portions and the plurality of second signal line portions are located in two different layers; and the plurality of first signal line portions and the plurality of third signal line portions are located in two different layers. Optionally, the plurality of second signal line portions and the plurality of third signal line portions are located in the same layer. In one example, the plurality of first signal line portions are located in a first conductive layer, the plurality of second signal line portions are located in a second signal line layer, and the plurality of third signal line portions are located in a second signal line layer. In one example, the plurality of first signal line portions are located in a second conductive layer, the plurality of second signal line portions are located in a second signal line layer, and the plurality of third signal line portions are located in a second signal line layer. In some embodiments, the signal lines located in the second signal line layer are made of a substantially transparent conductive material. In the plurality of light-transmitting regions TR, signal lines of the second signal line layer are present, while signal lines and electrodes of the first conductive layer, the second conductive layer, the first signal line layer, the third signal line layer, and the anode layer are absent. Because the signal lines of the second signal line layer are made of a substantially transparent conductive material, light can pass through multiple light-transmitting areas TR.

[0340] In some embodiments, each of the plurality of second signal line portions is respectively connected to two adjacent first signal line portions of the plurality of first signal line portions. Each of the plurality of third signal line portions is respectively connected to two adjacent first signal line portions of the plurality of first signal line portions. Two adjacent first signal line portions of the plurality of first signal line portions are connected via individual second signal line portions of the plurality of second signal line portions and via individual third signal line portions of the plurality of third signal line portions. Two adjacent first signal line portions of the plurality of first signal line portions, individual second signal line portions of the plurality of second signal line portions, and individual third signal line portions of the plurality of third signal line portions form a loop substantially surrounding a region of transistors and capacitors of a pixel driving circuit having a sub-pixel. In one example, the loop substantially surrounds a region of transistors and capacitors having a corresponding first sub-pixel. In another example, the loop substantially surrounds a region of transistors and capacitors having a sub-pixel of a first color. In yet another example, the loop substantially surrounds a region of transistors and capacitors having a red sub-pixel.

[0341] In some embodiments, the array substrate includes a plurality of rings arranged in a row. Optionally, the plurality of rings respectively surround a region of pixel driving circuitry for a sub-pixel of the same color. Each ring in the plurality of rings surrounds a region of pixel driving circuitry for a sub-pixel of the same color. In one example, the plurality of rings surround a region of pixel driving circuitry for a red sub-pixel.

[0342] In some embodiments, the plurality of rings substantially surround the region of the anode of a sub-pixel having the same color. Each of the plurality of rings substantially surrounds the region of the anode of a sub-pixel having the same color. In one example, the plurality of rings substantially surround the region of the anode having a red sub-pixel.

[0343] In some embodiments, the subpixels in the array substrate are arranged in multiple rows and columns. In the m-th row of subpixels Rm, the array substrate includes a row of first subpixels. In the (m+1)-th row of subpixels R(m+1), the array substrate includes a row of third subpixels. In the (m+2)-th row of subpixels R(m+2), the array substrate includes a row of second subpixels. Optionally, a row of first subpixels is a row of subpixels of a first color, a row of second subpixels is a row of subpixels of a second color, and a row of third subpixels is a row of subpixels of a third color. The first color, the second color, and the third color are three different colors. In one example, the first color is red, the second color is green, and the third color is blue.

[0344] In some embodiments, in the nth column of sub-pixels Cn, the array substrate includes a column of third sub-pixels. In the (n-1)th column of sub-pixels C(n-1), the array substrate includes a column of alternating first and second sub-pixels. In the (n+1)th column of sub-pixels C(n+1), the array substrate includes a column of alternating first and second sub-pixels. Optionally, the column of third sub-pixels is a column of sub-pixels of a third color, and the column of alternating first and second sub-pixels is a column of alternating first and second color sub-pixels. Optionally, in the nth column of sub-pixels Cn, each of the plurality of light-transmitting regions TR separates two adjacent third sub-pixels.

[0345] Reference Figure 2A , Figure 2B , Figures 16A to 16M , Figures 17A to 17M as well as Figures 20 to 27 In some embodiments, a first signal line portion of a plurality of first signal line portions is connected to one or more transistors in the pixel driving circuit of the third sub-pixel in the nth column sub-pixel Cn and the (m+1)th row sub-pixel R(m+1), connected to one or more transistors in the pixel driving circuit of the second sub-pixel in the (n-1)th column sub-pixel C(n-1) and the (m+2)th row sub-pixel R(m+2), and connected to one or more transistors in the pixel driving circuit of the first sub-pixel in the (n+1)th column sub-pixel C(n+1) and the mth row sub-pixel Rm.

[0346] In some embodiments, a second signal line portion of a plurality of second signal line portions connects a first signal line portion to a first adjacent first signal line portion, and the first adjacent first signal line portion is connected to one or more transistors in the pixel driving circuit of the first sub-pixel in the (n-1)th column sub-pixel C(n-1) and the first sub-pixel in the mth row sub-pixel Rm.

[0347] In some embodiments, a third signal line portion of a plurality of third signal line portions is connected to a first signal line portion and a second adjacent first signal line portion, and the second adjacent first signal line portion is connected to one or more transistors in the pixel driving circuit of a second sub-pixel in the (n+1)th column sub-pixel C(n+1) and the (m+2)th row sub-pixel R(m+2).

[0348] Figure 28A This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure. Figure 28B It is shown Figure 28A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate. Figure 28C It is shown Figure 28A A schematic diagram of the structure of the first conductive layer in a portion of the array substrate depicted in the figure. Figure 28D It is shown Figure 28A A schematic diagram of the structure of the second conductive layer in a portion of the array substrate depicted in the figure. Figure 28E It is shown Figure 28A A schematic diagram of the structure of the interlayer dielectric layer in a portion of the array substrate depicted in the figure. Figure 28F It is shown Figure 28A A schematic diagram of the structure of the first signal line layer in a portion of the array substrate depicted in the figure. Figure 28G It is shown Figure 28A A schematic diagram of the structure of the passivation layer in a portion of the array substrate depicted in the figure. Figure 28H It is shown Figure 28A A schematic diagram of the structure of the first planarization layer in a portion of the array substrate depicted in the figure. Figure 28I It is shown Figure 28A A schematic diagram of the structure of the third signal line layer in a portion of the array substrate depicted in the figure. Figure 28J It is shown Figure 28A A schematic diagram of the structure of the second planarization layer in a portion of the array substrate described herein. Figure 28K It is shown Figure 28A A schematic diagram of the structure of the anode layer in a portion of the array substrate depicted in the diagram. Figure 28L It is shown Figure 28A A schematic diagram of the structure of the pixel-defining layer in a portion of the array substrate depicted in the figure. Figure 29 It is along Figure 28A A cross-sectional view of line B-B' in the diagram.

[0349] Figure 28A To Figure 28M and Figure 29 The array substrate depicted in the image and Figures 3A to 3M and Figure 4 The difference between the array substrates depicted in the text is that... Figure 28A To Figure 28M and Figure 29 The array substrate depicted does not include the second signal line layer.

[0350] Reference Figure 28A To Figure 28M and Figure 29 In some embodiments, the array substrate includes: a substrate BS; a semiconductor material layer SML located on the substrate BS; a gate insulating layer GI located on the side of the semiconductor material layer SML away from the substrate BS; a first conductive layer CT1 located on the side of the gate insulating layer GI away from the semiconductor material layer SML; an insulating layer IN located on the side of the first conductive layer CT1 away from the gate insulating layer GI; a second conductive layer CT2 located on the side of the insulating layer IN away from the first conductive layer CT1; an interlayer dielectric layer ILD located on the side of the second conductive layer CT2 away from the insulating layer IN; and a first signal line layer SL1 located on the side of the interlayer dielectric layer ILD away from the first conductive layer CT1. The structure comprises: a conductive layer CT2 on one side; a passivation layer PVX located on the side of the first signal line SL1 away from the interlayer dielectric layer ILD; a first planarization layer PLN1 located on the side of the passivation layer PVX away from the first signal line layer SL1; a third signal line layer SL3 located on the side of the first planarization layer PLN1 away from the passivation layer PVX; a second planarization layer PLN2 located on the side of the third signal line layer SL3 away from the first planarization layer PLN1; an anode layer ADL located on the side of the second planarization layer PLN2 away from the third signal line layer SL3; and a pixel defining layer PDL located on the side of the anode layer ADL away from the second planarization layer PLN2.

[0351] Reference Figure 2A , Figure 2B , Figure 28A and Figure 28BThe corresponding pixel driving circuits are labeled with numbers, which represent regions corresponding to multiple transistors (including first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, and driving transistor Td) in the corresponding pixel driving circuit. The corresponding pixel driving circuits are also labeled with numbers representing components of each of the multiple transistors in the pixel driving circuit. For example, first transistor T1 includes an active layer ACT1, a first electrode S1, and a second electrode D1. Second transistor T2 includes an active layer ACT2, a first electrode S2, and a second electrode D2. Third transistor T3 includes an active layer ACT3, a first electrode S3, and a second electrode D3. Fourth transistor T4 includes an active layer ACT4, a first electrode S4, and a second electrode D4. Fifth transistor T5 includes an active layer ACT5, a first electrode S5, and a second electrode D5. Sixth transistor T6 includes an active layer ACT6, a first electrode S6, and a second electrode D6. Driving transistor Td includes an active layer ACTd, a first electrode Sd, and a second electrode Dd. In one example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) in the corresponding pixel driving circuit are part of the overall structure. In another example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd), the first electrode (S1, S2, S3, S4, S5, S6, and Sd), and the second electrode (D1, D2, D3, D4, D5, D6, and Dd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) in the corresponding pixel driving circuit are part of the overall structure. In yet another example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) are located in the same layer. In another example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd), the first electrodes (S1, S2, S3, S4, S5, S6, and Sd), and the second electrodes (D1, D2, D3, D4, D5, D6, and Dd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) are located in the same layer.

[0352] Reference Figure 2A , Figure 2B , Figure 28A and Figure 28CIn some embodiments, the first conductive layer includes a plurality of reset control signal lines rst, a plurality of light emission control signal lines em, a plurality of gate signal lines GL, and a first capacitor electrode Ce1 of the storage capacitor Cst. Various suitable electrode materials and various suitable manufacturing methods can be used to fabricate the first conductive layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, the plurality of reset control signal lines rst, the plurality of light emission control signal lines em, the plurality of gate signal lines GL, and the first capacitor electrode Ce1 of the storage capacitor Cst are located in the same layer.

[0353] Reference Figure 2A , Figure 2B , Figure 28A and Figure 28D In some embodiments, the second conductive layer includes a plurality of initialization signal lines Vint and a second capacitor electrode Ce2 for a storage capacitor Cst. Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the second conductive layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the second conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, the plurality of initialization signal lines Vint and the second capacitor electrode Ce2 for the storage capacitor Cst are in the same layer.

[0354] In some embodiments, the second capacitor electrodes of a row pixel driving circuit are interconnected to form a line for transmitting voltage supply signals.

[0355] Figure 28E The image depicts vias extending through the interlayer dielectric layer (ILD).

[0356] Reference Figure 2A , Figure 2B , Figure 28A and Figure 28FIn some embodiments, the first signal line layer includes node connection lines Cln, voltage connection pads VCP, data signal connection pads DCP, electrode connection lines Cle, and reset signal connection lines Cli. Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the first signal line layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first signal line layer include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. In some embodiments, the first signal line layer includes multiple sublayers stacked together. In one example, the first signal line layer includes a stacked titanium / aluminum / titanium multilayer structure. In another example, the first signal line layer includes a stacked molybdenum / aluminum / molybdenum multilayer structure. Optionally, the node connection lines Cln, voltage connection pads VCP, data signal connection pads DCP, electrode connection lines Cle, and reset signal connection lines Cli are located in the same layer.

[0357] Node connection line Cln is connected to the first capacitor electrode Ce1 and to the second electrode of the third transistor T3 and / or the second electrode of the first transistor T1. Data signal connection pad DCP connects the corresponding data line among multiple data lines to the first electrode of the second transistor T2. Reset signal connection line Cli connects the corresponding initialization signal line among multiple initialization signal lines to the first electrodes of the first transistor T1 and the sixth transistor T6. Voltage connection pad VCP connects the corresponding voltage supply line among multiple voltage supply lines to the first electrode of the fourth transistor T4 and to the second capacitor electrode of the storage capacitor. Electrode connection line Cle is connected to the second electrodes of the fifth transistor T5 and the sixth transistor T6, respectively.

[0358] Figure 28G The image depicts vias extending through the passivation layer PVX.

[0359] Figure 28H The image depicts vias extending through the first planarization layer PLN1.

[0360] Reference Figure 2A , Figure 2B , Figure 28A and Figure 28I In some embodiments, the third signal line layer includes multiple data lines DL and an anode connection pad ACP. The anode connection pad ACP is connected to the fourth node N4 and the corresponding anode in the corresponding sub-pixel, respectively. The anode connection pad ACP is connected to the second electrodes of the fifth transistor T5 and the sixth transistor T6, and the corresponding anode in the corresponding sub-pixel is connected to the anode connection pad ACP.

[0361] Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the third signal line layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the third signal line layer include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. In some embodiments, the second signal line layer comprises multiple sublayers stacked together. In one example, the second signal line layer comprises a stacked titanium / aluminum / titanium multilayer structure. In another example, the second signal line layer comprises a stacked molybdenum / aluminum / molybdenum multilayer structure. Optionally, multiple data lines (DL), voltage bridges (VCB), and anode pads (ACP) are located in the same layer.

[0362] Figure 28J The image depicts vias extending through the second planarization layer PLN2.

[0363] Reference Figure 2A , Figure 2B , Figure 28A and Figure 28K In some embodiments, the anode layer includes the anode of the corresponding light-emitting element. The anode is connected to an anode connection pad in the third signal line layer, and the anode connection pad is connected to the second electrode of the fifth transistor T5 and the sixth transistor T6.

[0364] Figure 28L The image depicts a via extending through the pixel-defined layer (PDL). (See reference...) Figure 28L The array substrate includes sub-pixel openings SA configured to accommodate light-emitting material.

[0365] Reference Figure 2A , Figure 2B , Figures 28A to 28L and Figure 29 In some embodiments, the first capacitor electrode Ce1 is located on the side of the gate insulating layer GI away from the substrate BS. In some embodiments, the array substrate further includes a first via v1 and a second via v2. The first via v1 extends through the interlayer dielectric layer ILD and the insulating layer IN. The second via v2 extends through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. Optionally, the node connection line Cln is connected to the first capacitor electrode Ce1 through the first via v1, and the node connection line Cln is connected to the semiconductor material layer SML through the second via v2. Optionally, the node connection line Cln is connected to the second electrode D3 of the third transistor and / or the second electrode D1 of the first transistor, such as... Figure 29 The description.

[0366] In some embodiments, the array substrate further includes a sixth via v6. A voltage connection pad VCP is connected to the first electrode S4 of the fourth transistor T4 via the sixth via v6, thereby providing a voltage supply signal to the first electrode S4 of the fourth transistor T4. In one example, the sixth via v6 extends through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI.

[0367] In some embodiments, the array substrate further includes a seventh via v7. The voltage connection bridge VCB is connected to the voltage connection pad VCP via the seventh via v7. In one example, the seventh via v7 extends through the first planarization layer PLN1 and the passivation layer PVX.

[0368] Figure 30A This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure. Figure 30B It is shown Figure 30A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate. Figure 30C It is shown Figure 30A A schematic diagram of the structure of the first conductive layer in a portion of the array substrate depicted in the figure. Figure 30D It is shown Figure 30A A schematic diagram of the structure of the second conductive layer in a portion of the array substrate depicted in the figure. Figure 30E It is shown Figure 30A A schematic diagram of the structure of the interlayer dielectric layer in a portion of the array substrate depicted in the figure. Figure 30F It is shown Figure 30A A schematic diagram of the structure of the first signal line layer in a portion of the array substrate. Figure 30G It is shown Figure 30A A schematic diagram of the structure of the passivation layer in a portion of the array substrate depicted in the figure. Figure 30H It is shown Figure 30A A schematic diagram of the structure of the first planarization layer in a portion of the array substrate depicted in the figure. Figure 30I It is shown Figure 30A A schematic diagram of the structure of the third signal line layer in a portion of the array substrate depicted in the figure. Figure 30J It is shown Figure 30A A schematic diagram of the structure of the second planarization layer in a portion of the array substrate described herein. Figure 30K It is shown Figure 30A A schematic diagram of the structure of the anode layer in a portion of the array substrate depicted in the diagram. Figure 30L It is shown Figure 30A A schematic diagram of the structure of the pixel-defining layer in a portion of the array substrate depicted in the figure.

[0369] In some embodiments, refer to Figure 30AThe smallest repeating unit of multiple sub-pixels of the array substrate includes a corresponding first sub-pixel sp1, a corresponding second sub-pixel sp2, and a corresponding third sub-pixel sp3. Figure 28A A portion of the array substrate depicted corresponds to Figure 30A A portion of the corresponding third sub-pixel sp3 depicted in the image.

[0370] In some embodiments, each of the corresponding first sub-pixel sp1, the corresponding second sub-pixel sp2, and the corresponding third sub-pixel sp3 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a driving transistor Td, and a storage capacitor Cst.

[0371] In some embodiments, the corresponding first sub-pixel sp1 is a sub-pixel of a first color (e.g., red), the corresponding second sub-pixel sp2 is a sub-pixel of a second color (e.g., green), and the corresponding third sub-pixel sp3 is a sub-pixel of a third color (e.g., blue). In some embodiments, the corresponding first sub-pixel sp1, the corresponding second sub-pixel sp2, and the corresponding third sub-pixel sp3 are three sub-pixels of a pixel in an array substrate.

[0372] Figure 31 This is a schematic diagram illustrating a voltage supply network in a portion of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 30A , Figure 30H , Figure 30J and Figure 31 In some embodiments, the array substrate includes multiple voltage-connected bridges (VCBS). Optionally, the multiple VCBS are arranged in a multi-row and multi-column array.

[0373] In some embodiments, each voltage bridge in the plurality of voltage-connected bridges (VCBS) includes a second capacitor electrode of a plurality of pixel driving circuits. Optionally, each voltage bridge in the plurality of voltage-connected bridges (VCBS) includes a second capacitor electrode of the pixel driving circuit of the corresponding first sub-pixel sp1, the corresponding second sub-pixel sp2, and the corresponding third sub-pixel sp3. Optionally, the respective voltage bridge in the plurality of voltage-connected bridges (VCBS) is configured to provide a voltage supply signal to the first electrode of the fourth transistor of the pixel driving circuit of the corresponding first sub-pixel sp1, the corresponding second sub-pixel sp2, and the corresponding third sub-pixel sp3.

[0374] In some embodiments, a corresponding voltage supply line in a plurality of voltage supply lines Vdd is connected to a voltage connection bridge in two adjacent columns of a plurality of voltage connection bridges VCBS. In some embodiments, a corresponding voltage connection bridge in a plurality of voltage connection bridges VCBS is respectively connected to two adjacent voltage supply lines in a plurality of voltage supply lines Vdd. In some embodiments, the plurality of voltage supply lines Vdd includes a first adjacent voltage supply line AVdd1 and a second adjacent voltage supply line AVdd2. Each voltage connection bridge in the plurality of voltage connection bridges VCBS is connected to the first adjacent voltage supply line AVdd1 and connected to the second adjacent voltage supply line AVdd2.

[0375] In some embodiments, multiple voltage supply lines (including a first adjacent voltage supply line AVdd1 and a second adjacent voltage supply line AVdd2) are located in the second conductive layer, and multiple voltage connection bridges VCBS are located in the second conductive layer CT2.

[0376] In some embodiments, two adjacent voltage connection bridges in a plurality of voltage connection bridges in the same pixel row VCBS are connected to the same voltage supply line in a plurality of voltage supply lines, such as Figure 31 As depicted. Reference Figure 9 In some embodiments, a pixel row includes a row m sub-pixel Rm, a row (m+1) sub-pixel R(m+1), and a row (m+2) sub-pixel R(m+2).

[0377] In some embodiments, voltage connection bridges in multiple voltage connection bridges within the same pixel column of a VCBS are connected to the same two adjacent voltage supply lines among multiple voltage supply lines. (See reference...) Figure 9 In some embodiments, the pixel column includes the nth column sub-pixel Cn, the (n-1)th column sub-pixel C(n-1), and the (n+1)th column sub-pixel C(n+1).

[0378] Figure 32 This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 32 In some embodiments, the array substrate includes multiple light-transmitting regions TR that allow light to pass through. In these multiple light-transmitting regions TR, there are no signal lines or electrodes from the first conductive layer, second conductive layer, first signal line layer, third signal line layer, and anode layer.

[0379] In some embodiments, the array substrate is a full-display (FDC) array substrate with a camera, wherein the array substrate further includes photoelectric sensors located in a plurality of light-transmitting regions TR configured to detect light.

[0380] Figure 33 This is a schematic diagram illustrating a reset signal network in a portion of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 30A , Figure 30D , Figure 30H and Figure 33 Each of the multiple initialization signal lines includes multiple first initialization signal line portions Vint-1 and multiple second initialization signal line portions Vint-2. The multiple first initialization signal line portions Vint-1 and the multiple second initialization signal line portions Vint-2 are located in two different layers. In one example, the multiple first initialization signal line portions Vint-1 are located in a second conductive layer, while the multiple second initialization signal line portions Vint-2 are located in a first signal line layer. Each second initialization signal line portion in the multiple second initialization signal line portions Vint-2 is connected to two adjacent first initialization signal line portions in the multiple first initialization signal line portions Vint-1. Two adjacent first initialization signal line portions in the multiple first initialization signal line portions Vint-1 are connected through individual second initialization signal line portions in the multiple second initialization signal line portions Vint-2.

[0381] In some embodiments, each of the plurality of initialization signal lines includes a plurality of first initialization signal line portions Vint-1 and a plurality of third initialization signal line portions Vint-3. The plurality of first initialization signal line portions Vint-1 and the plurality of third initialization signal line portions Vint-3 are located in two different layers. In one example, the plurality of first initialization signal line portions Vint-1 are located in a second conductive layer, while the plurality of third initialization signal line portions Vint-3 are located in a first signal line layer. Each third initialization signal line portion in the plurality of third initialization signal line portions Vint-3 is respectively connected to two adjacent first initialization signal line portions in the plurality of first initialization signal line portions Vint-1 in the same row. Two adjacent first initialization signal line portions in the plurality of first initialization signal line portions Vint-1 are connected through individual third initialization signal line portions in the plurality of third initialization signal line portions Vint-3.

[0382] In some embodiments, each of the plurality of initialization signal lines includes a plurality of first initialization signal line portions Vint-1, a plurality of second initialization signal line portions Vint-2, and a plurality of third initialization signal line portions Vint-3. The plurality of first initialization signal line portions Vint-1 and the plurality of second initialization signal line portions Vint-2 are located in two different layers; and the plurality of first initialization signal line portions Vint-1 and the plurality of third initialization signal line portions Vint-3 are located in two different layers. Optionally, the plurality of second initialization signal line portions Vint-2 and the plurality of third initialization signal line portions Vint-3 are located in the same layer. In one example, the plurality of first initialization signal line portions Vint-1 are located in a second conductive layer, the plurality of second initialization signal line portions Vint-2 are located in a first signal line layer, and the plurality of third initialization signal line portions Vint-3 are located in the first signal line layer. In the plurality of light-transmitting regions TR, there are no signal lines or electrodes in the first conductive layer, the second conductive layer, the first signal line layer, the third signal line layer, and the anode layer.

[0383] In some embodiments, each of the plurality of second initialization signal line portions Vint-2 is connected to two adjacent first initialization signal line portions Vint-1. Each of the plurality of third initialization signal line portions Vint-3 is connected to two adjacent first initialization signal line portions Vint-1. Two adjacent first initialization signal line portions in Vint-1 are connected via individual second initialization signal line portions in Vint-2 and via individual third initialization signal line portions in Vint-3. The two adjacent first initialization signal line portions in Vint-1, the individual second initialization signal line portions in Vint-2, and the individual third initialization signal line portions in Vint-3 form a first ring that substantially surrounds the region of the transistor and capacitor of the pixel driving circuit having a sub-pixel. In one example, the first ring substantially surrounds the region of the transistor and capacitor having a corresponding first sub-pixel. In another example, the first ring essentially surrounds the region of transistors and capacitors with subpixels of the first color. In yet another example, the first ring essentially surrounds the region of transistors and capacitors with red subpixels.

[0384] In some embodiments, the array substrate includes a plurality of first rings LPS1 arranged in a row. Optionally, the plurality of first rings LPS1 respectively substantially surround the region of the pixel driving circuit of a sub-pixel of the same color. Each of the plurality of first rings LPS1 substantially surrounds the region of the pixel driving circuit of a sub-pixel of the same color. In one example, the plurality of first rings LPS1 substantially surround the region of the pixel driving circuit of a red sub-pixel.

[0385] In some embodiments, a plurality of first rings LPS1 substantially surround the region of the anode of a sub-pixel having the same color. Each of the plurality of first rings LPS1 substantially surrounds the region of the anode of a sub-pixel having the same color. In one example, the plurality of first rings LPS1 substantially surround the region of the anode having a red sub-pixel.

[0386] Figure 34 This is a schematic diagram illustrating a reset signal network in a portion of an array substrate according to some embodiments of the present disclosure. In some embodiments, reference is made to... Figure 34 The subpixels in the array substrate are arranged in multiple rows and columns. In the m-th row of subpixels Rm, the array substrate includes a row of first subpixels. In the (m+1)-th row of subpixels R(m+1), the array substrate includes a row of third subpixels. In the (m+2)-th row of subpixels R(m+2), the array substrate includes a row of second subpixels. Optionally, a row of first subpixels is a row of subpixels of a first color, a row of second subpixels is a row of subpixels of a second color, and a row of third subpixels is a row of subpixels of a third color. Figure 34 The text represents the corresponding first sub-pixel sp1, the corresponding second sub-pixel sp2, and the corresponding third sub-pixel sp3.

[0387] In some embodiments, in the nth column of sub-pixels Cn, the array substrate includes a column of third sub-pixels. In the (n-1)th column of sub-pixels C(n-1), the array substrate includes a column of alternating first and second sub-pixels. In the (n+1)th column of sub-pixels C(n+1), the array substrate includes a column of alternating first and second sub-pixels. Optionally, the column of third sub-pixels is a column of sub-pixels of a third color, and the column of alternating first and second sub-pixels is a column of alternating first and second color sub-pixels. Optionally, in the nth column of sub-pixels Cn, each of the plurality of light-transmitting regions TR separates two adjacent third sub-pixels.

[0388] Reference Figure 2A , Figure 2B , Figures 3A to 3M , Figures 30A to 30L and Figure 34In some embodiments, the first initialization signal line portion of the plurality of first initialization signal line portions Vint-1 is connected to the first electrode of one or more reset transistors in the pixel driving circuit of the third sub-pixel in the nth column sub-pixel Cn and the (m+1)th row sub-pixel R(m+1), connected to the first electrode of one or more reset transistors in the pixel driving circuit of the first sub-pixel in the (n-1)th column sub-pixel C(n-1) and the mth row sub-pixel Rm, and connected to the first electrode of one or more reset transistors in the pixel driving circuit of the second sub-pixel in the (n+1)th column sub-pixel C(n+1) and the (m+2)th row sub-pixel R(m+2).

[0389] In some embodiments, the second initialization signal line portion of the plurality of second initialization signal line portions Vint-2 connects the first initialization signal line portion to a first adjacent first initialization signal line portion, and the first adjacent first initialization signal line portion is connected to the first electrode of one or more reset transistors in the pixel driving circuit of the second sub-pixel in the (n-1)th column sub-pixel C(n-1) and the (m+2)th row sub-pixel R(m+2).

[0390] In some embodiments, the third initialization signal line portion of the plurality of third initialization signal line portions Vint-3 connects the first initialization signal line portion to the second adjacent first initialization signal line portion, and the second adjacent first initialization signal line portion is connected to the first electrode of one or more reset transistors in the pixel driving circuit of the first sub-pixel in the (n+1)th column sub-pixel C(n+1) and the first sub-pixel in the mth row sub-pixel Rm.

[0391] Figure 35 This is a schematic diagram illustrating a gate scan signal network in a portion of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 30A , Figure 30C , Figure 30H and Figure 35 Each of the plurality of gate signal lines includes a plurality of first gate signal line portions GL-1 and a plurality of second gate signal line portions GL-2. The plurality of first gate signal line portions GL-1 and the plurality of second gate signal line portions GL-2 are located in two different layers. In one example, the plurality of first gate signal line portions GL-1 are located in a first conductive layer, and the plurality of second gate signal line portions GL-2 are located in a first signal line layer. Each second gate signal line portion in the plurality of second gate signal line portions GL-2 is connected to two adjacent first gate signal line portions in the plurality of first gate signal line portions GL-1. Two adjacent first gate signal line portions in the plurality of first gate signal line portions GL-1 are connected through individual second gate signal line portions in the plurality of second gate signal line portions GL-2.

[0392] In some embodiments, each of the plurality of gate signal lines includes a plurality of first gate signal line portions GL-1 and a plurality of third gate signal line portions GL-3. The plurality of first gate signal line portions GL-1 and the plurality of third gate signal line portions GL-3 are located in two different layers. In one example, the plurality of first gate signal line portions GL-1 are located in a first conductive layer, and the plurality of third gate signal line portions GL-3 are located in a first signal line layer. Each third gate signal line portion in the plurality of third gate signal line portions GL-3 is respectively connected to two adjacent first gate signal line portions in the plurality of first gate signal line portions GL-1 in the same row. Two adjacent first gate signal line portions in the plurality of first gate signal line portions GL-1 are connected through separate third gate signal line portions in the plurality of third gate signal line portions GL-3.

[0393] In some embodiments, each of the plurality of gate signal lines includes a plurality of first gate signal line portions GL-1, a plurality of second gate signal line portions GL-2, and a plurality of third gate signal line portions GL-3. The plurality of first gate signal line portions GL-1 and the plurality of second gate signal line portions GL-2 are located in two different layers; and the plurality of first gate signal line portions GL-1 and the plurality of third gate signal line portions GL-3 are located in two different layers. Optionally, the plurality of second gate signal line portions GL-2 and the plurality of third gate signal line portions GL-3 are located in the same layer. In one example, the plurality of first gate signal line portions GL-1 are located in a first conductive layer, the plurality of second gate signal line portions GL-2 are located in a first signal line layer, and the plurality of third gate signal line portions GL-3 are located in a first signal line layer. In the plurality of light-transmitting regions TR, there are no signal lines or electrodes in the first conductive layer, the second conductive layer, the first signal line layer, the third signal line layer, and the anode layer.

[0394] In some embodiments, each of the plurality of second gate signal line portions GL-2 is connected to two adjacent first gate signal line portions GL-1. Each of the plurality of third gate signal line portions GL-3 is connected to two adjacent first gate signal line portions GL-1. Two adjacent first gate signal line portions in GL-1 are connected via individual second gate signal line portions in GL-2 and via individual third gate signal line portions in GL-3. Two adjacent first gate signal line portions in GL-1, individual second gate signal line portions in GL-2, and individual third gate signal line portions in GL-3 form a second ring that substantially surrounds the region of the transistor and capacitor of the pixel driving circuit having a sub-pixel. In one example, the second ring substantially surrounds the region of the transistor and capacitor having a corresponding first sub-pixel. In another example, the second ring substantially surrounds the region of the transistor and capacitor having a sub-pixel of a first color. In another example, the second ring essentially surrounds the area containing transistors and capacitors with red subpixels.

[0395] In some embodiments, the array substrate includes a plurality of second rings LPS2 arranged in a row. Optionally, the plurality of second rings LPS2 respectively substantially surround the region of the pixel driving circuitry of a sub-pixel of the same color. Each of the plurality of second rings LPS2 substantially surrounds the region of the pixel driving circuitry of a sub-pixel of the same color. In one example, the plurality of second rings LPS2 substantially surround the region of the pixel driving circuitry of a red sub-pixel.

[0396] In some embodiments, a plurality of second rings LPS2 substantially surround the region of the anode of a sub-pixel having the same color. Each of the plurality of second rings LPS2 substantially surrounds the region of the anode of a sub-pixel having the same color. In one example, the plurality of second rings LPS2 substantially surround the region of the anode having a red sub-pixel.

[0397] Figure 36 This is a schematic diagram illustrating a gate scan signal network in a portion of an array substrate according to some embodiments of the present disclosure. In some embodiments, reference is made to... Figure 36The subpixels in the array substrate are arranged in multiple rows and columns. In the m-th row of subpixels Rm, the array substrate includes a row of first subpixels. In the (m+1)-th row of subpixels R(m+1), the array substrate includes a row of third subpixels. In the (m+2)-th row of subpixels R(m+2), the array substrate includes a row of second subpixels. Optionally, a row of first subpixels is a row of subpixels of a first color, a row of second subpixels is a row of subpixels of a second color, and a row of third subpixels is a row of subpixels of a third color. Figure 36 The text represents the corresponding first sub-pixel sp1, the corresponding second sub-pixel sp2, and the corresponding third sub-pixel sp3.

[0398] In some embodiments, in the nth column of sub-pixels Cn, the array substrate includes a column of third sub-pixels. In the (n-1)th column of sub-pixels C(n-1), the array substrate includes a column of alternating first and second sub-pixels. In the (n+1)th column of sub-pixels C(n+1), the array substrate includes a column of alternating first and second sub-pixels. Optionally, the column of third sub-pixels is a column of sub-pixels of a third color, and the column of alternating first and second sub-pixels is a column of alternating first and second color sub-pixels. Optionally, in the nth column of sub-pixels Cn, each of the plurality of light-transmitting regions TR separates two adjacent third sub-pixels.

[0399] Reference Figure 2A , Figure 2B , Figures 3A to 3M , Figures 30A to 30L and Figure 36 In some embodiments, the first gate signal line portion of the plurality of first gate signal line portions GL-1 is connected to the gate of one or more data write transistors in the pixel driving circuit of the third sub-pixel in the nth column sub-pixel Cn and the (m+1)th row sub-pixel R(m+1), connected to the gate of one or more data write transistors in the pixel driving circuit of the first sub-pixel in the (n-1)th column sub-pixel C(n-1) and the mth row sub-pixel Rm, and connected to the gate of one or more data write transistors in the pixel driving circuit of the second sub-pixel in the (n+1)th column sub-pixel C(n+1) and the (m+2)th row sub-pixel R(m+2).

[0400] In some embodiments, the second gate signal line portion of the plurality of second gate signal line portions GL-2 connects the first gate signal line portion to the first adjacent first gate signal line portion, and the first adjacent first gate signal line portion is connected to the gate of one or more data writing transistors in the pixel driving circuit of the second sub-pixel in the (n-1)th column sub-pixel C(n-1) and the (m+2)th row sub-pixel R(m+2).

[0401] In some embodiments, the third gate signal line portion of the plurality of third gate signal line portions GL-3 connects the first gate signal line portion to the second adjacent first gate signal line portion, and the second adjacent first gate signal line portion is connected to the gate of one or more data writing transistors in the pixel driving circuit of the first sub-pixel in the (n+1)th column sub-pixel C(n+1) and the mth row sub-pixel Rm.

[0402] Figure 37 This is a schematic diagram illustrating a reset control signal network in a portion of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 30A , Figure 30C , Figure 30H and Figure 37 Each of the plurality of reset control signal lines includes a plurality of first reset control signal line portions rst-1 and a plurality of second reset control signal line portions rst-2. The plurality of first reset control signal line portions rst-1 and the plurality of second reset control signal line portions rst-2 are located in two different layers. In one example, the plurality of first reset control signal line portions rst-1 are located in a first conductive layer, and the plurality of second reset control signal line portions rst-2 are located in a first signal line layer. Each second reset control signal line portion in the plurality of second reset control signal line portions rst-2 is respectively connected to two adjacent first reset control signal line portions in the plurality of first reset control signal line portions rst-1. Two adjacent first reset control signal line portions in the plurality of first reset control signal line portions rst-1 are connected through individual second reset control signal line portions in the plurality of second reset control signal line portions rst-2.

[0403] In some embodiments, each of the plurality of reset control signal lines includes a plurality of first reset control signal line portions rst-1 and a plurality of third reset control signal line portions rst-3. The plurality of first reset control signal line portions rst-1 and the plurality of third reset control signal line portions rst-3 are located in two different layers. In one example, the plurality of first reset control signal line portions rst-1 are located in a first conductive layer, and the plurality of third reset control signal line portions rst-3 are located in a first signal line layer. Each third reset control signal line portion rst-3 is respectively connected to two adjacent first reset control signal line portions rst-1 in the same row. Two adjacent first reset control signal line portions rst-1 are connected via individual third reset control signal line portions rst-3.

[0404] In some embodiments, each of the plurality of reset control signal lines includes a plurality of first reset control signal line portions rst-1, a plurality of second reset control signal line portions rst-2, and a plurality of third reset control signal line portions rst-3. The plurality of first reset control signal line portions rst-1 and the plurality of second reset control signal line portions rst-2 are located in two different layers; and the plurality of first reset control signal line portions rst-1 and the plurality of third reset control signal line portions rst-3 are located in two different layers. Optionally, the plurality of second reset control signal line portions rst-2 and the plurality of third reset control signal line portions rst-3 are located in the same layer. In one example, the plurality of first reset control signal line portions rst-1 are located in a first conductive layer, the plurality of second reset control signal line portions rst-2 are located in a first signal line layer, and the plurality of third reset control signal line portions rst-3 are located in a first signal line layer. In the plurality of light-transmitting regions TR, there are no signal lines or electrodes in the first conductive layer, the second conductive layer, the first signal line layer, the third signal line layer, and the anode layer.

[0405] In some embodiments, each of the plurality of second reset control signal line portions rst-2 is connected to two adjacent first reset control signal line portions rst-1. Each of the plurality of third reset control signal line portions rst-3 is connected to two adjacent first reset control signal line portions rst-1. Two adjacent first reset control signal line portions rst-1 are connected via individual second reset control signal line portions rst-2 and via individual third reset control signal line portions rst-3. The two adjacent first reset control signal line portions rst-1, the individual second reset control signal line portions rst-2, and the individual third reset control signal line portions rst-3 form a third ring, which substantially surrounds the region of the transistor and capacitor of the pixel driving circuit having sub-pixels. In one example, the third ring essentially surrounds the region with the transistor and capacitor corresponding to the first sub-pixel. In another example, the third ring essentially surrounds the region with the transistor and capacitor of the first color sub-pixel. In yet another example, the third ring essentially surrounds the region with the transistor and capacitor of the red sub-pixel.

[0406] In some embodiments, the array substrate includes a plurality of third rings LPS3 arranged in a row. Optionally, the plurality of third rings LPS3 respectively surround the region of the pixel driving circuit of a sub-pixel of the same color. Each of the plurality of third rings LPS3 surrounds the region of the pixel driving circuit of a sub-pixel of the same color. In one example, the plurality of third rings LPS3 surround the region of the pixel driving circuit of a red sub-pixel.

[0407] In some embodiments, the plurality of third rings LPS3 substantially surround the region of the anode of the sub-pixel having the same color. Each of the plurality of third rings LPS3 substantially surrounds the region of the anode of the sub-pixel having the same color. In one example, the plurality of third rings LPS3 substantially surround the region of the anode having a red sub-pixel.

[0408] Figure 38 This is a schematic diagram illustrating a reset control signal network in a portion of an array substrate according to some embodiments of the present disclosure. In some embodiments, reference is made to... Figure 38 The subpixels in the array substrate are arranged in multiple rows and columns. In the m-th row of subpixels Rm, the array substrate includes a row of first subpixels. In the (m+1)-th row of subpixels R(m+1), the array substrate includes a row of third subpixels. In the (m+2)-th row of subpixels R(m+2), the array substrate includes a row of second subpixels. Optionally, a row of first subpixels is a row of subpixels of a first color, a row of second subpixels is a row of subpixels of a second color, and a row of third subpixels is a row of subpixels of a third color. Figure 38 The text represents the corresponding first sub-pixel sp1, the corresponding second sub-pixel sp2, and the corresponding third sub-pixel sp3.

[0409] In some embodiments, in the nth column of sub-pixels Cn, the array substrate includes a column of third sub-pixels. In the (n-1)th column of sub-pixels C(n-1), the array substrate includes a column of alternating first and second sub-pixels. In the (n+1)th column of sub-pixels C(n+1), the array substrate includes a column of alternating first and second sub-pixels. Optionally, the column of third sub-pixels is a column of sub-pixels of a third color, and the column of alternating first and second sub-pixels is a column of alternating first and second color sub-pixels. Optionally, in the nth column of sub-pixels Cn, each of the plurality of light-transmitting regions TR separates two adjacent third sub-pixels.

[0410] Reference Figure 2A , Figure 2B , Figures 3A to 3M , Figures 30A to 30L and Figure 38In some embodiments, the first reset control signal line portion of the plurality of first reset control signal line portions rst-1 is connected to the gate of one or more reset control transistors in the pixel driving circuit of the third sub-pixel in the nth column sub-pixel Cn and the (m+1)th row sub-pixel R(m+1), connected to the gate of one or more reset control transistors in the pixel driving circuit of the first sub-pixel in the (n-1)th column sub-pixel C(n-1) and the mth row sub-pixel Rm, and connected to the gate of one or more reset control transistors in the pixel driving circuit of the second sub-pixel in the (n+1)th column sub-pixel C(n+1) and the (m+2)th row sub-pixel R(m+2).

[0411] In some embodiments, the second reset control signal line portion in the plurality of second reset control signal line portions rst-2 connects the first reset control signal line portion to the first adjacent first reset control signal line portion, and the first adjacent first reset control signal line portion is connected to the gate of one or more reset control transistors in the pixel driving circuit of the second sub-pixel in the (n-1)th column sub-pixel C(n-1) and the (m+2)th row sub-pixel R(m+2).

[0412] In some embodiments, the third reset control signal line portion of the plurality of third reset control signal line portions rst-3 connects the first reset control signal line portion to the second adjacent first reset control signal line portion, and the second adjacent first reset control signal line portion is connected to the gate of one or more reset control transistors in the pixel driving circuit of the first sub-pixel in the (n+1)th column sub-pixel C(n+1) and the mth row sub-pixel Rm.

[0413] Figure 39 This is a schematic diagram illustrating a light-emitting control signal network in a portion of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 30A , Figure 30C , Figure 30H and Figure 39Each of the plurality of light-emitting control signal lines includes a plurality of first light-emitting control signal line portions em-1 and a plurality of second light-emitting control signal line portions em-2. The plurality of first light-emitting control signal line portions em-1 and the plurality of second light-emitting control signal line portions em-2 are located in two different layers. In one example, the plurality of first light-emitting control signal line portions em-1 are located in a first conductive layer, and the plurality of second light-emitting control signal line portions em-2 are located in a first signal line layer. Each second light-emitting control signal line portion in the plurality of second light-emitting control signal line portions em-2 is respectively connected to two adjacent first light-emitting control signal line portions in the plurality of first light-emitting control signal line portions em-1. Two adjacent first light-emitting control signal line portions in the plurality of first light-emitting control signal line portions em-1 are connected through individual second light-emitting control signal line portions in the plurality of second light-emitting control signal line portions em-2.

[0414] In some embodiments, each of the plurality of light-emitting control signal lines includes a plurality of first light-emitting control signal line portions em-1 and a plurality of third light-emitting control signal line portions em-3. The plurality of first light-emitting control signal line portions em-1 and the plurality of third light-emitting control signal line portions em-3 are located in two different layers. In one example, the plurality of first light-emitting control signal line portions em-1 are located in a first conductive layer, and the plurality of third light-emitting control signal line portions em-3 are located in a first signal line layer. Each third light-emitting control signal line portion em-3 is respectively connected to two adjacent first light-emitting control signal line portions em-1 in the same row. Two adjacent first light-emitting control signal line portions em-1 are connected through individual third light-emitting control signal line portions em-3.

[0415] In some embodiments, each of the plurality of light-emitting control signal lines includes a plurality of first light-emitting control signal line portions em-1, a plurality of second light-emitting control signal line portions em-2, and a plurality of third light-emitting control signal line portions em-3. The plurality of first light-emitting control signal line portions em-1 and the plurality of second light-emitting control signal line portions em-2 are located in two different layers; and the plurality of first light-emitting control signal line portions em-1 and the plurality of third light-emitting control signal line portions em-3 are located in two different layers. Optionally, the plurality of second light-emitting control signal line portions em-2 and the plurality of third light-emitting control signal line portions em-3 are located in the same layer. In one example, the plurality of first light-emitting control signal line portions em-1 are located in a first conductive layer, the plurality of second light-emitting control signal line portions em-2 are located in a first signal line layer, and the plurality of third light-emitting control signal line portions em-3 are located in a first signal line layer. In the plurality of light-transmitting regions TR, there are no signal lines or electrodes in the first conductive layer, the second conductive layer, the first signal line layer, the third signal line layer, and the anode layer.

[0416] In some embodiments, each of the plurality of second light-emitting control signal line portions em-2 is connected to two adjacent first light-emitting control signal line portions em-1. Each of the plurality of third light-emitting control signal line portions em-3 is connected to two adjacent first light-emitting control signal line portions em-1. Two adjacent first light-emitting control signal line portions em-1 are connected via individual second light-emitting control signal line portions em-2 and via individual third light-emitting control signal line portions em-3. The two adjacent first light-emitting control signal line portions em-1, the individual second light-emitting control signal line portions em-2, and the individual third light-emitting control signal line portions em-3 form a fourth ring, which substantially surrounds the region of the transistor and capacitor of the pixel driving circuit having a sub-pixel. In one example, the fourth ring substantially surrounds the region of the transistor and capacitor having a corresponding first sub-pixel. In another example, the fourth ring essentially surrounds the area of ​​transistors and capacitors with the first color subpixel. In yet another example, the fourth ring essentially surrounds the area of ​​transistors and capacitors with the red subpixel.

[0417] In some embodiments, the array substrate includes a plurality of fourth rings LPS4 arranged in a row. Optionally, the plurality of fourth rings LPS4 respectively substantially surround the region of the pixel driving circuit of a sub-pixel of the same color. Each of the plurality of fourth rings LPS4 substantially surrounds the region of the pixel driving circuit of a sub-pixel of the same color. In one example, the plurality of fourth rings LPS4 substantially surround the region of the pixel driving circuit of a red sub-pixel.

[0418] In some embodiments, a plurality of fourth rings LPS4 substantially surround the region of the anode of a sub-pixel having the same color. Each of the plurality of fourth rings LPS4 substantially surrounds the region of the anode of a sub-pixel having the same color. In one example, the plurality of fourth rings LPS4 substantially surround the region of the anode having a red sub-pixel.

[0419] Figure 40 This is a schematic diagram illustrating a light-emitting control signal network in a portion of an array substrate according to some embodiments of the present disclosure. In some embodiments, reference is made to... Figure 40 The subpixels in the array substrate are arranged in multiple rows and columns. In the m-th row of subpixels Rm, the array substrate includes a row of first subpixels. In the (m+1)-th row of subpixels R(m+1), the array substrate includes a row of third subpixels. In the (m+2)-th row of subpixels R(m+2), the array substrate includes a row of second subpixels. Optionally, a row of first subpixels is a row of subpixels of a first color, a row of second subpixels is a row of subpixels of a second color, and a row of third subpixels is a row of subpixels of a third color. Figure 40 The text represents the corresponding first sub-pixel sp1, the corresponding second sub-pixel sp2, and the corresponding third sub-pixel sp3.

[0420] In some embodiments, in the nth column of sub-pixels Cn, the array substrate includes a column of third sub-pixels. In the (n-1)th column of sub-pixels C(n-1), the array substrate includes a column of alternating first and second sub-pixels. In the (n+1)th column of sub-pixels C(n+1), the array substrate includes a column of alternating first and second sub-pixels. Optionally, the column of third sub-pixels is a column of sub-pixels of a third color, and the column of alternating first and second sub-pixels is a column of alternating first and second color sub-pixels. Optionally, in the nth column of sub-pixels Cn, each of the plurality of light-transmitting regions TR separates two adjacent third sub-pixels.

[0421] Reference Figure 2A , Figure 2B , Figures 3A to 3M , Figures 30A to 30L and Figure 40In some embodiments, the first light emission control signal line portion em-1 of the plurality of first light emission control signal line portions is connected to the gate of one or more light emission control transistors in the pixel driving circuit of the third sub-pixel in the nth column sub-pixel Cn and the (m+1)th row sub-pixel R(m+1), connected to the gate of one or more light emission control transistors in the pixel driving circuit of the first sub-pixel in the (n-1)th column sub-pixel C(n-1) and the mth row sub-pixel Rm, and connected to the gate of one or more light emission control transistors in the pixel driving circuit of the second sub-pixel in the (n+1)th column sub-pixel C(n+1) and the (m+2)th row sub-pixel R(m+2).

[0422] In some embodiments, the second light emission control signal line portion in the plurality of second light emission control signal line portions em-2 connects the first light emission control signal line portion to the first adjacent first light emission control signal line portion, and the first adjacent first light emission control signal line portion is connected to the gate of one or more light emission control transistors in the pixel driving circuit of the second sub-pixel in the (n-1)th column sub-pixel C(n-1) and the (m+2)th row sub-pixel R(m+2).

[0423] In some embodiments, the third light emission control signal line portion of the plurality of third light emission control signal line portions em-3 connects the first light emission control signal line portion to the second adjacent first light emission control signal line portion, and the second adjacent first light emission control signal line portion is connected to the gate of one or more light emission control transistors in the pixel driving circuit of the first sub-pixel in the (n+1)th column sub-pixel C(n+1) and the mth row sub-pixel Rm.

[0424] Reference Figure 30A , Figure 30C , Figure 30H and Figures 33 to 40 In some embodiments, the array substrate includes a plurality of signal lines, each of which includes a plurality of first signal line portions and a plurality of second signal line portions. The plurality of first signal line portions and the plurality of second signal line portions are located in two different layers. In one example, the plurality of first signal line portions are located in a first conductive layer, and the plurality of second signal line portions are located in the first signal line layer. In another example, the plurality of first signal line portions are located in a second conductive layer, and the plurality of second signal line portions are located in the first signal line layer. Each of the plurality of second signal line portions is respectively connected to two adjacent first signal line portions. Two adjacent first signal line portions are connected through individual second signal line portions.

[0425] In some embodiments, each of the plurality of signal lines includes a plurality of first signal line portions and a plurality of third signal line portions. The plurality of first signal line portions and the plurality of third signal line portions are located in two different layers. In one example, the plurality of first signal line portions are located in a first conductive layer, and the plurality of third signal line portions are located in the first signal line layer. In another example, the plurality of first signal line portions are located in a second conductive layer, and the plurality of third signal line portions are located in the first signal line layer. Each of the plurality of third signal line portions is respectively connected to two adjacent first signal line portions in the same row. Two adjacent first signal line portions are connected through a separate third signal line portion.

[0426] In some embodiments, each of the plurality of signal lines includes a plurality of first signal line portions, a plurality of second signal line portions, and a plurality of third signal line portions. The plurality of first signal line portions and the plurality of second signal line portions are located in two different layers; and the plurality of first signal line portions and the plurality of third signal line portions are located in two different layers. Optionally, the plurality of second signal line portions and the plurality of third signal line portions are located in the same layer. In one example, the plurality of first signal line portions are located in a first conductive layer, the plurality of second signal line portions are located in a first signal line layer, and the plurality of third signal line portions are located in a first signal line layer. In one example, the plurality of first signal line portions are located in a second conductive layer, the plurality of second signal line portions are located in a first signal line layer, and the plurality of third signal line portions are located in a first signal line layer. In the plurality of light-transmitting regions TR, there are no signal lines or electrodes in the first conductive layer, the second conductive layer, the first signal line layer, the third signal line layer, and the anode layer.

[0427] In some embodiments, each of the plurality of second signal line portions is connected to two adjacent first signal line portions of the plurality of first signal line portions. Each of the plurality of third signal line portions is connected to two adjacent first signal line portions of the plurality of first signal line portions. Two adjacent first signal line portions of the plurality of first signal line portions are connected via individual second signal line portions of the plurality of second signal line portions and via individual third signal line portions of the plurality of third signal line portions. Two adjacent first signal line portions of the plurality of first signal line portions, individual second signal line portions of the plurality of second signal line portions, and individual third signal line portions of the plurality of third signal line portions form a loop that substantially surrounds the region of the transistor and capacitor of the pixel driving circuit having a sub-pixel. In one example, the loop substantially surrounds the region of the transistor and capacitor having a corresponding first sub-pixel. In another example, the loop substantially surrounds the region of the transistor and capacitor having a sub-pixel of a first color. In yet another example, the loop substantially surrounds the region of the transistor and capacitor having a red sub-pixel.

[0428] In some embodiments, the array substrate includes a plurality of rings arranged in a row. Optionally, the plurality of rings respectively surround a region of pixel driving circuitry for a sub-pixel of the same color. Each ring in the plurality of rings surrounds a region of pixel driving circuitry for a sub-pixel of the same color. In one example, the plurality of rings surround a region of pixel driving circuitry for a red sub-pixel.

[0429] In some embodiments, the plurality of rings substantially surround the region of the anode of a sub-pixel having the same color. Each of the plurality of rings substantially surrounds the region of the anode of a sub-pixel having the same color. In one example, the plurality of rings substantially surround the region of the anode having a red sub-pixel.

[0430] In some embodiments, the subpixels in the array substrate are arranged in multiple rows and columns. In the m-th row of subpixels Rm, the array substrate includes a row of first subpixels. In the (m+1)-th row of subpixels R(m+1), the array substrate includes a row of third subpixels. In the (m+2)-th row of subpixels R(m+2), the array substrate includes a row of second subpixels. Optionally, a row of first subpixels is a row of subpixels of a first color, a row of second subpixels is a row of subpixels of a second color, and a row of third subpixels is a row of subpixels of a third color. The first color, the second color, and the third color are three different colors. In one example, the first color is red, the second color is green, and the third color is blue.

[0431] In some embodiments, in the nth column of sub-pixels Cn, the array substrate includes a column of third sub-pixels. In the (n-1)th column of sub-pixels C(n-1), the array substrate includes a column of alternating first and second sub-pixels. In the (n+1)th column of sub-pixels C(n+1), the array substrate includes a column of alternating first and second sub-pixels. Optionally, the column of third sub-pixels is a column of sub-pixels of a third color, and the column of alternating first and second sub-pixels is a column of alternating first and second color sub-pixels. Optionally, in the nth column of sub-pixels Cn, each of the plurality of light-transmitting regions TR separates two adjacent third sub-pixels.

[0432] Reference Figure 2A , Figure 2B , Figures 3A to 3M , Figures 30A to 30L as well as Figures 33 to 40 In some embodiments, a first signal line portion of a plurality of first signal line portions is connected to one or more transistors in the pixel driving circuit of the third sub-pixel in the nth column sub-pixel Cn and the (m+1)th row sub-pixel R(m+1), connected to one or more transistors in the pixel driving circuit of the first sub-pixel in the (n-1)th column sub-pixel C(n-1) and the mth row sub-pixel Rm, and connected to one or more transistors in the pixel driving circuit of the second sub-pixel in the (n+1)th column sub-pixel C(n+1) and the (m+2)th row sub-pixel R(m+2).

[0433] In some embodiments, a second signal line portion of a plurality of second signal line portions connects a first signal line portion to a first adjacent first signal line portion, and the first adjacent first signal line portion is connected to one or more transistors in the pixel driving circuit of the second sub-pixel in the (n-1)th column sub-pixel C(n-1) and the (m+2)th row sub-pixel R(m+2).

[0434] In some embodiments, a third signal line portion of a plurality of third signal line portions is connected to a first signal line portion and a second adjacent first signal line portion, and the second adjacent first signal line portion is connected to one or more transistors in the pixel driving circuit of the first sub-pixel in the (n+1)th column sub-pixel C(n+1) and the mth row sub-pixel Rm.

[0435] On the other hand, the present invention provides a display device comprising an array substrate manufactured as described herein or by means of the methods described herein, and one or more integrated circuits connected to the array substrate. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, laptops, digital photo albums, GPS, etc. Optionally, the display device is an organic light-emitting diode (OLED) display device. Optionally, the display device is a miniature OLED display device. Optionally, the display device is a miniature OLED display device.

[0436] On the other hand, this disclosure provides a method for manufacturing an array substrate. In some embodiments, the method includes forming a plurality of signal lines. Optionally, forming each of the plurality of signal lines includes forming a plurality of first signal line portions, forming a plurality of second signal line portions, and forming a plurality of third signal line portions. Optionally, the plurality of first signal line portions and the plurality of second signal line portions are formed in two different layers. Optionally, the plurality of first signal line portions and the plurality of third signal line portions are located in two different layers. Optionally, each of the plurality of second signal line portions is respectively connected to two adjacent first signal line portions. Optionally, each of the plurality of third signal line portions is respectively connected to two adjacent first signal line portions. Optionally, two individual first signal line portions, an individual second signal line portion, and an individual third signal line portion form a loop, the loop substantially surrounding a region of transistors and capacitors of a pixel driving circuit having sub-pixels. Optionally, the two separate first signal line portions are connected via a separate second signal line portion and via a separate third signal line portion.

[0437] For illustrative and descriptive purposes, the foregoing description of embodiments of the invention has been provided. It is not exhaustive, nor is it intended to limit the invention to the precise forms or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Clearly, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to explain the principles of the invention and its best mode of practical application, thereby enabling those skilled in the art to understand the various embodiments of the invention and the various modifications suitable for the particular use or implementation contemplated. The scope of the invention is intended to be defined by the appended claims and their equivalents, wherein, unless otherwise stated, all terms are to be interpreted in their broadest reasonable sense. Therefore, the terms “the invention,” “the present invention,” etc., do not necessarily limit the scope of the claims to the specific embodiments, and references to exemplary embodiments of the invention do not imply limitation of the invention, nor should such limitation be inferred. The invention is defined only by the spirit and scope of the appended claims. Furthermore, these claims may involve the use of “first,” “second,” etc., followed by nouns or elements. These terms should be understood as nomenclature and should not be construed as limiting the number of elements modified by these nomenclatures unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the invention. It should be understood that changes to the described embodiments can be made by those skilled in the art without departing from the scope of the invention as defined by the appended claims. Furthermore, the elements and components in this disclosure are not intended for public distribution, whether or not they are expressly recited in the appended claims.

Claims

1. An array substrate comprising a plurality of signal lines; in, Each of the plurality of signal lines includes a plurality of first signal line portions, a plurality of second signal line portions, and a plurality of third signal line portions; The plurality of first signal line portions and the plurality of second signal line portions are located in two different layers; The plurality of first signal line portions and the plurality of third signal line portions are located in two different layers; Each of the plurality of second signal line portions is respectively connected to two adjacent first signal line portions among the plurality of first signal line portions; Each of the plurality of third signal line portions is respectively connected to two adjacent first signal line portions among the plurality of first signal line portions; Two individual first signal line portions of the plurality of first signal line portions, a single second signal line portion of the plurality of second signal line portions, and a single third signal line portion of the plurality of third signal line portions form a loop, the loop substantially surrounding the region of the transistor and capacitor of the pixel driving circuit having sub-pixels; as well as The two separate first signal line portions are connected via the separate second signal line portion and via the separate third signal line portion.

2. The array substrate according to claim 1, comprising a plurality of rings arranged in a row in sequence; in, The plurality of rings respectively surround the region of the pixel driving circuit of the sub-pixels of the same color; and Each of the plurality of rings substantially surrounds the region of the pixel driving circuitry of the sub-pixel of the same color; the substantially surrounding indicates at least 50% surrounding.

3. The array substrate according to claim 1, comprising a plurality of rings arranged in a row in sequence; in, The plurality of rings respectively surround substantially the region of the anode of a sub-pixel having the same color; and Each of the plurality of rings substantially surrounds the region of the anode of the sub-pixel having the same color.

4. The array substrate according to any one of claims 1 to 3, wherein, Subpixels are arranged in multiple rows and columns; In the m-th row of sub-pixels, the array substrate includes a row of first sub-pixels of a first color; In the (m+1)th row of sub-pixels, the array substrate includes a row of third sub-pixels of the third color; In the (m+2)th row of sub-pixels, the array substrate includes a row of second sub-pixels of the second color; In the nth column of sub-pixels, the array substrate includes a column of third sub-pixels of the third color; In the (n-1)th column of sub-pixels, the array substrate includes a column of alternating first sub-pixels of the first color and second sub-pixels of the second color; In the (n+1)th column of sub-pixels, the array substrate includes a column of alternating first sub-pixels of the first color and second sub-pixels of the second color; The first signal line portion of the plurality of first signal line portions is connected to one or more transistors in the pixel driving circuit of the third sub-pixel in the nth column sub-pixel and the (m+1)th row sub-pixel, connected to one or more transistors in the pixel driving circuit of the first sub-pixel in the (n-1)th column sub-pixel and the mth row sub-pixel, and connected to one or more transistors in the pixel driving circuit of the second sub-pixel in the (n+1)th column sub-pixel and the (m+2)th row sub-pixel.

5. The array substrate according to claim 4, wherein, The second signal line portion of the plurality of second signal line portions connects the first signal line portion to the first adjacent first signal line portion, and the first adjacent first signal line portion is connected to one or more transistors in the pixel driving circuit of the second sub-pixel in the (n-1)th column sub-pixel and the (m+2)th row sub-pixel.

6. The array substrate according to claim 4, wherein, The third signal line portion of the plurality of third signal line portions connects the first signal line portion to the second adjacent first signal line portion, and the second adjacent first signal line portion is connected to one or more transistors in the pixel driving circuit of the first sub-pixel in the (n+1)th column sub-pixel and the first sub-pixel in the mth row sub-pixel.

7. The array substrate according to claim 4 further includes a plurality of light-transmitting areas; in, In the nth column of sub-pixels, each of the plurality of light-transmitting regions separates two adjacent third sub-pixels.

8. The array substrate according to any one of claims 1 to 3, wherein, The plurality of signal lines includes a plurality of initialization signal lines; The plurality of first signal line portions include a plurality of first initialization signal line portions; The plurality of second signal line portions include a plurality of second initialization signal line portions; and The plurality of third signal line portions include a plurality of third initialization signal line portions.

9. The array substrate according to any one of claims 1 to 3, wherein, The plurality of signal lines includes a plurality of gate signal lines; The plurality of first signal line portions include a plurality of first gate signal line portions; The plurality of second signal line portions include a plurality of second gate signal line portions; and The plurality of third signal line portions include a plurality of third gate signal line portions.

10. The array substrate according to any one of claims 1 to 3, wherein, The plurality of signal lines includes a plurality of reset control signal lines; The plurality of first signal line portions include a plurality of first reset control signal line portions; The plurality of second signal line portions include a plurality of second reset control signal line portions; and The plurality of third signal line portions include a plurality of third reset control signal line portions.

11. The array substrate according to any one of claims 1 to 3, wherein, The plurality of signal lines includes a plurality of light emission control signal lines; The plurality of first signal line portions include a plurality of first light emission control signal line portions; The plurality of second signal line portions include a plurality of second light emission control signal line portions; and The plurality of third signal line portions include a plurality of third light emission control signal line portions.

12. The array substrate according to any one of claims 1 to 3, further comprising a plurality of light-transmitting regions; in, The array substrate includes a first conductive layer, a second conductive layer, a first signal line layer, a third signal line layer, and an anode layer; In the plurality of light-transmitting regions, there are no signal lines and electrodes of the first conductive layer, the second conductive layer, the first signal line layer, the third signal line layer, and the anode layer.

13. The array substrate according to claim 12, further comprising a second signal line layer; in, The signal lines located in the second signal line layer comprise a substantially transparent conductive material; as well as The signal lines of the second signal line layer are present in the plurality of light-transmitting regions.

14. The array substrate according to claim 13, wherein, The plurality of second signal line portions and the plurality of third signal line portions are located in the second signal line layer; and The plurality of first signal lines are located in the first conductive layer or the second conductive layer.

15. The array substrate according to any one of claims 1 to 3, further comprising a plurality of voltage supply lines and a plurality of voltage connection bridges located in two different layers; The multiple voltage connection bridges are arranged in an array of multiple rows and columns; Two adjacent voltage connection bridges in the same pixel row are connected to the same voltage supply line in the plurality of voltage supply lines; and The voltage connection bridges in the same pixel column are connected to the same adjacent voltage supply lines in the multiple voltage supply lines.

16. The array substrate according to claim 15, wherein, The plurality of voltage supply lines include a first adjacent voltage supply line, a second adjacent voltage supply line, and a third adjacent voltage supply line; The first adjacent voltage supply line is configured to provide a voltage supply signal to the first pixel driving circuit in the corresponding first sub-pixel, the second adjacent voltage supply line is configured to provide a voltage supply signal to the second pixel driving circuit in the corresponding second sub-pixel, and the third adjacent voltage supply line is configured to provide a voltage supply signal to the third pixel driving circuit in the corresponding third sub-pixel. as well as Each of the plurality of voltage connection bridges is respectively connected to the first adjacent voltage supply line, the second adjacent voltage supply line, and the third adjacent voltage supply line.

17. The array substrate according to claim 16, wherein, Each of the first adjacent voltage supply line, the second adjacent voltage supply line, and the third adjacent voltage supply line includes a plurality of alternating first voltage supply line portions and a plurality of second voltage supply line portions; Each of the plurality of voltage connection bridges is respectively connected to the first adjacent voltage supply line portion and the second adjacent voltage supply line portion of the first adjacent voltage supply line, respectively connected to the first adjacent voltage supply line portion and the second adjacent voltage supply line portion of the second adjacent voltage supply line, and respectively connected to the first adjacent voltage supply line portion and the second adjacent voltage supply line portion of the third adjacent voltage supply line.

18. The array substrate according to claim 15, wherein, The plurality of voltage supply lines includes a first adjacent voltage supply line and a second adjacent voltage supply line; Each of the plurality of voltage supply lines is connected to two adjacent columns of voltage connection bridges in the plurality of voltage connection bridges; and Each of the plurality of voltage connection bridges is connected to the first adjacent voltage supply line and to the second adjacent voltage supply line.

19. The array substrate according to claim 15, wherein, Each of the plurality of voltage connection bridges includes a second capacitor electrode of a plurality of pixel driving circuits.

20. A display device comprising an array substrate according to any one of claims 1 to 19, and one or more integrated circuits connected to the array substrate.

21. An array substrate comprising a plurality of voltage supply lines and a plurality of voltage connection bridges located in two different layers; in, The multiple voltage connection bridges are arranged in an array of multiple rows and columns; Two adjacent voltage connection bridges in the same pixel row are connected to the same voltage supply line in the multiple voltage supply lines; as well as The voltage connection bridges in the same pixel column are connected to the same adjacent voltage supply lines in the multiple voltage supply lines.

22. The array substrate according to claim 21, wherein, The plurality of voltage supply lines include a first adjacent voltage supply line, a second adjacent voltage supply line, and a third adjacent voltage supply line; The first adjacent voltage supply line is configured to provide a voltage supply signal to the first pixel driving circuit in the corresponding first sub-pixel, the second adjacent voltage supply line is configured to provide a voltage supply signal to the second pixel driving circuit in the corresponding second sub-pixel, and the third adjacent voltage supply line is configured to provide a voltage supply signal to the third pixel driving circuit in the corresponding third sub-pixel. as well as Each of the plurality of voltage connection bridges is respectively connected to the first adjacent voltage supply line, the second adjacent voltage supply line, and the third adjacent voltage supply line.

23. The array substrate according to claim 22, wherein, Each of the first adjacent voltage supply line, the second adjacent voltage supply line, and the third adjacent voltage supply line includes a plurality of alternating first voltage supply line portions and a plurality of second voltage supply line portions; Each of the plurality of voltage connection bridges is respectively connected to the first adjacent voltage supply line portion and the second adjacent voltage supply line portion of the first adjacent voltage supply line, respectively connected to the first adjacent voltage supply line portion and the second adjacent voltage supply line portion of the second adjacent voltage supply line, and respectively connected to the first adjacent voltage supply line portion and the second adjacent voltage supply line portion of the third adjacent voltage supply line.

24. The array substrate according to claim 21, wherein, The plurality of voltage supply lines includes a first adjacent voltage supply line and a second adjacent voltage supply line; Each of the plurality of voltage supply lines is connected to two adjacent columns of voltage connection bridges in the plurality of voltage connection bridges; and Each of the plurality of voltage connection bridges is connected to the first adjacent voltage supply line and to the second adjacent voltage supply line.

25. The array substrate according to claim 21, wherein, Each of the plurality of voltage connection bridges includes a second capacitor electrode of a plurality of pixel driving circuits.

26. The array substrate according to any one of claims 21 to 25, further comprising a plurality of signal lines; in, Each of the plurality of signal lines includes a plurality of first signal line portions, a plurality of second signal line portions, and a plurality of third signal line portions; The plurality of first signal line portions and the plurality of second signal line portions are located in two different layers; The plurality of first signal line portions and the plurality of third signal line portions are located in two different layers; Each of the plurality of second signal line portions is respectively connected to two adjacent first signal line portions among the plurality of first signal line portions; Each of the plurality of third signal line portions is respectively connected to two adjacent first signal line portions among the plurality of first signal line portions; Two individual first signal line portions of the plurality of first signal line portions, a single second signal line portion of the plurality of second signal line portions, and a single third signal line portion of the plurality of third signal line portions form a loop, the loop substantially surrounding the region of the transistor and capacitor of the pixel driving circuit having sub-pixels; as well as The two separate first signal line portions are connected via the separate second signal line portion and via the separate third signal line portion.

27. The array substrate of claim 26, comprising a plurality of rings arranged in a row in sequence; in, The plurality of rings respectively surround the region of the pixel driving circuit of the sub-pixels of the same color; and Each of the plurality of rings substantially surrounds the region of the pixel driving circuitry of the sub-pixels of the same color.

28. The array substrate of claim 26, comprising a plurality of rings arranged in a row in sequence; in, The plurality of rings respectively surround substantially the region of the anode of a sub-pixel having the same color; and Each of the plurality of rings substantially surrounds the region of the anode of the sub-pixel having the same color.

29. The array substrate according to claim 26, wherein, Subpixels are arranged in multiple rows and columns; In the m-th row of sub-pixels, the array substrate includes a row of first sub-pixels of a first color; In the (m+1)th row of sub-pixels, the array substrate includes a row of third sub-pixels of the third color; In the (m+2)th row of sub-pixels, the array substrate includes a row of second sub-pixels of the second color; In the nth column of sub-pixels, the array substrate includes a column of third sub-pixels of the third color; In the (n-1)th column of sub-pixels, the array substrate includes a column of alternating first sub-pixels of the first color and second sub-pixels of the second color; In the (n+1)th column of sub-pixels, the array substrate includes a column of alternating first sub-pixels of the first color and second sub-pixels of the second color; The first signal line portion of the plurality of first signal line portions is connected to one or more transistors in the pixel driving circuit of the third sub-pixel in the nth column sub-pixel and the (m+1)th row sub-pixel, connected to one or more transistors in the pixel driving circuit of the first sub-pixel in the (n-1)th column sub-pixel and the mth row sub-pixel, and connected to one or more transistors in the pixel driving circuit of the second sub-pixel in the (n+1)th column sub-pixel and the (m+2)th row sub-pixel.

30. The array substrate according to claim 29, wherein, The second signal line portion of the plurality of second signal line portions connects the first signal line portion to the first adjacent first signal line portion, and the first adjacent first signal line portion is connected to one or more transistors in the pixel driving circuit of the second sub-pixel in the (n-1)th column sub-pixel and the (m+2)th row sub-pixel.

31. The array substrate according to claim 29, wherein, The third signal line portion of the plurality of third signal line portions connects the first signal line portion to the second adjacent first signal line portion, and the second adjacent first signal line portion is connected to one or more transistors in the pixel driving circuit of the first sub-pixel in the (n+1)th column sub-pixel and the first sub-pixel in the mth row sub-pixel.

32. The array substrate according to claim 29 further includes a plurality of light-transmitting areas; in, In the nth column of sub-pixels, each of the plurality of light-transmitting regions separates two adjacent third sub-pixels.

33. The array substrate according to claim 26, wherein, The plurality of signal lines includes a plurality of initialization signal lines; The plurality of first signal line portions include a plurality of first initialization signal line portions; The plurality of second signal line portions include a plurality of second initialization signal line portions; and The plurality of third signal line portions include a plurality of third initialization signal line portions.

34. The array substrate according to claim 26, wherein, The plurality of signal lines includes a plurality of gate signal lines; The plurality of first signal line portions include a plurality of first gate signal line portions; The plurality of second signal line portions include a plurality of second gate signal line portions; and The plurality of third signal line portions include a plurality of third gate signal line portions.

35. The array substrate according to claim 26, wherein, The plurality of signal lines includes a plurality of reset control signal lines; The plurality of first signal line portions include a plurality of first reset control signal line portions; The plurality of second signal line portions include a plurality of second reset control signal line portions; and The plurality of third signal line portions include a plurality of third reset control signal line portions.

36. The array substrate according to claim 26, wherein, The plurality of signal lines includes a plurality of light emission control signal lines; The plurality of first signal line portions include a plurality of first light emission control signal line portions; The plurality of second signal line portions include a plurality of second light emission control signal line portions; and The plurality of third signal line portions include a plurality of third light emission control signal line portions.

37. The array substrate according to claim 26, further comprising a plurality of light-transmitting regions; in, The array substrate includes a first conductive layer, a second conductive layer, a first signal line layer, a third signal line layer, and an anode layer; In the plurality of light-transmitting regions, there are no signal lines and electrodes of the first conductive layer, the second conductive layer, the first signal line layer, the third signal line layer, and the anode layer.

38. The array substrate according to claim 37, further comprising a second signal line layer; in, The signal lines located in the second signal line layer comprise a substantially transparent conductive material; as well as The signal lines of the second signal line layer are present in the plurality of light-transmitting regions.

39. The array substrate according to claim 38, wherein, The plurality of second signal line portions and the plurality of third signal line portions are located in the second signal line layer; and The plurality of first signal lines are located in the first conductive layer or the second conductive layer.

40. A display device comprising an array substrate according to any one of claims 21 to 39, and one or more integrated circuits connected to the array substrate.

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