Method and device for repairing weak memory order problem

Abstract

This application discloses a method and apparatus for repairing weak memory ordering issues, relating to the field of computer technology. The method can automatically repair weak memory ordering issues in a multi-threaded program during the compilation phase. The method comprises: determining a read / write instruction set in the code to be repaired; classifying the instructions in the read / write instruction set to determine a target instruction; and inserting a memory barrier instruction between the read / write instruction preceding the target instruction and the target instruction; wherein the read / write instruction set includes read instructions and / or write instructions in the code to be repaired, and the instructions in the read / write instruction set are used to access memory.

Description

[0001] This application is a divisional application. The application number of the original application is: 202011303988.0, and the original application date is November 19, 2020. The entire content of the original application is incorporated into this application by reference. Technical Field

[0002] The present application relates to the field of computer technology, and in particular to a method and device for repairing weak memory ordering problems. Background Art

[0003] When a multi-threaded program developed based on a non-weak memory model runs on a computer device that uses a weak memory model, the instruction semantics supported by the hardware under different memory models are different. This may cause the threads running in parallel in the program to execute read and write instructions for memory access out of order, resulting in a weak memory order problem.

[0004] For example, when a multi-threaded program developed based on a strong memory model runs on a computer device with a weak memory model, weak memory ordering may occur when the program's parallel threads execute read and write instructions to access memory. This can lead to logical errors in the program's intended functionality, resulting in inaccurate output.

[0005] Based on this, how to fix the weak memory order problem of multi-threaded programs is a technical problem that needs to be solved urgently. Summary of the Invention

[0006] The present application provides a method and apparatus for repairing weak memory ordering problems, which can automatically repair weak memory ordering problems in a multi-threaded program during the compilation phase of the program.

[0007] To achieve the above objectives, this application provides the following technical solutions:

[0008] In a first aspect, the present application provides a method for repairing a weak memory ordering issue, the method comprising: determining a read / write instruction set in the code to be repaired; classifying the instructions in the read / write instruction set to determine a target instruction; and inserting a memory barrier instruction between the read / write instruction preceding the target instruction and the target instruction. The read / write instruction set includes read instructions and / or write instructions in the code to be repaired, and the instructions in the read / write instruction set are used to access memory.

[0009] By using the method provided by the present application, the target instructions can be determined by classifying the instructions to be repaired. Then, a memory barrier instruction is inserted before the target instruction so that the target instruction can be executed in the order required by the program itself, thereby automatically repairing the weak memory order problem of the multi-threaded program. The method provided by the embodiment of the present application can automatically repair the weak memory order problem of the multi-threaded program, greatly improving the efficiency of repairing the weak memory order problem of the program.

[0010] In one possible design, the "classifying instructions in the read / write instruction set to determine target instructions" specifically includes: determining a first category of instructions in the read / write instruction set; and determining target instructions based on the first category of instructions. The instructions in the first category are weakly memory-order-safe instructions. The target instructions are instructions in the read / write instruction set other than the first category of instructions.

[0011] In another possible design, the "determining target instructions based on the first category of instructions" specifically includes: determining a target instruction set based on the first category of instructions; and determining target instructions within the target instruction set based on the optimization strategy. The target instruction set includes all instructions in the read / write instruction set except for the first category of instructions. The optimization strategy indicates the types of read / write instructions for which weak memory ordering issues need to be fixed.

[0012] In another possible design method, the above-mentioned optimization strategy includes at least one of the following strategies: a first strategy, determining the read-write instructions in the target instruction set that are in the whitelist as the target instructions; or, determining the read-write instructions in the target instruction set other than the read-write instructions in the blacklist as the target instructions. A second strategy, determining only the dependent read-write instructions among the read-write instructions with context dependencies in the target instruction set as the target instructions. A third strategy, determining the read-write instructions in the target instruction set other than the read-write instructions related to special registers as the target instructions. A fourth strategy, determining the read-write instructions in the target instruction set other than the read-write instructions related to input and output parameters as the target instructions.

[0013] In another possible design, the first category of instructions includes at least one of instructions for reading and writing non-shared variables between threads, or read and write instructions with order-preserving semantics.

[0014] Through these possible designs, we can accurately identify safe, first-category instructions that don't suffer from weak memory ordering issues. By eliminating these first-category instructions, we can identify the target instructions. This method quickly eliminates unnecessary read and write instructions from the code to be repaired, minimizing the insertion of unnecessary memory barrier instructions and improving the performance of the repaired multi-threaded program.

[0015] In addition, through optimization strategies, the insertion of unnecessary memory barrier instructions can be further reduced, thereby further improving the running performance of the repaired multi-threaded program.

[0016] In another possible design, the step of "classifying the instructions in the read / write instruction set to determine target instructions" specifically includes classifying the instructions in the read / write instruction set based on the optimization strategy to determine target instructions. The optimization strategy indicates the type of read / write instruction for which the weak memory ordering issue needs to be fixed.

[0017] Through this possible implementation method, the present application can use optimization strategies to determine the read and write instructions that need to insert memory barrier instructions in the read and write instruction set, thereby reducing the insertion of unnecessary memory barrier instructions and improving the running performance of the repaired multi-threaded program.

[0018] In another possible design, the method further includes: obtaining a fifth strategy configured by the user, and adding the fifth strategy to the optimization strategy.

[0019] Here, the fifth strategy can be a strategy of user-defined configuration. In this way, through this possible design, the application allows the code to be repaired to be repaired to be repaired by the strategy of user-defined configuration, thereby improving the flexibility of the application of the application.

[0020] In another possible design, before the above-mentioned "determining the target instruction", the above-mentioned method also includes: receiving instruction information, where the instruction information is used to instruct the user to select the optimization strategy from the candidate optimization strategies.

[0021] Here, the optimization strategy to be selected can be an optimization strategy preset by the repair device. In this way, through this possible design method, the user can freely select the optimization strategy for repairing the code to be repaired from the optimization strategy to be selected, thereby improving the flexibility of the application of this application.

[0022] Through this possible implementation, users can customize the configuration optimization strategy, thereby achieving flexible application of the method of the present application.

[0023] In another possible design, the "determining the read / write instruction set" specifically includes: identifying instructions in a target function to determine the read / write instruction set. The target function is any function in the code to be repaired.

[0024] Through this possible design, the present application can identify and repair weak memory order problems in the code to be repaired on a function basis, so that the method of the present application can be applied to repair weak memory order problems in large-scale multi-threaded programs, thereby improving the practicality of the method of the present application.

[0025] In another possible design approach, the code to be repaired is an intermediate language obtained by compiling the source code of the multi-threaded program through a compiler.

[0026] In another possible design approach, the code to be repaired is assembly code obtained by compiling the source code of the multi-threaded program with a compiler.

[0027] Through these two possible designs, the method for repairing the weak memory order problem provided by the present application can be executed synchronously with the source code compilation of the multi-threaded program, thereby automatically repairing the weak memory order problem of the multi-threaded program, thereby improving the efficiency of repairing the weak memory order problem of the multi-threaded program.

[0028] In a second aspect, the present application provides a device for repairing weak memory order problems.

[0029] In one possible design, the device is used to execute any one of the methods provided in the first aspect above. The present application can divide the functional modules of the device according to any one of the methods provided in the first aspect above. For example, each functional module can be divided corresponding to each function, or two or more functions can be integrated into one processing module. Exemplarily, the present application can divide the device into a determination unit and an insertion unit, etc. according to the function. The description of the possible technical solutions and beneficial effects executed by the above-mentioned divided functional modules can refer to the technical solutions provided by the first aspect or its corresponding possible design, and will not be repeated here.

[0030] In another possible design, the apparatus for repairing weak memory ordering includes a memory and one or more processors, the memory and the processors being coupled. The memory is configured to store computer instructions, and the processors are configured to invoke the computer instructions to execute any of the methods provided in the first aspect and any possible design thereof.

[0031] In a third aspect, the present application provides a computer-readable storage medium, such as a non-transitory computer-readable storage medium, storing a computer program (or instruction) thereon, which, when executed on a device for repairing a weak memory ordering problem, causes the device for repairing a weak memory ordering problem to perform any of the methods provided in any possible implementation of the first aspect or the second aspect.

[0032] In a fourth aspect, the present application provides a computer program product, which, when run on an apparatus for repairing weak memory ordering problems, enables any method provided by any possible implementation in the first aspect to be executed.

[0033] In a fifth aspect, the present application provides a chip system, comprising: a processor, the processor being used to call and run a computer program stored in a memory from the memory, and execute any one of the methods provided in the implementation manner in the first aspect.

[0034] It can be understood that any of the devices, computer storage media, computer program products or chip systems provided above can be applied to the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding methods and will not be repeated here.

[0035] In this application, the name of the device for repairing weak memory ordering does not limit the device or functional module itself. In actual implementation, these devices or functional modules may appear with other names. As long as the functions of each device or functional module are similar to those of this application, they fall within the scope of the claims of this application and their equivalents.

[0036] These and other aspects of the present application will become more readily apparent from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A schematic diagram of a process of compiling program source code into machine executable program code in the prior art;

[0038] Figure 2 A schematic diagram of the hardware structure of a computing device provided in an embodiment of the present application;

[0039] Figure 3 A flowchart of a method for repairing weak memory ordering problems provided in an embodiment of the present application;

[0040] Figure 4a A repair device provided in an embodiment of the present application obtains a schematic diagram of an optimization strategy selected by a user from among candidate optimization strategies based on a graphical interactive interface;

[0041] Figure 4b A flowchart of another method for repairing weak memory order problems provided in an embodiment of the present application;

[0042] Figure 5 A schematic structural diagram of a repair device provided in an embodiment of the present application;

[0043] Figure 6 A schematic diagram of the structure of a chip system provided in an embodiment of the present application;

[0044] Figure 7 A schematic diagram of the structure of a computer program product provided in an embodiment of the present application. DETAILED DESCRIPTION

[0045] In order to better understand the embodiments of the present application, some of the terms or technologies involved in the embodiments of the present application are explained below:

[0046] 1) Compiler

[0047] Compilers are typically used to translate from one language to another. For example, they translate the source code of a program developed by a developer in a high-level computer language (such as C or C++) into machine language code (such as binary code) that a machine can understand and execute.

[0048] Generally, a compiler can integrate assembly functionality. This allows the compiler to first compile the program source code, processed by a preprocessor, into assembly code. This assembly code is the assembly language code. The assembly function then further compiles this assembly code into target code. This target code is a machine-readable language code, such as binary code. This target code is then combined with a linker to create a program code that can be executed by a machine.

[0049] Optionally, to improve compilation performance, the compiler may first compile the program source code processed by the preprocessor into an intermediate language before compiling it into assembly code. This intermediate language is generated by the compiler after parsing the preprocessed program source code, and is used to optimize the target code compiled by the compiler.

[0050] As an example, refer to Figure 1 , Figure 1 A schematic diagram of the process of compiling program source code into machine executable program code is shown.

[0051] like Figure 1 As shown, after the program source code is processed by the preprocessor 11, it is input into the compiler 12. The subcompiler 121 of the compiler 12 can compile the preprocessed program source code into assembly code and output it. Next, the assembler 122 assembles the assembly code output by the subcompiler 121 to obtain the target code. This target code is the code that the machine can recognize. Finally, after the target code is processed by the linker 13, an executable program that can be run by the machine is obtained.

[0052] Among them, after the sub-compiler 121 parses the pre-processed program source code, it can generate an intermediate language. The sub-compiler 121 can also further compile the intermediate language to obtain Figure 1 The assembly code shown.

[0053] 2) Multi-threaded programs

[0054] An instance of a running program is typically called a process. A process can contain at least one thread, which is a single, sequential flow of control within a process. Typically, a process can contain multiple threads concurrently, which can run in parallel across multiple processing cores in a computer device to perform different tasks. Of course, a process can also contain only one thread, and this is not a limitation.

[0055] Therefore, a multi-threaded program refers to a program that includes multiple threads in one process during operation.

[0056] 3) Other terms

[0057] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0058] In the embodiments of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0059] In this application, the term "at least one" means one or more, and the term "plurality" means two or more. For example, "plurality of second messages" means two or more second messages. The terms "system" and "network" are often used interchangeably herein.

[0060] It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the listed items. The term "and / or" describes an association between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " in this application generally indicates that the associated objects are in an "or" relationship.

[0061] It should also be understood that in the various embodiments of the present application, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0062] It should be understood that determining B based on A does not mean determining B based solely on A. B can also be determined based on A and / or other information.

[0063] It will also be understood that the term “comprise” (also known as “includes,” “including,” “comprises,” and / or “comprising”) when used in this specification specifies the presence of stated features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0064] It should be understood that references throughout this specification to "one embodiment," "an embodiment," or "one possible implementation" mean that specific features, structures, or characteristics associated with that embodiment or implementation are included in at least one embodiment of this application. Therefore, the appearance of "in one embodiment," "in an embodiment," or "one possible implementation" throughout this specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0065] It should be understood that the threads running in parallel in a multi-threaded program have independent control flows, but there may be logical relationships between the instructions used by different threads to access memory (for simplicity of description, this embodiment of the application abbreviates "access memory" as "memory access"). Here, the instructions used to access memory generally include read instructions and / or write instructions.

[0066] For example, in a multi-threaded program developed based on a non-weak memory model, write instruction 1, used for memory access in the first thread, is used to write (store) the value 0 in register 1 to memory. Read instruction 2, used for memory access in the second thread, is used to read (load) the value 0 from memory into register 2. Therefore, there is a logical order relationship between write instruction 1 and read instruction 2. That is, after write instruction 1 writes the value 0 in register 1 to memory, read instruction 2 can read the value 0 from memory into the register.

[0067] When the first thread and the second thread of the multi-threaded program are running in parallel through the two processing cores of a computer device that adopts a weak memory model, if the write instruction 1 is executed before the read instruction or the write instruction that precedes the write instruction 1 in the first thread, this may cause the write instruction 1 to be executed later than the read instruction 2 in the second thread. When the write instruction 1 is executed later than the read instruction 2 in the second thread, when the read instruction 2 in the second thread is executed, the memory is empty, that is, the value 0 in register 1 has not been written to the memory. In this case, the tasks executed by the first thread and the second thread have logical errors, which may cause the program to crash or the output results to be inaccurate. This situation is called the problem of weak memory ordering caused by the write instruction 1 in the first thread.

[0068] Typically, when a program's threads are running, weak memory ordering may occur, including the following: read-read (loadload), write-write (storestore), read-write (loadstore), and write-read (storeload). This means that the execution order of two read instructions is reversed, the execution order of two write instructions is reversed, the execution order of read and write instructions is reversed, and the execution order of write and read instructions is reversed. Here, reversed instruction execution order means that the execution order of instructions is opposite to the execution order required by the program itself.

[0069] For the above-mentioned weak memory order problem, a memory barrier instruction can usually be inserted before the memory access instruction to ensure that the two memory access instructions can be executed in the order required by the program.

[0070] For example, in program 1 developed based on a non-weak memory model, the normal execution order of instruction 1 for memory access and instruction 2 for memory access is "instruction 1 → instruction 2". When program 1 is run on a computer device using a weak memory model, a weak memory ordering issue may occur between instruction 1 and instruction 2. In this case, a memory barrier instruction can be inserted between instruction 1 and instruction 2. This ensures that when program 1 is run on a computer device using a weak memory model, instruction 1 and instruction 2 can be executed in the order "instruction 1 → instruction 2".

[0071] However, in traditional methods, the locations where memory barrier instructions need to be inserted in a program are generally determined by the developer based on experience. This method is extremely inefficient when the program is large.

[0072] Based on this, an embodiment of the present application provides a method for repairing weak memory order problems, which is applied to a device for repairing weak memory order problems (for ease of description, in the embodiments of the present application below, the "device for repairing weak memory order problems" will be referred to as the "repair device"). The method identifies the code to be repaired to determine the read-write instruction set in the code to be repaired, and the read-write instruction set includes read-write instructions for accessing memory. Then, the repair device classifies the read-write instructions in the read-write instruction set based on the determined read-write instruction set to determine the target instruction that needs to insert a memory barrier. Finally, a memory barrier instruction is inserted before the target instruction, thereby automatically repairing the weak memory order problem of the code to be repaired, greatly improving the efficiency of repairing the weak memory order problem of the code to be repaired.

[0073] The code to be repaired may be an intermediate language obtained by compiling a multi-threaded program source code through a compiler, or an assembly code obtained by compiling a compiler, which is not specifically limited in the embodiment of the present application.

[0074] The multi-threaded program source code may be a program source code developed using a high-level computer language such as C, C++ or Fortran, and this embodiment of the present application does not specifically limit this.

[0075] The embodiment of the present application also provides a repair device, which can be applied to any computing device with computing processing capabilities. The computing device can be a general-purpose computer or server, etc., and the embodiment of the present application does not make specific limitations on this.

[0076] refer to Figure 2 , Figure 2 FIG. 1 shows a hardware structure diagram of a computing device 20 provided in an embodiment of the present application. The above-mentioned device for repairing memory access problems can be applied to the computing device 20. Figure 2 As shown, the computing device 20 includes a processor 21, a memory 22, a communication interface 23, an input / output interface 24, and a bus 25. The processor 21, the memory 22, the communication interface 23, and the input / output interface 24 may be connected via the bus 25.

[0077] The processor 21 is the control center of the computing device 20 and can be a general-purpose central processing unit (CPU) or other general-purpose processors, etc. The general-purpose processor can be a microprocessor or any conventional processor.

[0078] As an example, the processor 21 may include one or more CPUs, such as Figure 2 CPU 0 and CPU 1 are shown in FIG. Among them, CPU 0 and CPU 1 can run two threads of the multi-threaded program in parallel.

[0079] The memory 22 may be a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM) or other type of dynamic storage device that can store information and instructions, an electrically erasable programmable read-only memory (EEPROM), a disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto.

[0080] In one possible implementation, the memory 22 may exist independently of the processor 21. The memory 22 may be connected to the processor 21 via a bus 25 and used to store data, instructions, or program code. When the processor 21 calls and executes the instructions or program code stored in the memory 22, the method for repairing the access disorder problem provided in the embodiment of the present application can be implemented.

[0081] In another possible implementation, the memory 22 may also be integrated with the processor 21 .

[0082] Communication interface 23 is used to connect computing device 20 to other devices (such as network nodes in a public cloud) via a communication network. The communication network can be Ethernet, a radio access network (RAN), a wireless local area network (WLAN), etc. Communication interface 23 can include a receiving unit for receiving data and a sending unit for sending data.

[0083] The input / output interface 24 is used to implement human-computer interaction between the user and the computing device 20. The input / output interface 24 can be a mouse, keyboard, touch screen, etc., but is certainly not limited thereto.

[0084] As an example, a user may submit a blacklist or a whitelist, etc. to a computing device based on an input / output interface.

[0085] The bus 25 can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 2 Only one thick line is used in the diagram, but this does not mean that there is only one bus or one type of bus.

[0086] It should be pointed out that Figure 2 The structure shown in the figure does not constitute a limitation on the computing device 20, except Figure 2 In addition to the components shown, the computing device 20 may include more or fewer components than shown, or combine certain components, or arrange the components differently.

[0087] The following describes a method for repairing weak memory order problems provided by an embodiment of the present application in conjunction with the accompanying drawings.

[0088] refer to Figure 3 , Figure 3 The following is a flow chart showing a method for repairing weak memory order problems provided by an embodiment of the present application. This method can be applied to Figure 2 The repair device shown. The method may include the following steps:

[0089] S101. The repair device determines a read and write instruction set.

[0090] Specifically, the repair device may determine the read-write instruction set in the code to be repaired, where the read-write instruction set includes read instructions and / or write instructions in the code to be repaired, and the instructions in the read-write instruction set are used for memory access.

[0091] For example, the read instruction "ldr x1, [x0]" reads the value from the memory address pointed to by general register x0 and writes the value to general register x1. Another example is the write instruction "str x1, [x0]" writes the value in general register x1 to the memory address pointed to by general register x0.

[0092] For the sake of simplicity, in the following description of the embodiments of the present application, “read instructions and / or write instructions” are referred to as “read and write instructions” for short.

[0093] The code to be repaired can be an intermediate language obtained by compiling the source code of a multi-threaded program with a compiler. Alternatively, the code to be repaired can be assembly code obtained by compiling the source code of a multi-threaded program with a compiler, which is not specifically limited in the present embodiment. For the description of the compiler and intermediate language, please refer to the above description and will not be repeated here.

[0094] Alternatively, the code to be repaired may be an intermediate language obtained by compiling a module to be repaired in the source code of a multi-threaded program with a compiler. Alternatively, the code to be repaired may be assembly code obtained by compiling a module to be repaired in the source code of a multi-threaded program with a compiler, which is not specifically limited in this embodiment of the present application.

[0095] The module to be repaired can be one of multiple modules obtained by a developer dividing the source code of a multi-threaded program. Alternatively, the module to be repaired can be one of multiple modules obtained by a preprocessor or compiler dividing the source code of a multi-threaded program. This embodiment of the present application is not limited to this.

[0096] The source code of the multi-threaded program may be divided according to the functions or uses that the code can achieve, but is certainly not limited thereto.

[0097] The multiple modules generated by partitioning the source code of a multi-threaded program include secure modules and non-secure modules. A secure module is a module whose read and write instructions, generated after compiling the source code, do not cause weak memory ordering issues. A non-secure module is a module whose read and write instructions, generated after compiling the source code, do cause weak memory ordering issues. Therefore, this non-secure module is the module to be repaired.

[0098] Optionally, the security module may be run through a large number of tests to determine that it does not cause weak memory ordering issues, which is not specifically limited.

[0099] Specifically, the repairing device may identify instructions in the code to be repaired to determine the read and write instructions in the code to be repaired, thereby obtaining a read and write instruction set corresponding to the code to be repaired.

[0100] In one possible implementation, the repair device can identify instructions in a target function, using functions in the code to be repaired as units, to determine the read and write instructions in the target function, thereby obtaining a read and write instruction set corresponding to the target function. The target function is any function in the code to be repaired. It should be understood that the code to be repaired is composed of at least one function.

[0101] Specifically, the repair device can traverse each instruction in the target function and identify each instruction in the target function to determine the read and write instructions in the target function, thereby obtaining the read and write instruction set corresponding to the target function.

[0102] In this way, after the repair device identifies the instructions in each function in the code to be repaired, it can determine the read and write instruction set corresponding to each function. The set of read and write instruction sets corresponding to each function includes all read and write instructions in the code to be repaired.

[0103] It can be seen that when the read-write instruction set is determined in this manner, each function in the code to be repaired can correspond to a read-write instruction set, that is, the functions in the code to be repaired correspond one-to-one with the determined read-write instruction set. Alternatively, the code to be repaired can also correspond to a read-write instruction set. In this case, the read-write instruction set can be obtained by aggregating the read-write instruction sets determined based on each function by the repair device. This embodiment of the application does not specifically limit this.

[0104] In another possible implementation, the repair device may traverse the instructions in the code to be repaired and identify the instructions in the code to be repaired to determine the read and write instructions in the code to be repaired, thereby obtaining a read and write instruction set corresponding to the code to be repaired.

[0105] It can be seen that when the read and write instruction sets are determined in this way, the code to be repaired corresponds to one read and write instruction set.

[0106] S102: The repair device determines a first type of instruction based on the read and write instruction set.

[0107] The repair device can determine the first category of instructions in the read and write instruction set based on the determined read and write instruction set. Here, the instructions in the first category of instructions will not cause weak memory ordering problems, that is, the first category of instructions are weak memory order safe instructions.

[0108] Among them, the instructions in the first category of instructions can be instructions that themselves will not cause weak memory ordering problems, or instructions that will not cause weak memory ordering problems in a preset context, and there is no limitation on this.

[0109] Optionally, the first category of instructions may include at least one of instructions for reading and writing non-shared variables between threads, or read and write instructions with order-preserving semantics.

[0110] Among them, non-shared variables between threads are variables that are dedicated to a thread (for example, the first thread) and are not called by threads other than the first thread. In this way, instructions that read and write such variables usually do not cause weak memory ordering issues.

[0111] Illustratively, the instructions for reading and writing non-shared variables between threads may include at least one of instructions for reading and writing local variables or instructions for reading and writing thread local variables.

[0112] For read and write instructions with order-preserving semantics, their own semantics prevent weak memory ordering issues from occurring during execution.

[0113] S103. The repair device determines a target instruction set according to the first type of instructions, and determines a target instruction in the target instruction set.

[0114] The instructions in the target instruction set are all instructions in the read-write instruction set except the first category of instructions. In this way, the repair device can determine the target instruction set from the read-write instruction set based on the first category of instructions determined above.

[0115] Furthermore, the repair device may determine the target instruction in the target instruction set.

[0116] In a possible implementation, the repair device may determine all instructions in the target instruction set as target instructions. In other words, the repair device repairs all instructions in the target instruction set.

[0117] In another possible implementation, the repair device may determine the target instruction in the target instruction set based on at least one of the following optimization strategies: wherein the optimization strategy is used to indicate the type of read and write instructions for which the weak memory ordering problem needs to be repaired.

[0118] The repair device may be pre-installed with the optimization strategy, or the repair device may obtain the optimization strategy configured by the user when starting to repair the code to be repaired, which is not limited to this.

[0119] The optimization strategy may include the first strategy to the fourth strategy described below. It is understood that the first strategy to the fourth strategy are only exemplary descriptions, and the embodiments of the present application are not limited thereto.

[0120] In one case, when the above-mentioned optimization strategy is pre-configured by the user, the user can submit the optimization strategy to the repair device through the input and output interface of the computing device and adopt any of the following methods: a graphical interactive interface, command line insertion, or setting a configuration file. In response, the repair device can obtain the user-configured optimization strategy and determine the target instructions based on the obtained optimization strategy when repairing the code to be repaired.

[0121] For example, a user submits an optimization strategy to a repair device through the input / output interface of a computing device by setting a configuration file. Typically, the user can place a pre-configured optimization strategy file in the root directory of the repair device and modify the suffix format of the file, thereby setting the optimization strategy configuration file in the repair device. In this way, when the repair device executes the method provided in the embodiments of the present application, it can determine the target instruction in the target instruction set and repair it according to the optimization strategy indicated in the configuration file.

[0122] Of course, the above-mentioned optimization strategy may also include a fifth strategy that is customized and configured by the user based on his or her own needs, which is not limited in the embodiment of the present application.

[0123] In this case, the repair device can pre-acquire the user-defined fifth strategy and add it to the aforementioned optimization strategy. This allows the repair device to determine target instructions based on the optimization strategy that includes the fifth strategy when repairing the code to be repaired. The process of pre-acquiring the user-defined fifth strategy by the repair device can be found in the description above regarding the repair device acquiring the user-defined optimization strategy, and will not be further elaborated here.

[0124] In another embodiment, the aforementioned optimization strategy is pre-installed in the repair device. Thus, the repair device can determine the target instruction during the repair process of the code to be repaired based on the pre-installed optimization strategy. Of course, the repair device can also use the pre-installed optimization strategy as a candidate optimization strategy. Thus, when the repair device begins repairing the code to be repaired, it can receive instruction information input by the user and determine the target instruction based on the optimization strategy indicated by the instruction information. Here, the instruction information indicates the optimization strategy selected by the user from the candidate optimization strategies.

[0125] It should be understood that the optimization strategy preset in the repair device may include a user-defined fifth strategy pre-acquired by the repair device. Of course, the repair device may also acquire the user-defined fifth strategy when repairing the code to be repaired, and this is not limited to this. The following description uses the example of the repair device acquiring the user-defined fifth strategy when repairing the code to be repaired as an example.

[0126] Exemplary, reference Figure 4a , Figure 4a The figure shows a schematic diagram of the repair device obtaining the optimization strategy selected by the user from the candidate optimization strategies based on the graphical interactive interface. Figure 4aAs shown in (a) of FIG, when the repair device begins preparing to repair the code to be repaired, or when compiling the source code of a multi-threaded program, the repair device can display options such as a first strategy, a second strategy, a third strategy, a fourth strategy, and a custom optimization strategy through a dialog box 411 on a display interface 41 of the computing device (e.g., a display), thereby inquiring the user about the optimization strategy to be used when repairing the code to be repaired. The first strategy, the second strategy, the third strategy, and the fourth strategy are optimization strategies preset by the repair device. The custom optimization strategy is an optimization strategy that requires immediate user submission.

[0127] like Figure 4a As shown in (a) of FIG, when the user uses the mouse (or keyboard) to select the options "First Strategy" and "Second Strategy," instruction information indicating "First Strategy" and "Second Strategy" is sent to the repair device. Based on the instruction information, the repair device can determine that the optimization strategies selected by the user are "First Strategy" and "Second Strategy." In this way, the repair device can identify the target instruction in the target instruction set based on the optimization strategies selected by the user and repair it.

[0128] like Figure 4a As shown in (b) in FIG, when the user selects the option "Customize Optimization Strategy" by controlling the mouse (or keyboard), the user can control the mouse (or keyboard) to Figure 4a In the dialog box 412 shown in (c) of the figure, the user uploads the policy that he or she has pre-customized. For example, the user can first use the mouse (or keyboard) to click the "browse" icon to find the storage directory "Aa / bb / cc / " of the custom policy. Then, the user can use the mouse (or keyboard) to click the "upload" icon to upload the user-customized policy. In response, the repair device receives the custom policy uploaded by the user. In this way, the repair device can determine the target instruction in the target instruction set based on the custom policy and repair it.

[0129] It can be seen that by allowing users to customize configuration strategies and allowing users to freely select optimization strategies from candidate optimization strategies, the application of the method provided in the embodiment of the present application is made more flexible.

[0130] It should be understood that the repair device obtains the user-configured optimization strategy before executing the technical solution described in the embodiments of this application. In this way, the repair device can use the configured optimization strategy to repair the read and write instructions of the type indicated by the optimization strategy during the execution of the method provided in the embodiments of this application.

[0131] The first strategy to the fourth strategy are described below as an example:

[0132] First strategy: the repair device may determine the read-write instructions in the target instruction set that belong to the whitelist as the target instruction, or the repair device may determine the read-write instructions in the target instruction set except the read-write instructions in the blacklist as the target instruction.

[0133] The above-mentioned whitelist and blacklist may be a blacklist and whitelist of functions in the code to be repaired, or a blacklist and whitelist of different functional modules in the code to be repaired, and there is no limitation on this.

[0134] The following uses the above whitelist and blacklist as an example to illustrate the blacklist and whitelist of functions in the code to be repaired.

[0135] The function blacklist generally includes functions such as safe functions and / or hot functions in the code to be repaired.

[0136] Here, a safe function can generally be a function that does not cause weak memory ordering issues when an executable program generated through conventional compilation is run. Alternatively, a safe function can be a function that does not include shared variables in its source code, and so on, without limitation. Since safe functions generally do not cause weak memory ordering issues, the repair device does not need to repair weak memory ordering issues in safe functions.

[0137] Hot functions are typically functions that are frequently called by a program. For example, if function A is called by a program more than or equal to a preset threshold, then function A is a hot function. Since the weak memory ordering problem of an instruction is fixed by inserting a memory barrier instruction before the instruction, inserting a memory barrier instruction into a hot function will cause the program's running performance to degrade due to its frequent calls. Therefore, the repair device does not repair the weak memory ordering problem of the hot function.

[0138] Of course, the hot functions in the function blacklist can also be hot functions that are determined in advance through the above-mentioned method of determining safe functions to prevent weak memory ordering problems.

[0139] The function whitelist usually includes functions in the code to be repaired, except for the hot functions and / or safe functions mentioned above. For such functions, the repair device can repair the weak memory ordering problem.

[0140] It should be understood that the repair device may preset the above-mentioned function blacklist and / or function whitelist, and the repair device may also obtain the function blacklist and / or function whitelist pre-configured by the user, which is not limited to this.

[0141] When the above-mentioned function blacklist and / or function whitelist is pre-configured by the user, the user can submit the pre-configured function blacklist and / or function whitelist to the repair device through the input and output interface of the computing device, and through any of the methods such as graphical interactive interface, command line insertion or setting a configuration file. In response, the repair device can obtain the function blacklist and / or function whitelist configured by the user. Here, the process of the repair device obtaining the function blacklist and / or function whitelist configured by the user can refer to the description of the process of the repair device obtaining the user-defined optimization strategy, and will not be repeated here.

[0142] The second strategy: the repair device may determine, among the read and write instructions with context dependencies in the target instruction set, only the dependent read and write instructions as target instructions.

[0143] Optionally, the repair device can analyze the instructions in the target instruction set and determine only dependent read and write instructions based on the context dependencies of the read and write instructions in the target instruction set. Here, only dependent read and write instructions refer to instructions that do not depend on other read and write instructions in the target instruction set.

[0144] As an example, if the target instruction set includes the following instructions:

[0145] Instruction 1: ldr x0, [s1];

[0146] Instruction 2: str x0, [s2];

[0147] Among them, instruction 1 "ldr x0, [s1]" means reading register x0 from the memory address indicated by register s1. Instruction 2 "str x0, [s2]" means writing the value in register x0 to the memory address indicated by register s2. It can be seen that when instruction 1 is not executed, that is, when the value in register x0 is not read from the memory address indicated by register s1, instruction 2 cannot be executed to write the value in register x0 to the memory address indicated by register s2. In other words, instruction 1 and instruction 2 are instructions with a dependency relationship, and instruction 1 is a dependency of instruction 2. That is, the execution of instruction 2 depends on the execution of instruction 1. In this case, when the execution of instruction 1 does not depend on other read and write instructions in the target instruction set, the repair device can determine that instruction 1 is a read and write instruction that serves only as a dependency.

[0148] For read and write instructions that have context dependencies and rely on other instructions for execution, such instructions usually do not have weak memory ordering issues. Therefore, the repair device usually does not repair such instructions.

[0149] The third strategy: the repair device may determine the read and write instructions in the target instruction set except the read and write instructions related to the special register as the target instructions.

[0150] A dedicated register generally refers to a register that is used only for a specific instruction or occasion. For example, the dedicated register may be a floating-point register. Here, a floating-point register is a register used to store floating-point numbers.

[0151] Taking the dedicated register as a floating-point register as an example, the repair device can determine whether the register is a floating-point register by identifying the name of the register in the read / write instruction. If the register in the read / write instruction is a floating-point register, the repair device can determine that the read / write instruction is a read / write instruction that operates on the floating-point register.

[0152] Since special registers are usually not used to read or write global control variables, read and write instructions that operate on special registers usually do not cause weak memory ordering problems. Therefore, the repair device usually does not need to repair read and write instructions that operate on special registers.

[0153] Fourth strategy: The repair device may determine the read and write instructions in the target instruction set, excluding the read and write instructions related to input and output parameters, as target instructions.

[0154] Among them, input and output parameters include the parameters that need to be input when calling a function, as well as the return value of the function.

[0155] For example, when the general register x0 is a register for storing the return value of a function, if the instructions in the target instruction set are as follows:

[0156] B malloc;

[0157] str x11,[x0];

[0158] Here, "B" indicates an instruction class similar to a function call, and "malloc" is the name of the function used to allocate memory. Therefore, the instruction "B malloc" calls the malloc function. When the malloc function is executed, the memory address returned by malloc is written to general register x0. In this case, the instruction "Str x11, [x0]" writes the value in register x11 to the memory address indicated by general register x0, which is also the memory address returned by malloc. In this case, the instruction "str x11, [x0]" is a read / write instruction related to input and output parameters.

[0159] Usually, in a scenario like this, weak memory ordering issues will not occur for read and write instructions related to input and output parameters, so the repair device does not need to repair them.

[0160] It should be noted that when the repair device determines the target instruction based on the fourth strategy, it can also determine the target instruction based on the contextual logical relationship of the instructions in the target instruction set, which will not be elaborated on.

[0161] It should be noted that when the optimization strategy employed by the repair device is any combination of the first through fourth strategies described above, the repair device can preset the priorities of the multiple strategies within the combination. Thus, when the same read or write instruction produces opposite results based on two different strategies, the repair device can, based on the priorities, process the instruction using the strategy with the higher priority. Priority indicates the priority level of a strategy; a strategy with a higher priority level is used over a strategy with a lower optimization level.

[0162] For example, when the combined strategy is the second and third strategies described above, if instruction 1 is the only dependent instruction, the repair device should repair instruction 1 according to the second strategy. Meanwhile, if instruction 1 is an instruction that reads or writes a floating-point register, the repair device should not repair instruction 1 according to the third strategy. In this case, the different strategies in the combined strategy produce opposite results for the same instruction. In this case, if the second strategy in the combined strategy has a higher priority than the third strategy, the repair device will determine instruction 1 as the target instruction based on the second strategy and repair it.

[0163] S104. The repair device inserts a memory barrier instruction between the previous read / write instruction of the target instruction determined above and the target instruction.

[0164] After determining the target instruction, the repair device inserts a memory barrier instruction between the previous read / write instruction of the target instruction and the target instruction, thereby repairing the weak memory order problem of the instructions in the code to be repaired.

[0165] The memory barrier instruction is used to indicate that the target instruction will be executed after the read and write instructions before the memory barrier instruction are completed.

[0166] For example, if the target instruction is instruction 1 and the previous read / write instruction is instruction 2, the repair device inserts a memory barrier instruction between instruction 1 and instruction 2. The memory barrier instruction is used to indicate that instruction 1 is executed after instruction 2.

[0167] Thus, embodiments of the present application provide a method for repairing weak memory ordering issues. During the compilation of a multi-threaded program's source code, this method classifies the instructions to be repaired to determine a target instruction set. Then, an optimization strategy is used to further identify target instructions within the target instruction set that require insertion of memory barrier instructions, so that the target instructions can be executed in the order required by the program itself. Using this method, a repair device can automatically repair weak memory ordering issues in multi-threaded programs.

[0168] Optional, reference Figure 4b In another method for repairing the weak memory order problem provided in an embodiment of the present application, the above-mentioned S102-S103 can be replaced by the following step S202.

[0169] S202. The repair device classifies the instructions in the read-write instruction set based on the optimization strategy to determine the target instruction.

[0170] The read-write instruction set is the read-write instruction set determined by the repair device in S101.

[0171] The optimization strategy is used to indicate the type of read and write instructions that need to fix the weak memory ordering problem. The description of this optimization strategy can be found in the description of the optimization strategy above and will not be repeated here.

[0172] Specifically, based on the above-mentioned optimization strategy, the repair device can divide the read / write instructions in the read / write instruction set determined in step S101 into read / write instructions that require the insertion of memory barrier instructions and read / write instructions that do not require the insertion of memory barrier instructions. Then, the repair device determines the read / write instructions that require the insertion of memory barrier instructions as target instructions.

[0173] Thus, during the compilation of multi-threaded program source code, the method for repairing weak memory ordering provided by the embodiments of the present application can directly classify the instructions to be repaired using an optimization strategy, thereby determining the target instructions that require the insertion of memory barrier instructions. This ensures that the target instructions are executed in the order required by the program itself. Through this method, a repair device can automatically repair weak memory ordering issues in multi-threaded programs.

[0174] In order to more easily understand the method provided in the embodiment of the present application, the following is an example of applying the method for repairing the weak memory ordering problem provided in the embodiment of the present application in the GNU Compiler Collection (GCC) to repair the weak memory ordering problem of a multi-threaded program.

[0175] Among them, GCC supports the compilation of program source code developed in high-level computer languages ​​such as C, C++, or Fortran. The working process of GCC compiling program source code includes: pre-processing, compiling, assembling, and linking. The method for repairing weak memory ordering problems provided in the embodiment of the present application can be applied in the compilation stage.

[0176] During the compilation phase, GCC compiles the preprocessed multi-threaded program source code to generate the compiler's intermediate language (e.g., register transformation language (RTL) expressions). GCC then uses the final module to output the optimized intermediate language as assembly code.

[0177] Typically, the final module outputs intermediate language as assembly code using functions as units. Specifically, the final module outputs intermediate language as assembly code through the final_start_function, final, and final_end_function interfaces.

[0178] The final_start_function interface is used to initialize the function state. For example, it analyzes the number of instructions in the function in the intermediate language and determines the number of insn statements, which will not be described in detail here.

[0179] The final interface is used to output the intermediate language as assembly code. The method for repairing the weak memory order problem provided by the embodiment of the present application (for example Figure 3 or Figure 4b The method for repairing weak memory ordering issues (shown in the figure) can be executed at this stage. Specifically, the repair device can execute the method described in S101-S104 above through the final interface to insert a memory barrier instruction before the target instruction. The final interface then calls the output_asm_insn function to output the insn statement as assembly code.

[0180] An insn statement contains multiple assembly instructions, and the length of each assembly instruction is generally 4. Since the number of insn statements and instructions is determined when the function state is initialized, the final interface usually determines the length of an insn statement.

[0181] However, when the repair device repairs read and write instructions through the final interface, it inserts a memory barrier instruction before the target instruction. Therefore, the repair instruction changes the length of the insn statement. In this case, before the final interface is output as assembly code, the final_start_functio interface needs to perform corresponding processing on the original process of obtaining the insn statement length (such as get_attr_length) to obtain the length of the insn statement after the memory barrier instruction is inserted. For example, the number of instructions in the insn statement can be reduced by function calls to control the length of the insn statement, etc., and there are no restrictions on this.

[0182] Finally, final_end_function is used to clean up the resources used to output the intermediate language into assembly code.

[0183] Then, GCC continues to assemble and link the repaired assembly code to output executable program code. Here, the specific working process of GCC is not described in detail in the embodiment of the present application. It should be understood that the executable program code that GCC ultimately outputs is the program code that has repaired the weak memory order.

[0184] In summary, the embodiments of the present application provide a method for repairing weak memory ordering problems. During the compilation of the source code of a multi-threaded program, the method classifies the instructions to be repaired to determine a target instruction set. Then, the target instructions that need to be inserted with memory barrier instructions are further determined in the target instruction set through an optimization strategy, so that the target instructions can be executed in the order required by the program itself, thereby automatically repairing the weak memory ordering problem of the multi-threaded program. The method provided by the embodiments of the present application can repair the weak memory ordering problem of the multi-threaded program, greatly improving the efficiency of repairing the weak memory ordering problem of the program.

[0185] In addition, in the embodiment of the present application, weak memory order problems in the code to be repaired are identified and repaired in units of functions, so that the method provided in the embodiment of the present application can be applied to the repair of weak memory order problems in large-scale multi-threaded programs, thereby improving the practicality of the method provided in the embodiment of the present application.

[0186] The above mainly introduces the solution provided by the embodiment of the present application from the perspective of method. In order to realize the above functions, it includes hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should easily appreciate that, in combination with the units and algorithm steps of each example described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in a hardware or computer software driven hardware manner depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0187] In the embodiment of the present application, the functional modules of the repair device can be divided according to the above method examples. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one processing module. The above integrated modules can be implemented in the form of hardware or software functional modules. It should be noted that the division of modules in the embodiment of the present application is schematic and is only a logical functional division. In actual implementation, other division methods can be used.

[0188] like Figure 5 As shown, Figure 5 FIG2 shows a structural diagram of a repair device 50 provided in an embodiment of the present application. The repair device 50 can be used to perform the above-mentioned method for repairing weak memory order problems, for example, to perform Figure 3 The repairing device 50 may include a determining unit 51 and an inserting unit 52 .

[0189] A determination unit 51 is configured to determine a read / write instruction set in the code to be repaired, and to classify the instructions in the read / write instruction set to determine a target instruction. The read / write instruction set includes read instructions and / or write instructions in the code to be repaired, and the instructions in the read / write instruction set are used to access memory. An insertion unit 52 is configured to insert a memory barrier instruction between the target instruction and the previous read / write instruction.

[0190] As an example, combined with Figure 3 , the determining unit 51 can be used to execute S101-S103, and the inserting unit 52 can be used to execute S104.

[0191] Optionally, the determining unit 51 is specifically configured to determine a first category of instructions in the read / write instruction set, and to determine a target instruction based on the first category of instructions, wherein the instructions in the first category of instructions are weakly memory-order-safe instructions, and the target instruction is an instruction in the read / write instruction set other than the first category of instructions.

[0192] As an example, combined with Figure 3 , the determining unit 51 can be used to execute S102-S103.

[0193] Optionally, the determination unit 51 is specifically configured to determine a target instruction set based on the first category of instructions; and to determine target instructions within the target instruction set based on an optimization strategy, wherein the target instruction set includes all instructions in the read / write instruction set except for the first category of instructions. The optimization strategy is configured to indicate the types of read / write instructions for which the weak memory ordering issue needs to be fixed.

[0194] As an example, combined with Figure 3 , the determining unit 51 can be used to execute S103.

[0195] Optionally, the determining unit 51 is specifically configured to classify the instructions in the read and write instruction set based on an optimization strategy to determine target instructions. The optimization strategy is used to indicate the type of read and write instructions that require repair of the weak memory ordering problem.

[0196] Optionally, the above-mentioned optimization strategy includes at least one of the following strategies: a first strategy, determining the read-write instructions in the target instruction set that are in the whitelist as the target instructions; or, determining the read-write instructions in the target instruction set other than the read-write instructions in the blacklist as the target instructions. A second strategy, determining only the dependent read-write instructions among the read-write instructions with context dependencies in the target instruction set as the target instructions. A third strategy, determining the read-write instructions in the target instruction set other than the read-write instructions related to special registers as the target instructions. A fourth strategy, determining the read-write instructions in the target instruction set other than the read-write instructions related to input and output parameters as the target instructions.

[0197] Optionally, the repairing device 50 further includes: an acquiring unit 53, configured to acquire a fifth strategy configured by the user; and an adding unit 54, configured to add the fifth strategy to the above-mentioned optimization strategy.

[0198] Optionally, the repair device 50 further includes: a receiving unit 55, configured to receive instruction information before the determining unit 51 determines the target instruction, wherein the instruction information is used to instruct the user to select the above-mentioned optimization strategy from the candidate optimization strategies.

[0199] Optionally, the first category of instructions includes at least one of instructions for reading and writing non-shared variables between threads, or read and write instructions with order-preserving semantics.

[0200] Optionally, the repair device 50 further includes: an identification unit 56 for identifying instructions in a target function to determine the read and write instruction set. The target function is any function in the code to be repaired.

[0201] As an example, combined with Figure 3 , the identification unit 56 can be used to execute S101.

[0202] Optionally, the code to be repaired is an intermediate language obtained by compiling the source code of the multi-threaded program with a compiler, or the code to be repaired is an assembly code obtained by compiling the source code of the multi-threaded program with a compiler.

[0203] For the detailed description of the above optional methods, please refer to the above method embodiments, which will not be repeated here. In addition, the explanation of any of the above-mentioned repair devices 50 and the description of the beneficial effects can refer to the above-mentioned corresponding method embodiments, which will not be repeated here.

[0204] As an example, combined with Figure 2 The determination unit 51, the insertion unit 52, the addition unit 54 and the identification unit 56 in the repair device 50 can be Figure 2 Processor 21 in the Figure 2 The program code in the memory 22 is implemented. The acquisition unit 53 and the receiving unit 55 can be Figure 2 It is implemented by the input and output interface 24 or the communication interface 25.

[0205] The embodiment of the present application also provides a chip system 60, such as Figure 6 As shown, the chip system 60 includes at least one processor and at least one interface circuit. As an example, when the chip system 60 includes a processor and an interface circuit, the processor may be Figure 6 The processor 61 shown in the solid line frame (or the processor 61 shown in the dotted line frame) may be Figure 6 The interface circuit 62 shown in the solid line frame (or the interface circuit 62 shown in the dotted line frame). When the chip system 60 includes two processors and two interface circuits, the two processors include Figure 6 The processor 61 shown in the solid line frame and the processor 61 shown in the dotted line frame, the two interface circuits include Figure 6 The interface circuit 62 shown in the solid line frame and the interface circuit 62 shown in the dotted line frame are not limited to this.

[0206] The processor 61 and the interface circuit 62 can be interconnected via a line. For example, the interface circuit 62 can be used to receive signals (such as obtaining an optimization strategy, etc.). For another example, the interface circuit 62 can be used to send signals to other devices (such as the processor 61). Exemplarily, the interface circuit 62 can read instructions stored in the memory and send the instructions to the processor 61. When the instruction is executed by the processor 61, the repair device can perform the various steps in the above embodiment. Of course, the chip system 60 can also include other discrete components, which is not specifically limited in the embodiment of the present application.

[0207] Another embodiment of the present application further provides a computer-readable storage medium, which stores instructions. When the instructions are run on a repair device, the repair device executes each step performed by the repair device in the method flow shown in the above method embodiment.

[0208] In some embodiments, the disclosed methods may be implemented as computer program instructions encoded in a machine-readable format on a computer-readable storage medium or on other non-transitory media or articles of manufacture.

[0209] Figure 7 The figure schematically shows a conceptual partial view of a computer program product provided by an embodiment of the present application, where the computer program product includes a computer program for executing a computer process on a computing device.

[0210] In one embodiment, the computer program product is provided using a signal bearing medium 70. The signal bearing medium 70 may include one or more program instructions that, when executed by one or more processors, may provide the above-described computer program product. Figure 3 Thus, for example, reference to Figure 3 One or more features of S101 to S104 may be performed by one or more instructions associated with the signal bearing medium 70. Figure 7 The program instructions in also describe example instructions.

[0211] In some examples, the signal-bearing medium 70 may include a computer-readable medium 71 such as, but not limited to, a hard drive, a compact disk (CD), a digital video disk (DVD), a digital tape, a memory, a read-only memory (ROM), a random access memory (RAM), and the like.

[0212] In some implementations, the signal bearing medium 70 may include a computer recordable medium 72 such as, but not limited to, a memory, a read / write (R / W) CD, a R / W DVD, or the like.

[0213] In some embodiments, signal bearing medium 70 may include communication medium 73 such as, but not limited to, digital and / or analog communication media (eg, fiber optic cables, waveguides, wired communication links, wireless communication links, etc.).

[0214] The signal bearing medium 70 may be communicated by a wireless form of communication medium 73 (eg, a wireless communication medium conforming to the IEEE 1902.11 standard or other transmission protocols). The one or more program instructions may be, for example, computer executable instructions or logic implemented instructions.

[0215] In some examples, such as for Figure 3 The described repair apparatus may be configured to provide various operations, functions, or actions in response to one or more program instructions via computer-readable media 71 , computer-recordable media 72 , and / or communication media 73 .

[0216] Should be understood that the arrangement described here is only for the purpose of example. Thus, those skilled in the art will understand that other arrangements and other elements (such as, machines, interfaces, functions, sequences, and functional groups, etc.) can be used instead, and some elements can be omitted altogether according to the desired result. In addition, many of the described elements can be implemented as discrete or distributed components or in any appropriate combination and position in conjunction with the functional entities implemented by other components.

[0217] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using a software program, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer executes the instructions on the computer and when the computer executes the instructions, the process or function according to the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, computer, server or data center to another website, computer, server or data center by wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more media that can be integrated. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (eg, a solid state disk (SSD)).

[0218] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A method for repairing weak memory ordering problems, characterized in that: The method comprises: Determining a read / write instruction set in the code to be repaired, where instructions in the read / write instruction set are used to access memory, and the read / write instruction set includes read instructions or write instructions in the code to be repaired; Classifying the instructions in the read / write instruction set to determine a target instruction, and inserting a memory barrier instruction between a previous read / write instruction of the target instruction and the target instruction; The classifying the instructions in the read / write instruction set to determine the target instruction includes: Determine a first category of instructions in the read / write instruction set, and determine the target instruction based on the first category of instructions; wherein the first category of instructions is used to indicate instructions with weak memory order safety, and the target instruction is an instruction in the read / write instruction set other than the first category of instructions; Alternatively, based on an optimization strategy, the instructions in the read and write instruction set are classified to determine the target instruction; the optimization strategy is used to indicate the type of read and write instructions that need to repair the weak memory order problem.

2. The method according to claim 1, characterized in that The classifying the instructions in the read and write instruction set based on the optimization strategy to determine the target instruction includes: Dividing the instructions in the read-write instruction set into read-write instructions that require insertion of memory barrier instructions and read-write instructions that do not require insertion of memory barrier instructions according to the optimization strategy; The read / write instruction that needs to be inserted with a memory barrier instruction is determined as the target instruction.

3. The method according to claim 1, characterized in that The optimization strategy includes at least one of the following strategies: A first strategy is to determine the read / write instructions in the target instruction set that are in the whitelist as the target instructions; or to determine the read / write instructions in the target instruction set other than the read / write instructions in the blacklist as the target instructions; the target instruction set includes all instructions in the read / write instruction set; A second strategy is to determine, among the read and write instructions with context dependencies in the target instruction set, only dependent read and write instructions as the target instructions; A third strategy is to determine the read and write instructions in the target instruction set, excluding the read and write instructions related to the special register, as the target instructions; A fourth strategy is to determine the read and write instructions in the target instruction set, except for the read and write instructions related to input and output parameters, as the target instructions.

4. The method according to claim 3, characterized in that The method further comprises: Get the fifth policy configured by the user; The fifth strategy is added to the optimization strategy.

5. The method according to claim 3 or 4, characterized in that Before determining the target instruction, the method further includes: Instruction information is received, where the instruction information is used to instruct a user to select the optimization strategy from candidate optimization strategies.

6. The method according to any one of claims 1 to 5, characterized in that The first category of instructions includes at least one of instructions for reading and writing non-shared variables between threads, or read and write instructions with order-preserving semantics.

7. The method according to any one of claims 1 to 6, characterized in that Determining the read and write instruction set specifically includes: Instructions in a target function are identified to determine the read and write instruction set; wherein the target function is any function in the code to be repaired.

8. The method according to any one of claims 1 to 7, characterized in that The code to be repaired is an intermediate language obtained by compiling the source code of a multi-threaded program through a compiler; or The code to be repaired is an assembly code obtained by compiling the source code of the multi-threaded program through a compiler.

9. A device for repairing weak memory order problems, characterized in that: The device comprises: a determining unit, configured to determine a read / write instruction set in the code to be repaired, where the instructions in the read / write instruction set are used to access memory, and the read / write instruction set includes read instructions and / or write instructions in the code to be repaired; and to classify the instructions in the read / write instruction set to determine a target instruction; an insertion unit, configured to insert a memory barrier instruction between a previous read / write instruction of the target instruction and the target instruction; The determination unit is specifically used to determine the first category of instructions in the read-write instruction set, and determine the target instruction based on the first category of instructions; wherein, the first category of instructions is used to indicate instructions with weak memory order safety, and the target instruction is an instruction in the read-write instruction set other than the first category of instructions, or is specifically used to classify the instructions in the read-write instruction set based on an optimization strategy to determine the target instruction; the optimization strategy is used to indicate the type of read-write instruction that needs to fix the weak memory order problem.

10. The device according to claim 9, characterized in that The determination unit is specifically used to: divide the instructions in the read and write instruction set into read and write instructions that require the insertion of memory barrier instructions and read and write instructions that do not require the insertion of internal barrier instructions according to the optimization strategy, and determine the read and write instructions that require the insertion of memory barrier instructions as the target instructions.

11. The device according to claim 9, characterized in that The optimization strategy includes at least one of the following strategies: A first strategy is to determine the read / write instructions in the target instruction set that are in the whitelist as the target instructions; or to determine the read / write instructions in the target instruction set other than the read / write instructions in the blacklist as the target instructions; the target instruction set includes all instructions in the read / write instruction set; A second strategy is to determine, among the read and write instructions with context dependencies in the target instruction set, only dependent read and write instructions as the target instructions; A third strategy is to determine the read and write instructions in the target instruction set, excluding the read and write instructions related to the special register, as the target instructions; A fourth strategy is to determine the read and write instructions in the target instruction set, except for the read and write instructions related to input and output parameters, as the target instructions.

12. The device according to claim 11, characterized in that The device further comprises: an acquiring unit, configured to acquire a fifth policy configured by a user; An adding unit is used to add the fifth strategy to the optimization strategy.

13. The device according to claim 11 or 12, characterized in that The device further comprises: The receiving unit is configured to receive instruction information before the determining unit determines the target instruction, wherein the instruction information is used to instruct a user to select the optimization strategy from the candidate optimization strategies.

14. The device according to any one of claims 9 to 13, characterized in that The first category of instructions includes at least one of instructions for reading and writing non-shared variables between threads, or read and write instructions with order-preserving semantics.

15. The device according to any one of claims 9 to 14, characterized in that The device further comprises: An identification unit is used to identify instructions in a target function to determine the read and write instruction set; wherein the target function is any function in the code to be repaired.

16. The device according to any one of claims 9 to 15, characterized in that The code to be repaired is an intermediate language obtained by compiling the source code of a multi-threaded program through a compiler; or The code to be repaired is an assembly code obtained by compiling the source code of the multi-threaded program through a compiler.

17. A device for repairing weak memory order problems, characterized in that: The apparatus comprises: a memory and one or more processors, wherein the memory is used to store computer instructions, and the processor is used to call the computer instructions to execute the method according to any one of claims 1 to 8.

18. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is run on a computer, the computer is caused to execute the method according to any one of claims 1 to 8.

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