Method for generating and processing single instruction multiple data (SIMD) instruction and related equipment

Abstract

The embodiment of the invention discloses an SIMD (Single Instruction Multiple Data) instruction generation method, an SIMD instruction processing method and related equipment, which are used in the field of SIMD instruction generation in the field of chips. The method comprises the following steps: acquiring the length of each cyclic dimension of a first tensor calculation formula, and selecting information of a second SIMD instruction model matched with the first tensor calculation formula from information of multiple groups of first SIMD instruction models according to the length of each cyclic dimension of the first tensor calculation formula, and according to the length of the at least one cyclic dimension of the first tensor calculation formula and the second SIMD instruction model, generating a first SIMD instruction after conversion of the first tensor calculation formula. According to the method, the information of the second SIMD instruction model is selected from the information of the multiple groups of first SIMD instruction models according to the length of each cyclic dimension of the tensor calculation formula, and then the first SIMD instruction converted by the first tensor calculation formula is generated according to the second SIMD instruction model, so that the efficiency of the SIMD instruction generation process is greatly improved.

Description

[0001] This application is a divisional application. The application number of the original application is 202010177489.5, and the original application date is March 13, 2020. The entire content of the original application is incorporated into this application by reference. Technical Field

[0002] The present invention relates to the field of artificial intelligence, and in particular to a method for generating and processing Single Instruction Multiple Data (SIMD) instructions and related equipment. Background Art

[0003] Starting in the 1990s, major chip manufacturers began integrating single instruction multiple data (SIMD) instruction extensions into their processors. SIMD instructions offer significant acceleration when processing computationally intensive problems with simple control flow and few data dependencies. They are widely used to accelerate computer programs such as image processing, video processing, and scientific computing.

[0004] Currently, the process of converting input tensor calculation formulas into SIMD instructions mainly relies on a brute force search method. The brute force search method gives each parameter in the SIMD instruction a limited value range. For all parameters in the SIMD instruction, all possible parameter combinations within the parameter value range are enumerated. For each parameter combination, the SIMD instruction under this parameter combination needs to be converted into the corresponding tensor calculation formula. The input tensor calculation formula and the converted tensor calculation formula are compared to see if they are equivalent. If they are equivalent, the SIMD instruction under this parameter combination is obtained; if not, the above operation is performed on the next parameter combination.

[0005] However, the value space of each parameter is large, and it takes a long time to obtain the SIMD instruction that matches an input tensor calculation formula through brute force search, which is inefficient. Summary of the Invention

[0006] An embodiment of the present application provides a method for generating and processing a SIMD instruction and related equipment, which is used to select information of a second SIMD instruction model from multiple groups of information of first SIMD instruction models based on the length of each loop dimension of a tensor calculation formula, and then generate a first SIMD instruction after converting the first tensor calculation formula based on the second SIMD instruction model, thereby greatly improving the efficiency of the SIMD instruction generation process.

[0007] To solve the above technical problems, the embodiments of the present application provide the following technical solutions:

[0008] In a first aspect, an embodiment of the present application provides a method for processing SIMD instructions, which can be used in the field of SIMD instruction generation in the chip field. The method includes: a SIMD instruction generation device obtains the length of each loop dimension of a first tensor calculation formula. Wherein, the tensor calculation formula includes a for loop or a nested plurality of for loops, each for loop defines an operation formula to be executed by the for loop, the operation formula includes a tensor and an operator, and of course, each for loop may also include a value range of coordinates in the tensor. A tensor is a multilinear map defined on the Cartesian product of a vector space and a dual space. The operator in the tensor calculation formula determines the operation type of the tensor calculation formula. The operation type of the first tensor calculation formula can specifically be addition or multiplication. The tensor calculation formula can specifically be expressed in the form of a for loop. A tensor calculation formula can include multiple data objects. A loop dimension of the tensor calculation formula refers to a for loop in the tensor calculation formula. The length of a loop dimension in the tensor calculation formula refers to the upper limit of the value of the coordinates in a for loop of the tensor calculation formula, and a data object refers to a tensor in the tensor calculation formula. The SIMD instruction generation device obtains information of multiple groups of first SIMD instruction models. Wherein, the information of each group of first SIMD instruction models corresponds to at least one loop dimension of a tensor calculation formula, and the information of each group of first SIMD instruction models includes a first constraint condition, and the first constraint condition is used to indicate the constraint condition of the length of each loop dimension in at least one loop dimension. The SIMD instruction generation device selects the information of the second SIMD instruction model from the information of multiple groups of first SIMD instruction models according to the first constraint condition and the length of each loop dimension of the first tensor calculation formula, and the information of the second instruction model matches the first tensor calculation formula, and the length of the loop dimension of the first tensor calculation formula satisfies the first constraint condition in the information of the second SIMD instruction model. The SIMD instruction generation device generates the parameter value of the second SIMD instruction model according to the length of at least one loop dimension of the first tensor calculation formula and the second SIMD instruction model, and brings the parameter value of the second SIMD instruction model into the second SIMD instruction model to generate the first SIMD instruction, thereby obtaining the first SIMD instruction after the conversion of the first tensor calculation formula. The second SIMD instruction model is used to generate the first SIMD instruction. The format of the first SIMD instruction model is the same as that of the first SIMD instruction. The difference is that the parameter values ​​of each parameter in the first SIMD instruction model have not been determined, while the parameter values ​​of each parameter in the SIMD instruction have been determined.In this implementation, a specific implementation scheme for converting the first tensor calculation formula into a SIMD instruction is realized through the aforementioned method; multiple groups of first SIMD instruction model information are generated in advance, and during the conversion process, a matching second SIMD instruction model is selected from the information of several groups of first SIMD instruction models based on the length of each loop dimension of the tensor calculation formula, thereby greatly improving the efficiency of the SIMD instruction generation process.

[0009] In a possible implementation of the first aspect, the information of each group of first SIMD instruction models also includes first indication information, where the first indication information is used to indicate the correspondence between K first parameters of a first SIMD instruction model and at least one loop dimension of a tensor calculation formula, where K is an integer greater than or equal to 1, and the first parameter indicates the number of times an operation is repeatedly performed on a data object in a tensor calculation formula.

[0010] In a possible implementation of the first aspect, the at least one loop dimension includes N loop dimensions, and the at least one set of first SIMD instruction model information includes information of multiple types of SIMD instruction models. The value of N corresponding to the information of different types of SIMD instruction models is different, and N is an integer greater than or equal to 1. In this implementation, the information of the at least one set of first SIMD instruction models is divided into categories based on the number of loop dimensions corresponding to the information of the first SIMD instruction models, thereby facilitating subsequent separate management of information of different types of first SIMD instruction models and improving management accuracy.

[0011] In one possible implementation of the first aspect, the first constraint is related to the type of chip executing the converted first SIMD instruction, and the first constraint may be different for different types of chips. In this implementation, the SIMD instruction model information set is generated based on a specific chip, and different chips generate different SIMD instruction model information. This not only expands the application scenarios of this solution but also improves the compatibility between the SIMD instruction model and the chip.

[0012] In a possible implementation of the first aspect, the SIMD instruction generation device generates a first SIMD instruction after the conversion of the first tensor calculation formula according to the length of at least one loop dimension of the first tensor calculation formula and the second SIMD instruction model, which may include: the SIMD instruction generation device generates multiple first SIMD instructions according to the length of at least one loop dimension of the first tensor calculation formula and the second SIMD instruction model. Specifically, the SIMD instruction generation device can generate parameter values ​​for the second SIMD instruction model based on the length of each loop dimension in the N loop dimensions of the first tensor calculation formula, the second SIMD instruction model and the coordinate linearization coefficient of the first tensor calculation formula, and bring the parameter values ​​of the second SIMD instruction model into the second SIMD instruction to obtain the first SIMD instruction. The aforementioned generated parameter values ​​include the parameter value of each first parameter in the second SIMD instruction model, the parameter value of the destination address offset and the parameter value of the source address offset. The SIMD instruction generation device selects a SIMD instruction from the plurality of first SIMD instructions that satisfies an optimization objective based on a cost function for each of the plurality of first SIMD instructions, and uses the SIMD instruction as the first SIMD instruction after conversion of the first tensor calculation formula, wherein the SIMD instruction that satisfies the optimization objective is the SIMD instruction for which the function value of the cost function is the largest or smallest, and the cost function indicates the optimization objective associated with the first SIMD instruction. In this implementation, a cost function is pre-generated to assist in selecting the optimal SIMD instruction during the SIMD instruction conversion phase for executing a tensor calculation formula of the target operation type. The cost function is generated based on the optimization objective and can meet the user's SIMD instruction optimization requirements.

[0013] In a possible implementation of the first aspect, the optimization objective indicated by the cost function includes at least one of the following: minimum total number of SIMD instruction executions, maximum total number of SIMD instruction executions, minimum number of whole blocks and tail blocks in SIMD instructions, maximum number of whole blocks and tail blocks in SIMD instructions, maximum interval between whole blocks and tail blocks in SIMD instructions, minimum interval between whole blocks and tail blocks in SIMD instructions, minimum SIMD instruction scheduling delay, maximum SIMD instruction scheduling delay, minimum total execution time of SIMD instructions, maximum computational overhead of address offsets in SIMD instructions, and minimum computational overhead of address offsets in SIMD instructions. In this implementation, multiple scenarios of optimization objectives are provided, expanding the application scenarios of this solution.

[0014] In a possible implementation of the first aspect, the independent variables of the cost function include at least one of the following: the parameter value of the first parameter in the first SIMD instruction, the number of whole blocks in the first SIMD instruction, the number of tail blocks in the first SIMD instruction, the number of address offset calculations in the first SIMD instruction, the duration of executing a SIMD instruction, and the duration of switching from executing a first SIMD instruction to executing another first SIMD instruction. Furthermore, the parameter value of the first parameter in the SIMD instruction may include the parameter value of the first parameter of the whole block portion of the SIMD instruction and the parameter value of the first parameter of the tail block portion of the SIMD instruction. In this implementation, the SIMD instruction cost function takes into account both the SIMD instruction parameters and the chip hardware parameters, so that the generated optimal SIMD instruction can better utilize the performance of the chip.

[0015] In a possible implementation of the first aspect, the SIMD instruction generation device generates a first SIMD instruction after the conversion of the first tensor calculation formula according to the length of at least one loop dimension of the first tensor calculation formula and the second SIMD instruction model, which may include: the SIMD instruction generation device obtains the first parameter corresponding to the first loop dimension of the first tensor calculation formula according to the first indication information in the information of the second SIMD instruction model. Wherein, the first loop dimension is a loop dimension of at least one loop dimension, and the length of the first loop dimension does not divide the value range of the corresponding first parameter. With respect to the meaning that the length of the first loop dimension does not divide the value range of the corresponding first parameter, one or more first parameters in the SIMD instruction are used to implement the calculation of a first loop dimension, then the length of the first loop dimension does not divide one of the one or more first parameters, or the product of multiple parameters. For example, the one or more first parameters include the fifth parameter and the sixth parameter, then the value range of the first parameter corresponding to the length of the first loop dimension does not divide the value range of the fifth parameter refers to the value range of the first loop dimension that the length of the first loop dimension does not divide the value range of the fifth parameter, or the value product of the fifth parameter and the sixth parameter that the length of the first loop dimension does not divide the value range of the fifth parameter. The SIMD instruction generation device generates parameter values ​​for the whole block portion of the first SIMD instruction and the parameter values ​​for the tail block portion of the first SIMD instruction based on the length of the first loop dimension. Regarding the meanings of the whole block and the tail block, the whole block refers to the portion in the SIMD instruction where the number of data is equal to the preset number, and the tail block refers to the portion in the SIMD instruction where the number of data is less than the preset number. When the chip performs batch calculations on data by calling SIMD instructions, each batch can process a fixed number of data. If the number of data to be processed is not divisible by the aforementioned fixed number, a tail block will be set. The number of data in the tail block is less than the aforementioned fixed number, and the number of data in the whole block is equal to the aforementioned fixed number. If the number of data to be processed is divisible by the aforementioned fixed number, there is no tail block. In this implementation, the technology of the whole block and the tail block can solve the problem of the value range of the first parameter corresponding to the non-divisible length of the first loop dimension, expand the application scenario of this solution, and thus expand the scope of applicability of this solution.

[0016] In a possible implementation of the first aspect, a SIMD instruction generation device generates a first SIMD instruction after conversion of the first tensor calculation formula based on the length of at least one loop dimension of the first tensor calculation formula and a second SIMD instruction model, which may include: the SIMD instruction generation device obtains a first parameter corresponding to the second loop dimension of the first tensor calculation formula based on first indication information in information of the second SIMD instruction model, wherein the second loop dimension is the highest loop dimension among the at least one loop dimensions, and the length of the second loop dimension exceeds the upper limit of the corresponding first parameter; the SIMD instruction generation device generates a parameter value for the entire block portion of the first SIMD instruction based on the length of the second loop dimension. In this implementation, the entire block and tail block technologies can be used to expand the value range of the length of the loop dimension in the constraint condition, thereby expanding the scope of applicability of this solution.

[0017] In a possible implementation of the first aspect, at least one set of first SIMD instruction model information includes information about a third SIMD instruction model, information about a fourth SIMD instruction model, and information about a fifth SIMD instruction model. The value of N corresponding to the third SIMD instruction model information is less than the value of N corresponding to the fourth SIMD instruction model information. The value of N corresponding to the fourth SIMD instruction model information is less than the value of N corresponding to the fifth SIMD instruction model information. N corresponding to the fourth SIMD instruction model information is greater than or equal to 2. The SIMD instruction generation device selects at least one set of second SIMD instruction model information from the at least one set of first SIMD instruction model information, including: the SIMD instruction generation device selects the second SIMD instruction model information from the third SIMD instruction model information; and if the second SIMD instruction model information does not exist in the fourth SIMD instruction model information, the SIMD instruction generation device terminates the selection of the second SIMD instruction model information from the fifth SIMD instruction model information. Furthermore, the SIMD instruction generation device first performs the second SIMD instruction model information selection operation on the third SIMD instruction model information, and then performs the second SIMD instruction model information selection operation on the fourth SIMD instruction model information. In this implementation, if there is no matching model in the low-dimensional model, there is no need to match the high-dimensional model, which can effectively reduce the number of matches and further improve the generation efficiency of SIMD instructions.

[0018] In a possible implementation of the first aspect, the method further includes: the SIMD instruction generation device obtains a second constraint condition, the second constraint condition being used to indicate the number of destination addresses in the first SIMD instruction model and the number of source addresses in the first SIMD instruction model. The SIMD instruction generation device obtains the number of destination addresses in the first tensor calculation formula and the number of source addresses in the first tensor calculation formula. The SIMD instruction generation device selects at least one set of information about the second SIMD instruction model from the at least one set of information about the first SIMD instruction model, including: when the number of destination addresses in the first tensor calculation formula is the same as the number of destination addresses in the first SIMD instruction model, and the number of source addresses in the first tensor calculation formula is the same as the number of source addresses in the first SIMD instruction model, selecting at least one set of information about the second SIMD instruction model from the at least one set of information about the first SIMD instruction model. The method further includes: when the number of destination addresses in the first tensor calculation formula is different from the number of destination addresses in the first SIMD instruction model, or when the number of source addresses in the first tensor calculation formula is different from the number of source addresses in the first SIMD instruction model, outputting a warning message. In this implementation, during the execution of the SIMD instruction automatic conversion operation, it will first be determined whether the number of destination addresses and the number of source addresses in the first tensor calculation formula meet the requirements for the number of destination addresses and the number of source addresses in the SIMD instruction model. Only when the constraints are met will the subsequent SIMD instruction model matching operation be performed to improve the efficiency of the SIMD instruction automatic conversion process; in addition, if it is not met, an alarm message will be output in time to remind technical personnel to intervene in time.

[0019] In a possible implementation of the first aspect, the SIMD instruction generation device obtains information of at least one group of first SIMD instruction models, including: the SIMD instruction generation device obtains information of at least one group of first SIMD instruction models from the information set of the SIMD instruction model. Wherein, the information set of the SIMD instruction model includes at least one information subset of the SIMD instruction model, each information subset of the SIMD instruction model corresponds to a tensor calculation formula of an operation type, different information subsets of SIMD instruction models correspond to tensor calculation formulas of different operation types, and the information subset of the SIMD instruction model to which the information of at least one group of first SIMD instruction models belongs corresponds to the operation type of the first tensor calculation formula. In this implementation, the information of the first SIMD instruction model is generated for a tensor calculation formula of a specific operation type, that is, the information of the SIMD instruction model corresponding to the tensor calculation formula of different operation types is different, so that the information of the first SIMD instruction model is more consistent with the tensor calculation formula of the operation type of the first tensor calculation formula, and is conducive to improving the efficiency of the SIMD instruction generation process.

[0020] In a possible implementation of the first aspect, the method includes: a SIMD instruction generation device obtains a first parameter value and a second parameter value corresponding to a first SIMD instruction model, wherein the first parameter value is K, which is used to indicate that the first SIMD instruction model includes K first parameters, K is an integer greater than or equal to 1, and the second parameter value indicates the value constraints of the K first parameters, and the first parameter reflects the number of times an operation is repeatedly performed on a data object in a tensor calculation formula that matches the first SIMD instruction model. The SIMD instruction generation device generates information of the first SIMD instruction model based on the first parameter value and the second parameter value. Specifically, the SIMD instruction processing device generates first indication information included in the information of the first SIMD instruction model based on the first parameter; and generates first constraint conditions included in the information of the first SIMD instruction model based on the first indication information and the second parameter. In this implementation, the information set of the SIMD instruction model generated corresponding to the chip is used to indicate the SIMD instruction conversion operation for executing the tensor calculation formula; in addition, a plurality of groups of first SIMD instruction model information are generated in advance, and during the conversion process, a matching combination is first screened out from a number of combinations based on the lengths of the N loop dimensions of the tensor calculation formula, which greatly reduces the difficulty of the SIMD instruction generation process and improves the efficiency of automatically generating SIMD instructions.

[0021] In a possible implementation of the first aspect, the method further includes: the SIMD instruction generation device obtains a third parameter value, the third parameter value indicating the number constraint of the whole block in the first SIMD instruction model. The SIMD instruction generation device generates information of the first SIMD instruction model based on the first parameter value and the second parameter value, including: generating first indication information based on the first parameter value; generating a first constraint condition based on the first indication information, the second parameter value, and the third parameter value. The first constraint condition includes a constraint condition on the length of the second loop dimension in the first SIMD instruction model. By setting the whole block method, the upper limit of the value of the length of the second loop dimension can be expanded. Furthermore, the whole block method is set to the upper limit of the value of the length of the product-type expanded second loop dimension. In this implementation, the number constraint of the whole block in the target type of SIMD instruction in the chip is pre-acquired, and combined with the number constraint of the whole block, a constraint condition for indicating the length of the loop dimension of the tensor calculation formula is generated. Through the whole block and tail block technology, the value range of the length of the loop dimension in the constraint condition can be expanded, thereby expanding the scope of application of this solution.

[0022] In a possible implementation of the first aspect, the method further includes: the SIMD instruction generation device obtains a fourth parameter value, the fourth parameter value is used to indicate the number of destination addresses of the first SIMD instruction model and the number of source addresses of the first SIMD instruction model. The SIMD instruction generation device generates a second constraint condition based on the fourth parameter value, and the second constraint condition is used to indicate the number of destination addresses and the number of source addresses in the tensor calculation formula that matches the first SIMD instruction model. In this implementation, the number of destination addresses and the number of source addresses in the SIMD instructions of the target type of the chip are obtained in advance, and then the second constraint condition is generated. The second constraint condition is used to indicate the number of destination addresses and the number of source addresses in the tensor calculation formula of the target operation type, so that the second constraint condition can be used to preliminarily determine whether the SIMD instruction model matches the tensor calculation formula to be converted, thereby avoiding waste of computer resources and improving the efficiency of the tensor calculation formula conversion stage.

[0023] In one possible implementation of the first aspect, the method further includes: the SIMD instruction generation device obtaining a cost function corresponding to the first SIMD instruction. The cost function is used to select an optimal SIMD instruction using the cost function when the SIMD instruction generation device performs a SIMD instruction conversion operation of a tensor computation formula of a target operation type.

[0024] In a second aspect, an embodiment of the present application provides a method for processing a SIMD instruction, which can be used in the field of SIMD instruction generation in the chip field. The method may include: a SIMD instruction processing device obtains a first parameter value and a second parameter value corresponding to a first SIMD instruction model. The first parameter value is K, which is used to indicate that the first SIMD instruction model includes K first parameters, K is an integer greater than or equal to 1, and the second parameter value indicates the value constraint of the K first parameters. The first parameter reflects the number of times an operation is repeatedly performed on a data object in a tensor calculation formula that matches the first SIMD instruction model. The SIMD instruction processing device generates information of the first SIMD instruction model based on the first parameter value and the second parameter value, wherein the information of a first SIMD instruction model corresponds to a first SIMD instruction model, and the information of the first SIMD instruction model includes first indication information and a first constraint condition. The first indication information is used to indicate the correspondence between the K first parameters and at least one loop dimension of the tensor calculation formula that matches the first SIMD instruction model, and the first constraint condition is used to indicate the constraint condition of the length of each loop dimension in the at least one loop dimension.

[0025] In a possible implementation of the second aspect, the method further includes: the SIMD instruction processing apparatus obtaining a third parameter value, where the third parameter value indicates a quantity constraint for the entire block in the first SIMD instruction model. The SIMD instruction processing apparatus generates information about the first SIMD instruction model based on the first parameter value and the second parameter value, including: generating first indication information based on the first parameter value; and generating a first constraint condition based on the first indication information, the second parameter value, and the third parameter value.

[0026] In a possible implementation of the second aspect, the method further includes: the SIMD instruction processing device obtains a fourth parameter value, the fourth parameter value is used to indicate the number of destination addresses of the first SIMD instruction model and the number of source addresses of the first SIMD instruction model; based on the fourth parameter value, a second constraint condition is generated, the second constraint condition is used to indicate the number of destination addresses and the number of source addresses in the tensor calculation formula matching the first SIMD instruction model.

[0027] In a possible implementation of the second aspect, the method further includes: the SIMD instruction processing device obtains a cost function corresponding to the first SIMD instruction model, wherein the cost function is used to screen out SIMD instructions that meet the optimization goal, and the SIMD instructions that meet the optimization goal are SIMD instructions with the largest or smallest function value of the cost function, and the independent variables of the cost function include at least one of the following: the parameter value of the first parameter in the first SIMD instruction, the number of whole blocks in the first SIMD instruction, the number of tail blocks in the first SIMD instruction, the number of calculations of the address offset in the first SIMD instruction, the duration of executing a SIMD instruction, and the duration of switching from the process of executing a first SIMD instruction to the process of executing another first SIMD instruction.

[0028] In a possible implementation of the second aspect, the optimization objectives of the cost function include at least one of the following: minimum total number of SIMD instruction executions, maximum total number of SIMD instruction executions, minimum number of whole blocks and tail blocks in SIMD instructions, maximum number of whole blocks and tail blocks in SIMD instructions, maximum interval between whole blocks and tail blocks in SIMD instructions, minimum interval between whole blocks and tail blocks in SIMD instructions, minimum SIMD instruction scheduling delay, maximum SIMD instruction scheduling delay, minimum total execution time of SIMD instructions, maximum computational overhead of address offset in SIMD instructions, and minimum computational overhead of address offset in SIMD instructions.

[0029] In the second aspect of the present application, the specific implementation methods and beneficial effects of the SIMD instruction processing device executing the second aspect and each possible implementation method of the second aspect can be specifically referred to the first aspect. The SIMD instruction processing device can also execute various other possible implementation methods in the first aspect, which will not be repeated here.

[0030] In a third aspect, an embodiment of the present application provides a SIMD instruction generation device, which can be used in the SIMD instruction generation field in the chip field, and the device includes: an acquisition module, used to obtain the length of each loop dimension of a first tensor calculation formula; the acquisition module is also used to obtain information of multiple groups of first single-instruction multiple-data SIMD instruction models, wherein the information of each group of first SIMD instruction models corresponds to at least one loop dimension of a tensor calculation formula, and the information of each group of first SIMD instruction models includes a first constraint condition, and the first constraint condition is used to indicate the constraint condition of the length of each loop dimension in at least one loop dimension; a selection module is used to select information of a second SIMD instruction model from the information of multiple groups of first SIMD instruction models according to the first constraint condition and the length of each loop dimension of the first tensor calculation formula, the information of the second instruction model matches the first tensor calculation formula, and the length of the loop dimension of the first tensor calculation formula satisfies the first constraint condition in the information of the second SIMD instruction model; a generation module is used to generate a first SIMD instruction after the conversion of the first tensor calculation formula according to the length of at least one loop dimension of the first tensor calculation formula and the second SIMD instruction model.

[0031] The constituent modules of the SIMD instruction generation device provided in the third aspect of this application can also be used to execute the steps performed by the SIMD instruction generation device in various possible implementation methods of the first aspect. For details, please refer to the description in the first aspect and the various possible implementation methods in the first aspect, and will not be repeated here.

[0032] In a fourth aspect, an embodiment of the present application provides a SIMD instruction processing device, which can be used in the SIMD instruction generation field in the chip field. The device includes: an acquisition module, used to obtain a first parameter value and a second parameter value corresponding to a first SIMD instruction model, wherein the value of the first parameter value is K, used to indicate that the first SIMD instruction model includes K first parameters, K is an integer greater than or equal to 1, and the second parameter value indicates the value constraint of the K first parameters, and the first parameter reflects the number of times an operation is repeatedly performed on a data object in a tensor calculation formula matching the first SIMD instruction model; a generation module, used to generate information of the first SIMD instruction model based on the first parameter value and the second parameter value, wherein the information of a first SIMD instruction model corresponds to a first SIMD instruction model, and the information of the first SIMD instruction model includes first indication information and first constraint conditions, the first indication information is used to indicate the correspondence between the K first parameters and at least one loop dimension of the tensor calculation formula matching the first SIMD instruction model, and the first constraint condition is used to indicate the constraint condition on the length of each loop dimension in at least one loop dimension.

[0033] The constituent modules of the SIMD instruction generation device provided in the fourth aspect of this application can also be used to execute the steps performed by the SIMD instruction generation device in various possible implementation methods of the second aspect. For details, please refer to the description in the second aspect and the various possible implementation methods in the second aspect, and will not be repeated here.

[0034] In the fifth aspect, an embodiment of the present application provides an execution device, including a processor, which is coupled to a memory; the memory is used to store programs; and the processor is used to execute the programs in the memory, so that the execution device executes the steps performed by the SIMD instruction generation device in each possible implementation method of the first aspect.

[0035] In the sixth aspect, an embodiment of the present application provides an execution device, including a processor, which is coupled to a memory; the memory is used to store programs; and the processor is used to execute the programs in the memory, so that the execution device executes the steps performed by the SIMD instruction processing device in each possible implementation method of the second aspect.

[0036] In the seventh aspect, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program. When the computer-readable storage medium is run on a computer, it enables the computer to execute the SIMD instruction processing method described in the first aspect above, or enables the computer to execute the SIMD instruction processing method described in the second aspect above.

[0037] In an eighth aspect, an embodiment of the present application provides a computer program product, which includes a program. When the aforementioned program is run on a computer, it enables the computer to execute the processing method of SIMD instructions described in the first aspect above, or enables the computer to execute the processing method of SIMD instructions described in the second aspect above.

[0038] In a ninth aspect, the present application provides a chip system, which includes a processor for supporting a terminal device or a communication device to implement the functions involved in the above aspects, for example, sending or processing the data and / or information involved in the above methods. In one possible design, the chip system also includes a memory, which is used to store program instructions and data necessary for the terminal device or communication device. The chip system can be composed of a chip, or it can include a chip and other discrete devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 A system architecture diagram of a SIMD instruction processing system provided in an embodiment of the present application;

[0040] Figure 2 A flowchart of a method for processing SIMD instructions provided in an embodiment of the present application;

[0041] Figure 3 Another flowchart of a method for processing SIMD instructions provided in an embodiment of the present application;

[0042] Figure 4 A schematic diagram of the correspondence between the first parameter and the loop dimension in the SIMD instruction processing method provided in an embodiment of the present application;

[0043] Figure 5 A flow chart of a method for generating SIMD instructions provided in an embodiment of the present application;

[0044] Figure 6 A flowchart of another method for processing SIMD instructions provided in an embodiment of the present application;

[0045] Figure 7 A structural diagram of a SIMD instruction generation device provided in an embodiment of the present application;

[0046] Figure 8 A structural diagram of a SIMD instruction processing device provided in an embodiment of the present application;

[0047] Figure 9 A schematic diagram of the structure of the execution device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0048] An embodiment of the present application provides a method for generating and processing a SIMD instruction and related equipment, which is used to select information of a second SIMD instruction model from multiple groups of information of first SIMD instruction models based on the length of each loop dimension of a tensor calculation formula, and then generate a first SIMD instruction after converting the first tensor calculation formula based on the second SIMD instruction model, thereby greatly improving the efficiency of the SIMD instruction generation process.

[0049] The embodiments of the present application are described below in conjunction with the accompanying drawings. Those skilled in the art will appreciate that, with the development of technology and the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0050] The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, and this is merely a way of distinguishing the objects of the same attributes when describing them in the embodiments of the present application. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, so that the process, method, system, product or equipment comprising a series of units need not be limited to those units, but may include other units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0051] It should be understood that the processing method of the SIMD instructions provided in the embodiments of the present application can be applied to the development process of various types of chips. Among them, the aforementioned chip can be specifically manifested as a central processing unit (CPU), an AI chip or other types of chips. Further, AI chips include but are not limited to neural network processors (neural-network processing unit, NPU), graphics processing units (graphics processing unit, GPU), application specific integrated circuits (application specific integrated circuit, ASIC), field programmable gate arrays (field programmable gate array, FPGA), etc. In the development process of the aforementioned various chips, the generation method of the SIMD instructions provided in the embodiments of the present application can be used to realize the automatic conversion of tensor calculation formulas to SIMD instructions.

[0052] First, see Figure 1 , Figure 1 A system architecture diagram of a SIMD instruction processing system provided in an embodiment of the present application, Figure 1 : A SIMD instruction model processing device 100 and a SIMD instruction model generating device 200 are shown. The SIMD instruction model processing device 100 is used to generate a software package including information of multiple sets of first SIMD instruction models, and configure the software package in the SIMD instruction model generating device 200. When the SIMD instruction model generating device 200 needs to perform a conversion operation from a first tensor calculation formula to a SIMD instruction, the length of each loop dimension of the first tensor calculation formula is obtained, and information of a second SIMD instruction model is selected from the information of the multiple sets of first SIMD instruction models according to the length of each loop dimension of the first tensor calculation formula. The information of the second instruction model is matched with the first tensor calculation formula, thereby generating a first SIMD instruction after the first tensor calculation formula is converted.

[0053] The SIMD instruction model processing device 100 and the SIMD instruction model generating device 200 may be integrated into the same device or located in different devices. When integrated into the same device, the SIMD instruction model processing device 100 may configure a software package including information about multiple sets of first SIMD instruction models on the SIMD instruction model generating device 200 via a bus. When located in different devices, the SIMD instruction model processing device 100 may configure the software package in the SIMD instruction model processing device via a wired network, a wireless network, or a removable storage medium.

[0054] Furthermore, the SIMD instruction model processing device 100 and the SIMD instruction model generating device 200 can both be devices with communication functions, such as desktop computers, laptop computers, personal digital assistants (PDAs), tablet computers, handheld devices, wearable devices, etc., which are not limited here. It should be understood that although Figure 1 FIG. 1 shows a SIMD instruction model processing device 100 and three SIMD instruction model generating devices 200, but Figure 1 This is only for facilitating understanding of this solution and is not intended to limit the number of devices.

[0055] To facilitate understanding of this solution, before introducing the SIMD instruction processing method provided in the embodiment of the present application, the following terms appearing in the embodiment of the present application are first introduced:

[0056] Tensor calculation formulas include one or more nested for-loops. Each for-loop defines the calculation formula to be executed by the for-loop. The calculation formula includes tensors and operators. Of course, each for-loop can also include the range of values ​​of the coordinates in the tensor. Tensors are multilinear maps defined on the Cartesian product of a vector space and a dual space. The operators in the tensor calculation formula determine the operation type of the tensor calculation formula. The operation type of the first tensor calculation formula can be addition or multiplication.

[0057] Loop dimension: A tensor calculation formula can be specifically expressed in the form of a for loop. A tensor calculation formula can include multiple data objects. A loop dimension of a tensor calculation formula refers to a for loop in the tensor calculation formula.

[0058] Length of loop dimension: The length of a loop dimension in a tensor calculation formula refers to the upper limit of the coordinate values ​​in a for loop of the tensor calculation formula.

[0059] SIMD instruction model: The format of the SIMD instruction model is the same as that of the SIMD instruction. The difference is that the parameter values ​​of each parameter in the SIMD instruction model have not yet been determined, while the parameter values ​​of each parameter in the SIMD instruction have been determined.

[0060] Whole block and tail block: When the chip performs batch calculations on data objects by calling SIMD instructions, each batch can process a fixed number of data objects. If the number of data objects to be processed is not divisible by the aforementioned fixed number, a tail block will be set. The number of data objects in the tail block is less than the aforementioned fixed number, and the number of data objects in the whole block is equal to the aforementioned fixed number. If the number of data objects to be processed is divisible by the aforementioned fixed number, there will be no tail block.

[0061] The length of the first loop dimension is not evenly divisible by the value range of the corresponding first parameter: one or more first parameters in the SIMD instruction are used to implement calculations of a first loop dimension, and the aforementioned one or more first parameters include a fifth parameter and a sixth parameter, and the fifth parameter is sorted earlier in the aforementioned one or more first parameters than the sixth parameter is sorted in the aforementioned one or more first parameters. Then, the length of the first loop dimension is not evenly divisible by the value range of the corresponding first parameter refers to the length of the first loop dimension that is not evenly divisible by the value range of the fifth parameter, or, the length of the first loop dimension is not evenly divisible by the product of the values ​​of the fifth parameter and the sixth parameter.

[0062] Next, the specific implementation of the embodiment of the present application is described. Figure 2 , Figure 2 A flow chart of a method for processing SIMD instructions provided in an embodiment of the present application. The scheme provided in an embodiment of the present application can be divided into a stage of generating information of a SIMD instruction model and a stage of converting a tensor calculation formula. In the stage of generating information of a SIMD instruction model, a SIMD instruction processing device generates an information set of a SIMD instruction model, and the information set of a SIMD instruction model includes information of at least one first SIMD instruction model; in the stage of converting a tensor calculation formula, after obtaining a first tensor calculation formula of an operation type of a first tensor calculation formula, the SIMD instruction generating device obtains a SIMD instruction model that matches the first tensor calculation formula according to the information of the first SIMD instruction model generated in advance, and then generates a SIMD instruction corresponding to the first tensor calculation formula. The following describes the specific implementation process of the stage of generating information of a SIMD instruction model and the stage of converting a tensor calculation formula in the method for processing SIMD instructions provided in an embodiment of the present application.

[0063] 1. SIMD instruction model information generation stage

[0064] In the embodiments of this application, please refer to Figure 3 , Figure 3 A flowchart of a method for processing a single instruction, multiple data (SIMD) instruction provided in an embodiment of the present application is provided. The method for processing a single instruction, multiple data (SIMD) instruction provided in an embodiment of the present application may include:

[0065] 301. A SIMD instruction processing apparatus obtains a first parameter value and a second parameter value corresponding to a first SIMD instruction model.

[0066] In an embodiment of the present application, since the chip can support one or more types of SIMD instructions, the SIMD instruction processing device will select a target type of SIMD instruction from the aforementioned one or more types of SIMD instructions to generate information of a first SIMD instruction model of the target type as the target of a generation operation. Among them, the specific manifestation of the chip can be found in the above description and will not be repeated here. The target type of SIMD instruction is a SIMD instruction among the one or more types of SIMD instructions supported by the chip. Each type of SIMD instruction corresponds to a tensor calculation formula of an operation type. The SIMD instruction formats of different types of SIMD instructions are different; when the target type of SIMD instruction is called by the chip, it is used to implement the operation of the tensor calculation formula of the target operation type. Furthermore, the tensor calculation formula is a calculation formula including a tensor (tensor) and an operator. The tensor is a multilinear mapping defined on the Cartesian product of the vector space and the dual space. The zero-order tensor can be called a scalar, and the first-order tensor can be called a vector. The operator in the tensor calculation formula determines the operation type of the tensor calculation formula. The target operation type can be specifically addition, multiplication or other types of operation types.

[0067] To further understand this solution, the SIMD instructions in the embodiment of this application are shown by the following formula:

[0068] SIMD_OP([dst i ],[src j ],[repeat k ],[dstStride i,k ],[srcStride j,k ],[other z ]);(1)

[0069] Among them, OP stands for operator, [dst i ](i=0,1,…,I-1) represents the destination address set of the data object corresponding to the SIMD instruction, i is an integer greater than or equal to 0, [src j ](j=0,1,…,J-1) represents the source address set of the data object corresponding to the SIMD instruction, j is an integer greater than or equal to 0, [repeatk ](k=0,1,…,K-1) represents the K first parameters in the embodiment of the present application, and the first parameter refers to repeat k The value of the first parameter reflects the chip's execution of repeat k The parameter is the number of times the operation is repeated on the data object. K is an integer greater than or equal to 1. The operations performed on the data object include reading, calculating, and writing. 0≤repeat k ≤R k ,(k=0,1,…,K-1),R k Represents repeat k The upper limit of the value, R k The value of is determined by the chip. When executing the SIMD instruction shown in formula (1), the chip follows the formula ([0,repeat0],[0,repeat1],…,[0,repeat K-1 ]) in the order of performing operations on the data objects corresponding to the SIMD instructions, *dstStride i,k +(i=0,1,…,I-1;k=0,1,…,K-1) represents the chip executing a certain repeat k The parameter is the destination address dst corresponding to the data object i The address offset, *srcStride j,k +(j=0,1,…,J-1;k=0,1,…,K-1) represents the chip executing a certain repeat k The parameter is the source address src corresponding to the data object j The address offset of [other z ](z=0,1,…,Z-1) are other parameters, and z is an integer greater than or equal to 0. It should be understood that the above formula (1) is only a schematic diagram for facilitating the understanding of SIMD instructions. In other implementations, the order of arrangement of the parameters in the SIMD instruction may be different from that in formula (1), or the parameters in the SIMD instruction may be added or deleted based on formula (1), which is not limited here.

[0070] The tensor calculation formula in the embodiment of the present application is shown by the following formula:

[0071] for(x0,x1,…,x H-1 )in(X0,X1,…,X H-1 ):

[0072] [D i (x0,x1,…,x H-1 )]=OP([S j (x0,x1,…,x H-1 )])(2)

[0073] The tensor calculation formula can be specifically expressed in the form of a for loop. A loop dimension of the tensor calculation formula refers to the dimension where a coordinate of a data object in the tensor calculation formula in the for loop form is located. Formula (2) shows a tensor calculation formula including H loop dimensions, (x0, x1, ..., x H-1 ) represents the tensor D i and tensor S j The coordinates of , where i = 0, 1, ..., I-1, and I is an integer greater than or equal to 0, the value of I represents the number of destination addresses in the tensor calculation formula, j = 0, 1, ..., J-1, and J is an integer greater than or equal to 0, the value of J represents the number of source addresses in the tensor calculation formula, OP represents the operator (also known as the operation type), (X0, X1, ..., X H-1 ) includes H X θ , X θ =[0,E θ ],(θ=0,1,…,H-1),E θ Is a non-negative integer representing the length of the θth loop dimension of the tensor calculation formula, x θ ∈X θ , the length of a loop dimension in a tensor calculation formula is related to the value range of a data object in the tensor calculation formula.

[0074] An equivalent linearized expression of the above formula (2) is as follows:

[0075]

[0076] in, Represents tensor D i Coordinate linearization coefficient, x p represents (x0, x1, ..., x H-1 ), Represents the tensor S j Coordinate linearization coefficient of .

[0077] Furthermore, a specific example of a tensor calculation formula is shown below:

[0078]

[0079] Among them, formula (4) is a tensor calculation formula including 6 loop dimensions, that is, H=6, tensor D0, tensor S0 and tensor S1 all include (x0, x1, x2, x3, x4, x5), the number of destination addresses of the tensor calculation formula shown in formula (4) is 1, the number of source addresses is 2, the length E0 of the loop dimension where x0 is located is 16, the length E1 of the loop dimension where x1 is located is 4, the length E2 of the loop dimension where x2 is located is 6, the length E3 of the loop dimension where x3 is located is 4, the length E4 of the loop dimension where x4 is located is 6, and the length E5 of the loop dimension where x5 is located is 6. The value of is 1, The value of is 16. The value of is 48. The value is 304. The value of is 912. The value of is 5776. The value of is 1, The value of is 16. The value of is 48. The value is 304. The value of is 912. The value of is 5776. The value of is 1, The value of is 0, The value of is 16. The value of is 0, The value of is 96. The value of is 576. It should be understood that the examples of tensor calculation formulas in the above formulas (2), (3) and (4) are only for the convenience of understanding this solution and are not used to limit this solution.

[0080] The SIMD instruction processing device obtains the first parameter value and the second parameter value corresponding to the target type of SIMD instruction. The first parameter value is K, which is used to indicate that the target type of SIMD instruction includes K first parameters, and the target function refers to the repeat in the above formula (1) k The second parameter value is used to indicate the value constraints of the K first parameters in the chip. The second parameter value refers to the K R in the above formula (1). k The chip can implement the tensor calculation formula of the target operation type when executing the SIMD instruction of the target type, and the K first parameters correspond to the N loop dimensions in the tensor calculation formula of the target operation type, where N is an integer less than or equal to K and greater than or equal to 1. Furthermore, the chip can implement the calculation of a loop dimension of the tensor calculation formula through one-dimensional or multi-dimensional first parameters. It should be noted that the tensor calculation formula of the aforementioned target operation type may include H loop dimensions, where H is an integer greater than or equal to N.

[0081] Specifically, in one implementation, after understanding the specifications and performance of the chip, the user can obtain the first parameter value and the second parameter value corresponding to the target type of SIMD instruction in the chip, and then the SIMD instruction processing device can receive the first parameter value and the second parameter value input by the user. More specifically, the display interface of the SIMD instruction processing device can directly display the input boxes for the first parameter value and the second parameter value, so that the user can input the first parameter value and the second parameter value through the aforementioned input boxes. The SIMD instruction processing device can also receive a file containing the first parameter value and the second parameter value input from the user, so that the SIMD instruction processing device can extract the input boxes for the first parameter value and the second parameter value from the aforementioned file. The aforementioned file can be specifically expressed as a text document, a spreadsheet document, a program code or other format file, etc. In another implementation, the SIMD instruction processing device can also receive the SIMD instruction model of the target type in the chip input by the user. The SIMD instruction processing device parses the aforementioned SIMD instruction model to obtain the parameter value of the first parameter. The way in which the SIMD instruction processing device obtains the second parameter value is similar to that in the aforementioned implementation and will not be repeated here.

[0082] Optionally, the SIMD instruction processing device obtains a third parameter value, which is used to indicate the number constraint of the whole block (Body) in the SIMD instruction of the target type. Among them, the SIMD instruction processing device can implement tensor calculation operations through SIMD instructions of the whole block part and the tail block (Tail) part. Furthermore, when the chip performs batch calculations on data objects by calling SIMD instructions, each batch can process a fixed number of data objects. If the number of data objects to be processed is not divisible by the aforementioned fixed number, a tail block will be set, and the number of data objects in the tail block is less than the aforementioned fixed number, and the number of data objects in the whole block is equal to the aforementioned fixed number; if the number of data objects to be processed is divisible by the aforementioned fixed number, there is no tail block. As an example, please refer to the following formula:

[0083]

[0084] The above formula shows that a set of SIMD instructions (5) and (6) are used in conjunction with a For-x loop to implement the H loop dimensions of the tensor calculation formula. The above formula (5) represents the whole block part of a set of SIMD instructions, and the above formula (6) represents the tail block part of a set of SIMD instructions. p represents (x N ,x N+1 ,…,x H-1 ), Represents tensor Di Medium x p The coordinate linearization coefficient of represent Any parameter in The number of K first parameters representing the entire block of SIMD instructions, and in, Repeat in SIMD instructions representing the target type in the chip k The upper limit of the number of parameter blocks, is an integer greater than or equal to 0, The destination address D representing the entire block of a group of SIMD instructions i middle The address offset of Represents the tensor S j Medium x p The coordinate linearization coefficient of The source address S represents the entire block of SIMD instructions. j middle The address offset of represents the K first parameters of a block of SIMD instructions, The value of [dstStride] reflects the number of times the chip repeats the operation on the data object when executing the K first parameters of the entire block in a set of SIMD instructions. i,k ] indicates that the chip is executing a repeat k The parameter is the destination address dst corresponding to the data object i The address offset, *srcStride j,k +(j=0,1,…,J-1;k=0,1,…,K-1) represents the chip executing a certain repeat k The parameter is the source address src corresponding to the data object j The address offset of represent Any parameter in represents the number of K first parameters of the tail block part of a group of SIMD instructions, and in, Repeat in SIMD instructions representing the target type in the chip k The upper limit of the number of parameter tail blocks, The value of is 0 or 1. When there is no tail block, When the representation has a tail block, Represents the destination address D of the tail block of a group of SIMD instructions i middle The address offset of Represents the source address S of the tail block of a group of SIMD instructions j middle The address offset of Represents the K first parameters of the tail block part of a group of SIMD instructions, The value of reflects the number of repetitions of the operation performed on the data object by the chip when executing the K first parameters of the tail block portion of a set of SIMD instructions. It should be understood that in other embodiments, tensor calculation operations can be implemented using only the whole block portion and the tail block portion of a set of SIMD instructions without the need for a For loop; or, tensor calculation operations can be implemented using only the whole block portion without the tail block portion, etc. The above examples are merely for facilitating the understanding of the concepts of whole block and tail block and are not intended to limit this solution.

[0085] A set of SIMD instructions is used to implement the calculation of N loop dimensions of a tensor calculation formula. Correspondingly, the whole block portion of the set of SIMD instructions includes N types of whole blocks, each whole block corresponding to one loop dimension of the N loop dimensions; the tail block portion of the set of SIMD instructions includes N types of tail blocks, each tail block corresponding to one loop dimension of the N loop dimensions, where N is an integer greater than or equal to 1. The number constraint on the whole blocks in the target type of SIMD instructions included in the third parameter refers to the upper limit on the number of whole blocks corresponding to the second loop dimension in the N types of whole blocks. As an example, for example, if the third parameter also includes the number constraint on the whole blocks in the target type of SIMD instructions, where the number constraint value of the whole blocks is 5, and a set of SIMD instructions of the target type is used to implement the calculation of 2 loop dimensions of a tensor calculation formula, then the upper limit on the number of whole blocks corresponding to the second loop dimension of the tensor calculation formula in the whole block portion of the target type of SIMD instructions is 5. It should be understood that this example is only for the convenience of understanding of this solution and is not used to limit this solution.

[0086] Specifically, similar to the manner in which the SIMD instruction processing apparatus obtains the second parameter, in one implementation, the SIMD instruction processing apparatus may receive the third parameter value input by the user through an input box. In another implementation, the SIMD instruction processing apparatus may receive a file containing the third parameter value input by the user.

[0087] Optionally, the SIMD instruction processing apparatus obtains a fourth parameter value, the fourth parameter value being used to indicate the number of destination addresses of the target type of SIMD instructions and the number of source addresses of the target type of SIMD instructions. The number of destination addresses of the target type of SIMD instructions is also the value of I in formula (1), and the number of source addresses of the target type of SIMD instructions is also the value of J in formula (1). As an example, for example, if a certain SIMD instruction includes dst0, src0, and src1, then the number of destination addresses in the SIMD instruction is 1, and the number of source addresses is 2. It should be understood that the examples here are only for the convenience of understanding this solution and are not used to limit this solution.

[0088] Specifically, similar to the manner in which the SIMD instruction processing apparatus obtains the first parameter, in one implementation, the SIMD instruction processing apparatus may receive a fourth parameter value input by a user through an input box. In another implementation, the SIMD instruction processing apparatus may receive a file containing the fourth parameter value input by a user. In another implementation, the SIMD instruction processing apparatus may receive a SIMD instruction model of a target type in a chip input by a user and extract the fourth parameter value therefrom.

[0089] 302. A SIMD instruction processing apparatus generates information of a first SIMD instruction model.

[0090] In an embodiment of the present application, after executing step 301, the SIMD instruction processing device can generate at least one set of first SIMD instruction model information based on the parameters obtained in step 301. The information of the first SIMD instruction model is used to indicate the SIMD instruction conversion operation of the tensor calculation formula of the target operation type according to the information of the first SIMD instruction model. Each set of first SIMD instruction model information corresponds to a first SIMD instruction model, and the first SIMD instruction model is used to generate a SIMD instruction of the target type. The format of a first SIMD instruction model is the same as the format of the SIMD instruction of the target type, except that the parameter values ​​of each parameter in the first SIMD instruction model have not yet been determined, while the parameter values ​​of each parameter in the SIMD instruction have been determined. Each set of first SIMD instruction model information includes first indication information and first constraint conditions, wherein the first indication information is used to indicate the correspondence between the K first parameters included in the first SIMD instruction model and the N loop dimensions of the tensor calculation formula that matches the information of the first SIMD instruction model, and the first constraint condition is used to indicate the constraint conditions on the length of the N loop dimensions of the tensor calculation formula that matches the information of the first SIMD instruction model under the premise of the correspondence indicated by the first indication information.

[0091] Furthermore, the information of at least one group of first SIMD instruction models includes information of multiple types of SIMD instruction models, and the value of N corresponding to the information of different types of SIMD instruction models is different, and N is an integer greater than or equal to 1. In this implementation, the information of at least one group of first SIMD instruction models is divided into categories according to the number of loop dimensions corresponding to the information of the first SIMD instruction model, which facilitates the subsequent management of the information of different types of first SIMD instruction models separately and improves the management accuracy. The first constraint condition is related to the chip type, and the first constraint conditions of different types of chips may be different. In the embodiment of the present application, the information set of the SIMD instruction model is generated based on a specific chip, and different chips will generate different SIMD instruction model information, which not only expands the application scenario of this solution, but also improves the fit between the SIMD instruction model and the chip. Optionally, the information of the first SIMD instruction model may also include a third constraint condition, which is used to indicate the value constraint of the address offset in the SIMD instruction model under the premise of the corresponding relationship indicated by the first indication information.

[0092] Specifically, in one case, if only the first parameter and the second parameter are obtained in step 301, and the third parameter (i.e., the constraint on the number of whole blocks in the target type of SIMD instruction) and the fourth parameter (i.e., the number of destination addresses and the number of source addresses in the target type of SIMD instruction) are not obtained, the SIMD instruction processing apparatus may default the number of whole blocks to 1 and the number of tail blocks to 0. Step 302 may include: the SIMD instruction processing apparatus generating first indication information included in the information of the first SIMD instruction model based on the first parameter; and the SIMD instruction processing apparatus generating first constraints included in the information of the first SIMD instruction model based on the first indication information and the second parameter.

[0093] More specifically, regarding the process of generating the first indication information, there are K repeats in the target type SIMD instruction of the target chip. k , repeat k The correspondence between the loop dimension of the tensor calculation formula of the target operation type can be one-to-one or many-to-one; and K repeats k The permutations and combinations can be made at will, and the value of N can be any value between 1 and K. After knowing the value of K, the SIMD instruction processing device can repeat K of the target type of SIMD instructions. k Perform permutations and combinations to generate up to K repeats k 2 between N cyclic dimensions K-1 There are at most 2 corresponding relationships. K-1First indication information, each first indication information can indicate the generation of a first SIMD instruction model, that is, there can be at most 2 K-1 The first SIMD instruction model.

[0094] Furthermore, if K repeats of the target type SIMD instruction are used k represents a loop dimension of the target operation type (that is, the value of N is 1), then K repeats k There is a corresponding relationship with 1 loop dimension. If K repeats in the target type SIMD instruction k Represents the K' loop dimensions of the target operation type (that is, the value of N is K'), K' is an integer greater than 1 and less than K, then K repeat k There is a K′ cyclic dimension There are corresponding relationships, that is, there can be A SIMD instruction model, a SIMD instruction processing device can generate the aforementioned If K repeats of the target type SIMD instruction are used k Indicates the K loop dimensions of the target operation type (that is, the value of N is K), then K repeat k There is a corresponding relationship between K and the number of loop dimensions. For example, if K is 3, then K repeats k There are four corresponding relationships between the N loop dimensions (that is, there are four first indication information). In the first corresponding relationship, the 3D repeat k Together they represent one cyclic dimension. In the second correspondence, the first two dimensions repeat k Used to represent 1 loop dimension, the next dimension is repeat k Used to represent 1 cyclic dimension. In the third correspondence, the first dimension repeat k Used to represent 1 loop dimension, the last two dimensions are used to represent 1 loop dimension, in the fourth correspondence, 3D repeat k Represent the three circular dimensions respectively.

[0095] To more intuitively show the correspondence between the first parameter and the loop dimension, see Figure 4 , Figure 4 A schematic diagram of the correspondence between the first parameter and the loop dimension in the processing method of the SIMD instruction provided in the embodiment of the present application. Wherein, K' refers to N values, representing K repeats in the target type of SIMD instruction kIt is divided into K' groups, which are respectively used to represent the K' loop dimensions of the tensor computation formula of the target operation type. As shown in the figure, repeat0 and repeat1 are used to represent the first loop dimension among the K' loop dimensions of the tensor computation formula of the target operation type, repeat2 to repeat6 are used to represent the second loop dimension among the K' loop dimensions of the tensor computation formula of the target operation type, repeat K-3 and repeat K-2 are used to represent the (K'-1)th loop dimension among the K' loop dimensions of the tensor computation formula of the target operation type, repeat K-1 is used to represent the K'th loop dimension among the K' loop dimensions of the tensor computation formula of the target operation type, etc., Figure 4 which intuitively shows the correspondence between the first parameter and the loop dimension. Hereinafter, the correspondence of other loop dimensions among the K' loop dimensions will not be described. It should be understood that Figure 4 the examples in

[0096] are only for facilitating the understanding of the concept of the first indication information and are not used to limit the present solution. K-1 For the process of generating the first constraint condition. In order to ensure the feasibility of the correspondence indicated by the first indication information, the SIMD instruction processing device also needs to generate 2 K-1 first constraint conditions that correspond one-to-one with 2 k first indication information. If one loop dimension x k in the tensor computation formula of the target operation type is represented by K repeats k in the SIMD instruction, and the length of the loop dimension x k is E , then the following constraint condition needs to be satisfied k , that is, the length of one loop dimension of the tensor computation formula needs to be less than or equal to the product upper limit of K first parameters. If K repeats k are used to represent K' loop dimensions, where K' is an integer greater than 1 and less than K, there are correspondence relationships between K repeats and K' loop dimensions. In the s-th correspondence relationship among the foregoing correspondence relationships, for any loop dimension x k (0 ≤ k < K') in the tensor computation formula of the target operation type is represented by repeat parameters, that is where, η represents any value from 0 to in The subscript of , and ζ=0,1,…,k-1, then it needs to satisfy This constraint. If K repeats in SIMD instructions k The K loop dimensions x in the tensor computation used to represent the target operation type k , that is, each dimension of the SIMD instruction is repeated k Both are used to represent a loop dimension x in the tensor calculation formula of the target operation type k , the loop dimension x k The length is E k , then it is necessary to satisfy E k ≤R k This constraint, that is, the length of the tensor calculation loop dimension must be less than or equal to repeat k To give a more intuitive understanding of the first constraint, the following table shows the upper limit of .

[0097] Table 1

[0098]

[0099] Refer to Table 1 above. Table 1 more intuitively shows the specific presentation form of the first constraint condition under the premise of the corresponding relationship indicated by the first indication information. Since it has been described in detail in the text part before Table 1, it will not be described in detail here.

[0100] In another case, if the first parameter, the second parameter, and the third parameter (i.e., the number constraint of the whole blocks in the target type of SIMD instructions in the chip) are obtained in step 301, and the fourth parameter (i.e., the number of destination addresses and the number of source addresses of the target type of SIMD instructions) are not obtained. Step 302 may include: the SIMD instruction processing device generates a first indication information based on the first parameter value; the SIMD instruction processing device generates a first constraint condition based on the first indication information, the second parameter value, and the third parameter value. In an embodiment of the present application, the number constraint of the whole blocks in the target type of SIMD instructions in the chip is obtained in advance, and combined with the number constraint of the whole block, a constraint condition for indicating the length of the loop dimension of the tensor calculation formula is generated. Through the technology of whole blocks and tail blocks, the value range of the length of the loop dimension in the constraint condition can be expanded, thereby expanding the scope of applicability of this solution.

[0101] Specifically, for the specific implementation method of the SIMD instruction processing device generating one or more first indication information according to the first parameter value, you can refer to the description in the previous case, which will not be repeated here. The SIMD instruction processing device generates a first constraint condition according to the first indication information, the second parameter value and the third parameter value. Among them, the influence of the number of whole blocks in the three parameters on the first constraint condition is considered. Let the number of whole blocks in the target type of SIMD instructions in the chip be in, represents the upper limit on the number of whole blocks of SIMD instructions of the target type in the chip, represents the constraint on the number of whole blocks in the target type of SIMD instructions in the third parameter, then the restriction R in the first constraint k will be relaxed to From the above formula, we can know that by setting the whole block as the product formula, the first constraint condition R k Furthermore, the target type SIMD instruction is used to implement the calculation of N loop dimensions of the tensor calculation formula, and the upper limit of the constraint of the second loop dimension is relaxed through the whole block and tail block technology. As an example, for example, if the value of N is 2, the first constraint before expansion is E0≤16×4,E1≤8, and the upper limit of the number of whole blocks is 5, then the first constraint after expansion is E0≤16×4,E1≤8×5, that is, only the constraints corresponding to the Nth (i.e., 2nd) loop dimension are expanded.

[0102] In another case, if the first parameter, the second parameter, and the fourth parameter (i.e., the number of destination addresses and the number of source addresses of the target type of SIMD instruction) are obtained in step 301, and the third parameter (i.e., the constraint on the number of whole blocks in the target type of SIMD instruction) is not obtained, the SIMD instruction processing device may default to the number of whole blocks being 1. Step 302 may include: the SIMD instruction processing device generates first indication information based on the first parameter value; generates a first constraint condition based on the first indication information and the second parameter information; and generates a second constraint condition based on the fourth parameter value, wherein the information subset of the SIMD instruction model may include only one second constraint condition in the information subset of the entire SIMD instruction model, or may include the second constraint condition in the information of each group of the first SIMD instruction model. The second constraint condition is used to indicate the number of destination addresses in the tensor calculation formula of the target operation type and the number of source addresses in the tensor calculation formula of the target operation type. In an embodiment of the present application, the number of destination addresses and the number of source addresses in the SIMD instructions of the target type of the chip are obtained in advance, and then a second constraint condition is generated. The second constraint condition is used to indicate the number of destination addresses and the number of source addresses in the tensor calculation formula of the target operation type, so that a preliminary judgment can be made based on the second constraint condition whether the SIMD instruction model matches the tensor calculation formula to be converted, thereby avoiding waste of computer resources and improving the efficiency of the tensor calculation formula conversion stage.

[0103] Specifically, for the specific implementation method of the SIMD instruction processing device generating the first indication information based on the first parameter value, and the specific implementation method of the SIMD instruction processing device generating the first constraint condition based on the first indication information and the second parameter information, please refer to the specific implementation method of the SIMD instruction processing device when only the first parameter and the second parameter are obtained in step 301, which will not be described in detail here. For the specific implementation method of the SIMD instruction processing device generating one or more second constraints based on the fourth parameter value, after obtaining the number of destination addresses and the number of source addresses of the target type of SIMD instructions, the SIMD instruction processing device can determine the number of destination addresses of the target type of SIMD instructions as the number of destination addresses in the tensor calculation formula of the target operation type in the second constraint condition, and determine the number of source addresses of the target type of SIMD instructions as the number of source addresses in the tensor calculation formula of the target operation type in the second constraint condition. As an example, if the number of destination addresses in the target type of SIMD instruction is 1 and the number of source addresses is 2, then the second constraint condition limits the number of constrained destination addresses in the tensor calculation formula of the target operation type to 1, and the second constraint condition limits the number of constrained source addresses in the tensor calculation formula of the target operation type to 2. It should be understood that the examples here are only for the convenience of understanding this solution and are not used to limit this solution.

[0104] In another case, if the first parameter, second parameter, third parameter, and fourth parameter are obtained in step 301, step 302 may include: the SIMD instruction processing device generating one or more first indication information based on the first parameter value; generating one or more first constraints based on the first indication information and the second parameter information; and generating a second constraint based on the fourth parameter value. The specific implementation of the SIMD instruction processing device performing the aforementioned steps can be referred to the descriptions of the above three cases and will not be repeated here.

[0105] 303. The SIMD instruction processing device obtains a first parameter calculation rule.

[0106] In some embodiments of the present application, the SIMD instruction processing device may further generate one or more first parameter calculation rules corresponding to information of the first SIMD instruction model. The first parameter calculation rules are used by the SIMD instruction generation device to generate parameter values ​​of the first parameter, the address offset of the destination address, and the address offset of the source address in the SIMD instruction model according to the first parameter calculation rules. The number of first parameter calculation rules may be the same as the number of first constraints. The first parameter calculation rules are used to indicate the parameter value calculation rules of the first parameter, the address offset of the destination address, and the address offset of the source address under the premise of the corresponding relationship indicated by the first indication information. Optionally, the first parameter calculation rules are also used to indicate the value-taking rules of the number of whole blocks in the SIMD instruction under the premise of the corresponding relationship indicated by the first indication information. In the whole block and tail block technology, the problem of non-divisibility is solved by the tail block in the SIMD instruction. If non-divisibility exists, the number of tail blocks is 1. If non-divisibility does not exist, the number of tail blocks is 0. Therefore, there is no value-taking rule for the number of tail blocks.

[0107] Furthermore, in one case, if the target type SIMD instruction does not use the whole block and tail block technology, the number of whole blocks defaults to 1, and the number of tail blocks defaults to 0. Combining formula (1), formula (3) and Table 1 for example, let stride i,k =dstStride i,k , (i=0,1,…,I-1) and stride j+I,k =srcStride j,k ,(j=0,1,…,J-1), that is, [stride l,k ], (l=0,1,…,I+J-1) are used to represent all the offset (stride) parameters. and That is to say (l=0,1,…,I+J-1) is used to represent the coordinate linearization coefficients of all tensors and ensures the stride l,kand The variables l in are one-to-one correspondence. The following table shows the calculation rules for the first parameter.

[0108] Table 2

[0109]

[0110] Refer to Table 2 above. Since the meanings of all the letters in Table 2 have been introduced in formula (1), formula (3) and Table 1, they will not be repeated here. k A loop dimension x in the tensor computation used to represent the target operation type k , then the first parameter calculation rule can be expressed as the row where the value of N is 1 in Table 2 above. If K repeats k Represents K' cyclic dimensions, where K' is an integer greater than 1 and less than K, and K repeats k There are K′ cyclic dimensions The corresponding relationship mentioned above The sth kind in the correspondence relationship In the corresponding relationship, the first parameter calculation rule can be expressed as the value of N in Table 2 above, which is the row where K' is located. k The K loop dimensions x in the tensor computation used to represent the target operation type k , that is, each dimension of the SIMD instruction is repeated k Both are used to represent a loop dimension x in the tensor calculation formula of the target operation type k , then the first parameter calculation rule can be expressed as the row where the value of N in Table 2 is K. It should be understood that the example in Table 2 is only for the convenience of understanding the concept of the first parameter calculation rule and is not used to limit this solution.

[0111] In another case, the target type SIMD instruction uses the whole block and tail block technology, and the length of the first loop dimension and the value constraint of the first parameter corresponding to the first loop dimension determine that there is a non-divisible situation. It is necessary to solve the non-divisible problem by setting the tail block in the whole block and tail block technology. Among them, the first loop dimension is any dimension of the N loop dimensions of the tensor calculation formula. Regarding the meaning of the value range of the corresponding first parameter that the length of the first loop dimension is not divisible, one or more first parameters in the SIMD instruction are used to implement the calculation of a first loop dimension, and the one or more first parameters include the fifth parameter and the sixth parameter. The fifth parameter is sorted in the one or more first parameters before the fifth parameter in the one or more first parameters. Then, the value range of the corresponding first parameter that the length of the first loop dimension is not divisible refers to the value range of the fifth parameter that the length of the first loop dimension is not divisible, or the product of the values ​​of the fifth parameter and the sixth parameter that the length of the first loop dimension is not divisible. As an example, for example, the SIMD instruction of the target type is used to implement the operation of two loop dimensions (that is, the value of N is 2) of the tensor calculation formula, the first loop dimension is the first loop dimension of the two loop dimensions, the length of the first loop dimension is E0, and the first parameter corresponding to the first loop dimension includes repeat0, repeat1 and repeat2. According to the calculation rules of Table 2 above, it is known that repeat0 and repeat1 in repeat0, repeat1 and repeat2 need to be used to represent the first loop dimension of the tensor calculation formula. The length of the first loop dimension and the value constraint of the first parameter corresponding to the first loop dimension determine that the existence of non-divisibility means that the product of E2 and repeat0 and repeat1 is not divisible. As an example of solving the problem of non-divisibility by setting a tail block, combined with the above example, if the product of E2 and repeat0 and repeat1 is not divisible, it can be done through and Multiply and E2 is represented by addition, that is, the setting of the tail block in the whole block and tail block technology solves the problem of non-divisibility by addition. It should be understood that the above examples are only for the convenience of understanding this solution and are not used to limit this solution. Correspondingly, the first parameter calculation rule can also include the following Table 3 in addition to Table 2. Table 3 is used to adjust some parameter values ​​obtained by Table 2. The parameter calculation rule shown in Table 3 is used to generate the parameter values ​​of the whole block part and the parameter values ​​of the tail block part of the SIMD instruction. Please refer to the following Table 3. Table 3 combines the above formula (1), formula (3), formula (5), formula (6), Table 1 and Table 2 to give examples of the explanations of the meanings of various letters.

[0112] Table 3

[0113]

[0114] Since the meanings of the letters in Table 3 have been introduced in Formula (1), Formula (3), Formula (5), Formula (6), Table 1 and Table 2, they are not repeated here.

[0115] In another case, if the whole block and tail block techniques are used in the SIMD instructions of the target type, the third parameter sets an upper limit on the number of whole blocks in the SIMD instructions of the target type. When the length of the second loop dimension of the tensor calculation formula exceeds the upper limit of the product of the Nth whole block, the whole block and tail block technologies are simultaneously used to expand the upper limit of the value of the Nth whole block corresponding to the second loop dimension, and in the case of the non-divisibility problem between the length of the first loop dimension and the value constraint of the first parameter corresponding to the first loop dimension, the first parameter calculation rule can include the following Table 4 in addition to Table 2. Table 4 is used to adjust some parameter values ​​obtained by Table 2. The parameter calculation rule shown in Table 4 is used to generate the parameter values ​​of the whole block part and the parameter values ​​of the tail block part of the SIMD instruction. Please refer to the following Table 4. Table 4 combines the explanations of the meanings of various letters in the above formulas (1), (3), (5), (6), Table 1 and Table 2 to give examples.

[0116] Table 4

[0117]

[0118] Since the meanings of the letters in Table 4 have been introduced in Formula (1), Formula (3), Formula (5), Formula (6), Table 1 and Table 2, they are not repeated here.

[0119] 304. The SIMD instruction processing apparatus obtains a cost function corresponding to the first SIMD instruction model.

[0120] In some embodiments of the present application, the SIMD instruction processing device will obtain a cost function corresponding to the information of the first SIMD instruction model. The cost function is used to use the cost function to filter out the optimal SIMD instruction in the SIMD instruction conversion operation of the tensor calculation formula of the target operation type executed by the SIMD instruction generation device. Corresponding to the cost function can be one or more optimization objectives (i.e., the dependent variable of the cost function), the aforementioned optimization objectives include but are not limited to the minimum total number of SIMD instruction executions, the maximum total number of SIMD instruction executions, the minimum number of whole blocks and tail blocks in the SIMD instruction, the maximum number of whole blocks and tail blocks in the SIMD instruction, the maximum interval between the whole block and the tail block in the SIMD instruction, the minimum interval between the whole block and the tail block in the SIMD instruction, the minimum SIMD instruction scheduling delay, the maximum SIMD instruction scheduling delay, the minimum total execution time of the SIMD instruction, the maximum computational overhead of the address offset in the SIMD instruction, the maximum value of the first parameter of one or several dimensions among the K first parameters of the SIMD instruction, the minimum value of the first parameter of several dimensions among the K first parameters of the SIMD instruction, dstStride i,k The parameter value is the smallest when i takes a certain value or several values, dstStride i,k The parameter value is the largest when i takes a certain value or several values, srcStride j,k The parameter value is minimum and / or srcStride when j takes a certain value or several values j,k The parameter value is the maximum when the parameter j takes a certain value or several values. It should be understood that the above examples of optimization targets are for the purpose of facilitating the understanding of this solution. In actual situations, other types of optimization targets may exist. The specific optimization target can be determined in combination with factors such as the hardware performance of the chip. In the embodiments of this application, various scenarios of optimization targets are provided to expand the application scenarios of this solution.

[0121] The independent variables of the cost function include at least one of the following: the parameter value of the first parameter in the first SIMD instruction, the number of whole blocks in the first SIMD instruction, the number of tail blocks in the first SIMD instruction, the number of address offset calculations in the first SIMD instruction, the execution time of a SIMD instruction, the time of switching from the execution of a first SIMD instruction to the execution of another first SIMD instruction, and the time when the chip executes different repeat parameters in the SIMD instruction. Furthermore, the parameter value of the first parameter in the SIMD instruction can include the parameter value of the first parameter of the whole block part of the SIMD instruction and the parameter value of the first parameter of the tail block part of the SIMD instruction, and the number of whole blocks in the SIMD instruction can include the number of each type of whole blocks in the N types of whole blocks of the whole block part of the SIMD instruction. In the embodiment of the present application, a cost function is pre-generated to assist in selecting the optimal SIMD instruction in the SIMD instruction conversion stage of executing the tensor calculation formula of the target operation type. The cost function is generated based on the optimization target and can meet the user's SIMD instruction optimization requirements. The SIMD instruction cost function takes into account both the SIMD instruction parameters and the chip hardware parameters, so that the generated optimal SIMD instruction can better exert the performance of the chip.

[0122] Specifically, in one implementation, step 304 may include: the SIMD instruction processing device may receive a cost function corresponding to the information of the first SIMD instruction model input by a person skilled in the art. That is, after knowing the user's optimization goal, the person skilled in the art may manually generate a cost function corresponding to the information of the first SIMD instruction model, and then input it into the SIMD instruction processing device. Furthermore, a cost function input box may be provided on the display interface of the SIMD instruction processing device to receive the cost function input by the user through the input box; the SIMD instruction processing device may also receive a file including a cost function, which includes but is not limited to a text document, a table, and a coding file.

[0123] In another implementation, step 304 may include: the SIMD instruction processing apparatus may receive an optimization target input by a person skilled in the art, and generate a cost function corresponding to information of the first SIMD instruction model based on the optimization target and the SIMD instruction model of the target type. The specific implementation method of the SIMD instruction processing apparatus receiving the optimization target is similar to the specific implementation method of the SIMD instruction processing apparatus receiving the cost function, and is not further described here.

[0124] It should be noted that the execution order of step 303 and step 304 is not limited in the embodiment of the present application. Step 303 may be executed first and then step 304; or step 304 may be executed first and then step 303.

[0125] 305. The SIMD instruction processing device outputs information of the first SIMD instruction model.

[0126] In an embodiment of the present application, since the chip may include one or more types of SIMD instructions, the SIMD instruction processing device executes steps 301 to 304 once to generate information of a first SIMD instruction model corresponding to a type of SIMD instruction (that is, a set of SIMD instruction models), a first parameter calculation rule and a cost function. The SIMD instruction processing device executes steps 301 to 304 once for each of the one or more types of SIMD instructions of the chip, and then obtains information of one or more first SIMD instruction models corresponding to the one or more types of SIMD instructions, a first parameter calculation rule and a cost function, and then performs an output operation.

[0127] Specifically, steps 303 and 304 are optional steps. If steps 303 and 304 are performed, step 305 may include: the SIMD instruction processing device outputting first indication information, first constraint conditions, first parameter calculation rules, and a cost function. If only step 304 is performed without step 303, step 305 may include: the SIMD instruction processing device outputting first indication information, first constraint conditions, and a cost function. If only step 303 is performed without step 304, step 305 may include: the SIMD instruction processing device outputting first indication information, first constraint conditions, and a cost function.

[0128] More specifically, with respect to the output method of the information of the first SIMD instruction model, the first parameter calculation rule and / or the cost function, the SIMD instruction processing device may directly display the information of the first SIMD instruction model, the first parameter calculation rule and / or the cost function in a display interface, and then those skilled in the art may configure the information of the first SIMD instruction model, the first parameter calculation rule and / or the cost function in the SIMD instruction generation device. The SIMD instruction processing device may also package the information of the first SIMD instruction model, the first parameter calculation rule and / or the cost function into a file and output the file, and then those skilled in the art may configure the information of the first SIMD instruction model, the first parameter calculation rule and / or the cost function in the SIMD instruction generation device. The SIMD instruction processing device may also directly send the information of the first SIMD instruction model, the first parameter calculation rule and / or the cost function to the SIMD instruction generation device via a wireless network or a wired network, etc. The output method of the SIMD instruction processing device is not limited at this time.

[0129] In an embodiment of the present application, the information set of the SIMD instruction model generated corresponding to the chip is used to indicate the SIMD instruction conversion operation for executing the tensor calculation formula; in addition, a plurality of groups of first SIMD instruction model information are generated in advance, and during the conversion process, a matching combination method is first screened out from a number of combination methods based on the length of the N loop dimensions of the tensor calculation formula, which greatly reduces the difficulty of the SIMD instruction generation process and improves the efficiency of automatically generating SIMD instructions.

[0130] 2. Conversion stage of tensor calculation formula

[0131] In the embodiments of this application, please refer to Figure 5 , Figure 5 A flow chart of a method for generating a SIMD instruction provided in an embodiment of the present application is provided. The method for processing a single instruction multiple data SIMD instruction provided in an embodiment of the present application may include:

[0132] 501. A SIMD instruction generation device obtains the length of each loop dimension of a first tensor calculation formula.

[0133] In the embodiment of the present application, the SIMD instruction generation device can obtain the lengths of H loop dimensions of the first tensor calculation formula after obtaining the first tensor calculation formula during the conversion process of executing the tensor calculation formula to the SIMD instruction. The first tensor calculation formula includes a total of H loop dimensions. For the concepts of tensor calculation formula, loop dimension, and the length of loop dimension of tensor calculation formula, please refer to the above Figure 3 The description of step 201 in the corresponding embodiment will not be repeated here.

[0134] 502. The SIMD instruction generation device obtains the number of destination addresses in the first tensor calculation formula and the number of source addresses in the first tensor calculation formula.

[0135] In some embodiments of the present application, after obtaining the first tensor calculation formula, the SIMD instruction generation device can also obtain the number of destination addresses of the first tensor calculation formula and the number of source addresses in the first tensor calculation formula. For the concept of the number of destination addresses of the first tensor calculation formula and the concept of the number of source addresses in the first tensor calculation formula, please refer to the above Figure 3 The description of step 201 in the corresponding embodiment will not be repeated here.

[0136] 503. The SIMD instruction generation device obtains an operation type of the first tensor calculation formula.

[0137] In some embodiments of the present application, after obtaining the first tensor calculation formula, the SIMD instruction generation device can also obtain the operation type of the first tensor calculation formula of the first tensor calculation formula. For the concept of the operation type of the first tensor calculation formula of the first tensor calculation formula, please refer to the above Figure 3 The description of step 201 in the corresponding embodiment will not be repeated here.

[0138] It should be noted that the execution order of step 501, step 502 and step 503 is not limited in the embodiment of the present application. Steps 501, 502 and 503 can be executed simultaneously, or they can be arranged in any order.

[0139] 504. The SIMD instruction generation device obtains information of multiple groups of first SIMD instruction models.

[0140] In an embodiment of the present application, step 503 is an optional step. If step 503 is executed, step 504 may include: the SIMD instruction generation device obtains information of multiple groups of first SIMD instruction models from the information set of the SIMD instruction model. Specifically, the SIMD instruction generation device may be pre-configured with an information set of the SIMD instruction model, and the information set of the SIMD instruction model may include at least one information subset of the SIMD instruction model. Each information subset of the SIMD instruction model corresponds to a tensor calculation formula of an operation type, and different information subsets of SIMD instruction models correspond to tensor calculation formulas of different operation types. The information subset of the SIMD instruction model to which the information of at least one group of the first SIMD instruction model belongs corresponds to the operation type of the first tensor calculation formula. After obtaining the operation type of the first tensor calculation formula, the SIMD instruction generation device may obtain information of the first SIMD instruction model that matches the operation type of the first tensor calculation formula from the information set of the SIMD instruction model. Among them, the operation type of the first tensor calculation formula may be addition, multiplication or other operation types, etc. In an embodiment of the present application, the information of the first SIMD instruction model is generated for a tensor calculation formula of a certain specific operation type, that is, the information of the SIMD instruction model corresponding to the tensor calculation formula of different operation types is different, so that the information of the first SIMD instruction model is more consistent with the tensor calculation formula of the operation type of the first tensor calculation formula, and is conducive to improving the efficiency of the SIMD instruction generation process.

[0141] If step 503 is not performed, the embodiment of the present application does not limit the execution order of steps 501 and 502 and step 504. Steps 501 and 502 may be performed first, and then step 504; or step 504 may be performed first, and then steps 501 and 502. Step 504 may include: the SIMD instruction generation device obtains multiple sets of first SIMD instruction model information from the storage medium, and determines the information of all first SIMD instruction models in the multiple sets of first SIMD instruction model information as the first SIMD instruction model information.

[0142] 505. The SIMD instruction generation device determines whether the number of destination addresses in the first tensor calculation formula is the same as the number of destination addresses in the first SIMD instruction model, and whether the number of source addresses in the first tensor calculation formula is the same as the number of source addresses in the first SIMD instruction model. If not, proceed to step 506; if the same, proceed to step 507.

[0143] In some embodiments of the present application, the information of the first SIMD instruction model may further include a second constraint, where the second constraint is used to indicate the number of destination addresses in a tensor calculation formula that matches the information of the first SIMD instruction model and the number of source addresses in a tensor calculation formula that matches the information of the first SIMD instruction model. After the SIMD instruction generation apparatus obtains the number of destination addresses and the number of source addresses in the first tensor calculation formula in step 502 and obtains the second constraint from the information of the first SIMD instruction model, it may perform a determination operation.

[0144] 506. The SIMD instruction generation device outputs warning information.

[0145] In some embodiments of the present application, when the number of destination addresses in the first tensor calculation formula differs from the number of destination addresses in the first SIMD instruction model, or when the number of source addresses in the first tensor calculation formula differs from the number of source addresses in the first SIMD instruction model, the SIMD instruction generation device outputs an alarm message; the alarm message is used to inform the user that the SIMD instruction automatic conversion process has failed. Specifically, the alarm message can be output in the form of a text box, voice, or a flashing signal light, etc. The output method of the alarm message is not limited at this time.

[0146] 507. The SIMD instruction generation device selects information of a second SIMD instruction model from multiple groups of information of first SIMD instruction models.

[0147] In the embodiment of the present application, steps 502, 505, and 506 are all optional steps. If step 502 is not performed, steps 505 and 506 do not need to be performed, and step 507 can be performed directly after step 504 is performed. If step 502 is performed, steps 505 and 506 need to be performed, and step 507 may include: the SIMD instruction generation device selects information of a second SIMD instruction model that matches the first tensor calculation formula based on the lengths of H loop dimensions of the first tensor calculation formula, when the number of destination addresses in the first tensor calculation formula and the number of source addresses in the first tensor calculation formula meet the constraints of the second constraint condition. In an embodiment of the present application, during the execution of the SIMD instruction automatic conversion operation, it will first be determined whether the number of destination addresses and the number of source addresses in the first tensor calculation formula meet the requirements for the number of destination addresses and the number of source addresses in the SIMD instruction model. Only when the constraints are met will the subsequent SIMD instruction model matching operation be executed. If not, an alarm message will be output in a timely manner to improve the efficiency of the SIMD instruction automatic conversion process.

[0148] For details, see Figure 3 As described in step 202 in the corresponding embodiment, the information of the first SIMD instruction model includes information of multiple groups of first SIMD instruction models, and the information of each group of SIMD instruction models includes first indication information and first constraints. The first constraints are used to indicate the constraints on the lengths of N loop dimensions of the tensor calculation formula that matches the information of the first SIMD instruction model under the premise of the corresponding relationship indicated by the first indication information, where N is an integer greater than or equal to 1 and less than or equal to H. After obtaining the information of the first SIMD instruction model, the SIMD instruction generation device obtains multiple first constraints therefrom. For specific presentation forms, please refer to Table 1 above. After obtaining the lengths of the H loop dimensions, the lengths of the H loop dimensions are matched with the multiple first constraints, so that at least one first constraint matching the first tensor calculation formula can be obtained. As an example, for example, E0 is obtained from the lengths of the H loop dimensions, and it is determined whether E0 satisfies As another example, if the value of N is K′, then k is any integer from 0 to K′-1, and the lengths of H cyclic dimensions are distributed to obtain E0, E1, ... to E K′ , and then judge E0, E1... to E K′Whether the corresponding first constraint is satisfied will not be given in further examples. After selecting at least one first constraint matching the first tensor calculation formula from the information of the first SIMD instruction model based on the lengths of the H loop dimensions, at least one first indication information corresponding to the at least one matching first constraint is obtained, that is, information of a second SIMD instruction model matching the first tensor calculation formula is selected, and the information of the second SIMD instruction model includes information of at least one set of the first SIMD instruction model.

[0149] More specifically, in one implementation, at least one set of first SIMD instruction model information includes information about a third SIMD instruction model, information about a fourth SIMD instruction model, and information about a fifth SIMD instruction model. The value of N corresponding to the third SIMD instruction model information is less than the value of N corresponding to the fourth SIMD instruction model information. The value of N corresponding to the fourth SIMD instruction model information is less than the value of N corresponding to the fifth SIMD instruction model information. N corresponding to the fourth SIMD instruction model information is greater than or equal to 2. Step 507 may include: the SIMD instruction generation device selects information about the second SIMD instruction model from the information about the third SIMD instruction model; and if information about the second SIMD instruction model does not exist in the information about the fourth SIMD instruction model, terminating the selection of information about the second SIMD instruction model from the information about the fifth SIMD instruction model. Furthermore, the SIMD instruction generation device first performs an operation to select information about the second SIMD instruction model on the information about the third SIMD instruction model, and then performs an operation to select information about the second SIMD instruction model on the information about the fourth SIMD instruction model. In the embodiment of the present application, if there is no matching model in the low-dimensional model, there is no need to match the high-dimensional model, which can effectively reduce the number of matches and further improve the generation efficiency of SIMD instructions.

[0150] In another implementation, the SIMD instruction generation device may adopt a random matching method to match each first constraint condition in multiple first constraints according to the length of H loop dimensions to obtain at least one first constraint condition that matches the first tensor calculation formula.

[0151] 508. The SIMD instruction generation apparatus obtains a second SIMD instruction model corresponding to the information of the second SIMD instruction model.

[0152] In an embodiment of the present application, after obtaining information about a second SIMD instruction model, the SIMD instruction generation device obtains a second SIMD instruction model corresponding to the information about the second SIMD instruction model, because the information about the second SIMD instruction model includes information about at least one group of first SIMD instruction models, and each group of information about the first SIMD instruction model corresponds to a first SIMD instruction model. Specifically, in one implementation, the information about the first SIMD instruction model may not include the first SIMD instruction model, and the SIMD instruction generation device generates the second SIMD instruction model based on the instruction format of the SIMD instruction of the target type of the chip and at least one first indication information included in the information about the second SIMD instruction model. In another implementation, the information about each group of first SIMD instruction models also includes the first SIMD instruction model. After obtaining information about the second SIMD instruction model, the SIMD instruction generation device obtains at least one first SIMD instruction model from the information about at least one group of first SIMD instruction models included in the information about the second SIMD instruction model, and determines all obtained first SIMD instruction models as second SIMD instruction models.

[0153] 509. The SIMD instruction generation device generates parameter values ​​of a second SIMD instruction model.

[0154] In an embodiment of the present application, the SIMD instruction generation device can generate parameter values ​​for the second SIMD instruction model based on the lengths of the N loop dimensions of the first tensor calculation formula, the first indication information included in the information of the second SIMD instruction model, the first constraint condition included in the information of the second SIMD instruction model, and the coordinate linearization coefficient of the first tensor calculation formula. The parameter values ​​generated above include the parameter values ​​of the K first parameters, the parameter value of the destination address offset, and the parameter value of the source address offset. Optionally, the parameter values ​​generated above may also include the number of whole blocks and the number of tail blocks.

[0155] Specifically, the SIMD instruction generation device may be pre-configured with a first parameter calculation rule, so that after obtaining the lengths of the N loop dimensions of the first tensor calculation formula, the coordinate linearization coefficient of the first tensor calculation formula, and the second SIMD instruction model, the SIMD instruction generation device generates the model parameters of each SIMD instruction model included in the second SIMD instruction model according to the pre-configured first parameter calculation rule. The SIMD instruction generation device may also generate the first parameter calculation rule after obtaining the lengths of the N loop dimensions of the first tensor calculation formula, the coordinate linearization coefficient of the first tensor calculation formula, and the second SIMD instruction model, and then generate the model parameters of each SIMD instruction model included in the second SIMD instruction model according to the generated first parameter calculation rule.

[0156] More specifically, in one case, the target type SIMD instruction does not use the whole block and tail block technology, then the specific form of the first parameter calculation rule can refer to the above Figure 3 Corresponding to Table 2 in the embodiment, the SIMD instruction generation device brings the acquired lengths of the N loop dimensions of the first tensor calculation formula and the coordinate linearization coefficients of the first tensor calculation formula into the parameter calculation rules shown in the above Table 2, thereby respectively obtaining the model parameters of each SIMD instruction model included in the second SIMD instruction model.

[0157] In another case, the whole block and tail block technology is used in the SIMD instruction of the target type, and step 509 may include: the SIMD instruction generation device obtains the first parameter corresponding to the first loop dimension of the first tensor calculation formula according to the first indication information in the information of the second SIMD instruction model, wherein the first loop dimension is a loop dimension of at least one loop dimension, and the length of the first loop dimension is not divisible by the value range of the corresponding first parameter. The SIMD instruction generation device generates the parameter value of the whole block part of the first SIMD instruction and the parameter value of the tail block part of the first SIMD instruction based on the length of the first loop dimension. Since the length of the first loop dimension and the value constraint of the first parameter corresponding to the first loop dimension determine that there is a concept of non-divisibility, and the method of solving the non-divisibility by setting the tail block has been already described. Figure 3 In the embodiment of the present application, the technology of whole block and tail block is used to solve the problem of non-divisibility between the loop dimension and the first parameter, which expands the applicable situations of the solution and broadens the applicable scope of the solution.

[0158] Specifically, for the parameter value generation process of any SIMD instruction model in the second SIMD instruction model, the SIMD instruction generation device can first perform a model parameter generation operation for the SIMD instruction model using the parameter calculation rules shown in Table 2. During the generation process, it can be determined whether the length of the first loop dimension and the value constraint of the first parameter corresponding to the first loop dimension are not divisible. If not divisible, the SIMD instruction generation device then sets the SIMD tail block portion, adjusts some parameter values ​​of the whole block portion of the SIMD instruction using the parameter calculation rules shown in Table 3, and generates parameter values ​​for the tail block portion of the SIMD instruction.

[0159] In another case, the whole block and tail block technology is used in the SIMD instruction of the target type, and step 509 may include: the SIMD instruction generation device obtains the first parameter corresponding to the second loop dimension of the first tensor calculation formula according to the first indication information in the information of the second SIMD instruction model, wherein the second loop dimension is a loop dimension with the highest dimension in at least one loop dimension, and the length of the second loop dimension exceeds the upper limit of the value of the corresponding first parameter. The SIMD instruction generation device generates the parameter value of the whole block part of the first SIMD instruction based on the length of the second loop dimension. In the embodiment of the present application, the whole block and tail block technology is used to solve the problem that the length of the Nth loop dimension is greater than the upper limit of the value of the first parameter corresponding to the second loop dimension, further expanding the applicable circumstances of this solution and further expanding the applicable scope of this solution.

[0160] Specifically, for the parameter value generation process of any SIMD instruction model in the second SIMD instruction model, the SIMD instruction generation device can first perform a model parameter generation operation of the SIMD instruction model through the parameter calculation rules shown in Table 2. During the generation process, it can be determined whether the length of the Nth loop dimension is greater than the upper limit of the value of the first parameter corresponding to the second loop dimension. If it is determined that the value exceeds the upper limit, the parameter calculation rules shown in Table 4 are used to adjust the partial parameter values ​​of the entire block of the SIMD instruction.

[0161] In another case, the target type SIMD instruction uses the whole block and tail block technology, and step 509 may include: the SIMD instruction generation device obtains the value constraint of the first parameter corresponding to the first loop dimension of the first tensor calculation formula based on the first indication information included in the information of the second SIMD instruction model. If the length of the Nth loop dimension is greater than the upper limit of the value of the first parameter corresponding to the second loop dimension and it is determined based on the length of the first loop dimension and the value constraint of the first parameter corresponding to the first loop dimension that there is non-divisibility, generate the parameter value of the whole block portion of the target SIMD instruction and the parameter value of the tail block portion of the target SIMD instruction.

[0162] Specifically, for the parameter value generation process of any SIMD instruction model in the second SIMD instruction model, the SIMD instruction generation device can first perform a model parameter generation operation of the SIMD instruction model using the parameter calculation rules shown in Table 2. During the generation process, it can be determined whether the length of the Nth loop dimension is greater than the upper limit of the value of the first parameter corresponding to the second loop dimension, and whether the length of the first loop dimension and the value constraint of the first parameter corresponding to the first loop dimension are not divisible. If it is determined that the value exceeds the upper limit and is not divisible, the parameter values ​​of the entire block of the SIMD instruction are adjusted using the parameter calculation rules shown in Table 4, and the parameter values ​​of the tail block of the SIMD instruction are generated.

[0163] 510. The SIMD instruction generation device substitutes the parameter value into the second SIMD instruction model to obtain a first SIMD instruction.

[0164] In an embodiment of the present application, the SIMD instruction generation device substitutes the parameter values ​​into each second SIMD instruction model included in at least one second SIMD instruction model to obtain one or more first SIMD instructions, and the number of SIMD instructions in the first SIMD instruction is consistent with the number of second SIMD instruction models.

[0165] 511. A SIMD instruction generation apparatus obtains a cost function corresponding to a first SIMD instruction, and generates a function value of the cost function for each group of target SIMD instructions in the first SIMD instruction.

[0166] In an embodiment of the present application, a plurality of cost functions corresponding to various types of SIMD instructions of the chip may be pre-configured in the SIMD instruction generation device, and a cost function corresponding to the first SIMD instruction of the chip is obtained, that is, a cost function corresponding to the target type of SIMD instruction of the chip is obtained, wherein the cost function indicates an optimization target related to the first SIMD instruction. The SIMD instruction generation device generates a function value of the cost function for each first SIMD instruction in one or more first SIMD instructions based on the parameter value of the target SIMD instruction and the hardware performance parameters of the chip. Optionally, the function value of the cost function for each first SIMD instruction in multiple first SIMD instructions may be generated only when multiple first SIMD instructions are obtained through step 510. For a detailed introduction to the cost function, please refer to the above Figure 3 The step 204 in the corresponding embodiment will not be described in detail here.

[0167] 512. The SIMD instruction generation device selects a SIMD instruction that meets the optimization target from the first SIMD instructions, and uses it as the first SIMD instruction after the first tensor calculation formula is converted.

[0168] In an embodiment of the present application, after obtaining the function value of the cost function of each first SIMD instruction in one or more first SIMD instructions, the SIMD instruction generation device selects the SIMD instruction with the largest function value from the one or more first SIMD instructions and uses it as the first SIMD instruction after the first tensor calculation formula is converted, or selects the SIMD instruction with the smallest function value from the one or more first SIMD instructions and uses it as the first SIMD instruction after the first tensor calculation formula is converted. In an embodiment of the present application, using the cost function to select the optimal SIMD instruction is conducive to improving the performance of the SIMD instruction execution process.

[0169] In an embodiment of the present application, a specific implementation scheme for converting a first tensor calculation formula into a SIMD instruction is implemented; multiple groups of first SIMD instruction model information are generated in advance, and during the conversion process, a matching second SIMD instruction model is selected from the information of multiple groups of first SIMD instruction models based on the length of each loop dimension of the tensor calculation formula, thereby greatly improving the efficiency of the SIMD instruction generation process.

[0170] To further understand this program, please participate Figure 6 , Figure 6 A flowchart of a method for processing SIMD instructions provided in an embodiment of the present application is provided. Figure 6 In this example, the target chip is the V chip. The optimization goal proposed by the user is to minimize the total time it takes for the V chip to execute SIMD instructions. The number of whole blocks of SIMD instructions cannot exceed 5, and the number of tail blocks cannot exceed 1. The input tensor calculation formula is as follows:

[0171]

[0172] Subject to the above conditions, the SIMD instruction processing method provided in the embodiment of the present application may include:

[0173] 601. A SIMD instruction processing apparatus obtains a first parameter value, a second parameter value, a third parameter value, and a fourth parameter value of a target type of SIMD instruction in a V chip.

[0174] In this embodiment, referring to the above formula (7), it can be seen that the target type of SIMD instruction is used to implement a tensor calculation formula with an addition operation type. Those skilled in the art can refer to the ISA of the V chip and obtain that the target type of SIMD instruction device format for implementing a tensor calculation formula with an addition operation type in the V chip is:

[0175] V_SIMD_OP(dst0,src0,src1,repeat1,repeat2,dstStride 0,1 ,srcStride0,1 ,srcStride 1,1

[0176] ,dstStride 0,2 ,srcStride 0,2 ,srcStride 1,2 );(8)

[0177] Those skilled in the art will know that the first parameter value (ie K) is 3, the second parameter value includes R0, R1 and R2, R0 is 16, R1 is 8, R2 is 4, due to the hardware performance requirements of the V chip, repeat0 is fixed to 16, dstStride i,0 and srcStride j,0 The first parameter value, the second parameter value, the third parameter value, the fourth parameter value, and the repeat0 and dstStride values ​​are all fixed to 1. The upper limit of the number of whole blocks included in the third parameter value is 5. The number of destination addresses (i.e., I) included in the fourth parameter value is 1. The number of source addresses (i.e., J) included in the fourth parameter value is 2. After knowing the above information, those skilled in the art can use the display interface of the SIMD instruction device to display the first parameter value, the second parameter value, the third parameter value, the fourth parameter value, and repeat0 and dstStride values. i,0 and srcStride j,0 The value constraint is input into the SIMD instruction device, and correspondingly, the SIMD instruction device obtains the above information.

[0178] 602. The SIMD instruction processing apparatus generates information of a first SIMD instruction model.

[0179] In this embodiment, after the SIMD instruction device learns that there are three first parameters in the SIMD instruction device, it can generate information of a first SIMD instruction model. The information of the first SIMD instruction model includes information of four groups of first SIMD instruction models, and each group of SIMD instruction model information includes a first indication information and a first constraint condition.

[0180] Specifically, the four first indication information are: (1) if the target type of SIMD instruction is used to implement a loop dimension of a tensor calculation formula, the three first parameters together correspond to a loop dimension of the tensor calculation formula; (2) if the target type of SIMD instruction is used to implement two loop dimensions of a tensor calculation formula, the first two first parameters of the three first parameters may correspond to a loop dimension of the tensor calculation formula, and the last first parameter may correspond to a loop dimension of the tensor calculation formula; (3) if the target type of SIMD instruction is used to implement two loop dimensions of a tensor calculation formula, the first first parameter of the three first parameters may correspond to a loop dimension of the tensor calculation formula, and the last two first parameters may correspond to a loop dimension of the tensor calculation formula; (4) if the target type of SIMD instruction is used to implement three loop dimensions of a tensor calculation formula, the three first parameters respectively correspond to the three loop dimensions of the tensor calculation formula.

[0181] Correspondingly, the four first indication information correspond to four first constraint conditions respectively. Please refer to the following Table 5. The letters in Table 5 are combined with the above Figure 3 Corresponding to the description in the embodiment.

[0182] Table 5

[0183]

[0184] 603. The SIMD instruction processing device obtains a cost function corresponding to a target type of SIMD instruction in the V chip, and the optimization goal is to minimize the total time for the V chip to execute the SIMD instructions.

[0185] In this embodiment, after knowing that the optimization goal set by the user for the V chip is to minimize the total execution time of SIMD instructions, the technical personnel in this field determines the cost function of the target type of SIMD instructions of the V chip when the optimization goal is to minimize the total execution time of SIMD instructions based on the unified model of the cost function of the target type of SIMD instructions of the V chip, and inputs it into the SIMD instruction processing device. Correspondingly, the SIMD instruction processing device receives the cost function corresponding to the target type of SIMD instructions in the V chip input by the technical personnel.

[0186] Combined with the above Figure 3 Corresponding to the definitions of the meanings of various letters in the embodiment, the unified model of the cost function of the target type of SIMD instructions of the V chip can be:

[0187]

[0188] in, represent the number of represent the number of represent the number of represent The number of t represents the switching time consumed by the V chip hardware processing the whole block part of the SIMD instruction and the tail block part of the SIMD instruction, c v Indicates the time consumed by the V chip hardware to call a SIMD instruction. Indicates the time consumed by the V chip hardware to execute SIMD instructions with different repeat parameters.

[0189] Combined with the above Figure 3 Corresponding to the definitions of the meanings of various letters in the embodiment, when the optimization goal is to minimize the total execution time of SIMD instructions, the cost function of the target type of SIMD instructions of the V chip can be:

[0190]

[0191] Among them, H represents the number of dimensions of the tensor calculation formula, E l Represents the length of the lth cycle dimension in the tensor calculation formula. Since the meanings of other letters in formula (10) have been Figure 3 The corresponding embodiments and formula (9) have been explained and will not be repeated here.

[0192] 604. The SIMD generation device obtains the number of destination addresses, the number of source addresses, the lengths of H loop dimensions, and the linear coordinate coefficients of the tensor of the first tensor calculation formula.

[0193] In this embodiment, after obtaining the first tensor calculation formula, the SIMD generation device can analyze the first tensor calculation formula to obtain the following parameters:

[0194] E0=16,E1=4,E2=6,E3=4,E4=3,E5=2,(11)

[0195] Tensor C,

[0196] Tensor S0,

[0197] Tensor S1,

[0198] OP is addition, H = 6 (15)

[0199] The meaning of the above letters can be understood with the help of Figure 3 The description in the corresponding embodiment will not be repeated here.

[0200] 605. The SIMD generation device obtains a second SIMD instruction model that matches the first tensor calculation formula.

[0201] In this embodiment, the SIMD generation device determines whether E0 satisfies the first constraint condition corresponding to the first indication information (1) in Table 5. If the judgment result is satisfied, the SIMD instruction model corresponding to the first indication information (1) is determined as a SIMD instruction model in the second SIMD instruction model. The SIMD generation device determines whether E0 and E1 meet the first constraint condition corresponding to the first indication information (2) in Table 5. If the judgment result is satisfied, the SIMD instruction model corresponding to the first indication information (2) is determined as a SIMD instruction model in the second SIMD instruction model. The SIMD generation device determines whether E0 and E1 meet the first constraint condition corresponding to the first indication information (3) in Table 5. If the judgment result is satisfied, the SIMD instruction model corresponding to the first indication information (3) is determined as a SIMD instruction model in the second SIMD instruction model. The SIMD generation device determines whether E0, E1 and E2 meet the first constraint condition corresponding to the first indication information (4) in Table 5. If the judgment result is satisfied, the SIMD instruction model corresponding to the first indication information (4) is determined as a SIMD instruction model in the second SIMD instruction model. The SIMD generation device obtains four SIMD instruction models that match the first tensor calculation formula by executing the above operations.

[0202] 606. The SIMD generating device generates parameter values ​​of the second SIMD instruction model.

[0203] In this embodiment, the SIMD generation device may be pre-configured with parameter calculation rules. After obtaining the four SIMD instruction models included in the second SIMD instruction model, the lengths of the N loop dimensions of the calculation formula to be processed, and the linear coordinate coefficients in the first tensor calculation formula, the model parameters of the four SIMD instruction models included in the second SIMD instruction model are generated. Please refer to the following Table 6, which shows the parameter calculation rules for the first parameter and the address offset parameter. The meanings of the letters in Table 2 can be combined with the above Figure 3 Please understand the description in the corresponding embodiment and do not elaborate on it this time.

[0204] Table 6

[0205]

[0206] The SIMD generation device substitutes the obtained lengths of the N loop dimensions and the linear coordinate coefficients in the first tensor calculation formula into the above Table 6, and calculates the parameter values ​​of the first parameter and the address offset parameter as follows, please refer to Table 7.

[0207] Table 7

[0208]

[0209] In the process of generating parameter values ​​of the first parameter and the address offset parameter, the SIMD generation device discovered that: in the 3D SIMD instruction model, there is a problem of non-divisibility between the third loop dimension of the tensor calculation formula and the first parameter repeat2 corresponding to the second loop dimension of the first tensor calculation formula in the 3D SIMD instruction model. That is, repeat2=E2 cannot be achieved in the 3D SIMD instruction model. It is necessary to solve the non-divisibility problem by setting a tail block in the whole block and tail block technology. Then, the parameter values ​​of the whole block part of the 3D SIMD instruction model and the parameter values ​​of the tail block part of the SIMD instruction are generated as follows:

[0210]

[0211] 607. The SIMD generation device brings the parameter values ​​of the second SIMD instruction model into the second SIMD instruction model to obtain four first SIMD instructions.

[0212] 608. The SIMD generating device generates function values ​​of the cost functions of the four first SIMD instructions, and selects the SIMD instruction with the largest cost function value.

[0213] In this embodiment, the SIMD generation device can obtain the hardware performance parameters of the V chip, that is, c t 、c v and The value of can be automatically obtained by the SIMD generation device. After the SIMD generation device generates parameters of four SIMD instructions matching the first tensor calculation formula in step 606, the corresponding parameters are substituted into formula (10) to obtain the function values ​​of the cost functions of the four SIMD instructions included in the first SIMD instruction. For details, please refer to the following Table 8.

[0214] Table 8

[0215]

[0216] In this embodiment, after obtaining the function values ​​of the cost functions of the four SIMD instructions matching the first tensor calculation formula, the SIMD generation device selects the SIMD instruction with the largest cost function value and determines it as the optimal SIMD instruction matching the first tensor calculation formula.

[0217] In order to have a more intuitive understanding of the beneficial effects brought by the embodiments of the present application, the following is combined with Table 9 and the above Figure 6 The corresponding embodiment further introduces the beneficial effects brought by the embodiment of the present application. The beneficial effects of Table 9 are based on the obtained Figure 6 The first tensor calculation formula in the corresponding embodiment is matched with the target type SIMD instruction. Please refer to the following Table 9.

[0218] Table 9

[0219] Embodiments of the present application Brute force search Number of searches 4 ≥589824(1×16×16×48×48)

[0220] Combined with the above Figure 6 It can be seen from the corresponding embodiments that the method provided in the embodiments of the present application performs a total of 4 search operations in order to obtain the first tensor calculation formula. However, when the current brute force search method is used, it is necessary to enumerate all parameter value combinations starting from 0. In order to identify a feasible SIMD instruction parameter combination, when the value of N is 1, 589,824 search operations need to be performed. Obviously, compared with the current brute force search method, the SIMD instruction processing method provided in the embodiments of the present application greatly improves the efficiency of the SIMD instruction matching process.

[0221] exist Figures 1 to 6 On the basis of the corresponding embodiment, in order to better implement the above solution of the embodiment of the present application, the following also provides related equipment for implementing the above solution. Figure 7 , Figure 7 A structural diagram of a SIMD instruction generation device provided in an embodiment of the present application, the SIMD instruction generation device 700 includes: an acquisition module 701, a selection module 702 and a generation module 703. Among them, the acquisition module 701 is used to obtain the length of each loop dimension of the first tensor calculation formula; the acquisition module 701 is also used to obtain information of multiple groups of first single instruction multiple data SIMD instruction models, wherein the information of each group of first SIMD instruction models corresponds to at least one loop dimension of a tensor calculation formula, and the information of each group of first SIMD instruction models includes a first constraint condition, and the first constraint condition is used to indicate the constraint condition of the length of each loop dimension in at least one loop dimension; the selection module 702 is used to select information of a second SIMD instruction model from the information of the multiple groups of first SIMD instruction models based on the first constraint condition and the length of each loop dimension of the first tensor calculation formula, the information of the second instruction model matches the first tensor calculation formula, and the length of the loop dimension of the first tensor calculation formula satisfies the first constraint condition in the information of the second SIMD instruction model; the generation module 703 is used to generate a first SIMD instruction after the first tensor calculation formula is converted based on the length of at least one loop dimension of the first tensor calculation formula and the second SIMD instruction model.

[0222] In an embodiment of the present application, a specific implementation scheme for converting a first tensor calculation formula into a SIMD instruction is implemented; multiple groups of first SIMD instruction model information are generated in advance, and during the conversion process, a matching second SIMD instruction model is selected from the information of multiple groups of first SIMD instruction models based on the length of each loop dimension of the tensor calculation formula, thereby greatly improving the efficiency of the SIMD instruction generation process.

[0223] In one possible design, the information of each group of first SIMD instruction models also includes first indication information, where the first indication information is used to indicate the correspondence between K first parameters of a first SIMD instruction model and at least one loop dimension of a tensor calculation formula, where K is an integer greater than or equal to 1, and the first parameter indicates the number of times an operation is repeatedly performed on a data object in a tensor calculation formula.

[0224] In one possible design, at least one loop dimension includes N loop dimensions, and at least one group of information of the first SIMD instruction model includes information of multiple types of SIMD instruction models. The value of N corresponding to the information of different types of SIMD instruction models is different, and N is an integer greater than or equal to 1.

[0225] In an embodiment of the present application, information of at least one group of first SIMD instruction models is classified according to the number of loop dimensions corresponding to the information of the first SIMD instruction model, which facilitates subsequent separate management of information of different types of first SIMD instruction models and improves management accuracy.

[0226] In one possible design, the first constraint condition is related to the type of chip that executes the converted first SIMD instruction.

[0227] In an embodiment of the present application, the information set of the SIMD instruction model is generated based on a specific chip, and different chips will generate different SIMD instruction model information, which not only expands the application scenarios of this solution, but also improves the fit between the SIMD instruction model and the chip.

[0228] In one possible design, the generation module 703 is specifically used to: generate multiple first SIMD instructions based on the length of at least one loop dimension of the first tensor calculation formula and the second SIMD instruction model; select the SIMD instruction that meets the optimization goal from the multiple first SIMD instructions based on the cost function of each first SIMD instruction in the multiple first SIMD instructions, and use it as the first SIMD instruction after the first tensor calculation formula is converted, wherein the SIMD instruction that meets the optimization goal is the SIMD instruction with the maximum or minimum function value of the cost function, and the cost function indicates the optimization goal related to the first SIMD instruction.

[0229] In an embodiment of the present application, a cost function is pre-generated to assist in selecting the optimal SIMD instruction in the SIMD instruction conversion stage of executing the tensor calculation formula of the target operation type. The cost function is generated based on the optimization target and can meet the user's SIMD instruction optimization needs.

[0230] In one possible design, the optimization objectives indicated by the cost function include at least one of the following: minimum total number of SIMD instruction executions, maximum total number of SIMD instruction executions, minimum number of whole blocks and tail blocks in SIMD instructions, maximum number of whole blocks and tail blocks in SIMD instructions, maximum interval between whole blocks and tail blocks in SIMD instructions, minimum interval between whole blocks and tail blocks in SIMD instructions, minimum SIMD instruction scheduling delay, maximum SIMD instruction scheduling delay, minimum total execution time of SIMD instructions, maximum computational overhead of address offset in SIMD instructions, and minimum computational overhead of address offset in SIMD instructions.

[0231] In the embodiments of the present application, multiple scenarios of optimization objectives are provided, which expands the application scenarios of this solution.

[0232] In one possible design, the independent variables of the cost function include at least one of the following: a parameter value of a first parameter in a first SIMD instruction, the number of whole blocks in the first SIMD instruction, the number of tail blocks in the first SIMD instruction, the number of times an address offset is calculated in the first SIMD instruction, the duration of executing a SIMD instruction, and the duration of switching from a process of executing a first SIMD instruction to a process of executing another first SIMD instruction.

[0233] In the embodiment of the present application, the SIMD instruction cost function takes into account both SIMD instruction parameters and chip hardware parameters, so that the generated optimal SIMD instruction can better exert the performance of the chip.

[0234] In one possible design, the generation module 703 is specifically used to obtain the first parameter corresponding to the first loop dimension of the first tensor calculation formula according to the first indication information in the information of the second SIMD instruction model, wherein the first loop dimension is a loop dimension of at least one loop dimension, and the length of the first loop dimension does not divide the value range of the corresponding first parameter; based on the length of the first loop dimension, generate the parameter value of the whole block part of the first SIMD instruction and the parameter value of the tail block part of the first SIMD instruction.

[0235] In the embodiment of the present application, the whole block and tail block technology can solve the problem that the length of the first loop dimension is not divisible by the value range of the corresponding first parameter, expand the application scenario of this solution, and thus expand the scope of applicability of this solution.

[0236] In one possible design, the generation module 703 is specifically used to: obtain a first parameter corresponding to a second loop dimension of the first tensor calculation formula according to the first indication information in the information of the second SIMD instruction model, wherein the second loop dimension is a loop dimension with the highest dimension among at least one loop dimension, and the length of the second loop dimension exceeds the upper limit of the value of the corresponding first parameter; based on the length of the second loop dimension, generate a parameter value of the entire block of the first SIMD instruction.

[0237] In the embodiment of the present application, the whole block and tail block technology can be used to expand the value range of the length of the loop dimension in the constraint condition, thereby expanding the applicability of the present solution.

[0238] In one possible design, at least one set of first SIMD instruction model information includes information about a third SIMD instruction model, information about a fourth SIMD instruction model, and information about a fifth SIMD instruction model, the value of N corresponding to the information about the third SIMD instruction model is smaller than the value of N corresponding to the information about the fourth SIMD instruction model, the value of N corresponding to the information about the fourth SIMD instruction model is smaller than the value of N corresponding to the information about the fifth SIMD instruction model, and N corresponding to the information about the fourth SIMD instruction model is greater than or equal to 2. The selection module 702 is specifically configured to select information about the second SIMD instruction model from the information about the third SIMD instruction model; and terminate the selection of information about the second SIMD instruction model from the information about the fifth SIMD instruction model if information about the second SIMD instruction model does not exist in the information about the fourth SIMD instruction model.

[0239] In the embodiment of the present application, if there is no matching model in the low-dimensional model, there is no need to match the high-dimensional model, which can effectively reduce the number of matches and further improve the generation efficiency of SIMD instructions.

[0240] In one possible design, the acquisition module 701 is further configured to acquire a second constraint condition, where the second constraint condition is configured to indicate the number of destination addresses in the first SIMD instruction model and the number of source addresses in the first SIMD instruction model.

[0241] The acquisition module 701 is further configured to acquire the number of destination addresses in the first tensor calculation formula and the number of source addresses in the first tensor calculation formula;

[0242] The selection module 702 is specifically used to select at least one group of second SIMD instruction model information from at least one group of first SIMD instruction model information when the number of destination addresses in the first tensor calculation formula is the same as the number of destination addresses in the first SIMD instruction model, and the number of source addresses in the first tensor calculation formula is the same as the number of source addresses in the first SIMD instruction model.

[0243] In an embodiment of the present application, during the execution of the SIMD instruction automatic conversion operation, it will first be determined whether the number of destination addresses and the number of source addresses in the first tensor calculation formula meet the requirements for the number of destination addresses and the number of source addresses in the SIMD instruction model. Only when the constraints are met, the subsequent SIMD instruction model matching operation will be performed to improve the efficiency of the SIMD instruction automatic conversion process; in addition, if it is not met, an alarm message will be output in time to remind technical personnel to intervene in time.

[0244] In one possible design, the acquisition module 701 is specifically used to obtain information of at least one group of first SIMD instruction models from the information set of the SIMD instruction model, wherein the information set of the SIMD instruction model includes at least one information subset of the SIMD instruction model, each information subset of the SIMD instruction model corresponds to a tensor calculation formula of an operation type, and the information subset of the SIMD instruction model to which the information of at least one group of first SIMD instruction models belongs corresponds to the operation type of the first tensor calculation formula.

[0245] In an embodiment of the present application, the information of the first SIMD instruction model is generated for a tensor calculation formula of a certain specific operation type, that is, the information of the SIMD instruction model corresponding to the tensor calculation formula of different operation types is different, so that the information of the first SIMD instruction model is more consistent with the tensor calculation formula of the operation type of the first tensor calculation formula, and is conducive to improving the efficiency of the SIMD instruction generation process.

[0246] It should be noted that the information interaction, execution process, etc. between the modules / units in the SIMD instruction generation device 700 are the same as those in the present application. Figure 5 and Figure 6 The corresponding method embodiments are based on the same concept. For specific contents, please refer to the description in the method embodiments shown above in this application, which will not be repeated here.

[0247] The present application also provides a SIMD instruction processing device, see Figure 8 , Figure 8A structural diagram of a SIMD instruction processing device provided in an embodiment of the present application, the SIMD instruction processing device 800 includes: an acquisition module 801 and a generation module 802. The acquisition module 801 is used to acquire a first parameter value and a second parameter value corresponding to a first SIMD instruction model, wherein the first parameter value is K, indicating that the first SIMD instruction model includes K first parameters, K is an integer greater than or equal to 1, and the second parameter value indicates the value constraint of the K first parameters, and the first parameter reflects the number of times an operation is repeatedly performed on a data object in a tensor calculation formula matching the first SIMD instruction model; the generation module 802 is used to generate information of the first SIMD instruction model based on the first parameter value and the second parameter value, wherein the information of one first SIMD instruction model corresponds to one first SIMD instruction model, and the information of the first SIMD instruction model includes first indication information and a first constraint condition, the first indication information is used to indicate the correspondence between the K first parameters and at least one loop dimension of the tensor calculation formula matching the first SIMD instruction model, and the first constraint condition is used to indicate the constraint condition of the length of each loop dimension in the at least one loop dimension.

[0248] In one possible design, acquisition module 801 is further configured to acquire a third parameter value, where the third parameter value indicates a quantity constraint for the entire block in the first SIMD instruction model. Generation module 802 is specifically configured to: generate first indication information based on the first parameter value; and generate a first constraint condition based on the first indication information, the second parameter value, and the third parameter value.

[0249] In one possible design, the acquisition module 801 is also used to obtain a fourth parameter value, which is used to indicate the number of destination addresses of the first SIMD instruction model and the number of source addresses of the first SIMD instruction model; the generation module 802 is also used to generate a second constraint condition based on the fourth parameter value, and the second constraint condition is used to indicate the number of destination addresses and the number of source addresses in the tensor calculation formula that matches the first SIMD instruction model.

[0250] In one possible design, the acquisition module 801 is further used to obtain a cost function corresponding to the first SIMD instruction model, wherein the cost function is used to screen out SIMD instructions that meet the optimization goal, and the SIMD instructions that meet the optimization goal are SIMD instructions with the largest or smallest function value of the cost function, and the independent variables of the cost function include at least one of the following: the parameter value of the first parameter in the first SIMD instruction, the number of whole blocks in the first SIMD instruction, the number of tail blocks in the first SIMD instruction, the number of times the address offset in the first SIMD instruction is calculated, the duration of executing a SIMD instruction, and the duration of switching from the process of executing a first SIMD instruction to the process of executing another first SIMD instruction.

[0251] It should be noted that the information interaction and execution process between the modules / units in the SIMD instruction processing device 800 are the same as those in the present application. Figure 3 、 Figure 4 and Figure 6 The corresponding method embodiments are based on the same concept. The specific implementation methods and beneficial effects brought about can be found in the description of the method embodiments shown above in this application, and will not be repeated here.

[0252] Next, we will introduce an execution device provided by the embodiment of the present application. Figure 9 , Figure 9 This is a schematic diagram of the structure of the execution device provided in the embodiment of the present application. The execution device 900 can be specifically manifested as a desktop computer, mobile phone, tablet, laptop, smart wearable device or radar data processing device, etc., which is not limited here. Among them, the execution device 900 can be deployed with Figure 3 and Figure 4 The SIMD instruction processing device described in the corresponding embodiment is used to implement Figure 8 The function of the SIMD instruction processing device 800 in the corresponding embodiment. Alternatively, the execution device 900 may be deployed with Figure 5 The SIMD instruction generating device described in the corresponding embodiment is used to implement Figure 7 The function of the SIMD instruction generation device 700 in the corresponding embodiment. Specifically, the execution device 900 may have relatively large differences due to different configurations or performances, and may include one or more central processing units (CPUs) 922 (for example, one or more processors) and a memory 932, and one or more storage media 930 (for example, one or more mass storage devices) for storing application programs 942 or data 944. Among them, the memory 932 and the storage medium 930 can be temporary storage or permanent storage. The program stored in the storage medium 930 may include one or more modules (not shown in the figure), and each module may include a series of instruction operations in the execution device. Furthermore, the central processing unit 922 can be configured to communicate with the storage medium 930 to execute a series of instruction operations in the storage medium 930 on the execution device 900.

[0253] The execution device 900 may also include one or more power supplies 926, one or more wired or wireless network interfaces 950, one or more input and output interfaces 958, and / or one or more operating systems 941, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™, etc.

[0254] In one embodiment of the present application, the central processing unit 922 is used to implement Figure 7 The function of the SIMD instruction generation device 700 in the corresponding embodiment. Specifically, the central processing unit 922 is used to obtain the length of each loop dimension of the first tensor calculation formula; obtain information of multiple groups of first single-instruction multiple-data SIMD instruction models, wherein the information of each group of first SIMD instruction models corresponds to at least one loop dimension of a tensor calculation formula, and the information of each group of first SIMD instruction models includes a first constraint condition, and the first constraint condition is used to indicate the constraint condition of the length of each loop dimension in at least one loop dimension; according to the first constraint condition and the length of each loop dimension of the first tensor calculation formula, select information of a second SIMD instruction model from the information of the multiple groups of first SIMD instruction models, the information of the second instruction model matches the first tensor calculation formula, and the length of the loop dimension of the first tensor calculation formula satisfies the first constraint condition in the information of the second SIMD instruction model; according to the length of at least one loop dimension of the first tensor calculation formula and the second SIMD instruction model, generate a first SIMD instruction after the first tensor calculation formula is converted.

[0255] It should be noted that the CPU 922 can also be used to execute Figure 7 The specific manner in which the central processing unit 922 performs the above steps in the corresponding embodiment of the SIMD instruction generation device 700 is the same as that in the present application. Figure 5 The corresponding method embodiments are based on the same concept, and the technical effects they bring are the same as those in this application. Figure 5 The corresponding method embodiments are the same. For specific contents, please refer to the description in the method embodiments shown above in this application, which will not be repeated here.

[0256] In one embodiment of the present application, the central processing unit 922 is used to implement Figure 7The function of the SIMD instruction generation device 700 in the corresponding embodiment. Specifically, the central processing unit 922 is used to obtain a first parameter value and a second parameter value corresponding to the first SIMD instruction model, wherein the first parameter value is K, which is used to indicate that the first SIMD instruction model includes K first parameters, K is an integer greater than or equal to 1, and the second parameter value indicates the value constraint of the K first parameters, and the first parameter reflects the number of times an operation is repeatedly performed on a data object in a tensor calculation formula matching the first SIMD instruction model; based on the first parameter value and the second parameter value, generate information of the first SIMD instruction model, wherein the information of one first SIMD instruction model corresponds to one first SIMD instruction model, and the information of the first SIMD instruction model includes first indication information and a first constraint condition, the first indication information is used to indicate the correspondence between the K first parameters and at least one loop dimension of the tensor calculation formula matching the first SIMD instruction model, and the first constraint condition is used to indicate the constraint condition of the length of each loop dimension in the at least one loop dimension.

[0257] It should be noted that the CPU 922 can also be used to execute Figure 8 The specific manner in which the central processing unit 922 performs the above steps in the corresponding embodiment of the SIMD instruction processing device 800 is the same as that in the present application. Figure 3 and Figure 4 The corresponding method embodiments are based on the same concept, and the technical effects they bring are the same as those in this application. Figure 3 and Figure 4 The corresponding method embodiments are the same. For specific contents, please refer to the description in the method embodiments shown above in this application, which will not be repeated here.

[0258] The present application also provides a computer program product which, when executed on a computer, enables the computer to execute the aforementioned Figure 3 and Figure 4 The steps executed by the execution device in the method described in the embodiment shown, or the steps of making the computer execute the above Figure 5 The illustrated embodiments describe the steps performed by the device in the method.

[0259] The present application also provides a computer-readable storage medium in which a program for signal processing is stored. When the program is run on a computer, the computer executes the above-mentioned Figure 3 and Figure 4 The steps executed by the execution device in the method described in the embodiment shown, or the steps of making the computer execute the above Figure 5 The illustrated embodiments describe the steps performed by the device in the method.

[0260] The execution device, execution device, terminal device or communication device provided in the embodiment of the present application can be specifically a chip, which includes: a processing unit and a communication unit. The processing unit can be, for example, a processor, and the communication unit can be, for example, an input / output interface, a pin or a circuit. The processing unit can execute the computer execution instructions stored in the storage unit to enable the chip in the execution device to execute the above Figure 3 and Figure 4 The processing method of the SIMD instruction described in the embodiment shown, or, to enable the chip in the execution device to execute the above Figure 5 The embodiment shown describes a method for generating SIMD instructions. Optionally, the storage unit is a storage unit within the chip, such as a register, a cache, etc. The storage unit may also be a storage unit located outside the chip within the wireless access device, such as a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM), etc.

[0261] The processor mentioned in any of the above places can be a general-purpose central processing unit, a microprocessor, an ASIC, or one or more integrated circuits for controlling the execution of the program of the above-mentioned first aspect method.

[0262] It should also be noted that the device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed across multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment. In addition, in the drawings of the device embodiments provided in this application, the connection relationship between the modules indicates that there is a communication connection between them, which can be specifically implemented as one or more communication buses or signal lines.

[0263] Through the description of the above embodiments, it is clear to those skilled in the art that the present application can be implemented by means of software plus necessary general-purpose hardware, and of course it can also be implemented by means of dedicated hardware including application-specific integrated circuits, dedicated CPUs, dedicated memories, dedicated components, etc. In general, all functions performed by computer programs can be easily implemented with corresponding hardware, and the specific hardware structures used to implement the same function can also be various, such as analog circuits, digital circuits, or dedicated circuits, etc. However, for the present application, software program implementation is a better implementation method in most cases. Based on such an understanding, the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a readable storage medium, such as a computer's floppy disk, USB flash drive, mobile hard disk, ROM, RAM, magnetic disk, or optical disk, etc., and includes a number of instructions to enable a computer device (which can be a personal computer, an execution device, or a network device, etc.) to execute the methods described in each embodiment of the present application.

[0264] In the above embodiments, all or part of the embodiments may be implemented by software, hardware, firmware, or any combination thereof. When implemented by software, all or part of the embodiments may be implemented in the form of a computer program product.

[0265] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, a computer, an execution device or a data center by wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) mode to another website, computer, execution device or data center. The computer-readable storage medium can be any available medium that a computer can store or a data storage device such as an execution device, a data center that includes one or more available media integrations. The available medium can be a magnetic medium, (such as a floppy disk, a hard disk, a magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid-state drive (SSD)).

Claims

1. A computer program product, characterized in that The computer program product comprises a program, and when the program is run on a computer, the computer is caused to perform the following steps: Get the length of each loop dimension in at least one loop dimension of the first tensor calculation formula; Acquire information of multiple groups of first single instruction multiple data (SIMD) instruction models, wherein the information of each group of first SIMD instruction models corresponds to at least one loop dimension of a tensor calculation formula, and the information of each group of first SIMD instruction models includes a first constraint condition, and the first constraint condition is used to indicate a constraint condition of a length of each loop dimension in the at least one loop dimension; Selecting information of a second SIMD instruction model from the plurality of groups of information of first SIMD instruction models according to the first constraint condition and the length of each loop dimension in at least one loop dimension of the first tensor calculation formula, wherein the length of the loop dimension of the first tensor calculation formula satisfies the first constraint condition in the information of the second SIMD instruction model; Generate a first SIMD instruction after converting the first tensor calculation formula according to the length of at least one loop dimension of the first tensor calculation formula and the second SIMD instruction model.

2. The computer program product according to claim 1, characterized in that Each group of information of the first SIMD instruction model also includes first indication information, where the first indication information is used to indicate the correspondence between K first parameters of a first SIMD instruction model and at least one loop dimension of a tensor calculation formula, where K is an integer greater than or equal to 1, and the first parameter indicates the number of times an operation is repeatedly performed on a data object in a tensor calculation formula.

3. The computer program product according to claim 2, characterized in that The number of loop dimensions is N, and the information of the at least one group of first SIMD instruction models includes information of multiple types of SIMD instruction models. The value of N corresponding to the information of different types of SIMD instruction models is different, and N is an integer greater than 1.

4. The computer program product according to claim 2, characterized in that The first constraint condition is related to a type of chip that executes the converted first SIMD instruction.

5. The computer program product according to any one of claims 1 to 4, characterized in that When the computer executes the first SIMD instruction converted from the first tensor calculation formula according to the length of at least one loop dimension of the first tensor calculation formula and the second SIMD instruction model, the method specifically includes: Generate a plurality of first SIMD instructions according to the length of at least one loop dimension of the first tensor calculation formula and the second SIMD instruction model; According to the cost function of each first SIMD instruction among the multiple first SIMD instructions, a SIMD instruction that meets the optimization target is selected from the multiple first SIMD instructions and used as the first SIMD instruction after the first tensor calculation formula is converted, wherein the cost function indicates the optimization target related to the first SIMD instruction.

6. The computer program product according to claim 5, characterized in that The optimization objectives indicated by the cost function include at least one of the following: minimum total number of SIMD instruction executions, maximum total number of SIMD instruction executions, minimum number of whole blocks and tail blocks in SIMD instructions, maximum number of whole blocks and tail blocks in SIMD instructions, maximum interval between whole blocks and tail blocks in SIMD instructions, minimum interval between whole blocks and tail blocks in SIMD instructions, minimum SIMD instruction scheduling delay, maximum SIMD instruction scheduling delay, minimum total execution time of SIMD instructions, maximum calculation overhead of address offset in SIMD instructions, and minimum calculation overhead of address offset in SIMD instructions.

7. The computer program product according to claim 5, characterized in that The independent variables of the cost function include at least one of the following: the parameter value of the first parameter in the first SIMD instruction, the number of whole blocks in the first SIMD instruction, the number of tail blocks in the first SIMD instruction, the number of times the address offset is calculated in the first SIMD instruction, the duration of executing a SIMD instruction, and the duration of switching from the process of executing a first SIMD instruction to the process of executing another first SIMD instruction.

8. The computer program product according to claim 2, characterized in that When the computer executes the first SIMD instruction converted from the first tensor calculation formula according to the length of at least one loop dimension of the first tensor calculation formula and the second SIMD instruction model, the method specifically includes: Acquire, according to the first indication information in the information of the second SIMD instruction model, a first parameter corresponding to a first loop dimension of the first tensor calculation formula, wherein the first loop dimension is one loop dimension of the at least one loop dimension, and a length of the first loop dimension does not divide a value range of the corresponding first parameter; Based on the length of the first loop dimension, a parameter value of a full block portion of the first SIMD instruction and a parameter value of a tail block portion of the first SIMD instruction are generated.

9. The computer program product according to claim 2, characterized in that When the computer executes the first SIMD instruction converted from the first tensor calculation formula according to the length of at least one loop dimension of the first tensor calculation formula and the second SIMD instruction model, the method specifically includes: Acquire, according to the first indication information in the information of the second SIMD instruction model, a first parameter corresponding to a second loop dimension of the first tensor calculation formula, wherein the second loop dimension is a loop dimension with the highest dimension among the at least one loop dimension, and a length of the second loop dimension exceeds an upper limit of a value of the corresponding first parameter; Parameter values ​​for the entire block portion of the first SIMD instruction are generated based on the length of the second loop dimension.

10. The computer program product according to claim 3, characterized in that The information of the at least one group of first SIMD instruction models includes information of a third SIMD instruction model, information of a fourth SIMD instruction model, and information of a fifth SIMD instruction model, a value of N corresponding to the information of the third SIMD instruction model is less than a value of N corresponding to the information of the fourth SIMD instruction model, a value of N corresponding to the information of the fourth SIMD instruction model is less than a value of N corresponding to the information of the fifth SIMD instruction model, and N corresponding to the information of the fourth SIMD instruction model is greater than or equal to 2; When the computer executes the step of selecting at least one set of information of the second SIMD instruction model from the at least one set of information of the first SIMD instruction model, the step specifically includes: Selecting information of the second SIMD instruction model from information of the third SIMD instruction model; When the information of the second SIMD instruction model does not exist in the information of the fourth SIMD instruction model, the selection of the information of the second SIMD instruction model from the information of the fifth SIMD instruction model is abandoned.

11. The computer program product according to any one of claims 1 to 4, characterized in that The computer also performs the following steps: Obtaining a second constraint condition, where the second constraint condition is used to indicate the number of destination addresses in the first SIMD instruction model and the number of source addresses in the first SIMD instruction model; Obtaining the number of destination addresses in the first tensor calculation formula and the number of source addresses in the first tensor calculation formula; The computer executes the step of selecting at least one set of information of a second SIMD instruction model from the at least one set of information of a first SIMD instruction model, including: When the number of destination addresses in the first tensor calculation formula is the same as the number of destination addresses in the first SIMD instruction model, and the number of source addresses in the first tensor calculation formula is the same as the number of source addresses in the first SIMD instruction model, at least one group of second SIMD instruction model information is selected from the at least one group of first SIMD instruction model information.

12. The computer program product according to any one of claims 1 to 4, characterized in that When the computer executes obtaining information of at least one set of first SIMD instruction models, the method specifically includes: The information of the at least one group of first SIMD instruction models is obtained from the information set of SIMD instruction models, wherein the information set of the SIMD instruction models includes at least one information subset of the SIMD instruction models, each information subset of the SIMD instruction model corresponds to a tensor calculation formula of an operation type, and the information subset of the SIMD instruction model to which the information of the at least one group of first SIMD instruction models belongs corresponds to the operation type of the first tensor calculation formula.

13. A computer program product, characterized in that The computer program product comprises a program, and when the program is run on a computer, the computer is caused to perform the following steps: Obtaining a first parameter value and a second parameter value corresponding to a first SIMD instruction model, wherein the value of the first parameter value is K, which is used to indicate that the first SIMD instruction model includes K first parameters, and K is an integer greater than or equal to 1, and the second parameter value indicates a value constraint of the K first parameters, and the first parameter reflects the number of times an operation is repeatedly performed on a data object in a tensor calculation formula matching the first SIMD instruction model; According to the first parameter value and the second parameter value, information of a first SIMD instruction model is generated, wherein the information of one first SIMD instruction model corresponds to one first SIMD instruction model, and the information of the first SIMD instruction model includes first indication information and a first constraint condition, the first indication information is used to indicate the correspondence between the K first parameters and at least one loop dimension of a tensor calculation formula matching the first SIMD instruction model, and the first constraint condition is used to indicate a constraint condition on the length of each loop dimension in the at least one loop dimension.

14. The computer program product according to claim 13, characterized in that The computer also performs the following steps: Obtaining a third parameter value, wherein the third parameter value indicates a quantity constraint of an entire block in the first SIMD instruction model; When the computer executes the step of generating information of a first SIMD instruction model according to the first parameter value and the second parameter value, the step specifically includes: Generate the first indication information according to the first parameter value; The first constraint condition is generated according to the first indication information, the second parameter value and the third parameter value.

15. The computer program product according to claim 13 or 14, characterized in that The computer also performs the following steps: Obtaining a fourth parameter value, where the fourth parameter value is used to indicate the number of destination addresses of the first SIMD instruction model and the number of source addresses of the first SIMD instruction model; A second constraint condition is generated according to the fourth parameter value, where the second constraint condition is used to indicate the number of destination addresses and the number of source addresses in a tensor calculation formula that matches the first SIMD instruction model.

16. The computer program product according to claim 13 or 14, characterized in that The computer also performs the following steps: A cost function corresponding to the first SIMD instruction model is obtained, wherein the cost function is used to screen out SIMD instructions that meet the optimization goal, the SIMD instructions that meet the optimization goal are SIMD instructions with the largest or smallest function value of the cost function, and the independent variables of the cost function include at least one of the following: a parameter value of the first parameter in the first SIMD instruction, the number of whole blocks in the first SIMD instruction, the number of tail blocks in the first SIMD instruction, the number of calculation times of the address offset in the first SIMD instruction, the duration of executing a SIMD instruction, and the duration of switching from a process of executing a first SIMD instruction to a process of executing another first SIMD instruction.

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