Dma transmission system, method, device, storage medium and program product

Abstract

Embodiments of the present application provide a DMA transmission system, method, device, storage medium and program product. The method comprises: reading and analyzing DMA configuration information of a target task by a DMA processor, determining a transmission rule corresponding to the target task according to the information obtained after the analysis, if it is determined that the transmission rule corresponding to the target task is in a preset list, determining a single transmission strategy of the target task according to the information indicated by the transmission rule, otherwise, determining a multiple transmission strategy of the target task according to the information indicated by the transmission rule, and sending the obtained transmission strategy to a DMA execution unit by the DMA processor, so that the DMA execution unit reads data of the target task from a source address based on the transmission strategy and writes the data into a target address. The method is used to improve the data transmission efficiency, improve the reliability of data transmission and the expansibility of data transmission scenarios.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of big data, and in particular to a DMA transmission system, method, device, storage medium and program product. BACKGROUND

[0002] DMA (Direct Memory Access) is a computer system technology, and data is exchanged between an external device and a memory through DMA technology.

[0003] The prior art integrates the function corresponding to the DMA technology on a DMA hardware chip, and when a user needs to transmit data between an external device and a system memory, a system processor initiates a request to the DMA hardware chip, so that the DMA hardware chip writes each batch of preset data read from an indicated source address to a target address immediately, until the transmission of the data to be transmitted is completed.

[0004] However, as the demand for data transmission increases, the current DMA hardware chip is difficult to flexibly adapt to more reading functions, thereby affecting the performance of system data transmission. SUMMARY

[0005] The embodiments of the present application provide a DMA transmission system, method, device, storage medium and program product to improve data transmission efficiency, improve data transmission reliability and expand the data transmission scenario.

[0006] In a first aspect, the embodiments of the present application provide a DMA transmission system, comprising:

[0007] a DMA processor configured to read DMA configuration information of a target task, determine a transmission rule corresponding to the target task according to the DMA configuration information, determine a transmission strategy corresponding to the target task according to the transmission rule and send the transmission strategy to a DMA execution unit; the transmission strategy includes a single transmission strategy and a multiple transmission strategy, wherein if the transmission rule corresponding to the target task is in a preset list, the corresponding transmission strategy is the single transmission strategy, otherwise, the corresponding transmission strategy is the multiple transmission strategy, and the DMA configuration information is written by a system processor;

[0008] a DMA execution unit configured to receive the transmission strategy, read data of the target task from a corresponding source address based on the transmission strategy, and write the data to a corresponding target address.

[0009] Optionally, the DMA configuration information includes a data width and a data distribution characteristic of the source address corresponding to the target task, and a data width and a data distribution characteristic of the target address.

[0010] The single transmission strategy includes a single read strategy and a single write strategy.

[0011] The DMA execution unit is specifically used for:

[0012] reading all data from the source address based on a single reading strategy, the single reading strategy including a reading number and a reading amount per time; the reading amount per time being determined according to a data width of the source address, and the reading number being determined according to the reading amount per time;

[0013] writing all data to the target address based on a single writing strategy, the single writing strategy including a writing number and a writing amount per time; the writing amount per time being determined according to a data width of the target address, and the writing number being determined according to the writing amount per time.

[0014] Optionally, the DMA execution unit is further used for:

[0015] determining a target amount of data to be transmitted each time based on a multiple transmission strategy;

[0016] reading the target amount of data from the source address, and writing the target amount of data to the target address after obtaining the target amount of data read currently, until all data of the target task are written to the target address.

[0017] Optionally, the DMA processor is further used for:

[0018] when it is determined that the target task includes a plurality of subtasks with the same DMA configuration information, determining a transmission rule corresponding to the subtasks according to configuration information of any one of the subtasks;

[0019] when the transmission rule corresponding to the subtasks is in a preset transmission rule list, determining that a transmission strategy of the target task is a single transmission strategy, or otherwise, determining that the transmission strategy of the target task is a multiple transmission strategy.

[0020] Optionally, the DMA execution unit is further used for:

[0021] determining a corresponding reading error correction code according to the data before writing the read data to the target address each time, and performing a secondary reading on the data based on the target address after writing the data to the target address, and determining a corresponding writing error correction code according to the data read secondarily;

[0022] determining whether the writing error correction code and the reading error correction code are consistent; when it is determined that the writing error correction code and the reading error correction code are consistent, determining that the data transmission is successful, or otherwise, re-writing the data to the target address based on the corresponding transmission strategy;

[0023] when it is determined that all data of the target task are transmitted successfully, generating a transmission state of successful transmission and feeding back to a system processor.

[0024] In a second aspect, the embodiments of the present application provide a data transmission method applied to a DMA processor, comprising:

[0025] reading DMA configuration information of the target task, determining a transmission rule corresponding to the target task according to the DMA configuration information; the DMA configuration information is written by a system processor;

[0026] determining a transmission strategy corresponding to the target task according to the transmission rule and sending the transmission strategy to a DMA execution unit; so that the DMA execution unit reads data of the target task from a corresponding source address based on the transmission strategy, and writes the data into a corresponding target address; the transmission strategy comprises a single transmission strategy and a multiple transmission strategy, wherein if the transmission rule corresponding to the target task is in a preset list, the corresponding transmission strategy is the single transmission strategy, otherwise, the corresponding transmission strategy is the multiple transmission strategy.

[0027] Optionally, when it is determined that the target task comprises a plurality of subtasks with the same DMA configuration information, a transmission rule corresponding to the subtasks is determined according to configuration information of any one of the subtasks;

[0028] when the transmission rule corresponding to the subtasks is in a preset transmission rule list, it is determined that the transmission strategy of the target task is the single transmission strategy, otherwise, it is determined that the transmission strategy corresponding to the target task is the multiple transmission strategy.

[0029] In a third aspect, the embodiments of the present application provide a data transmission method applied to a DMA execution unit, comprising:

[0030] receiving a transmission strategy corresponding to a target task; the transmission strategy is determined by a DMA processor according to a transmission rule corresponding to the target task, the transmission rule is determined according to read DMA configuration information of the target task, the DMA configuration information is written into the DMA processor by a system processor; the transmission strategy comprises a single transmission strategy and a multiple transmission strategy, wherein if the transmission rule corresponding to the target task is in a preset list, the corresponding transmission strategy is the single transmission strategy, otherwise, the corresponding transmission strategy is the multiple transmission strategy;

[0031] reading data of the target task from a corresponding source address based on the transmission strategy, and writing the data into a corresponding target address.

[0032] Optionally, the DMA configuration information comprises data width and data distribution characteristics of the source address corresponding to the target task, and data width and data distribution characteristics of the target address;

[0033] The single transmission strategy comprises a single read strategy and a single write strategy;

[0034] The single reading strategy comprises a reading number and a reading quantity of each reading. The reading quantity of each reading is determined according to a data width of the source address, and the reading number is determined according to the reading quantity of each reading.

[0035] The single writing strategy comprises a writing number and a writing quantity of each writing. The writing quantity of each writing is determined according to a data width of the target address, and the writing number is determined according to the writing quantity of each writing.

[0036] Optionally, the target quantity of data transmitted each time is determined based on a multiple transmission strategy.

[0037] The target quantity of data is read from the source address. After the target quantity of data is obtained, the target quantity of data is written to the target address, until all the data of the target task is written to the target address.

[0038] Optionally, before the read data is written to the target address each time, a corresponding reading error correction code is determined according to the data. After the data is written to the target address, the data is read again based on the target address, and a corresponding writing error correction code is determined according to the data read again.

[0039] It is determined whether the writing error correction code and the reading error correction code are consistent. When it is determined that the writing error correction code and the reading error correction code are consistent, it is determined that the data transmission is successful, otherwise, the data is re-written to the target address based on the corresponding transmission strategy.

[0040] When it is determined that all the data of the target task is successfully transmitted, a transmission state of successful transmission is generated and fed back to the system processor.

[0041] In a fourth aspect, an embodiment of the present application provides a data transmission device applied to a DMA processor, comprising:

[0042] A determination module is configured to read DMA configuration information of a target task, and determine a transmission rule corresponding to the target task according to the DMA configuration information. The DMA configuration information is written by a system processor.

[0043] A first processing module is configured to determine a transmission strategy corresponding to the target task according to the transmission rule and send the transmission strategy to a DMA execution unit. The DMA execution unit reads data of the target task from a corresponding source address based on the transmission strategy, and writes the data to a corresponding target address. The transmission strategy comprises a single transmission strategy and a multiple transmission strategy. If the transmission rule corresponding to the target task is in a preset list, the corresponding transmission strategy is the single transmission strategy, otherwise, the corresponding transmission strategy is the multiple transmission strategy.

[0044] Optionally, the first processing module is further configured to determine the transmission rule corresponding to the subtask according to the configuration information of any one of the subtasks when it is determined that the target task comprises a plurality of subtasks with the same DMA configuration information.

[0045] When the transmission rule corresponding to the subtask is in the preset transmission rule list, the transmission strategy of the target task is determined as a single transmission strategy, otherwise, the transmission strategy corresponding to the target task is determined as a multiple transmission strategy.

[0046] In a fifth aspect, an embodiment of the present application provides a data transmission device applied to a DMA execution unit, comprising:

[0047] The receiving module is configured to receive a transmission strategy corresponding to a target task, wherein the transmission strategy is determined by a DMA processor according to a transmission rule corresponding to the target task, the transmission rule is determined according to DMA configuration information of the target task read, the DMA configuration information is written into the DMA processor by a system processor, and the transmission strategy comprises a single transmission strategy and a multiple transmission strategy, wherein if the transmission rule corresponding to the target task is in a preset list, the corresponding transmission strategy is the single transmission strategy, otherwise, the corresponding transmission strategy is the multiple transmission strategy.

[0048] The second processing module is configured to read data of the target task from a corresponding source address based on the transmission strategy, and write the data into a corresponding target address.

[0049] Optionally, the DMA configuration information comprises data width and data distribution characteristics of the source address corresponding to the target task, and data width and data distribution characteristics of the target address.

[0050] The single transmission strategy comprises a single read strategy and a single write strategy.

[0051] The second processing module is further configured to read all data from the source address based on the single read strategy, wherein the single read strategy comprises a read frequency and a read quantity each time; the read quantity each time is determined according to the data width of the source address, and the read frequency is determined according to the read quantity each time.

[0052] The second processing module is further configured to write all data into the target address based on the single write strategy, wherein the single write strategy comprises a write frequency and a write quantity each time; the write quantity each time is determined according to the data width of the target address, and the write frequency is determined according to the write quantity each time.

[0053] Optionally, the second processing module is further configured to determine a target quantity of data transmitted each time based on the multiple transmission strategy.

[0054] The second processing module is further configured to read the target quantity of data from the source address, write the target quantity of data into the target address after obtaining the target quantity of data read currently, and write all data of the target task into the target address.

[0055] Optionally, the second processing module is further configured to determine a corresponding read error correction code according to the data before writing the read data into the target address each time; and perform a second reading on the data based on the target address after writing the data into the target address, and determine a corresponding write error correction code according to the second read data;

[0056] determine whether the write error correction code and the read error correction code are consistent; when it is determined that the write error correction code and the read error correction code are consistent, it is determined that the data transmission is successful, otherwise, the data is re-written into the target address based on the corresponding transmission strategy;

[0057] when it is determined that all data transmission of the target task is successful, a transmission state of successful transmission is generated and fed back to the system processor.

[0058] In a sixth aspect, an embodiment of the present application provides an electronic device, comprising: a memory, a processor;

[0059] The memory stores computer execution instructions;

[0060] The processor executes the computer execution instructions stored in the memory, so that the processor executes various possible implementations of the second aspect and / or the third aspect.

[0061] In a seventh aspect, an embodiment of the present application provides a computer readable storage medium, the computer readable storage medium stores computer execution instructions, and the computer execution instructions are executed by the processor to implement various possible implementations of the second aspect and / or the third aspect.

[0062] In an eighth aspect, an embodiment of the present application provides a computer program product, comprising a computer program, which is executed by the processor to implement various possible implementations of the second aspect and / or the third aspect.

[0063] The DMA transmission system, method, device, storage medium and program product provided by the embodiments of the present application write the DMA configuration information of the target task into the DMA processor through the system processor, read and analyze the DMA configuration information through the DMA processor, determine the transmission rule corresponding to the target task according to the information obtained after the analysis, if the transmission rule corresponding to the target task is in the preset list, determine the single transmission strategy corresponding to the target task according to the information indicated by the transmission rule, otherwise, determine the multiple transmission strategy corresponding to the target task according to the information indicated by the transmission rule. The transmission strategy obtained is sent to the DMA execution unit through the DMA processor, so that the DMA execution unit reads the data of the target task from the corresponding source address based on the transmission strategy, and writes the data into the corresponding target address. The embodiments of the present application improve the data transmission efficiency, improve the reliability of data transmission and the expansibility of data transmission scene. BRIEF DESCRIPTION OF DRAWINGS

[0064] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments consistent with the present application and, together with the description, further serve to explain the principles of the application.

[0065] Figure 1 The application scenario of the prior art provided in the present application is shown in the figure;

[0066] Figure 2 The structure of the chip system provided in the present application is shown in the figure;

[0067] Figure 3 The structure of the DMA processor provided in the present application is shown in the figure;

[0068] Figure 4 The flow of the data transmission method provided in the present application is shown in the figure;

[0069] Figure 5 The structure of the data transmission device provided in the present application is shown in the figure Figure 1 ;

[0070] Figure 6 The structure of the data transmission device provided in the present application is shown in the figure Figure 2 ;

[0071] Figure 7 The structure of the electronic device provided in the present application is shown in the figure.

[0072] The specific embodiments of the present application have been shown in the above figures, and will be described in more detail hereinafter. These figures and the written description are not intended to limit the scope of the inventive concepts in any way, but are merely to illustrate the inventive concepts to those skilled in the art by reference to the particular embodiments. DETAILED DESCRIPTION

[0073] The exemplary embodiments will be described in detail herein with reference to the attached drawings. Unless otherwise noted, the same reference numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments are not meant to represent all implementations consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as detailed in the appended claims.

[0074] It should be noted that the user information (including but not limited to user equipment information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in the present application are all information and data authorized by the user or authorized by all parties, and the collection, use and processing of related data need to comply with relevant laws, regulations and standards in relevant regions, and provide corresponding operation portal for user to choose authorization or refusal.

[0075] First, let me explain the terms used in this application:

[0076] DMA (Direct Memory Access) is a computer system technology that enables efficient data transfer between external devices and the computer's motherboard memory without the intervention of the computer processor.

[0077] Figure 1 The application scenario diagrams of the prior art provided in this application are as follows: Figure 1 As shown, the application scenarios of existing technologies include chip systems, which consist of a system processor, memory, system bus, external devices, and DMA hardware. DMA hardware refers to hardware designed based on DMA technology. For a transfer task that transfers target data from an external device to memory, the system processor transmits the configuration information corresponding to the transfer task to the DMA hardware. This allows the DMA hardware to transfer the target data via the bus, while simultaneously freeing up system processor resources to handle other tasks. This improves both the data transfer efficiency and the overall system performance.

[0078] However, as system complexity continues to increase, the demand for data transmission based on DMA technology also increases. In order to adapt to the data transmission requirements, existing technologies have continuously improved and developed DMA hardware, resulting in increasingly complex DMA hardware structures. When transmission anomalies occur during data transmission, it is difficult to troubleshoot the faults. Furthermore, the development cycle of DMA hardware is long. Therefore, existing technologies are unable to meet the current system's high demand for data transmission and diverse application scenarios, reducing the stability and efficiency of data transmission and affecting the overall performance and scalability of the system.

[0079] The data transmission method provided in the application comprises the following steps: writing, by a system processor, DMA configuration information of a target task into a DMA processor; determining, by the DMA processor after reading the DMA configuration information, a transmission rule of the target task; if the transmission rule is determined to be in a preset list, determining that a transmission strategy corresponding to the target task is a single-time transmission strategy; otherwise, determining that the transmission strategy corresponding to the target task is a multiple-time transmission strategy. The transmission strategy corresponding to the DMA configuration information of the target task is obtained based on the transmission rule and is sent to a DMA execution unit, so that the DMA execution unit reads all data of the target task from a source address based on an indication of the single-time transmission strategy when it is determined that the transmission strategy is the single-time transmission strategy, and writes the all data into a target address after reading the all data; if it is determined that the transmission strategy is the multiple-time transmission strategy, the DMA execution unit reads a certain amount of data from the source address based on an indication of the multiple-time transmission strategy, and writes the certain amount of data into the target address after reading the certain amount of data, and then repeatedly executes the steps of data reading and data writing until the all data transmission is completed. The application adopts different transmission strategies for tasks with different transmission rules, adopts the multiple-time transmission strategy for a task with a transmission rule that is not a preset rule, and adopts the single-time transmission strategy for a task with a transmission rule that is a preset rule, thereby improving the transmission efficiency of tasks corresponding to each transmission rule, improving the expansibility and reliability of the DMA transmission system for data transmission, realizing the diversification of application scenarios, and further improving the overall performance of the DMA transmission system. The error correction code of the current transmission data is calculated before and after each data writing, and the transmission state of the target task is determined based on the error correction code corresponding to each transmission data, so as to improve the convenience of troubleshooting when the transmission fails while ensuring the transmission efficiency.

[0080] The technical solutions of the application and how the technical solutions solve the above technical problems will be described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes can not be described again in some embodiments. The embodiments of the application will be described below with reference to the accompanying drawings.

[0081] The DMA transmission system provided in the application can be applied to various chip systems, including but not limited to: embedded microcontrollers, embedded system on chips, computer CPU systems, etc.

[0082] Figure 2 The structure diagram of the chip system provided in the application is as follows: Figure 2As shown, the chip system includes a system processor, a memory, an external device module, a bus, and a DMA transmission system including a DMA processor and a DMA execution unit. The DMA processor is configured to read DMA configuration information of a target task, determine a transmission rule corresponding to the target task according to the DMA configuration information, determine a transmission strategy corresponding to the target task according to the transmission rule and send the transmission strategy to the DMA execution unit; the transmission strategy includes a single transmission strategy and a multiple transmission strategy, wherein if the transmission rule corresponding to the target task is in a preset list, the corresponding transmission strategy is the single transmission strategy, otherwise, the corresponding transmission strategy is the multiple transmission strategy, and the DMA configuration information is written by the system processor; the DMA execution unit is configured to receive the transmission strategy, read data of the target task from a corresponding source address based on the transmission strategy, and write the data into a corresponding target address.

[0083] For example, the external device module includes but is not limited to a storage device, a network interface, an image processing device, an audio device, etc., and the memory includes but is not limited to an SRAM, a DRAM, a Flash, etc., which is configured to store data and programs, and the system bus is a bus of the chip system, which exchanges data with the DMA transmission system through the system bus. The DMA execution unit is a high-speed data transmission device, which performs a plurality of data transmission tasks in the chip system based on the control of the DMA processor.

[0084] For example, the data transmission between the memory A and the memory B, the data transmission between the memory A and the external device A, and the data transmission between the external device A and the external device B.

[0085] Optionally, the DMA configuration information includes data width and data distribution characteristics of the source address corresponding to the target task, and data width and data distribution characteristics of the target address. The data distribution characteristics include continuous and discontinuous. The preset list includes n preset rules, and n is a positive integer.

[0086] Optionally, Figure 3 A structure diagram of the DMA processor provided in the present application is shown as follows, Figure 3 As shown, the DMA processor includes a processor core, an instruction memory, a data memory, an external device handshake module, and a configuration register, wherein the processor core is a high-performance and low-power RiscV processor core, and RiscV is an open standard instruction architecture.

[0087] In a possible embodiment, the system processor writes the DMA configuration information corresponding to the target task into the configuration register of the DMA processor through the bus, after the writing is completed, the RiscV processor core of the DMA processor reads the DMA configuration information in the configuration register and parses it to obtain the source address information, the target address information, the transmission data length and the transmission priority. After the external device prepares all the data to be transmitted, the transmission instruction is sent to the RiscV processor core through the external handshake module, so that the RiscV processor core determines the transmission rule corresponding to the target task based on the transmission instruction and the parsed DMA configuration information, and determines the transmission strategy corresponding to the target task according to the transmission rule, wherein when the transmission rule is in the preset list, the obtained transmission strategy is a single transmission strategy, otherwise, the obtained transmission strategy is a multiple transmission strategy. The RiscV processor core sends the transmission strategy to the DMA execution unit, so that the DMA execution unit reads the data of the source address through the system bus, and writes the read data to the target address through the system bus.

[0088] In a possible embodiment, based on the single transmission strategy, the source address, the data width of the source address, the data distribution characteristics of the source address, the target address, the data width of the target address, the data distribution characteristics of the target address and the transmission data length indicated by the DMA configuration information are determined to determine the reading times, the reading byte number and the reading mode before writing all the data, and the writing times, the writing byte number and the writing mode after reading all the data, to obtain the transmission strategy corresponding to the target task.

[0089] In a possible embodiment, based on the multiple transmission strategy, the source address, the data width of the source address, the data distribution characteristics of the source address, the target address, the data width of the target address, the data distribution characteristics of the target address and the transmission data length indicated by the DMA configuration information are determined to determine the reading times, the reading byte number and the reading mode before writing each time, and the writing times, the writing byte number and the writing mode after reading each time, to obtain the transmission strategy corresponding to the target task.

[0090] Optionally, the instruction memory is used to store the instructions executed during the running of the DMA processor. The implementation principle and technical effects of the instruction memory of the embodiment are similar to those of the prior art, and the embodiment will not be described here.

[0091] The embodiment of the application determines the transmission rule corresponding to each task through the DMA processor, determines the transmission strategy in the transmission scenario corresponding to the target task based on the transmission rule, and controls the DMA execution unit to complete data reading and data writing of the target task according to the obtained transmission strategy, thereby improving the data transmission efficiency and reliability of the DMA transmission system. The complexity of implementing the data transmission function in the chip system is reduced by using the above-mentioned DMA processor to control and manage data transmission, the convenience of configuring and upgrading the DMA transmission system is improved, the development cost of the DMA transmission system is reduced, the flexibility and expansibility of the DMA transmission system are improved, and the response timeliness and overall performance of the chip system are further improved.

[0092] Optionally, the single transmission strategy includes a single read strategy and a single write strategy; the DMA execution unit reads all data from the source address based on the single read strategy, the single read strategy including a read number and a read quantity each time; the read quantity each time is determined according to the data width of the source address, and the read number is determined according to the read quantity each time; all data is written to the target address based on the single write strategy, the single write strategy including a write number and a write quantity each time; the write quantity each time is determined according to the data width of the target address, and the write number is determined according to the write quantity each time.

[0093] Optionally, the DMA configuration information further includes a transmission data length.

[0094] In a possible embodiment, the RiscV processor core parses the DMA configuration information of the target task, and obtains that the data width of the source address is 32 bits (4 bytes), the data distribution characteristic of the source address is a discrete characteristic, the data width of the target address is 32 bits (4 bytes), the data distribution characteristic of the target address is a continuous characteristic, and the transmission data length is 128 bytes.

[0095] For the above-mentioned DMA configuration information, in the prior art, 4 bytes of data are read from the source address to the system bus (corresponding to 3 bus cycles) once, then 4 bytes of data are written to the target address from the system bus (corresponding to 3 bus cycles) once, the above-mentioned steps are repeated 32 times, until 128 bytes of data transmission is completed, and at the time of 128 bytes of transmission, a total of 192 bus cycles of the chip system are consumed.

[0096] In the embodiment of the present application, the RiscV processor core determines the transfer rule of the target task based on the above-mentioned DMA configuration information as: the data width of the source address and the target address matches, but the data distribution characteristics are different. At this time, if it is determined that the transfer rule is preset rule 2 in the preset list, the single transfer strategy corresponding to the target task is generated and transmitted to the DMA control unit. The DMA control unit reads 32 times 4-byte data (corresponding to 96 bus cycles) from the source address to the system bus according to the single read strategy in the single transfer strategy. Based on the transmission protocol of the system bus, the data read each time is sorted to obtain 128-byte sorted data. Based on the single write strategy in the single transfer strategy, the 128-byte sorted data is written to the target address 32 times 4-byte data (corresponding to 33 bus cycles). In the embodiment of the present application, 129 bus cycles are required to transfer the above-mentioned 128-byte data. As can be seen, the number of bus cycles spent in the embodiment of the present application is less than the number of bus cycles in the prior art.

[0097] In the embodiment of the present application, by determining that the transfer rule of the target task is in the preset list, the single transfer strategy corresponding to the target task is obtained, and the single transfer strategy is used to read all the data of the target task and then write all the data to the target address, thereby improving the transmission efficiency and transmission reliability of the task with the transfer rule in the preset list, achieving efficient transmission under multiple transfer rules, expanding the data transmission scene of the DMA transmission system, and improving the data transmission efficiency and reliability in different scenes.

[0098] Optionally, when the DMA processor determines that the target task includes multiple sub-tasks with the same DMA configuration information, the transfer rule corresponding to the sub-tasks is determined according to the configuration information of any one sub-task; when the transfer rule corresponding to the sub-tasks is in the preset transfer rule list, the transfer strategy of the target task is determined as a single transfer strategy, otherwise, the transfer strategy corresponding to the target task is determined as a multiple transfer strategy.

[0099] In a possible embodiment, when the target task includes 2 sub-tasks (such as task 1 and task 2), the RiscV processor core parses the DMA configuration information corresponding to the 2 sub-tasks of the target task to obtain that the data width of the source address of task 1 and task 2 is 32 bits (4 bytes), the data distribution characteristics of the source address of task 1 and task 2 are continuous characteristics, the data width of the target address of task 1 and task 2 is 32 bits (4 bytes), the data distribution characteristics of the target address of task 1 and task 2 are continuous characteristics, and the transfer data length of task 1 and task 2 is 128 bytes.

[0100] For the above DMA configuration information, in the prior art, 4 bytes of data are read from the source address of task 1 to the system bus (corresponding to 3 bus cycles) by DMA hardware, then 4 bytes of data are written to the target address of task 1 (corresponding to 3 bus cycles) by the system bus, the above steps are repeated 32 times until the 128 bytes of data transmission of task 1 is completed. After the 128 bytes of task 1 are transmitted, 4 bytes of data are read from the source address of task 2 to the system bus (corresponding to 3 bus cycles), then 4 bytes of data are written to the target address of task 2 (corresponding to 3 bus cycles) by the system bus, and the transmission of the above 4 bytes of data is determined to be completed after the writing is completed, and then the above steps are repeated 32 times until the 128 bytes of data transmission of task 2 is completed. The transmission of 256 bytes of data of task 1 and task 2 corresponds to a total of 384 bus cycles of the chip system.

[0101] In the embodiment of the present application, the RiscV processor core determines the transmission rule of the target task based on the above DMA configuration information: the data width of the source address and the target address of the two sub-tasks matches and the data distribution characteristics are the same, at this time, if it is determined that the transmission rule is preset rule 3 in the preset list, a single transmission strategy corresponding to the target task is generated and transmitted to the DMA control unit. According to the single read strategy in the single transmission strategy, 64 times of 4 bytes of data are continuously read from the source address of task 1 and the source address of task 2 to the system bus (corresponding to 65 bus cycles), and based on the transmission protocol of the system bus, the data read each time is sorted and 128 bytes of sorted data are obtained. Based on the single write strategy in the single transmission strategy, 32 times of 4 bytes of data are continuously written to the target address of task 1 (corresponding to 33 bus cycles), and 32 times of 4 bytes of data are continuously written to the target address of task 2 (corresponding to 33 bus cycles), so that the writing of all data of the target task corresponds to 66 bus cycles. In the embodiment of the present application, 131 bus cycles are required to transmit 256 bytes of data of the target task. In the embodiment of the present application, the number of bus cycles required to transmit all data of the target task is less than the number of bus cycles in the prior art.

[0102] In the embodiment of the present application, when the DMA configuration information of the target task includes the DMA configuration information of a plurality of same sub-tasks, the transmission rule of the sub-task is determined in the preset list, that is, the single transmission strategy corresponding to the target task is obtained, and after all data of the plurality of sub-tasks are read, all data are written to the target address corresponding to each sub-task based on the single transmission strategy, thereby improving the transmission efficiency and transmission reliability of the task whose transmission rules of the plurality of sub-tasks are in the preset list, realizing efficient transmission of multiple tasks, expanding the data transmission scene of the DMA transmission system, improving the expansibility of the data transmission system, and improving the data transmission efficiency and reliability in different scenes.

[0103] For example, each system bus request reading 1 byte of data corresponds to 3 bus cycles, non-continuous reading 4 bytes of data is based on 4 system bus requests reading 4 bytes of data, and continuous writing 32 bytes of data is based on 1 system bus request writing 32 bytes of data.

[0104] Optionally, the DMA execution unit determines a corresponding read error correction code according to the data before writing the read data to the target address each time; and after writing the data to the target address, the DMA execution unit performs secondary reading on the data based on the target address, determines a corresponding write error correction code according to the data read secondarily, determines whether the write error correction code is consistent with the read error correction code, determines that the data transmission is successful when the codes are consistent, otherwise, rewrites the data to the target address based on the corresponding transmission strategy, and generates a transmission state of successful transmission and feeds back to the system processor when all the data of the target task is successfully transmitted.

[0105] Optionally, the transmission strategy further includes a secondary reading strategy, and the DMA execution unit performs secondary reading based on the secondary reading strategy. The secondary reading strategy is generated by the DMA processor according to the data width of the target address, the data distribution characteristics of the target address and the transmission data length when the data verification function in the configuration register is enabled according to the parsed DMA configuration information.

[0106] Optionally, the DMA execution unit includes a data buffer.

[0107] In a possible embodiment, for the single transmission strategy, the DMA control unit reads 32 times 4 bytes of data from the source address non-continuously according to the single read strategy in the single transmission strategy, obtains 128 bytes of data, and then sends the 128 bytes of data to the data memory of the DMA processor (or the data buffer of the DMA execution unit) to process the 128 bytes of data through the data memory to obtain a read error correction code corresponding to the 128 bytes of data. After obtaining the read error correction code, the DMA control unit writes 32 times 4 bytes of data to the target address continuously according to the single write strategy in the single transmission strategy, and after the writing is completed, reads 32 times 4 bytes of data from the target address continuously based on the secondary read strategy in the single transmission strategy, obtains 128 bytes of data read secondarily, and sends the 128 bytes of data read secondarily to the data memory of the DMA processor (or the data buffer of the DMA execution unit) to process the 128 bytes of data read secondarily through the data memory to obtain a write error correction code corresponding to the 128 bytes of data read secondarily. The read error correction code and the write error correction code are compared, if the comparison is consistent, it is determined that the data transmission of the target task is successful, and a transmission state of successful transmission is generated, if the comparison is inconsistent, the 128 bytes of data read from the source address and stored in the data memory are written to the target address again according to the single write strategy.

[0108] For example, the read error correction code refers to an error correction code corresponding to the data read from the source address of the target task, and the write error correction code refers to an error correction code corresponding to the data read from the target address of the target task. The method of calculating the error correction code is similar to the implementation principle of calculating the error correction code in the prior art, and the embodiment of the present application does not elaborate.

[0109] In a possible embodiment, the DMA processor records the number of transmitted data in real time, and when it is determined that the number of transmitted data at the current time reaches the transmission data length corresponding to the target task, it is determined that the data transmission is completed, and a transmission completion notification is sent to the system processor. The system processor sends a state reading instruction to the DMA execution unit based on the transmission completion notification, so that the DMA execution unit feeds back the transmission state of the target task to the system processor when receiving the state reading instruction.

[0110] The embodiment of the present application verifies the consistency of the data before and after writing, so that when it is determined according to the verification result that the data before and after writing are inconsistent, the corresponding data is written again in time, and the accuracy and reliability of data transmission are improved.

[0111] Optionally, the DMA execution unit determines a target quantity of data for each transmission based on the multiple transmission strategy; reads the target quantity of data from the source address, and after obtaining the target quantity of data currently read, writes the target quantity of data to the target address until all data of the target task is written to the target address.

[0112] In a possible embodiment, the RiscV processor core parses the DMA configuration information of the target task to obtain that the data width of the source address is 32 bits (4 bytes), the data distribution feature of the source address is a continuous feature, the data width of the target address is 32 bits (4 bytes), the data distribution feature of the target address is a continuous feature, and the transmission data length is 128 bytes.

[0113] For the above DMA configuration information, the RiscV processor core determines, based on the above DMA configuration information, that the transmission rule of the target task is that the data width of the source address and the target address matches and the data distribution features are the same, at this time, it is determined that the transmission rule is not in the preset list, and generates a multiple transmission strategy corresponding to the target task and transmits it to the DMA control unit. The DMA control unit determines, according to the multiple transmission strategy, that the target quantity of data for each transmission is 4 bytes of data, reads 4 bytes of data from the source address to the system bus based on the target quantity indicated by the multiple transmission strategy, and sends the read 4 bytes of data to the data storage of the DMA processor (or the data buffer of the DMA execution unit) to process the 4 bytes of data through the data storage to obtain the read error correction code corresponding to the 4 bytes of data. After obtaining the read error correction code, the DMA control unit writes 4 bytes of data to the target address according to the multiple transmission strategy, and after writing is completed, reads 4 bytes of data from the target address according to the second read strategy in the multiple transmission strategy, obtains the second read 4 bytes of data and sends it to the data storage of the DMA processor (or the data buffer of the DMA execution unit) to process the second read 4 bytes of data through the data storage to obtain the write error correction code corresponding to the second read 4 bytes of data. Compare the read error correction code and the write error correction code, if they are inconsistent, then re-write the 4 bytes of data read from the source address to the target address according to the single write strategy.

[0114] In a possible embodiment, the DMA control unit re-writes the 4 bytes of data corresponding to the read error correction code to the target address, reads 4 bytes of data from the target address again according to the second read strategy in the multiple transmission strategy and calculates the corresponding write error correction code, if the write error correction code and the read error correction code are still inconsistent, it is determined that the transmission state of the 4 bytes of data is transmission failure.

[0115] In a possible embodiment, when the DMA control unit determines that the comparison is consistent, it is determined that the transmission state of the 4-byte data is transmission success, and after determining the transmission success, the next reading and writing steps are repeated until the above steps are repeated 32 times, a plurality of transmission states are obtained, and the transmission state of the target task is determined according to the plurality of transmission states. If each transmission state obtained is transmission success, a transmission state of transmission success of the target task is generated and fed back to the system processor, and if it is determined that at least one of each transmission state corresponding to the obtained data is a transmission failure state, a transmission state of transmission failure of the target task is generated, and the transmission state of transmission failure of the target task and the retransmission failure data of the target task are fed back to the system processor, so that the system processor performs fault diagnosis according to the transmission failure data information.

[0116] The embodiment of the present application performs consistency verification on the data written each time when performing data transmission based on the multiple transmission strategy, obtains the corresponding transmission state, and performs fault elimination according to the transmission state corresponding to the data written each time when the target task transmission fails, thereby improving the efficiency and accuracy of fault diagnosis and further improving the reliability of data transmission.

[0117] Optionally, the DMA transmission system provided by the embodiment of the present application is obtained based on a programmable DMA processor and a programmable DMA execution unit. The DMA processor in the DMA transmission system can realize various logical controls of the data transmission process and dynamic upgrade functions for different requirements, and the DMA execution unit is used to perform efficient data transmission actions according to the transmission strategy transmitted by the DMA processor.

[0118] In a possible embodiment, the DMA execution unit includes a high-speed data transmission interface and a flow control module, wherein the high-speed data transmission interface supports multiple data widths and transmission protocols, and is used for data transmission between addresses of different data widths, and the flow control module is used for data reading and data writing according to the transmission strategy. The DMA transmission system provided by the embodiment improves the reliability and stability of data transmission, improves the scalability of the chip system, and realizes diversified application scenarios of the DMA transmission system.

[0119] Figure 4 The flowchart of the data transmission method provided by the present application is shown in Figure 4 The data transmission method provided by the present application is described in detail on the basis of Figure 2 The embodiment, and the method includes:

[0120] S401, the system processor writes DMA configuration information to the DMA processor.

[0121] More specifically, the system processor writes the DMA configuration information corresponding to the target task to the DMA processor.

[0122] S402, the DMA processor parses the DMA configuration information to obtain a transmission rule.

[0123] More specifically, the DMA processor reads and parses the written DMA configuration information to obtain that the data width of the source address is 8 bits (1 byte), the data distribution characteristic of the source address is a continuous characteristic, the data width of the target address is 32 bits (4 bytes), the data distribution characteristic of the target address is a continuous characteristic, and the transmission data length is 128 bytes. Based on the above-mentioned DMA configuration information, it is determined that the transmission rule of the target task is that the data widths of the source address and the target address are not matched and are both continuous characteristics. The transmission rule corresponding to the target task is determined according to the information obtained after parsing.

[0124] S403, the DMA processor determines a transmission strategy of the target task based on the transmission rule.

[0125] More specifically, the DMA processor determines that the transmission rule of the target task is in the preset list, and if it is determined that the transmission rule is in the preset list, the single transmission strategy corresponding to the target task is generated according to the source address, the data width of the source address, the data distribution characteristic of the source address, the transmission data length, the target address, the data width of the target address, and the data distribution characteristic of the target address indicated by the transmission rule. The single transmission strategy includes a single write strategy, a single read strategy, and a double read strategy.

[0126] S404, the DMA processor sends the transmission strategy to the DMA execution unit.

[0127] More specifically, the DMA processor sends the single transmission strategy to the DMA execution unit.

[0128] S405, the DMA execution unit reads the data of the source address of the target task based on the transmission strategy.

[0129] More specifically, the DMA control unit reads 1-byte data from the source address of the target task 128 times (corresponding to 129 bus cycles) according to the single read strategy in the single transmission strategy, obtains 128 bytes of data to the system bus, sorts the data read each time based on the transmission protocol of the system bus to obtain sorted 128 bytes of data.

[0130] S406, the DMA execution unit determines a read error correction code corresponding to the read data.

[0131] More specifically, the DMA execution unit stores the sorted 128 bytes of data to the data buffer of the DMA execution unit, and calculates the read error correction code corresponding to the 128 bytes of data through the data buffer.

[0132] S407, the DMA execution unit writes data to the target address of the target task based on the transmission strategy.

[0133] More specifically, the DMA execution unit writes the sorted 128-byte data to the target address 32 times of 4-byte data (corresponding to 33 bus cycles) based on the single write strategy in the single transmission strategy.

[0134] S408, the DMA execution unit reads the data written to the target address twice and determines the corresponding write error correction code.

[0135] More specifically, after writing 128-byte data, the DMA execution unit reads 32 times of 4-byte data from the target address according to the second read strategy in the single read strategy, obtains the second read 128-byte data and stores it in the data buffer of the DMA execution unit. The write error correction code corresponding to the second read 128-byte data is calculated through the data buffer.

[0136] S409, the DMA execution unit determines the transmission status of the target task according to the read error correction code and the write error correction code when determining that the transmission of the target task is completed.

[0137] More specifically, when the DMA execution unit determines that the transmission of 128-byte data of the target task is completed, it determines whether the read error correction code and the write error correction code corresponding to the target task are consistent. When it is determined to be consistent, the transmission status of the successful transmission of the target task is generated.

[0138] S410, the DMA processor sends a transmission completion notification to the system processor.

[0139] More specifically, the DMA processor records the number of real-time transmission data, determines the transmission completion of the target task based on the transmission data length corresponding to the target task, generates a transmission completion notification and sends it to the system processor.

[0140] S411, the system processor sends a state reading instruction to the DMA execution unit.

[0141] More specifically, after receiving the transmission completion notification, the system processor sends a state reading instruction to the DMA execution unit.

[0142] S412, the DMA execution unit sends the transmission status to the system processor.

[0143] More specifically, after receiving the state reading instruction, the DMA execution unit sends the transmission status of the successful transmission of the target task to the system processor.

[0144] Optionally, for the DMA configuration information obtained in step S402, the prior art reads 4 bytes of data from the source address non-continuously to the system bus 4 times (corresponding to 12 bus cycles) through the DMA hardware, writes 4 bytes of data to the target address non-continuously once (corresponding to 3 bus cycles) through the system bus, repeats the above steps 32 times until 128 bytes of data transmission is completed, and when 128 bytes of data transmission is completed, a total of 480 bus cycles of the chip system are consumed. However, the DMA execution unit in the embodiment needs 162 bus cycles to transmit 128 bytes of data of the target task. Therefore, the number of bus cycles required by the embodiment is less than the number of bus cycles required by the prior art.

[0145] The data transmission method provided by the embodiment of the application determines the transmission rule corresponding to the target task through the DMA processor, determines the transmission strategy of the target task according to the transmission rule and sends the transmission strategy to the DMA transmission unit, so that the data transmission is performed based on the transmission strategy through the DMA transmission unit, the diversity of the data transmission application scenarios is improved, the data transmission efficiency in each scenario is improved, and the reliability and accuracy of the data transmission are improved.

[0146] Figure 5 The structure of the data transmission device provided by the application is shown in the figure Figure 1 As shown in the figure Figure 5 The data transmission device 50 provided by the embodiment applied to the DMA processor includes:

[0147] The determining module 501 is configured to read the DMA configuration information of the target task, and determine the transmission rule corresponding to the target task according to the DMA configuration information; the DMA configuration information is written by the system processor;

[0148] The first processing module 502 is configured to determine the transmission strategy corresponding to the target task according to the transmission rule and send the transmission strategy to the DMA execution unit; so that the DMA execution unit reads the data of the target task from the corresponding source address based on the transmission strategy, and writes the data to the corresponding target address; the transmission strategy includes a single transmission strategy and a multiple transmission strategy, wherein if the transmission rule corresponding to the target task is in the preset list, the corresponding transmission strategy is the single transmission strategy, otherwise, the corresponding transmission strategy is the multiple transmission strategy.

[0149] Optionally, the first processing module 502 is further configured to determine the transmission rule corresponding to the subtask according to the configuration information of any one subtask when it is determined that the target task includes a plurality of subtasks with the same DMA configuration information.

[0150] When the transmission rule corresponding to the subtask is in the preset transmission rule list, it is determined that the transmission strategy of the target task is the single transmission strategy, otherwise, it is determined that the transmission strategy corresponding to the target task is the multiple transmission strategy.

[0151] The data transmission apparatus provided by the embodiment is applied to a DMA processor, and can execute the method applied to the DMA processor provided by the method embodiment, and has similar implementation principles and technical effects, which will not be described here.

[0152] Figure 6 Structure diagram of the data transmission apparatus provided by the application Figure 2 As shown in Figure 6 The data transmission apparatus 60 provided by the embodiment applied to a DMA execution unit includes:

[0153] The receiving module 601 is configured to receive a transmission strategy corresponding to a target task, wherein the transmission strategy is determined by a DMA processor according to a transmission rule corresponding to the target task, the transmission rule is determined according to DMA configuration information of the target task read, and the DMA configuration information is written into the DMA processor by a system processor; the transmission strategy includes a single transmission strategy and a multiple transmission strategy, wherein if the transmission rule corresponding to the target task is in a preset list, the corresponding transmission strategy is the single transmission strategy, otherwise, the corresponding transmission strategy is the multiple transmission strategy.

[0154] The second processing module 602 is configured to read data of the target task from a corresponding source address based on the transmission strategy, and write the data into a corresponding target address.

[0155] Optionally, the DMA configuration information includes data width and data distribution characteristics of the source address corresponding to the target task, and data width and data distribution characteristics of the target address.

[0156] The single transmission strategy includes a single read strategy and a single write strategy.

[0157] The second processing module 602 is further configured to read all data from the source address based on the single read strategy, wherein the single read strategy includes a read frequency and a read quantity each time; the read quantity each time is determined according to the data width of the source address, and the read frequency is determined according to the read quantity each time.

[0158] Based on the single write strategy, all data is written into the target address, wherein the single write strategy includes a write frequency and a write quantity each time; the write quantity each time is determined according to the data width of the target address, and the write frequency is determined according to the write quantity each time.

[0159] Optionally, the second processing module 602 is further configured to determine a target quantity of data each time based on the multiple transmission strategy.

[0160] The target quantity of data is read from the source address, and after the target quantity of data read currently is obtained, the target quantity of data is written into the target address, until all data of the target task is written into the target address.

[0161] Optionally, the second processing module 602 is further configured to determine a corresponding read error correction code according to the data before writing the read data into the target address each time; and perform secondary reading on the data based on the target address after writing the data into the target address, and determine a corresponding write error correction code according to the data read secondarily;

[0162] determine whether the write error correction code and the read error correction code are consistent; when it is determined that the write error correction code and the read error correction code are consistent, it is determined that the data transmission is successful, otherwise, the data is written into the target address again based on the corresponding transmission strategy;

[0163] when it is determined that all the data transmission of the target task is successful, a transmission state of successful transmission is generated and fed back to the system processor.

[0164] The data transmission device provided in the embodiment is applied to a DMA execution unit, can execute the method applied to the DMA execution unit provided in the method embodiment, and has similar implementation principles and technical effects, which will not be described here in detail.

[0165] Figure 7 The structure schematic diagram of the electronic device provided in the present application is shown in FIG. 7. Figure 7 As shown in the figure, the electronic device 70 provided in the embodiment includes at least one processor 701 and a memory 702. Optionally, the device 70 further includes a communication component 703. The processor 701, the memory 702 and the communication component 703 are connected through a bus 704.

[0166] In the specific implementation process, the at least one processor 701 executes the computer execution instructions stored in the memory 702, so that the at least one processor 701 executes the method described above.

[0167] The specific implementation process of the processor 701 can be referred to the method embodiment described above, which has similar implementation principles and technical effects, and will not be described here in detail.

[0168] In the above embodiment, it should be understood that the processor can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC) and the like. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor and the like. The steps of the method disclosed in the present application can be directly embodied as execution completed by a hardware processor, or executed by a combination of hardware and software modules in the processor.

[0169] The memory can include a Random Access Memory (RAM) and can also include a Non-volatile Memory (NVM), such as at least one disk memory.

[0170] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For the convenience of representation, the bus in the drawings of the present application does not limit to only one bus or one type of bus.

[0171] The present application also provides a computer program product, comprising a computer program, which, when executed by a processor, implements the above method.

[0172] The present application also provides a computer readable storage medium, which stores computer execution instructions, and when a processor executes the computer execution instructions, the above method is implemented.

[0173] The above readable storage medium can be realized by any type of volatile or non-volatile storage device or their combination, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read-Only Memory (EPROM), Programmable Read-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk or optical disk. The readable storage medium can be any available medium that can be accessed by a general or special purpose computer.

[0174] An exemplary readable storage medium is coupled to the processor, so that the processor can read information from the readable storage medium and write information to the readable storage medium. Of course, the readable storage medium can also be an integral part of the processor. The processor and the readable storage medium can be located in an Application Specific Integrated Circuit (ASIC). Of course, the processor and the readable storage medium can also exist as discrete components in the device.

[0175] The division of units is only a logical function division, and actual implementation can have another division manner, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0176] The units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, that is, can be located in one place, or can be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment scheme.

[0177] In addition, the functional units in each embodiment of the present application can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit.

[0178] If the functions are realized in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application or the part of the present application that essentially contributes to the prior art or the part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various program code storage media.

[0179] Those skilled in the art can understand that all or part of the steps of the above-mentioned method embodiments can be completed by program instruction related hardware. The aforementioned program can be stored in a computer readable storage medium. The program executes the steps including the above-mentioned method embodiments when executed; and the aforementioned storage medium includes: ROM, RAM, magnetic disk or optical disk, and various program code storage media.

[0180] It should be understood that many of the materials and devices exemplified in this disclosure are articles of manufacture (i.e., articles of manufacture) according to this disclosure. The articles of manufacture can be manufactured as such or can be manufactured by combining the materials and devices exemplified in this disclosure. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. It should be understood that, in some embodiments, equivalents to the specific electrode structures and / or methods described herein can be employed without departing from the scope of the application. Accordingly, the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of "including," "comprising," "having," "containing," "involving," "characterized by," "characterized into," and variations thereof herein, is meant to encompass the items listed thereafter, and equivalents thereof as well as additional items. Although the foregoing application has been described in some detail by way of illustration and example, it is not to be limited thereby, but rather, only by the scope of the appended claims.

Claims

1. A DMA transfer system, characterized by, Comprise: A DMA processor for reading DMA configuration information of a target task, determining a transmission rule corresponding to the target task according to the DMA configuration information, determining a transmission strategy corresponding to the target task according to the transmission rule and sending to a DMA execution unit; the transmission strategy comprises a single transmission strategy and a multiple transmission strategy, wherein if the transmission rule corresponding to the target task is in a preset list, the corresponding transmission strategy is the single transmission strategy, otherwise, the corresponding transmission strategy is the multiple transmission strategy, and the DMA configuration information is written by a system processor; the single transmission strategy is used to instruct writing all data after reading all data, and the multiple transmission strategy is used to instruct writing a target number of data after reading the target number of data until all data of the target task is read and written; A DMA execution unit for receiving the transmission strategy, reading data of the target task from a corresponding source address based on the transmission strategy, and writing the data to a corresponding target address.

2. The system of claim 1, wherein, The DMA configuration information comprises data width and data distribution characteristics of the source address corresponding to the target task, and data width and data distribution characteristics of the target address; The single transmission strategy comprises a single read strategy and a single write strategy; When the DMA execution unit reads data of the target task from a corresponding source address based on the transmission strategy and writes the data to a corresponding target address, it is specifically used for: Based on the single read strategy, reading all data from the source address, the single read strategy comprising a reading frequency and a reading amount each time; the reading amount each time is determined according to the data width of the source address, and the reading frequency is determined according to the reading amount each time; Based on the single write strategy, writing all data to the target address, the single write strategy comprising a writing frequency and a writing amount each time; the writing amount each time is determined according to the data width of the target address, and the writing frequency is determined according to the writing amount each time.

3. The system of claim 2, wherein, The DMA execution unit is also used for: Based on the multiple transmission strategy, determining a target number of data transmitted each time; Reading the target number of data from the source address, and after obtaining the target number of data read currently, writing the target number of data to the target address until all data of the target task is written to the target address.

4. The system of claim 3, wherein, The DMA processor is also used for: When determining that the target task comprises a plurality of subtasks with the same DMA configuration information, determining a transmission rule corresponding to the subtasks according to the configuration information of any one subtask; When the transmission rule corresponding to the subtasks is in a preset transmission rule list, determining that the transmission strategy of the target task is the single transmission strategy, otherwise, determining that the transmission strategy corresponding to the target task is the multiple transmission strategy.

5. The system according to any one of claims 1-4, wherein The DMA execution unit is also used for: Before writing the read data into a target address each time, a corresponding read error correction code is determined according to the data; and after writing the data into the target address, a secondary reading of the data is performed based on the target address, and a corresponding write error correction code is determined according to the data read secondarily; It is determined whether the write error correction code and the read error correction code are consistent; When it is determined that they are consistent, it is determined that the data transmission is successful, otherwise, the data is re-written into the target address based on a corresponding transmission strategy; When it is determined that all data transmission of the target task is successful, a transmission state of successful transmission is generated and fed back to a system processor.

6. A data transmission method, characterized by, Applied to a DMA processor, comprising: Reading DMA configuration information of a target task, and determining a transmission rule corresponding to the target task according to the DMA configuration information; the DMA configuration information is written by a system processor; A transmission strategy corresponding to the target task is determined according to the transmission rule and sent to a DMA execution unit; so that the DMA execution unit reads data of the target task from a corresponding source address based on the transmission strategy, and writes the data into a corresponding target address; the transmission strategy includes a single transmission strategy and a multiple transmission strategy, wherein if the transmission rule corresponding to the target task is in a preset list, the corresponding transmission strategy is the single transmission strategy, otherwise, the corresponding transmission strategy is the multiple transmission strategy; the single transmission strategy is used to instruct writing all data after reading all data, and the multiple transmission strategy is used to instruct writing target amount of data after reading target amount of data, until all data of the target task are read and written.

7. A data transmission method, characterized by, Applied to a DMA execution unit, comprising: Receiving a transmission strategy corresponding to a target task; the transmission strategy is determined by a DMA processor according to a transmission rule corresponding to the target task, the transmission rule is determined according to read DMA configuration information of the target task, and the DMA configuration information is written by a system processor into the DMA processor; the transmission strategy includes a single transmission strategy and a multiple transmission strategy, wherein if the transmission rule corresponding to the target task is in a preset list, the corresponding transmission strategy is the single transmission strategy, otherwise, the corresponding transmission strategy is the multiple transmission strategy; the single transmission strategy is used to instruct writing all data after reading all data, and the multiple transmission strategy is used to instruct writing target amount of data after reading target amount of data, until all data of the target task are read and written. Reading data of the target task from a corresponding source address based on the transmission strategy, and writing the data into a corresponding target address.

8. An electronic device, comprising: Comprising: A memory and a processor; The memory stores computer execution instructions; The processor executes the computer execution instructions stored in the memory, so that the processor executes the method of claim 6 or 7.

9. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer execution instructions, and the computer execution instructions are executed by the processor to implement the method of claim 6 or 7.

10. A computer program product, characterised in that, A computer program comprising computer program elements which, when executed by a processor, carry out the method according to claim 6 or 7. A computer program comprising computer program elements which, when executed by a processor, carry out the method according to claim 6

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