Method for generating readable file, intelligent terminal and computer-readable storage medium

Abstract

The present application discloses a method for generating a readable file, an intelligent terminal, and a computer-readable storage medium, wherein the method for generating a readable file comprises: obtaining design processing parameters and design processing graphics of a circuit board; using different colors and / or adding different character labels to render the design interlayer vias and / or design interlayer slots with different design processing parameters in the design processing graphics to obtain annotated processing graphics; adding different character name numbers to different design processing parameters, and storing them in a preset two-dimensional array in rows; obtaining processing process monitoring parameters and customer acceptance parameters; adding processing process monitoring parameters and customer acceptance parameters to a preset two-dimensional array in rows corresponding to different design processing parameters to render a quality inspection parameter document; exporting the annotated processing graphics and quality inspection parameter documents as readable files. Through the above scheme, the method for generating a readable file in the present application can realize one-click automatic drawing, which is simple and easy to expand.

Description

Technical Field

[0001] The present application relates to the field of data management technology, and in particular to a method for generating a readable file, an intelligent terminal, and a computer-readable storage medium. Background Art

[0002] In daily life and industrial production, to intuitively display and analyze specific information, software programs are often used to process and integrate information to generate readable files, such as PDF (Portable Document Format) files, Word (word processing) files, or any other reasonably readable and writable files. In particular, in the field of package substrates, customers have acceptance requirements for the diameter of vias, width, and length of slots in circuit boards. For example, for a certain set of holes: 200 ± 50 μm (micrometers), for a certain set of slots: width * length = > 100 ± 50 μm * 2000 ± 50 μm. If the finished product exceeds the upper and lower limits, the product is scrapped.

[0003] To ensure that the finished PCBs meet the customer's dimensional acceptance requirements, on-site quality inspectors need to perform multiple three-dimensional measurements of the hole diameters, slot widths, and slot lengths in the PCB. However, on-site quality inspectors are usually unable to view the graphic data provided by the customer, nor can they compare the vias and slots on the actual board with the acceptance values. Therefore, the design staff is required to produce quality inspection drawings to distinguish and mark vias of different diameters and slots of different (slot widths * slot lengths) in the PCB with different colors to indicate process dimensional monitoring and customer dimensional acceptance. This allows on-site quality inspectors to conduct random inspections of each batch of holes and slots in the PCB according to the quality inspection drawings and determine whether the actual dimensions meet process dimensional monitoring and customer dimensional acceptance.

[0004] However, the existing method of producing quality inspection drawings usually involves manually adding process dimension monitoring and customer dimension acceptance of holes and slots to the design drawings. As a result, the production process is time-consuming and labor-intensive, and prone to errors and omissions. When there are too many slots with different (slot width * slot length) dimensions and similar colors, on-site quality inspections cannot effectively distinguish them. Summary of the Invention

[0005] The main technical problem solved by this application is to provide a method for generating a readable file, an intelligent terminal and a computer-readable storage medium, so as to solve the problem that the method for generating a readable file in the prior art requires manual processing, the production process is time-consuming and labor-intensive, and prone to errors and omissions.

[0006] In order to solve the above problems, the first aspect of the present application provides a method for generating a readable file, wherein the method for generating a readable file includes: obtaining the design processing parameters and design processing graphics of the circuit board; using different colors and / or adding different character labels to render the design inter-layer vias and / or design inter-layer grooves with different design processing parameters in the design processing graphics to obtain marked processing graphics; adding different character name numbers to different design processing parameters, and storing them in a preset two-dimensional array in rows; obtaining the processing process monitoring parameters and customer acceptance parameters of the circuit board; adding the processing process monitoring parameters and customer acceptance parameters to the preset two-dimensional array in rows corresponding to different design processing parameters, to render to obtain a quality inspection parameter document; exporting the marked processing graphics and quality inspection parameter documents as readable files.

[0007] Among them, the step of obtaining the design processing parameters and design processing graphics of the circuit board includes: obtaining the initial design processing parameters and initial design processing graphics of the circuit board; classifying the initial design processing parameters and initial design processing graphics according to the design interlayer distribution and design opening direction of the design interlayer vias and / or design interlayer grooves in the initial design processing graphics, so as to obtain at least two design processing parameters and their corresponding at least two design processing graphics.

[0008] Among them, the design processing parameters include interlayer via parameters and interlayer slot parameters, the colors include a first color and a second color, and in the design processing graphics, different colors are used for the design interlayer vias and / or design interlayer slots with different design processing parameters, and / or different character labels are added for rendering to obtain the marked processing graphics. The steps include: in the design processing graphics, different first colors are used for rendering the design interlayer vias with different interlayer via parameters; different second colors are used for the design interlayer slots with different interlayer slot parameters, and different character labels are added for rendering to obtain the marked processing graphics.

[0009] Among them, the character label includes a first character label and / or a second character label. In the step of using different colors and / or adding different character labels to render the design inter-layer vias and / or design inter-layer grooves with different design processing parameters in the design processing graphics to obtain the marked processing graphics, it also includes: obtaining the first midpoint coordinates of the design inter-layer vias in the design processing graphics; adding different first character labels at the first midpoint coordinates for rendering; and / or obtaining the second midpoint coordinates of the design inter-layer grooves in the design processing graphics; adding different second character labels at the second midpoint coordinates for rendering.

[0010] After the step of obtaining the design processing parameters and the design processing graphics of the circuit board, the method further includes: establishing different drilling tool table serial number indexes for different design processing parameters.

[0011] Among them, after the step of rendering the design inter-layer vias and / or design inter-layer grooves with different design processing parameters in the design processing graphics with different colors and / or adding different character labels to obtain the marked processing graphics, it also includes: establishing a first identification code index link at the design inter-layer vias and / or design inter-layer grooves in the marked processing graphics; wherein the first identification code includes the inter-layer number, name number and dimension marking number.

[0012] Among them, after the step of adding different character name numbers to different design and processing parameters and storing them in a preset two-dimensional array in rows, it also includes: establishing a second identification code index link at the character name number in the preset two-dimensional array; wherein the second identification code includes an inter-layer number, a name number, a dimension number and a coordinate number.

[0013] Among them, after the step of adding the processing monitoring parameters and customer acceptance parameters corresponding to different design processing parameter branches into a preset two-dimensional array to render a quality inspection parameter document, it also includes: detecting whether the difference between the processing monitoring parameters and the customer acceptance parameters corresponding to the same design processing parameters is within the set threshold; if the difference is not within the set threshold, an alarm indication is issued.

[0014] In order to solve the above problems, the second aspect of the present application provides an intelligent terminal, wherein the intelligent terminal includes a memory and a processor coupled to each other, the memory stores program data; the processor is used to execute the program data to implement the method for generating a readable file as described in any of the above items.

[0015] In order to solve the above problems, the third aspect of the present application provides a computer-readable storage medium on which program instructions are stored. When the program instructions are executed by a processor, any of the above methods for generating a readable file is implemented.

[0016] The beneficial effect of the present invention is that, different from the prior art, the method for generating a readable file provided by the present application obtains the design processing parameters and design processing graphics of the circuit board, and uses different colors and / or adds different character labels to render the design interlayer vias and / or design interlayer grooves with different design processing parameters in the design processing graphics to obtain the marked processing graphics, and adds different character name numbers to different design processing parameters, and stores them in a preset two-dimensional array in rows, thereby obtaining the processing process monitoring parameters and customer acceptance parameters of the circuit board, and adding the processing process monitoring parameters and customer acceptance parameters to the preset two-dimensional array in rows corresponding to different design processing parameters, rendering to obtain a quality inspection parameter document, and exporting the marked processing graphics and quality inspection parameter documents as readable files, so that one-click automatic drawing can be achieved by parsing and processing the data, without the need for manual operation by personnel, simple and easy to expand, greatly improving the efficiency of drawing readable files, and effectively achieving zero errors in drawing and zero changes in readable files; and it is convenient for on-site quality inspectors to distinguish between design interlayer vias and / or design interlayer grooves with different design processing parameters, thereby speeding up the delivery time of circuit board products. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a flowchart of a first embodiment of a method for generating a readable file according to the present application;

[0018] Figure 2 This is a structural diagram of an embodiment of the present application for marking and processing graphics;

[0019] Figure 3 yes Figure 1 S11 is a flow chart of an embodiment;

[0020] Figure 4 yes Figure 1 A schematic diagram of a flow chart of an embodiment of S12;

[0021] Figure 5 yes Figure 1 A schematic flow chart of a specific embodiment of S12;

[0022] Figure 6 This is a flow chart of a second embodiment of the method for generating a readable file of the present application;

[0023] Figure 7 This is a schematic diagram of a framework of an embodiment of the smart terminal of the present application;

[0024] Figure 8 It is a schematic diagram of a framework of an embodiment of the computer-readable storage medium of the present application. DETAILED DESCRIPTION

[0025] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0026] The terms "first", "second" and "third" in this application are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, a feature defined as "first", "second" and "third" may explicitly or implicitly include at least one of such features. In the description of this application, "multiple" means at least two, for example, two, three, etc., unless otherwise clearly and specifically defined. All directional indications in the embodiments of this application (such as up, down, left, right, front, back...) are only used to explain the relative positional relationship, movement, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products or devices.

[0027] Reference herein to an "embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it refer to independent or alternative embodiments that are mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0028] The present application is described in detail below with reference to the accompanying drawings and implementation methods.

[0029] See also Figure 1 , Figure 1 This is a flowchart of the first embodiment of the method for generating a readable file of the present application. Specifically, it may include the following steps:

[0030] S11: Obtaining design processing parameters and design processing graphics of the circuit board.

[0031] Among them, the method for generating a readable file in this embodiment can be specifically understood as a method in which the design software running on an intelligent terminal, such as a computer, server or smart phone, or any reasonable terminal device with program processing capabilities, uses the original design data of the circuit board and / or the graphic data delivered by the customer to generate a reference file for on-site quality inspectors to conduct quality inspection.

[0032] Specifically, the smart terminal can also be understood as a software platform that receives user uploads, or directly obtains the original design data of the circuit board and / or the graphic data delivered by the customer from the local database, so as to parse, classify and process the data to obtain the design and processing parameters and design and processing graphics.

[0033] It is worth noting that the design processing parameters refer to the theoretical processing parameters designed by the circuit board designer to realize the design circuit logic in any reasonable processing process such as drilling, grooving, etching, electroplating, etc. between the core boards in the circuit board, such as the theoretical design parameters such as the aperture of the design interlayer via, the length and width of the design interlayer groove, and the etching depth; the design processing graphics refer to the structural schematic diagram used to indicate one or more of the reasonable processing positions of the circuit board, or any one or more core boards in the circuit board.

[0034] In addition, the software platform can be understood as any reasonable application software program such as software for processing graphic data, or circuit board design software, and this application does not limit this.

[0035] S12: rendering the design inter-layer vias and / or the design inter-layer slots with different design processing parameters in the design processing graphics with different colors and / or adding different character labels to obtain a marked processing graphics.

[0036] Among them, such as Figure 2 As shown, Figure 2 This is a structural schematic diagram of an embodiment of the marked processing graphics of the present application. The marked processing graphics can be specifically understood as a structural schematic diagram for indicating the hole positions and slot positions obtained after specific marking of the design processing graphics of the circuit board 20, or any one or more core boards in the circuit board 20. The designed interlayer vias 21 in the circuit board 20 can specifically include a first via 211, a second via 212, and a third via 213. The designed interlayer slots 22 can include a first slot 221, a second slot 222, a third slot 223, and a fourth slot 224. The apertures of the first via 211, the second via 212, and the third via 213 are different. The length and width of the first slot 221, the second slot 222, the third slot 223, and the fourth slot 224 are different. In order to facilitate size comparison in subsequent quality inspections, they need to be distinguished.

[0037] Specifically, based on the design processing graphics, the software platform sequentially locates each design interlayer via 21 and / or each design interlayer slot 22 in the design processing graphics, so as to sequentially process each design interlayer via 21 and / or each design interlayer slot with different design processing parameters, such as Figure 2 The first via hole 211 , the second via hole 212 , the third via hole 213 , the first slot body 221 , the second slot body 222 , the third slot body 223 and the fourth slot body 224 are rendered in different colors to obtain a marked processing pattern.

[0038] It is worth noting that the number of the first vias 211 can be one or more, and when the number of the first vias 211 is multiple, the software platform specifically uses the same color to render each first via 211 in the design and processing graphics; similarly, when the number of the second vias 212, the third vias 213, the first slot 221, the second slot 222, the third slot 223 or the fourth slot 224 is multiple, the software platform can also use the same color to render each second via 212, the third via 213, the first slot 221, the second slot 222, the third slot 223 or the fourth slot 224 in the design and processing graphics; but the rendering colors of the first via 211, the second via 212, the third via 213, the first slot 221, the second slot 222, the third slot 223 and the fourth slot 224 are different, or different vias use different colors, different slots use different colors, but the vias and slots can share the same color.

[0039] In other embodiments, the circuit board 20 may further include any reasonable number of vias, such as 1, 2 or 5, and / or any reasonable number of slots, such as 1, 2 or 5, and this application does not limit this.

[0040] In another embodiment, the software platform can also specifically add different character labels to render the design inter-layer vias 21 and / or design inter-layer slots 22 with different design processing parameters, that is, the first via 211, the second via 212, the third via 213, the first slot 221, the second slot 222, the third slot 223 and the fourth slot 224 in the design processing graphics; or, while using different colors for rendering, add different character labels to render the first via 211, the second via 212, the third via 213, the first slot 221, the second slot 222, the third slot 223 and the fourth slot 224 to obtain a marked processing graphics, which is not limited in this application.

[0041] In a specific embodiment, the first via 211, the second via 212 and the third via 213 in the marked processing figure can be rendered in red, green and yellow, and / or by adding a, b and c respectively; and the first slot body 221, the second slot body 222, the third slot body 223 and the fourth slot body 224 can be rendered in orange, gray, white and blue, and / or by adding 1, 2, 3 and 4 respectively.

[0042] In other embodiments, the character labels corresponding to different design layer vias 21 and design layer slots 22 can be English letters or Arabic numerals, or one or more other reasonable different types of characters such as Roman numerals, Latin letters, Chinese characters, etc. This application does not limit this.

[0043] S13: Add different character name numbers to different design processing parameters, and store them in a preset two-dimensional array in rows.

[0044] Specifically, the software platform classifies the currently acquired design and processing parameters to correspond to different design and processing parameters, such as 100, 80, 90*250, 90*1100, etc., and adds different character name numbers, a first via (aperture), b second via (aperture), 1 first slot (width*length), 1 first slot (width*length), 3 third slot (width*length), etc., and stores them in rows in a preset two-dimensional array, that is, different design and processing parameters are added with different character name numbers and stored in different rows in the preset two-dimensional array to facilitate subsequent distinction and interpretation.

[0045] It is worth noting that an array (one-dimensional array) refers to a structure used to store multiple data of the same type. Two-dimensional array: An array containing two dimensions, which can be regarded as a table, in which each row is a one-dimensional array.

[0046] In other embodiments, the character name number may also include one or more of any reasonable different types of characters such as Chinese characters, English letters, Arabic numerals, Roman numerals, Latin letters, etc., and this application does not limit this.

[0047] S14: Obtaining the processing monitoring parameters and customer acceptance parameters of the circuit board.

[0048] Furthermore, the software platform obtains processing monitoring parameters and customer acceptance parameters stored locally, uploaded by users, or sent by circuit board manufacturing and testing equipment.

[0049] It's worth noting that these process monitoring parameters refer to the actual measurement parameters obtained by three-dimensionally measuring and monitoring a specific dimension of a circuit board during production, such as the diameter of a via and / or the length and width of a slot. Three-dimensional measurement, also known as 3D measurement or 3D scanning, is a technology used to measure the size and shape of objects.

[0050] In addition, the customer acceptance parameters refer to the various dimensional parameters required by the customer for the finished circuit board.

[0051] S15: Add the processing monitoring parameters and customer acceptance parameters corresponding to different design processing parameter branches into a preset two-dimensional array to render and obtain a quality inspection parameter document.

[0052] Furthermore, the currently acquired processing monitoring parameters and customer acceptance parameters are added to the preset two-dimensional array in corresponding rows corresponding to different design processing parameters, that is, the processing monitoring parameters and customer acceptance parameters are added to different rows of the preset two-dimensional array corresponding to different design processing parameters, and correspond to different character name numbers to render a quality inspection parameter document.

[0053] For ease of understanding, as shown in Table 1 below, the processing process monitoring parameters may specifically include etching window process monitoring parameters, laser drilling process monitoring parameters, and electroplating finished product parameters. Table 1 can be understood as a preset two-dimensional array. Among them, different character name numbers are added to correspond to different design processing parameters, such as 100, 60, 90*250, 90*1100, etc., that is, a first via (aperture), b second via (aperture), 1 first slot (width * length), 3 third slot (width * length), etc., and are stored in the preset two-dimensional array in rows. The etching window process monitoring parameters, that is, 95+ / -7, 75+ / -7, (85+ / -7)*(245+ / -30), (85+ / -7)*(1095+ / -30), etc., and the laser drilling process monitoring parameters, that is, 100+ / -7, 80+ / -7, (90*250)+ / -7, (90*1100)+ / -7, etc., electroplating finished product parameters, i.e. 100+ / -50, 80+ / -50, (90*250)+ / -50, (90*1100)+ / -50, etc., and customer acceptance parameters, i.e. 100+ / -50, 80+ / -50, (90*250)+ / -50, (90*1100)+ / -50, etc., are added to the preset two-dimensional array in corresponding rows corresponding to different design and processing parameters, and after adding the corresponding project names, the quality inspection parameter document is rendered.

[0054] Table 1

[0055]

[0056] In other embodiments, when the number of designed inter-layer vias and / or designed inter-layer slots in the circuit board is any other reasonable number, the preset two-dimensional array may specifically have 1 row, 3 rows, 10 rows, or any other reasonable number of rows, and each via and slot may specifically correspond to any other reasonable character name number; the processing process monitoring parameters may specifically include one or two of the etching window process monitoring parameters, the laser drilling process monitoring parameters, and the electroplating finished product parameters, or further include any other reasonable parameters actually measured and monitored during the processing process, such as the drilling and water washing process monitoring parameters, and the present application does not limit this.

[0057] It is worth noting that in Figure 2 When the annotated processing graphics specifically correspond to the graphics after the design processing graphics of any one or more core boards of the circuit board are specifically annotated, the number of the design processing graphics and their corresponding annotated processing graphics can also specifically correspond to multiple. For example, when the circuit board is specifically a 4-layer board, the design processing graphics and its corresponding annotated processing graphics can also include one or more of the interlayer design processing graphics and their corresponding interlayer annotated processing graphics between every two core boards, such as the first core board and the second core board d12 of the circuit board, the fourth core board and the third core board d43 of the circuit board, the second core board and the third core board d23 of the circuit board, etc., and this application does not limit this.

[0058] S16: Export the marked processing graphics and quality inspection parameter documents as readable files.

[0059] Specifically, the marked processing graphics and their corresponding quality inspection parameter documents are laid out and exported as readable files, such as PDF files, Word files, or any other reasonable readable and writable files, to be displayed to users for quality inspection and comparison. This application does not limit this.

[0060] The above solution realizes one-click automatic drawing by parsing and processing the data, which completely eliminates the need for manual operation. It is simple and easy to expand, greatly improving the efficiency of drawing readable files and effectively achieving zero errors in drawing and zero changes in readable files. It also makes it easy for on-site quality inspectors to distinguish between design layer vias and / or design layer slots with different design processing parameters, thereby speeding up the delivery time of circuit board products.

[0061] Furthermore, in one embodiment, after the above S11, the method further includes: establishing different drilling tool table serial number indexes for different design processing parameters.

[0062] Specifically, a mapping relationship between each design processing parameter and the drilling tool table serial number is established in the software platform, and a unique matching index is established in the software platform to facilitate subsequent retrieval of the corresponding drilling tool table serial number based on the design processing parameter.

[0063] When the diameter of the designed interlayer via hole is the same as the groove width of the designed interlayer groove body, they will correspond to the same drilling tool table number.

[0064] Furthermore, in one embodiment, after the above S12, the method further includes: establishing a first identification code index link at the designed inter-layer vias and / or the designed inter-layer grooves in the marked processing graphics.

[0065] The first identification code includes a layer number, a name number, and a dimension number.

[0066] It is understandable that when there are multiple inter-layer vias and inter-layer slots in the design processing pattern, in order to facilitate subsequent comparison and identification, an identification code needs to be established for each inter-layer via and each inter-layer slot.

[0067] To facilitate identification and differentiation, the software platform can encode each design layer via and slot based on the design processing parameters, design layer distribution, and design opening direction. For example, if a via with a diameter of 80, a via with a diameter of 90, and a via with a diameter of 100 between the first and second core boards of a circuit board, and a slot with a slot width and slot length of 100*2000, and a slot with a slot width and slot length of 100*2500, the first identification codes will be created: d12_hole_80, d12_hole_90, d12_hole_100, d12_slot_100*2000, and d12_slot_100*2500.

[0068] Among them, d12 is the inter-layer number, corresponding to the design inter-layer distribution and design opening direction; the hole and slot are the name numbers, indicating the via and slot respectively; 80, 90, 100, 100*2000, and 100*2500 are the dimension marking numbers.

[0069] Furthermore, in other embodiments, the first identification code may specifically include a unique character identification number to facilitate subsequent identification of the designed inter-layer vias and / or designed inter-layer slots having the same design processing parameters.

[0070] It is understandable that the marked processing graphics can also be specifically displayed on the display interface of the software platform, so that when an index link with a first identification code is established at the design inter-layer vias and / or design inter-layer slots in the marked processing graphics, the user can display the first identification code by clicking on the index link to identify the design processing parameters, design inter-layer distribution and other information of each design inter-layer via and / or design inter-layer slot.

[0071] Furthermore, in one embodiment, after the above S13, the method further includes: establishing a second identification code index link at the character name number in the preset two-dimensional array.

[0072] The second identification code includes a layer number, a name number, a dimension number, and a coordinate number.

[0073] Similarly, the preset two-dimensional array can also be displayed on the display interface of the software platform, so that an index link of a second identification code can be established at each character name number in the preset two-dimensional array, so that the user can display the second identification code by clicking on the index link to identify the design processing parameters of the vias between design layers and / or the slots between design layers, the distribution between design layers and other information.

[0074] It is worth noting that the coordinate number can specifically be the midpoint coordinates of each design layer via and / or design layer slot in the marked processing graphics, and can be understood as a unique character identification number; and when multiple design layer vias or design layer slots have the same design processing parameters, the character name number corresponding to the design processing parameters will correspond to multiple second identification codes, that is, when clicking the index link at the character name number, multiple second identification codes will pop up.

[0075] In other embodiments, the index link of the second identification code can also be specifically established at each design and processing parameter in the preset two-dimensional array, or at the customer acceptance parameter, which is not limited in this application.

[0076] Furthermore, in one embodiment, after the above S15, the process further includes: displaying the design and processing graphics and the quality inspection parameter document on a display interface of the software platform.

[0077] Furthermore, in one embodiment, after the above S16, it specifically includes: a pop-up window is displayed to ask the user whether to open or print the readable file, and after the user clicks OK, the readable file is automatically opened or printed for the user to check whether the readable file is generated correctly.

[0078] See also Figure 3 , Figure 3 yes Figure 1In one embodiment, the method for generating a readable file of the present application includes, in addition to the above steps S11-S16, further more specific steps. Specifically, the above step S11 may further include the following steps:

[0079] S111: Acquire initial design processing parameters and initial design processing graphics of the circuit board.

[0080] Specifically, the software platform receives information uploaded by users or directly obtains the initial design and processing parameters and initial design and processing graphics of the circuit board from a local database.

[0081] The initial design and processing pattern can specifically correspond to an overall design drawing of the circuit board, or a decomposed interlayer design drawing obtained by decomposing each core board layer corresponding to each design and processing parameter. For example, in a circuit board with a four-layer core board, the initial design and processing pattern can specifically include d12, d43, d23, sca23, scb23, d13, d32, sca32, and scb32.

[0082] It is worth noting that the d12 refers to the decomposed interlayer design drawing showing the vias opened from the first core board to the second core board; similarly, the d23 refers to the decomposed interlayer design drawing showing the vias opened from the second core board to the third core board; the sca23 refers to the decomposed interlayer design drawing showing the first slot body opened from the second core board to the third core board; the scb23 refers to the decomposed interlayer design drawing showing the second slot body opened from the second core board to the third core board, and the length and width dimensions of the second slot body are different from the length and width dimensions of the first slot body; it should be particularly noted that the d32 refers to the decomposed interlayer design drawing showing the vias opened from the third core board to the second core board, which is different from d23; and by analogy, the reference meanings of d43, d13, sca32, and scb32 can be obtained, which will not be repeated here.

[0083] S112: Classifying the initial design processing parameters and the initial design processing graphics according to the design interlayer distribution and design opening direction of the design interlayer vias and / or design interlayer slots in the initial design processing graphics to obtain at least two design processing parameters and their corresponding at least two design processing graphics.

[0084] Furthermore, the specific method is to integrate, analyze, classify and process the initial design processing parameters and the initial design processing graphics according to the design interlayer distribution and design opening direction of each design interlayer via and / or each design interlayer slot in the initial design processing graphics to obtain at least two design processing parameters and their corresponding at least two design processing graphics.

[0085] For example, merging d23, sca23, and scb23 yields the designed processing figure d23+++; merging d32, sca32, and scb32 yields the designed processing figure d32+++; d12, d43, and d13 are equivalent to the designed processing figures d12+++, d43+++, and d13+++, respectively.

[0086] It is understandable that the software platform can specifically use d12+++ to obtain the marked processing graphics and their corresponding quality inspection parameter documents, as mentioned above Figure 2 As described in Table 1, and the Figure 2 And Table 1 can specifically constitute one page of the readable file, such as the specific display content of the first page; and the software platform can also use d43+++, d23+++, d32+++, and d13+++ in sequence to obtain other marked processing graphics and their corresponding quality inspection parameter documents, and constitute the specific display content of the second, third, fourth, and fifth pages of the readable file in sequence, which will not be repeated here.

[0087] See also Figure 4 , Figure 4 yes Figure 1 In one embodiment, the method for generating a readable file of the present application includes, in addition to the above steps S11-S16, further more specific steps. Specifically, in the above step S12, the following steps may also be included:

[0088] S121: In the design processing graphics, design inter-layer vias with different inter-layer via parameters are rendered using different first colors.

[0089] The design processing parameters include interlayer via parameters and interlayer slot parameters, and the color includes a first color and a second color.

[0090] Specifically, if Figure 2 As shown, Figure 2 What is shown can be understood as a software platform that can specifically utilize the annotated processing graphics obtained by d12+++, so that on the basis of the d12+++ design processing graphics, each designed interlayer via 21 with different interlayer via parameters is rendered with a different first color, for example, the first via 211, the second via 212, and the third via 213 are rendered with red, green, and yellow, respectively.

[0091] S122: using different second colors for the designed interlayer slots with different interlayer slot parameters, and adding different character labels for rendering to obtain a marked processing graphic.

[0092] Furthermore, on the basis of the design processing graphics, different second colors are used for the designed interlayer slots 22 with different interlayer slot parameters. For example, orange, gray, white and blue are used for the first slot 221, the second slot 222, the third slot 223 and the fourth slot 224 respectively, and different character labels such as 1, 2, 3 and 4 are added for rendering to obtain the marked processing graphics.

[0093] In other embodiments, the character labels corresponding to different design inter-layer vias 21 and design inter-layer slots 22 may be English letters or Arabic numerals, or one or more other reasonable different types of characters such as Roman numerals, Latin letters, Chinese characters, etc.; the second color may be the same as the first color or different, and this application does not limit this.

[0094] See also Figure 5 , Figure 5 yes Figure 1 A schematic flow chart of a specific embodiment of S12 in FIG.

[0095] Specifically, in one embodiment, in the above S12, the following steps may be further included:

[0096] S1211: Obtain the first midpoint coordinates of the designed inter-layer via in the designed processing graphic.

[0097] The character label includes a first character label and / or a second character label.

[0098] Specifically, if Figure 2 As shown, Figure 2 The software platform shown can be understood as a marked processing graphic obtained by using d12+++, and the software platform can specifically obtain the first midpoint coordinates of each designed inter-layer via 21 in the designed processing graphic.

[0099] S1212: Add different first character labels at the first midpoint coordinates for rendering.

[0100] Furthermore, different first character labels are added to the first midpoint coordinates of each design interlayer via 21 in the design processing graphics for rendering, for example, a, b, and c are added to the first midpoint coordinates of the first via 211, the second via 212, and the third via 213 for rendering respectively.

[0101] S1213: Obtain the second midpoint coordinates of the designed interlayer groove in the designed processing graphic.

[0102] Similarly, the second midpoint coordinates of each designed interlayer slot 22 in the designed processing pattern are obtained.

[0103] S1214: Add a different second character label at the second midpoint coordinate for rendering.

[0104] Different second character labels are added to the second midpoint coordinates of the slot 22 between each design layer in the design processing graphics for rendering. For example, 1, 2, 3, and 4 are added to the second midpoint coordinates of the first slot 221, the second slot 222, the third slot 223, and the fourth slot 224 for rendering respectively.

[0105] It is understandable that the first character label and the second character label can be the same or different, and can also be one or more of any other reasonable different types of characters such as Roman numerals, Latin letters, Chinese characters, etc. This application does not limit this.

[0106] See also Figure 6 , Figure 6 This is a flow chart of the second embodiment of the method for generating a readable file of the present application. The method for generating a readable file of this embodiment is Figure 1 A flowchart of a detailed embodiment of a method for generating a readable file in FIG. 1 includes the following steps:

[0107] S31: Obtaining design processing parameters and design processing graphics of the circuit board.

[0108] S32: rendering the design inter-layer vias and / or the design inter-layer slots with different design processing parameters in the design processing graph using different colors and / or adding different character labels to obtain a marked processing graph.

[0109] S33: Add different character name numbers to different design processing parameters, and store them in a preset two-dimensional array in rows.

[0110] S34: Obtaining the processing monitoring parameters and customer acceptance parameters of the circuit board.

[0111] S35: Add the processing monitoring parameters and customer acceptance parameters corresponding to different design processing parameter branches into the preset two-dimensional array to render and obtain a quality inspection parameter document.

[0112] S36: Export the marked processing graphics and quality inspection parameter documents as readable files.

[0113] Among them, S31, S32, S33, S34, S35 and S36 are Figure 1 S11, S12, S13, S14, S15 and S16 are the same. Please refer to S11, S12, S13, S14, S15 and S16 and their related text descriptions for details, which will not be repeated here.

[0114] S37: Detect whether the difference between the processing monitoring parameter and the customer acceptance parameter corresponding to the same design processing parameter is within a set threshold.

[0115] Specifically, the software platform can also automatically compare the processing monitoring parameters corresponding to the same design processing parameters in the preset two-dimensional array with the customer acceptance parameters to detect whether the difference between the two is within the set threshold, that is, to detect whether the processing monitoring parameters meet the customer acceptance requirements.

[0116] If the difference is within the set threshold, then S38 is executed; if the difference is not within the set threshold, then S39 is executed.

[0117] S38: Acceptance passed.

[0118] It can be understood that when it is determined that the difference between the processing monitoring parameters corresponding to the same design processing parameters and the customer acceptance parameters is within the set threshold, it indicates that the design inter-layer vias and / or design inter-layer grooves in the currently processed circuit board meet the customer acceptance requirements, that is, the acceptance is qualified.

[0119] S39: If the difference is not within the set threshold, an alarm indication is issued.

[0120] If the difference between the processing monitoring parameters and the customer acceptance parameters corresponding to the same design processing parameters is not within the set threshold, it indicates that the design inter-layer vias and / or design inter-layer grooves in the currently processed circuit board do not meet the customer acceptance requirements, and an audible and visual alarm indication must be issued, or an alarm window pops up to remind the user that defective products have occurred.

[0121] See also Figure 7 , Figure 7 Schematic diagram of a framework of an embodiment of the smart terminal of the present application. In this embodiment, the smart terminal 40 includes a memory 41 and a processor 42 coupled to each other, and the processor 42 is used to execute program instructions stored in the memory 41 to implement the steps of any of the above-mentioned embodiments of the method for generating a readable file.

[0122] In a specific implementation scenario, the smart terminal 40 may include but is not limited to: monitoring equipment, drones, mobile phones, tablet computers, and any other reasonable terminal devices that include flash memory and have data storage scenarios with multiple data sources. This application does not limit this.

[0123] Specifically, the processor 42 is used to control itself and the memory 41 to implement the steps of any of the above-mentioned video display method embodiments. The processor 42 can also be called a CPU (Central Processing Unit). The processor 42 may be an integrated circuit chip with signal processing capabilities. The processor 42 can also be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The general-purpose processor can be a microprocessor or the processor 42 can also be any conventional processor, etc. In addition, the processor 42 can be implemented by an integrated circuit chip.

[0124] See also Figure 8 , Figure 8 Schematic diagram of a computer-readable storage medium embodiment of the present invention. In this embodiment, the computer-readable storage medium 50 stores program instructions 51 that can be executed by a processor, and the program instructions 51 are used to implement the steps of any of the above-mentioned embodiments of the method for generating a readable file.

[0125] In the several embodiments provided in this application, it should be understood that the disclosed methods and devices can be implemented in other ways. For example, the device implementation methods described above are only schematic. For example, the division of modules or units is only a logical function division. There may be other division methods in actual implementation. For example, units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or units can be electrical, mechanical or other forms.

[0126] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0127] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0128] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) or a processor to execute all or part of the steps of each embodiment method of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

Claims

1. A method for generating a readable file, applied to process dimension monitoring of a circuit board, characterized in that: The generation of the readable file includes: Obtaining design and processing parameters and design and processing graphics of the circuit board; In the design processing graph, the design interlayer vias and / or the design interlayer slots with different design processing parameters are rendered in different colors and / or with different character labels to obtain a marked processing graph; Establishing a first identification code index link at the designed inter-layer via and / or the designed inter-layer slot in the marked processing graphic; wherein the first identification code includes an inter-layer number, a name number, and a dimension number; Add different character name numbers to different design processing parameters, and store them in a preset two-dimensional array in rows; Establishing a second identification code index link at the character name number in the preset two-dimensional array; wherein the second identification code includes a layer number, a name number, a dimension number, and a coordinate number; Obtaining processing monitoring parameters and customer acceptance parameters of the circuit board; Adding the processing monitoring parameters and the customer acceptance parameters corresponding to different design processing parameter branches into the preset two-dimensional array to render and obtain a quality inspection parameter document; The marked processing graphics and the quality inspection parameter document are exported as readable files.

2. The method for generating a readable file according to claim 1, wherein: The step of obtaining the design and processing parameters and the design and processing graphics of the circuit board includes: Obtaining initial design processing parameters and initial design processing graphics of the circuit board; The initial design processing parameters and the initial design processing graphics are classified according to the design inter-layer distribution and design opening direction of the design inter-layer vias and / or the design inter-layer grooves in the initial design processing graphics to obtain at least two of the design processing parameters and their corresponding at least two design processing graphics.

3. The method for generating a readable file according to claim 1, wherein: The design processing parameters include interlayer via parameters and interlayer slot parameters, the colors include a first color and a second color, and the steps of rendering the designed interlayer vias and / or designed interlayer slots having different design processing parameters in the design processing graph using different colors and / or adding different character labels to obtain a marked processing graph include: In the designed processing graph, the designed interlayer vias having different interlayer via parameters are rendered using different first colors respectively; The designed interlayer slots with different interlayer slot parameters are rendered in different second colors and with different character labels added thereto to obtain the marked processing graphics.

4. The method for generating a readable file according to claim 1, wherein: The character labels include a first character label and / or a second character label. In the step of rendering the designed inter-layer vias and / or designed inter-layer slots having different designed processing parameters in the designed processing graphic using different colors and / or adding different character labels to obtain a marked processing graphic, the step further includes: Obtaining the first midpoint coordinates of the designed inter-layer via in the designed processing graphic; Adding different first character labels at the first midpoint coordinates for rendering; and / or, obtaining the second midpoint coordinates of the designed interlayer groove in the designed processing graphic; A different second character label is added at the second midpoint coordinate for rendering.

5. The method for generating a readable file according to claim 1, wherein: After the step of obtaining the design and processing parameters and the design and processing graphics of the circuit board, the method further includes: Different drilling tool table serial number indexes are established for different design processing parameters.

6. The method for generating a readable file according to claim 1, wherein: After the step of adding the processing monitoring parameters and the customer acceptance parameters corresponding to different design processing parameter branches into the preset two-dimensional array to render and obtain a quality inspection parameter document, the method further includes: detecting whether a difference between the processing monitoring parameter and the customer acceptance parameter corresponding to the same design processing parameter is within a set threshold; If the difference is not within the set threshold, an alarm indication is issued.

7. An intelligent terminal, characterized in that: The intelligent terminal includes a memory and a processor coupled to each other; The memory stores program data; The processor is configured to execute the program data to implement the method for generating a readable file according to any one of claims 1 to 6.

8. A computer-readable storage medium, characterized in that The computer-readable storage medium stores program data, and the program data can be executed to implement the method for generating a readable file according to any one of claims 1 to 6.

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